4 * Qualcomm MSM Camera Subsystem - ISPIF Module
6 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
7 * Copyright (C) 2015-2016 Linaro Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 and
11 * only version 2 as published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/completion.h>
20 #include <linux/interrupt.h>
21 #include <linux/iopoll.h>
22 #include <linux/platform_device.h>
23 #include <media/media-entity.h>
24 #include <media/v4l2-device.h>
25 #include <media/v4l2-subdev.h>
30 #define MSM_ISPIF_NAME "msm_ispif"
32 #define ISPIF_RST_CMD_0 0x008
33 #define ISPIF_IRQ_GLOBAL_CLEAR_CMD 0x01c
34 #define ISPIF_VFE_m_CTRL_0(m) (0x200 + 0x200 * (m))
35 #define ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN (1 << 6)
36 #define ISPIF_VFE_m_IRQ_MASK_0(m) (0x208 + 0x200 * (m))
37 #define ISPIF_VFE_m_IRQ_MASK_0_ENABLE 0x0a493249
38 #define ISPIF_VFE_m_IRQ_MASK_1(m) (0x20c + 0x200 * (m))
39 #define ISPIF_VFE_m_IRQ_MASK_1_ENABLE 0x02493249
40 #define ISPIF_VFE_m_IRQ_MASK_2(m) (0x210 + 0x200 * (m))
41 #define ISPIF_VFE_m_IRQ_MASK_2_ENABLE 0x00001249
42 #define ISPIF_VFE_m_IRQ_STATUS_0(m) (0x21c + 0x200 * (m))
43 #define ISPIF_VFE_m_IRQ_STATUS_1(m) (0x220 + 0x200 * (m))
44 #define ISPIF_VFE_m_IRQ_STATUS_2(m) (0x224 + 0x200 * (m))
45 #define ISPIF_VFE_m_IRQ_CLEAR_0(m) (0x230 + 0x200 * (m))
46 #define ISPIF_VFE_m_IRQ_CLEAR_1(m) (0x234 + 0x200 * (m))
47 #define ISPIF_VFE_m_IRQ_CLEAR_2(m) (0x238 + 0x200 * (m))
48 #define ISPIF_VFE_m_INTF_INPUT_SEL(m) (0x244 + 0x200 * (m))
49 #define ISPIF_VFE_m_INTF_CMD_0(m) (0x248 + 0x200 * (m))
50 #define ISPIF_VFE_m_INTF_CMD_1(m) (0x24c + 0x200 * (m))
51 #define ISPIF_VFE_m_PIX_INTF_n_CID_MASK(m, n) (0x254 + 0x200 * (m) + 0x4 * (n))
52 #define ISPIF_VFE_m_RDI_INTF_n_CID_MASK(m, n) (0x264 + 0x200 * (m) + 0x4 * (n))
53 #define ISPIF_VFE_m_PIX_INTF_n_STATUS(m, n) (0x2c0 + 0x200 * (m) + 0x4 * (n))
54 #define ISPIF_VFE_m_RDI_INTF_n_STATUS(m, n) (0x2d0 + 0x200 * (m) + 0x4 * (n))
56 #define CSI_RDI_CLK_MUX_SEL 0x008
58 #define ISPIF_TIMEOUT_SLEEP_US 1000
59 #define ISPIF_TIMEOUT_ALL_US 1000000
70 CMD_DISABLE_FRAME_BOUNDARY = 0x0,
71 CMD_ENABLE_FRAME_BOUNDARY = 0x1,
72 CMD_DISABLE_IMMEDIATELY = 0x2,
73 CMD_ALL_DISABLE_IMMEDIATELY = 0xaaaaaaaa,
74 CMD_ALL_NO_CHANGE = 0xffffffff,
78 * ispif_isr - ISPIF module interrupt handler
79 * @irq: Interrupt line
82 * Return IRQ_HANDLED on success
84 static irqreturn_t ispif_isr(int irq, void *dev)
86 struct ispif_device *ispif = dev;
87 u32 value0, value1, value2;
89 value0 = readl(ispif->base + ISPIF_VFE_m_IRQ_STATUS_0(0));
90 value1 = readl(ispif->base + ISPIF_VFE_m_IRQ_STATUS_1(0));
91 value2 = readl(ispif->base + ISPIF_VFE_m_IRQ_STATUS_2(0));
93 writel(value0, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(0));
94 writel(value1, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(0));
95 writel(value2, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(0));
98 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
101 if ((value0 >> 27) & 0x1)
102 complete(&ispif->reset_complete);
108 * ispif_enable_clocks - Enable clocks for ISPIF module
110 * Return 0 on success or a negative error code otherwise
112 static int ispif_enable_clocks(int nclocks, struct clk **clock,
113 u8 *clock_for_reset, u8 reset)
118 for (i = 0; i < nclocks; i++) {
119 if (clock_for_reset[i] == reset) {
120 ret = clk_prepare_enable(clock[i]);
122 pr_err("clock enable failed\n");
131 for (i--; i >= 0; i--)
132 if (clock_for_reset[i] == reset)
133 clk_disable_unprepare(clock[i]);
139 * ispif_disable_clocks - Disable clocks for ISPIF module
141 static void ispif_disable_clocks(int nclocks, struct clk **clock,
142 u8 *clock_for_reset, u8 reset)
146 for (i = nclocks - 1; i >= 0; i--)
147 if (clock_for_reset[i] == reset)
148 clk_disable_unprepare(clock[i]);
152 * ispif_set_power - Power on/off ISPIF module
153 * @sd: ISPIF V4L2 subdevice
154 * @on: Requested power state
156 * Return 0 on success or a negative error code otherwise
158 static int ispif_set_power(struct v4l2_subdev *sd, int on)
160 struct ispif_device *ispif = v4l2_get_subdevdata(sd);
163 dev_err(ispif->camss->dev, "%s: Enter, on = %d\n",
167 ret = ispif_enable_clocks(ispif->nclocks, ispif->clock,
168 ispif->clock_for_reset, 0);
170 ispif_disable_clocks(ispif->nclocks, ispif->clock,
171 ispif->clock_for_reset, 0);
173 dev_err(ispif->camss->dev, "%s: Exit, on = %d\n",
179 static int ispif_reset(struct ispif_device *ispif)
183 ret = ispif_enable_clocks(ispif->nclocks, ispif->clock,
184 ispif->clock_for_reset, 1);
188 writel(0xfe0f1fff, ispif->base + ISPIF_RST_CMD_0);
189 wait_for_completion(&ispif->reset_complete);
191 ispif_disable_clocks(ispif->nclocks, ispif->clock,
192 ispif->clock_for_reset, 1);
198 static void ispif_reset_sw(struct ispif_device *ispif, u8 vfe)
201 writel_relaxed(ISPIF_VFE_m_CTRL_0_PIX0_LINE_BUF_EN,
202 ispif->base + ISPIF_VFE_m_CTRL_0(vfe));
203 writel_relaxed(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
204 writel_relaxed(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
205 writel_relaxed(0, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
206 writel_relaxed(0xffffffff, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
207 writel_relaxed(0xffffffff, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
208 writel_relaxed(0xffffffff, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
210 writel_relaxed(0, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
212 writel_relaxed(CMD_ALL_NO_CHANGE,
213 ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
214 writel_relaxed(CMD_ALL_NO_CHANGE,
215 ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
218 ispif->base + ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0));
220 ispif->base + ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1));
222 ispif->base + ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0));
224 ispif->base + ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1));
226 ispif->base + ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2));
229 writel_relaxed(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
233 static void ispif_select_clk_mux(struct ispif_device *ispif,
234 enum ispif_intf intf, u8 csid, u8 vfe)
240 val = readl_relaxed(ispif->base_clk_mux);
241 val &= ~(0xf << (vfe * 8));
242 val |= (csid << (vfe * 8));
243 writel_relaxed(val, ispif->base_clk_mux);
247 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
248 val &= ~(0xf << (vfe * 12));
249 val |= (csid << (vfe * 12));
250 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
254 val = readl_relaxed(ispif->base_clk_mux);
255 val &= ~(0xf << (4 + (vfe * 8)));
256 val |= (csid << (4 + (vfe * 8)));
257 writel_relaxed(val, ispif->base_clk_mux);
261 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
262 val &= ~(0xf << (4 + (vfe * 12)));
263 val |= (csid << (4 + (vfe * 12)));
264 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
268 val = readl_relaxed(ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
269 val &= ~(0xf << (8 + (vfe * 12)));
270 val |= (csid << (8 + (vfe * 12)));
271 writel_relaxed(val, ispif->base_clk_mux + CSI_RDI_CLK_MUX_SEL);
278 static int ispif_validate_intf_status(struct ispif_device *ispif,
279 enum ispif_intf intf, u8 vfe)
286 val = readl_relaxed(ispif->base +
287 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 0));
290 val = readl_relaxed(ispif->base +
291 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0));
294 val = readl_relaxed(ispif->base +
295 ISPIF_VFE_m_PIX_INTF_n_STATUS(vfe, 1));
298 val = readl_relaxed(ispif->base +
299 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 1));
302 val = readl_relaxed(ispif->base +
303 ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 2));
307 if ((val & 0xf) != 0xf)
313 static void ispif_select_csid(struct ispif_device *ispif,
314 enum ispif_intf intf, u8 csid, u8 vfe)
318 val = readl_relaxed(ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
321 val &= ~(BIT(1) | BIT(0));
325 val &= ~(BIT(5) | BIT(4));
329 val &= ~(BIT(9) | BIT(8));
333 val &= ~(BIT(13) | BIT(12));
337 val &= ~(BIT(21) | BIT(20));
343 writel_relaxed(val, ispif->base + ISPIF_VFE_m_INTF_INPUT_SEL(vfe));
347 static void ispif_enable_cid(struct ispif_device *ispif, enum ispif_intf intf,
348 u16 cid_mask, u8 vfe, u8 enable)
354 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 0);
357 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 0);
360 addr = ISPIF_VFE_m_PIX_INTF_n_CID_MASK(vfe, 1);
363 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 1);
366 addr = ISPIF_VFE_m_RDI_INTF_n_CID_MASK(vfe, 2);
370 val = readl_relaxed(ispif->base + addr);
377 writel_relaxed(val, ispif->base + addr);
381 static void ispif_config_irq(struct ispif_device *ispif, u8 vfe)
385 val = ISPIF_VFE_m_IRQ_MASK_0_ENABLE;
386 writel(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_0(vfe));
387 writel(val, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_0(vfe));
388 val = ISPIF_VFE_m_IRQ_MASK_1_ENABLE;
389 writel(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_1(vfe));
390 writel(val, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_1(vfe));
391 val = ISPIF_VFE_m_IRQ_MASK_2_ENABLE;
392 writel(val, ispif->base + ISPIF_VFE_m_IRQ_MASK_2(vfe));
393 writel(val, ispif->base + ISPIF_VFE_m_IRQ_CLEAR_2(vfe));
395 writel(0x1, ispif->base + ISPIF_IRQ_GLOBAL_CLEAR_CMD);
399 static void ispif_intf_cmd(struct ispif_device *ispif, u8 cmd,
400 enum ispif_intf intf, u8 vfe, u8 vc)
402 u32 val = CMD_ALL_NO_CHANGE;
405 val &= ~(0x3 << (vc * 2 + 8));
406 val |= (cmd << (vc * 2 + 8));
408 writel_relaxed(val, ispif->base + ISPIF_VFE_m_INTF_CMD_1(vfe));
411 val &= ~(0x3 << (vc * 2 + intf * 8));
412 val |= (cmd << (vc * 2 + intf * 8));
414 writel_relaxed(val, ispif->base + ISPIF_VFE_m_INTF_CMD_0(vfe));
420 * ispif_set_stream - Enable/disable streaming on ISPIF module
421 * @sd: ISPIF V4L2 subdevice
422 * @enable: Requested streaming state
424 * Main configuration of ISPIF module is also done here.
426 * Return 0 on success or a negative error code otherwise
428 static int ispif_set_stream(struct v4l2_subdev *sd, int enable)
430 struct ispif_device *ispif = v4l2_get_subdevdata(sd);
431 enum ispif_intf ispif_intf = RDI0;
433 u8 vc = 0; /* TODO: How to get this from sensor? */
438 dev_err(ispif->camss->dev, "%s: Enter, enable = %d\n",
442 u8 csid = ispif->csid_id;
444 if (!media_entity_remote_pad(
445 &ispif->pads[MSM_ISPIF_PAD_SINK])) {
451 ret = ispif_reset(ispif);
457 ispif_reset_sw(ispif, vfe);
459 ispif_select_clk_mux(ispif, ispif_intf, csid, vfe);
461 ret = ispif_validate_intf_status(ispif, ispif_intf, vfe);
465 ispif_select_csid(ispif, ispif_intf, csid, vfe);
467 ispif_enable_cid(ispif, ispif_intf, 1 << cid, vfe, 1);
469 ispif_config_irq(ispif, vfe);
471 ispif_intf_cmd(ispif, CMD_ENABLE_FRAME_BOUNDARY, ispif_intf, vfe, vc);
475 ispif_intf_cmd(ispif, CMD_DISABLE_FRAME_BOUNDARY, ispif_intf, vfe, vc);
477 ret = readl_poll_timeout(ispif->base + ISPIF_VFE_m_RDI_INTF_n_STATUS(vfe, 0),
479 (stop_flag & 0xf) == 0xf,
480 ISPIF_TIMEOUT_SLEEP_US,
481 ISPIF_TIMEOUT_ALL_US);
485 ispif_enable_cid(ispif, ispif_intf, 1 << cid, vfe, 0);
492 * msm_ispif_subdev_init - Initialize ISPIF device structure and resources
493 * @ispif: ISPIF device
494 * @camss: Camera sub-system structure
495 * @res: ISPIF module resources table
497 * Return 0 on success or a negative error code otherwise
499 int msm_ispif_subdev_init(struct ispif_device *ispif, struct camss *camss,
500 struct resources_ispif *res)
502 struct device *dev = camss->dev;
503 struct platform_device *pdev = container_of(dev, struct platform_device, dev);
508 ispif->camss = camss;
512 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[0]);
513 ispif->base = devm_ioremap_resource(dev, r);
514 if (IS_ERR(ispif->base)) {
515 dev_err(dev, "could not map memory\n");
516 return PTR_ERR(ispif->base);
519 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res->reg[1]);
520 ispif->base_clk_mux = devm_ioremap_resource(dev, r);
521 if (IS_ERR(ispif->base_clk_mux)) {
522 dev_err(dev, "could not map memory\n");
523 return PTR_ERR(ispif->base_clk_mux);
528 r = platform_get_resource_byname(pdev, IORESOURCE_IRQ, res->interrupt);
529 ispif->irq = r->start;
530 if (IS_ERR_VALUE(ispif->irq))
533 ret = devm_request_irq(dev, ispif->irq, ispif_isr,
534 IRQF_TRIGGER_RISING, "ispif", ispif);
536 dev_err(dev, "request_irq failed\n");
544 while (res->clock[i++])
547 ispif->clock = devm_kzalloc(dev, ispif->nclocks * sizeof(*ispif->clock),
550 dev_err(dev, "could not allocate memory\n");
554 ispif->clock_for_reset = devm_kzalloc(dev, ispif->nclocks *
555 sizeof(*ispif->clock_for_reset), GFP_KERNEL);
556 if (!ispif->clock_for_reset) {
557 dev_err(dev, "could not allocate memory\n");
561 for (i = 0; i < ispif->nclocks; i++) {
562 ispif->clock[i] = devm_clk_get(dev, res->clock[i]);
563 if (IS_ERR(ispif->clock[i]))
564 return PTR_ERR(ispif->clock[i]);
565 ispif->clock_for_reset[i] = res->clock_for_reset[i];
568 init_completion(&ispif->reset_complete);
573 static int ispif_link_setup(struct media_entity *entity,
574 const struct media_pad *local,
575 const struct media_pad *remote, u32 flags)
577 if ((local->flags & MEDIA_PAD_FL_SINK) &&
578 (flags & MEDIA_LNK_FL_ENABLED)) {
579 struct v4l2_subdev *sd;
580 struct ispif_device *ispif;
581 struct csid_device *csid;
583 sd = container_of(entity, struct v4l2_subdev, entity);
584 ispif = v4l2_get_subdevdata(sd);
586 sd = container_of(remote->entity, struct v4l2_subdev, entity);
587 csid = v4l2_get_subdevdata(sd);
589 ispif->csid_id = csid->id;
595 static const struct v4l2_subdev_core_ops ispif_core_ops = {
596 .s_power = ispif_set_power,
599 static const struct v4l2_subdev_video_ops ispif_video_ops = {
600 .s_stream = ispif_set_stream,
603 static const struct v4l2_subdev_pad_ops ispif_pad_ops;
605 static const struct v4l2_subdev_ops ispif_v4l2_ops = {
606 .core = &ispif_core_ops,
607 .video = &ispif_video_ops,
608 .pad = &ispif_pad_ops,
611 static const struct v4l2_subdev_internal_ops ispif_v4l2_internal_ops;
613 static const struct media_entity_operations ispif_media_ops = {
614 .link_setup = ispif_link_setup,
618 * msm_ispif_register_entities - Register subdev node for ISPIF module
619 * @ispif: ISPIF device
620 * @v4l2_dev: V4L2 device
622 * Return 0 on success or a negative error code otherwise
624 int msm_ispif_register_entities(struct ispif_device *ispif,
625 struct v4l2_device *v4l2_dev)
627 struct v4l2_subdev *sd = &ispif->subdev;
628 struct media_pad *pads = ispif->pads;
631 v4l2_subdev_init(sd, &ispif_v4l2_ops);
632 sd->internal_ops = &ispif_v4l2_internal_ops;
633 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
634 snprintf(sd->name, ARRAY_SIZE(sd->name), MSM_ISPIF_NAME);
635 v4l2_set_subdevdata(sd, ispif);
637 pads[MSM_ISPIF_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
638 pads[MSM_ISPIF_PAD_SRC].flags = MEDIA_PAD_FL_SOURCE;
640 sd->entity.ops = &ispif_media_ops;
641 ret = media_entity_init(&sd->entity, MSM_ISPIF_PADS_NUM, pads, 0);
643 pr_err("Fail to init media entity");
647 ret = v4l2_device_register_subdev(v4l2_dev, sd);
649 pr_err("Fail to register subdev");
650 media_entity_cleanup(&sd->entity);
657 * msm_ispif_unregister_entities - Unregister ISPIF module subdev node
658 * @ispif: ISPIF device
660 void msm_ispif_unregister_entities(struct ispif_device *ispif)
662 v4l2_device_unregister_subdev(&ispif->subdev);