drivers/memory/omap-gpmc.c

   1 /*
   2  * GPMC support functions
   3  *
   4  * Copyright (C) 2005-2006 Nokia Corporation
   5  *
   6  * Author: Juha Yrjola
   7  *
   8  * Copyright (C) 2009 Texas Instruments
   9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/err.h>
  19 #include <linux/clk.h>
  20 #include <linux/ioport.h>
  21 #include <linux/spinlock.h>
  22 #include <linux/io.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_mtd.h>
  30 #include <linux/of_device.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/omap-gpmc.h>
  33 #include <linux/mtd/nand.h>
  34 #include <linux/pm_runtime.h>
  35
  36 #include <linux/platform_data/mtd-nand-omap2.h>
  37 #include <linux/platform_data/mtd-onenand-omap2.h>
  38
  39 #include <asm/mach-types.h>
  40
  41 #define DEVICE_NAME             "omap-gpmc"
  42
  43 /* GPMC register offsets */
  44 #define GPMC_REVISION           0x00
  45 #define GPMC_SYSCONFIG          0x10
  46 #define GPMC_SYSSTATUS          0x14
  47 #define GPMC_IRQSTATUS          0x18
  48 #define GPMC_IRQENABLE          0x1c
  49 #define GPMC_TIMEOUT_CONTROL    0x40
  50 #define GPMC_ERR_ADDRESS        0x44
  51 #define GPMC_ERR_TYPE           0x48
  52 #define GPMC_CONFIG             0x50
  53 #define GPMC_STATUS             0x54
  54 #define GPMC_PREFETCH_CONFIG1   0x1e0
  55 #define GPMC_PREFETCH_CONFIG2   0x1e4
  56 #define GPMC_PREFETCH_CONTROL   0x1ec
  57 #define GPMC_PREFETCH_STATUS    0x1f0
  58 #define GPMC_ECC_CONFIG         0x1f4
  59 #define GPMC_ECC_CONTROL        0x1f8
  60 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  61 #define GPMC_ECC1_RESULT        0x200
  62 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  65 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  66 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  67 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  68 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  69
  70 /* GPMC ECC control settings */
  71 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  72 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  73 #define GPMC_ECC_CTRL_ECCREG1           0x001
  74 #define GPMC_ECC_CTRL_ECCREG2           0x002
  75 #define GPMC_ECC_CTRL_ECCREG3           0x003
  76 #define GPMC_ECC_CTRL_ECCREG4           0x004
  77 #define GPMC_ECC_CTRL_ECCREG5           0x005
  78 #define GPMC_ECC_CTRL_ECCREG6           0x006
  79 #define GPMC_ECC_CTRL_ECCREG7           0x007
  80 #define GPMC_ECC_CTRL_ECCREG8           0x008
  81 #define GPMC_ECC_CTRL_ECCREG9           0x009
  82
  83 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  84
  85 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  86
  87 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  88 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  89 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  90 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  91 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  92 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  93
  94 #define GPMC_CS0_OFFSET         0x60
  95 #define GPMC_CS_SIZE            0x30
  96 #define GPMC_BCH_SIZE           0x10
  97
  98 #define GPMC_MEM_END            0x3FFFFFFF
  99
 100 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 101 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 102
 103 #define CS_NUM_SHIFT            24
 104 #define ENABLE_PREFETCH         (0x1 << 7)
 105 #define DMA_MPU_MODE            2
 106
 107 #define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
 108 #define GPMC_REVISION_MINOR(l)          (l & 0xf)
 109
 110 #define GPMC_HAS_WR_ACCESS              0x1
 111 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 112 #define GPMC_HAS_MUX_AAD                0x4
 113
 114 #define GPMC_NR_WAITPINS                4
 115
 116 #define GPMC_CS_CONFIG1         0x00
 117 #define GPMC_CS_CONFIG2         0x04
 118 #define GPMC_CS_CONFIG3         0x08
 119 #define GPMC_CS_CONFIG4         0x0c
 120 #define GPMC_CS_CONFIG5         0x10
 121 #define GPMC_CS_CONFIG6         0x14
 122 #define GPMC_CS_CONFIG7         0x18
 123 #define GPMC_CS_NAND_COMMAND    0x1c
 124 #define GPMC_CS_NAND_ADDRESS    0x20
 125 #define GPMC_CS_NAND_DATA       0x24
 126
 127 /* Control Commands */
 128 #define GPMC_CONFIG_RDY_BSY     0x00000001
 129 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 130 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 131
 132 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 133 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 134 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 135 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 136 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 137 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 138 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 139 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
 140 /** CLKACTIVATIONTIME Max Ticks */
 141 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 142 #define GPMC_CONFIG1_PAGE_LEN(val)      ((val & 3) << 23)
 143 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 144 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 145 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 146 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 147 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
 148 /** WAITMONITORINGTIME Max Ticks */
 149 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 150 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  ((val & 3) << 16)
 151 #define GPMC_CONFIG1_DEVICESIZE(val)    ((val & 3) << 12)
 152 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 153 /** DEVICESIZE Max Value */
 154 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 155 #define GPMC_CONFIG1_DEVICETYPE(val)    ((val & 3) << 10)
 156 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 157 #define GPMC_CONFIG1_MUXTYPE(val)       ((val & 3) << 8)
 158 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 159 #define GPMC_CONFIG1_FCLK_DIV(val)      (val & 3)
 160 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 161 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 162 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 163 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 164
 165 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 166 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 167 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 168 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 169 /* All CONFIG7 bits except reserved bits */
 170 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 171                                          GPMC_CONFIG7_CSVALID_MASK |     \
 172                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 173
 174 #define GPMC_DEVICETYPE_NOR             0
 175 #define GPMC_DEVICETYPE_NAND            2
 176 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 177 #define WR_RD_PIN_MONITORING            0x00600000
 178
 179 /* ECC commands */
 180 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 181 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 182 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 183
 184 /* XXX: Only NAND irq has been considered,currently these are the only ones used
 185  */
 186 #define GPMC_NR_IRQ             2
 187
 188 enum gpmc_clk_domain {
 189         GPMC_CD_FCLK,
 190         GPMC_CD_CLK
 191 };
 192
 193 struct gpmc_cs_data {
 194         const char *name;
 195
 196 #define GPMC_CS_RESERVED        (1 << 0)
 197         u32 flags;
 198
 199         struct resource mem;
 200 };
 201
 202 /* Structure to save gpmc cs context */
 203 struct gpmc_cs_config {
 204         u32 config1;
 205         u32 config2;
 206         u32 config3;
 207         u32 config4;
 208         u32 config5;
 209         u32 config6;
 210         u32 config7;
 211         int is_valid;
 212 };
 213
 214 /*
 215  * Structure to save/restore gpmc context
 216  * to support core off on OMAP3
 217  */
 218 struct omap3_gpmc_regs {
 219         u32 sysconfig;
 220         u32 irqenable;
 221         u32 timeout_ctrl;
 222         u32 config;
 223         u32 prefetch_config1;
 224         u32 prefetch_config2;
 225         u32 prefetch_control;
 226         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 227 };
 228
 229 struct gpmc_device {
 230         struct device *dev;
 231         int irq;
 232         struct irq_chip irq_chip;
 233 };
 234
 235 static struct irq_domain *gpmc_irq_domain;
 236
 237 static struct resource  gpmc_mem_root;
 238 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 239 static DEFINE_SPINLOCK(gpmc_mem_lock);
 240 /* Define chip-selects as reserved by default until probe completes */
 241 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 242 static unsigned int gpmc_nr_waitpins;
 243 static resource_size_t phys_base, mem_size;
 244 static unsigned gpmc_capability;
 245 static void __iomem *gpmc_base;
 246
 247 static struct clk *gpmc_l3_clk;
 248
 249 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 250
 251 static void gpmc_write_reg(int idx, u32 val)
 252 {
 253         writel_relaxed(val, gpmc_base + idx);
 254 }
 255
 256 static u32 gpmc_read_reg(int idx)
 257 {
 258         return readl_relaxed(gpmc_base + idx);
 259 }
 260
 261 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 262 {
 263         void __iomem *reg_addr;
 264
 265         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 266         writel_relaxed(val, reg_addr);
 267 }
 268
 269 static u32 gpmc_cs_read_reg(int cs, int idx)
 270 {
 271         void __iomem *reg_addr;
 272
 273         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 274         return readl_relaxed(reg_addr);
 275 }
 276
 277 /* TODO: Add support for gpmc_fck to clock framework and use it */
 278 static unsigned long gpmc_get_fclk_period(void)
 279 {
 280         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 281
 282         rate /= 1000;
 283         rate = 1000000000 / rate;       /* In picoseconds */
 284
 285         return rate;
 286 }
 287
 288 /**
 289  * gpmc_get_clk_period - get period of selected clock domain in ps
 290  * @cs Chip Select Region.
 291  * @cd Clock Domain.
 292  *
 293  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 294  * prior to calling this function with GPMC_CD_CLK.
 295  */
 296 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 297 {
 298
 299         unsigned long tick_ps = gpmc_get_fclk_period();
 300         u32 l;
 301         int div;
 302
 303         switch (cd) {
 304         case GPMC_CD_CLK:
 305                 /* get current clk divider */
 306                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 307                 div = (l & 0x03) + 1;
 308                 /* get GPMC_CLK period */
 309                 tick_ps *= div;
 310                 break;
 311         case GPMC_CD_FCLK:
 312                 /* FALL-THROUGH */
 313         default:
 314                 break;
 315         }
 316
 317         return tick_ps;
 318
 319 }
 320
 321 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 322                                          enum gpmc_clk_domain cd)
 323 {
 324         unsigned long tick_ps;
 325
 326         /* Calculate in picosecs to yield more exact results */
 327         tick_ps = gpmc_get_clk_period(cs, cd);
 328
 329         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 330 }
 331
 332 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 333 {
 334         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 335 }
 336
 337 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 338 {
 339         unsigned long tick_ps;
 340
 341         /* Calculate in picosecs to yield more exact results */
 342         tick_ps = gpmc_get_fclk_period();
 343
 344         return (time_ps + tick_ps - 1) / tick_ps;
 345 }
 346
 347 unsigned int gpmc_clk_ticks_to_ns(unsigned ticks, int cs,
 348                                   enum gpmc_clk_domain cd)
 349 {
 350         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 351 }
 352
 353 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 354 {
 355         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 356 }
 357
 358 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 359 {
 360         return ticks * gpmc_get_fclk_period();
 361 }
 362
 363 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 364 {
 365         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 366
 367         return ticks * gpmc_get_fclk_period();
 368 }
 369
 370 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 371 {
 372         u32 l;
 373
 374         l = gpmc_cs_read_reg(cs, reg);
 375         if (value)
 376                 l |= mask;
 377         else
 378                 l &= ~mask;
 379         gpmc_cs_write_reg(cs, reg, l);
 380 }
 381
 382 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 383 {
 384         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 385                            GPMC_CONFIG1_TIME_PARA_GRAN,
 386                            p->time_para_granularity);
 387         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 388                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 389         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 390                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 391         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 392                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 393         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 394                            GPMC_CONFIG4_OEEXTRADELAY, p->we_extra_delay);
 395         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 396                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 397                            p->cycle2cyclesamecsen);
 398         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 399                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 400                            p->cycle2cyclediffcsen);
 401 }
 402
 403 #ifdef CONFIG_OMAP_GPMC_DEBUG
 404 /**
 405  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 406  * @cs:      Chip Select Region
 407  * @reg:     GPMC_CS_CONFIGn register offset.
 408  * @st_bit:  Start Bit
 409  * @end_bit: End Bit. Must be >= @st_bit.
 410  * @ma:x     Maximum parameter value (before optional @shift).
 411  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 412  * @name:    DTS node name, w/o "gpmc,"
 413  * @cd:      Clock Domain of timing parameter.
 414  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 415  * @raw:     Raw Format Option.
 416  *           raw format:  gpmc,name = <value>
 417  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 418  *           Where x ns -- y ns result in the same tick value.
 419  *           When @max is exceeded, "invalid" is printed inside comment.
 420  * @noval:   Parameter values equal to 0 are not printed.
 421  * @return:  Specified timing parameter (after optional @shift).
 422  *
 423  */
 424 static int get_gpmc_timing_reg(
 425         /* timing specifiers */
 426         int cs, int reg, int st_bit, int end_bit, int max,
 427         const char *name, const enum gpmc_clk_domain cd,
 428         /* value transform */
 429         int shift,
 430         /* format specifiers */
 431         bool raw, bool noval)
 432 {
 433         u32 l;
 434         int nr_bits;
 435         int mask;
 436         bool invalid;
 437
 438         l = gpmc_cs_read_reg(cs, reg);
 439         nr_bits = end_bit - st_bit + 1;
 440         mask = (1 << nr_bits) - 1;
 441         l = (l >> st_bit) & mask;
 442         if (!max)
 443                 max = mask;
 444         invalid = l > max;
 445         if (shift)
 446                 l = (shift << l);
 447         if (noval && (l == 0))
 448                 return 0;
 449         if (!raw) {
 450                 /* DTS tick format for timings in ns */
 451                 unsigned int time_ns;
 452                 unsigned int time_ns_min = 0;
 453
 454                 if (l)
 455                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 456                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 457                 pr_info("gpmc,%s = <%u> /* %u ns - %u ns; %i ticks%s*/\n",
 458                         name, time_ns, time_ns_min, time_ns, l,
 459                         invalid ? "; invalid " : " ");
 460         } else {
 461                 /* raw format */
 462                 pr_info("gpmc,%s = <%u>%s\n", name, l,
 463                         invalid ? " /* invalid */" : "");
 464         }
 465
 466         return l;
 467 }
 468
 469 #define GPMC_PRINT_CONFIG(cs, config) \
 470         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 471                 gpmc_cs_read_reg(cs, config))
 472 #define GPMC_GET_RAW(reg, st, end, field) \
 473         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 474 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 475         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 476 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 477         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 478 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 479         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 480 #define GPMC_GET_TICKS(reg, st, end, field) \
 481         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 482 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 483         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 484 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 485         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 486
 487 static void gpmc_show_regs(int cs, const char *desc)
 488 {
 489         pr_info("gpmc cs%i %s:\n", cs, desc);
 490         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 491         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 492         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 493         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 494         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 495         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 496 }
 497
 498 /*
 499  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 500  * see commit c9fb809.
 501  */
 502 static void gpmc_cs_show_timings(int cs, const char *desc)
 503 {
 504         gpmc_show_regs(cs, desc);
 505
 506         pr_info("gpmc cs%i access configuration:\n", cs);
 507         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 508         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 509         GPMC_GET_RAW_MAX(GPMC_CS_CONFIG1, 12, 13,
 510                          GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 511         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 512         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 513         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 514         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 515                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 516                                "burst-length");
 517         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 518         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 519         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 520         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 521         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 522
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 524
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 526
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 528         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 529
 530         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 532
 533         pr_info("gpmc cs%i timings configuration:\n", cs);
 534         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 535         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 536         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 537
 538         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 540         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 541         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 542                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 543                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 544                                 "adv-aad-mux-rd-off-ns");
 545                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 546                                 "adv-aad-mux-wr-off-ns");
 547         }
 548
 549         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 550         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 551         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 552                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 553                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 554         }
 555         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 556         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 557
 558         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 559         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 560         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 561
 562         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 563
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 565         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 566
 567         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 568                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 569                               "wait-monitoring-ns", GPMC_CD_CLK);
 570         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 571                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 572                               "clk-activation-ns", GPMC_CD_FCLK);
 573
 574         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 575         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 576 }
 577 #else
 578 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 579 {
 580 }
 581 #endif
 582
 583 /**
 584  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 585  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 586  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 587  *
 588  * @cs:      Chip Select Region.
 589  * @reg:     GPMC_CS_CONFIGn register offset.
 590  * @st_bit:  Start Bit
 591  * @end_bit: End Bit. Must be >= @st_bit.
 592  * @max:     Maximum parameter value.
 593  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 594  * @time:    Timing parameter in ns.
 595  * @cd:      Timing parameter clock domain.
 596  * @name:    Timing parameter name.
 597  * @return:  0 on success, -1 on error.
 598  */
 599 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 600                                int time, enum gpmc_clk_domain cd, const char *name)
 601 {
 602         u32 l;
 603         int ticks, mask, nr_bits;
 604
 605         if (time == 0)
 606                 ticks = 0;
 607         else
 608                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 609         nr_bits = end_bit - st_bit + 1;
 610         mask = (1 << nr_bits) - 1;
 611
 612         if (!max)
 613                 max = mask;
 614
 615         if (ticks > max) {
 616                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 617                        __func__, cs, name, time, ticks, max);
 618
 619                 return -1;
 620         }
 621
 622         l = gpmc_cs_read_reg(cs, reg);
 623 #ifdef CONFIG_OMAP_GPMC_DEBUG
 624         pr_info(
 625                 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 626                cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 627                         (l >> st_bit) & mask, time);
 628 #endif
 629         l &= ~(mask << st_bit);
 630         l |= ticks << st_bit;
 631         gpmc_cs_write_reg(cs, reg, l);
 632
 633         return 0;
 634 }
 635
 636 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd)  \
 637         if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
 638             t->field, (cd), #field) < 0)                       \
 639                 return -1
 640
 641 #define GPMC_SET_ONE(reg, st, end, field) \
 642         GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
 643
 644 /**
 645  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 646  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 647  * read  --> don't sample bus too early
 648  * write --> data is longer on bus
 649  *
 650  * Formula:
 651  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 652  *                    / waitmonitoring_ticks)
 653  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 654  * div <= 0 check.
 655  *
 656  * @wait_monitoring: WAITMONITORINGTIME in ns.
 657  * @return:          -1 on failure to scale, else proper divider > 0.
 658  */
 659 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 660 {
 661
 662         int div = gpmc_ns_to_ticks(wait_monitoring);
 663
 664         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 665         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 666
 667         if (div > 4)
 668                 return -1;
 669         if (div <= 0)
 670                 div = 1;
 671
 672         return div;
 673
 674 }
 675
 676 /**
 677  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 678  * @sync_clk: GPMC_CLK period in ps.
 679  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 680  *            Else, returns -1.
 681  */
 682 int gpmc_calc_divider(unsigned int sync_clk)
 683 {
 684         int div = gpmc_ps_to_ticks(sync_clk);
 685
 686         if (div > 4)
 687                 return -1;
 688         if (div <= 0)
 689                 div = 1;
 690
 691         return div;
 692 }
 693
 694 /**
 695  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 696  * @cs:     Chip Select Region.
 697  * @t:      GPMC timing parameters.
 698  * @s:      GPMC timing settings.
 699  * @return: 0 on success, -1 on error.
 700  */
 701 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 702                         const struct gpmc_settings *s)
 703 {
 704         int div;
 705         u32 l;
 706
 707         div = gpmc_calc_divider(t->sync_clk);
 708         if (div < 0)
 709                 return div;
 710
 711         /*
 712          * See if we need to change the divider for waitmonitoringtime.
 713          *
 714          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 715          * pure asynchronous accesses, i.e. both read and write asynchronous.
 716          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 717          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 718          *
 719          * This statement must not change div to scale async WAITMONITORINGTIME
 720          * to protect mixed synchronous and asynchronous accesses.
 721          *
 722          * We raise an error later if WAITMONITORINGTIME does not fit.
 723          */
 724         if (!s->sync_read && !s->sync_write &&
 725             (s->wait_on_read || s->wait_on_write)
 726            ) {
 727
 728                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 729                 if (div < 0) {
 730                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 731                                __func__,
 732                                t->wait_monitoring
 733                                );
 734                         return -1;
 735                 }
 736         }
 737
 738         GPMC_SET_ONE(GPMC_CS_CONFIG2,  0,  3, cs_on);
 739         GPMC_SET_ONE(GPMC_CS_CONFIG2,  8, 12, cs_rd_off);
 740         GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
 741
 742         GPMC_SET_ONE(GPMC_CS_CONFIG3,  0,  3, adv_on);
 743         GPMC_SET_ONE(GPMC_CS_CONFIG3,  8, 12, adv_rd_off);
 744         GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
 745         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 746                 GPMC_SET_ONE(GPMC_CS_CONFIG3,  4,  6, adv_aad_mux_on);
 747                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
 748                 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
 749         }
 750
 751         GPMC_SET_ONE(GPMC_CS_CONFIG4,  0,  3, oe_on);
 752         GPMC_SET_ONE(GPMC_CS_CONFIG4,  8, 12, oe_off);
 753         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 754                 GPMC_SET_ONE(GPMC_CS_CONFIG4,  4,  6, oe_aad_mux_on);
 755                 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
 756         }
 757         GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
 758         GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
 759
 760         GPMC_SET_ONE(GPMC_CS_CONFIG5,  0,  4, rd_cycle);
 761         GPMC_SET_ONE(GPMC_CS_CONFIG5,  8, 12, wr_cycle);
 762         GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
 763
 764         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 765
 766         GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
 767         GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
 768
 769         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
 770                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
 771         if (gpmc_capability & GPMC_HAS_WR_ACCESS)
 772                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
 773
 774         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 775         l &= ~0x03;
 776         l |= (div - 1);
 777         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 778
 779         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 780                             GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 781                             wait_monitoring, GPMC_CD_CLK);
 782         GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 783                             GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 784                             clk_activation, GPMC_CD_FCLK);
 785
 786 #ifdef CONFIG_OMAP_GPMC_DEBUG
 787         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 788                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 789 #endif
 790
 791         gpmc_cs_bool_timings(cs, &t->bool_timings);
 792         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 793
 794         return 0;
 795 }
 796
 797 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 798 {
 799         u32 l;
 800         u32 mask;
 801
 802         /*
 803          * Ensure that base address is aligned on a
 804          * boundary equal to or greater than size.
 805          */
 806         if (base & (size - 1))
 807                 return -EINVAL;
 808
 809         base >>= GPMC_CHUNK_SHIFT;
 810         mask = (1 << GPMC_SECTION_SHIFT) - size;
 811         mask >>= GPMC_CHUNK_SHIFT;
 812         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 813
 814         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 815         l &= ~GPMC_CONFIG7_MASK;
 816         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 817         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 818         l |= GPMC_CONFIG7_CSVALID;
 819         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 820
 821         return 0;
 822 }
 823
 824 static void gpmc_cs_enable_mem(int cs)
 825 {
 826         u32 l;
 827
 828         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 829         l |= GPMC_CONFIG7_CSVALID;
 830         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 831 }
 832
 833 static void gpmc_cs_disable_mem(int cs)
 834 {
 835         u32 l;
 836
 837         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 838         l &= ~GPMC_CONFIG7_CSVALID;
 839         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 840 }
 841
 842 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 843 {
 844         u32 l;
 845         u32 mask;
 846
 847         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 848         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 849         mask = (l >> 8) & 0x0f;
 850         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 851 }
 852
 853 static int gpmc_cs_mem_enabled(int cs)
 854 {
 855         u32 l;
 856
 857         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 858         return l & GPMC_CONFIG7_CSVALID;
 859 }
 860
 861 static void gpmc_cs_set_reserved(int cs, int reserved)
 862 {
 863         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 864
 865         gpmc->flags |= GPMC_CS_RESERVED;
 866 }
 867
 868 static bool gpmc_cs_reserved(int cs)
 869 {
 870         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 871
 872         return gpmc->flags & GPMC_CS_RESERVED;
 873 }
 874
 875 static void gpmc_cs_set_name(int cs, const char *name)
 876 {
 877         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 878
 879         gpmc->name = name;
 880 }
 881
 882 static const char *gpmc_cs_get_name(int cs)
 883 {
 884         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 885
 886         return gpmc->name;
 887 }
 888
 889 static unsigned long gpmc_mem_align(unsigned long size)
 890 {
 891         int order;
 892
 893         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 894         order = GPMC_CHUNK_SHIFT - 1;
 895         do {
 896                 size >>= 1;
 897                 order++;
 898         } while (size);
 899         size = 1 << order;
 900         return size;
 901 }
 902
 903 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 904 {
 905         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 906         struct resource *res = &gpmc->mem;
 907         int r;
 908
 909         size = gpmc_mem_align(size);
 910         spin_lock(&gpmc_mem_lock);
 911         res->start = base;
 912         res->end = base + size - 1;
 913         r = request_resource(&gpmc_mem_root, res);
 914         spin_unlock(&gpmc_mem_lock);
 915
 916         return r;
 917 }
 918
 919 static int gpmc_cs_delete_mem(int cs)
 920 {
 921         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 922         struct resource *res = &gpmc->mem;
 923         int r;
 924
 925         spin_lock(&gpmc_mem_lock);
 926         r = release_resource(res);
 927         res->start = 0;
 928         res->end = 0;
 929         spin_unlock(&gpmc_mem_lock);
 930
 931         return r;
 932 }
 933
 934 /**
 935  * gpmc_cs_remap - remaps a chip-select physical base address
 936  * @cs:         chip-select to remap
 937  * @base:       physical base address to re-map chip-select to
 938  *
 939  * Re-maps a chip-select to a new physical base address specified by
 940  * "base". Returns 0 on success and appropriate negative error code
 941  * on failure.
 942  */
 943 static int gpmc_cs_remap(int cs, u32 base)
 944 {
 945         int ret;
 946         u32 old_base, size;
 947
 948         if (cs > gpmc_cs_num) {
 949                 pr_err("%s: requested chip-select is disabled\n", __func__);
 950                 return -ENODEV;
 951         }
 952
 953         /*
 954          * Make sure we ignore any device offsets from the GPMC partition
 955          * allocated for the chip select and that the new base confirms
 956          * to the GPMC 16MB minimum granularity.
 957          */
 958         base &= ~(SZ_16M - 1);
 959
 960         gpmc_cs_get_memconf(cs, &old_base, &size);
 961         if (base == old_base)
 962                 return 0;
 963
 964         ret = gpmc_cs_delete_mem(cs);
 965         if (ret < 0)
 966                 return ret;
 967
 968         ret = gpmc_cs_insert_mem(cs, base, size);
 969         if (ret < 0)
 970                 return ret;
 971
 972         ret = gpmc_cs_set_memconf(cs, base, size);
 973
 974         return ret;
 975 }
 976
 977 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 978 {
 979         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 980         struct resource *res = &gpmc->mem;
 981         int r = -1;
 982
 983         if (cs > gpmc_cs_num) {
 984                 pr_err("%s: requested chip-select is disabled\n", __func__);
 985                 return -ENODEV;
 986         }
 987         size = gpmc_mem_align(size);
 988         if (size > (1 << GPMC_SECTION_SHIFT))
 989                 return -ENOMEM;
 990
 991         spin_lock(&gpmc_mem_lock);
 992         if (gpmc_cs_reserved(cs)) {
 993                 r = -EBUSY;
 994                 goto out;
 995         }
 996         if (gpmc_cs_mem_enabled(cs))
 997                 r = adjust_resource(res, res->start & ~(size - 1), size);
 998         if (r < 0)
 999                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1000                                       size, NULL, NULL);
1001         if (r < 0)
1002                 goto out;
1003
1004         /* Disable CS while changing base address and size mask */
1005         gpmc_cs_disable_mem(cs);
1006
1007         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1008         if (r < 0) {
1009                 release_resource(res);
1010                 goto out;
1011         }
1012
1013         /* Enable CS */
1014         gpmc_cs_enable_mem(cs);
1015         *base = res->start;
1016         gpmc_cs_set_reserved(cs, 1);
1017 out:
1018         spin_unlock(&gpmc_mem_lock);
1019         return r;
1020 }
1021 EXPORT_SYMBOL(gpmc_cs_request);
1022
1023 void gpmc_cs_free(int cs)
1024 {
1025         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1026         struct resource *res = &gpmc->mem;
1027
1028         spin_lock(&gpmc_mem_lock);
1029         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1030                 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1031                 BUG();
1032                 spin_unlock(&gpmc_mem_lock);
1033                 return;
1034         }
1035         gpmc_cs_disable_mem(cs);
1036         if (res->flags)
1037                 release_resource(res);
1038         gpmc_cs_set_reserved(cs, 0);
1039         spin_unlock(&gpmc_mem_lock);
1040 }
1041 EXPORT_SYMBOL(gpmc_cs_free);
1042
1043 /**
1044  * gpmc_configure - write request to configure gpmc
1045  * @cmd: command type
1046  * @wval: value to write
1047  * @return status of the operation
1048  */
1049 int gpmc_configure(int cmd, int wval)
1050 {
1051         u32 regval;
1052
1053         switch (cmd) {
1054         case GPMC_CONFIG_WP:
1055                 regval = gpmc_read_reg(GPMC_CONFIG);
1056                 if (wval)
1057                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1058                 else
1059                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1060                 gpmc_write_reg(GPMC_CONFIG, regval);
1061                 break;
1062
1063         default:
1064                 pr_err("%s: command not supported\n", __func__);
1065                 return -EINVAL;
1066         }
1067
1068         return 0;
1069 }
1070 EXPORT_SYMBOL(gpmc_configure);
1071
1072 void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs)
1073 {
1074         int i;
1075
1076         reg->gpmc_status = gpmc_base + GPMC_STATUS;
1077         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1078                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1079         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1080                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1081         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1082                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1083         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1084         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1085         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1086         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1087         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1088         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1089         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1090         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1091
1092         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1093                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1094                                            GPMC_BCH_SIZE * i;
1095                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1096                                            GPMC_BCH_SIZE * i;
1097                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1098                                            GPMC_BCH_SIZE * i;
1099                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1100                                            GPMC_BCH_SIZE * i;
1101                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1102                                            i * GPMC_BCH_SIZE;
1103                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1104                                            i * GPMC_BCH_SIZE;
1105                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1106                                            i * GPMC_BCH_SIZE;
1107         }
1108 }
1109
1110 static bool gpmc_nand_writebuffer_empty(void)
1111 {
1112         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1113                 return true;
1114
1115         return false;
1116 }
1117
1118 static struct gpmc_nand_ops nand_ops = {
1119         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1120 };
1121
1122 /**
1123  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1124  * @regs: the GPMC NAND register map exclusive for NAND use.
1125  * @cs: GPMC chip select number on which the NAND sits. The
1126  *      register map returned will be specific to this chip select.
1127  *
1128  * Returns NULL on error e.g. invalid cs.
1129  */
1130 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1131 {
1132         if (cs >= gpmc_cs_num)
1133                 return NULL;
1134
1135         gpmc_update_nand_reg(reg, cs);
1136
1137         return &nand_ops;
1138 }
1139 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1140
1141 int gpmc_get_client_irq(unsigned irq_config)
1142 {
1143         if (!gpmc_irq_domain) {
1144                 pr_warn("%s called before GPMC IRQ domain available\n",
1145                         __func__);
1146                 return 0;
1147         }
1148
1149         if (irq_config >= GPMC_NR_IRQ)
1150                 return 0;
1151
1152         return irq_create_mapping(gpmc_irq_domain, irq_config);
1153 }
1154
1155 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1156 {
1157         u32 regval;
1158
1159         regval = gpmc_read_reg(GPMC_IRQENABLE);
1160         if (endis)
1161                 regval |= BIT(hwirq);
1162         else
1163                 regval &= ~BIT(hwirq);
1164         gpmc_write_reg(GPMC_IRQENABLE, regval);
1165
1166         return 0;
1167 }
1168
1169 static void gpmc_irq_disable(struct irq_data *p)
1170 {
1171         gpmc_irq_endis(p->hwirq, false);
1172 }
1173
1174 static void gpmc_irq_enable(struct irq_data *p)
1175 {
1176         gpmc_irq_endis(p->hwirq, true);
1177 }
1178
1179 static void gpmc_irq_noop(struct irq_data *data) { }
1180
1181 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
1182
1183 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1184                         irq_hw_number_t hw)
1185 {
1186         struct gpmc_device *gpmc = d->host_data;
1187
1188         irq_set_chip_data(virq, gpmc);
1189         irq_set_chip_and_handler(virq, &gpmc->irq_chip, handle_simple_irq);
1190         irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1191
1192         return 0;
1193 }
1194
1195 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1196         .map    = gpmc_irq_map,
1197         .xlate  = irq_domain_xlate_twocell,
1198 };
1199
1200 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1201 {
1202         int hwirq, virq;
1203         u32 regval;
1204         struct gpmc_device *gpmc = data;
1205
1206         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1207
1208         if (!regval)
1209                 return IRQ_NONE;
1210
1211         for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++) {
1212                 if (regval & BIT(hwirq)) {
1213                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1214                         if (!virq) {
1215                                 dev_warn(gpmc->dev,
1216                                          "spurious irq detected hwirq %d, virq %d\n",
1217                                          hwirq, virq);
1218                         }
1219
1220                         generic_handle_irq(virq);
1221                 }
1222         }
1223
1224         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1225
1226         return IRQ_HANDLED;
1227 }
1228
1229 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1230 {
1231         u32 regval;
1232         int rc;
1233
1234         /* Disable interrupts */
1235         gpmc_write_reg(GPMC_IRQENABLE, 0);
1236
1237         /* clear interrupts */
1238         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1239         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1240
1241         gpmc->irq_chip.name = "gpmc";
1242         gpmc->irq_chip.irq_startup = gpmc_irq_noop_ret;
1243         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1244         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1245         gpmc->irq_chip.irq_shutdown = gpmc_irq_noop;
1246         gpmc->irq_chip.irq_ack = gpmc_irq_noop;
1247         gpmc->irq_chip.irq_mask = gpmc_irq_noop;
1248         gpmc->irq_chip.irq_unmask = gpmc_irq_noop;
1249
1250         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1251                                                 GPMC_NR_IRQ,
1252                                                 &gpmc_irq_domain_ops,
1253                                                 gpmc);
1254         if (!gpmc_irq_domain) {
1255                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1256                 return -ENODEV;
1257         }
1258
1259         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1260         if (rc) {
1261                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1262                         gpmc->irq, rc);
1263                 irq_domain_remove(gpmc_irq_domain);
1264                 gpmc_irq_domain = NULL;
1265         }
1266
1267         return rc;
1268 }
1269
1270 static int gpmc_free_irq(struct gpmc_device *gpmc)
1271 {
1272         int hwirq;
1273
1274         free_irq(gpmc->irq, gpmc);
1275
1276         for (hwirq = 0; hwirq < GPMC_NR_IRQ; hwirq++)
1277                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1278
1279         irq_domain_remove(gpmc_irq_domain);
1280         gpmc_irq_domain = NULL;
1281
1282         return 0;
1283 }
1284
1285 static void gpmc_mem_exit(void)
1286 {
1287         int cs;
1288
1289         for (cs = 0; cs < gpmc_cs_num; cs++) {
1290                 if (!gpmc_cs_mem_enabled(cs))
1291                         continue;
1292                 gpmc_cs_delete_mem(cs);
1293         }
1294
1295 }
1296
1297 static void gpmc_mem_init(void)
1298 {
1299         int cs;
1300
1301         /*
1302          * The first 1MB of GPMC address space is typically mapped to
1303          * the internal ROM. Never allocate the first page, to
1304          * facilitate bug detection; even if we didn't boot from ROM.
1305          */
1306         gpmc_mem_root.start = SZ_1M;
1307         gpmc_mem_root.end = GPMC_MEM_END;
1308
1309         /* Reserve all regions that has been set up by bootloader */
1310         for (cs = 0; cs < gpmc_cs_num; cs++) {
1311                 u32 base, size;
1312
1313                 if (!gpmc_cs_mem_enabled(cs))
1314                         continue;
1315                 gpmc_cs_get_memconf(cs, &base, &size);
1316                 if (gpmc_cs_insert_mem(cs, base, size)) {
1317                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1318                                 __func__, cs, base, base + size);
1319                         gpmc_cs_disable_mem(cs);
1320                 }
1321         }
1322 }
1323
1324 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1325 {
1326         u32 temp;
1327         int div;
1328
1329         div = gpmc_calc_divider(sync_clk);
1330         temp = gpmc_ps_to_ticks(time_ps);
1331         temp = (temp + div - 1) / div;
1332         return gpmc_ticks_to_ps(temp * div);
1333 }
1334
1335 /* XXX: can the cycles be avoided ? */
1336 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1337                                        struct gpmc_device_timings *dev_t,
1338                                        bool mux)
1339 {
1340         u32 temp;
1341
1342         /* adv_rd_off */
1343         temp = dev_t->t_avdp_r;
1344         /* XXX: mux check required ? */
1345         if (mux) {
1346                 /* XXX: t_avdp not to be required for sync, only added for tusb
1347                  * this indirectly necessitates requirement of t_avdp_r and
1348                  * t_avdp_w instead of having a single t_avdp
1349                  */
1350                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1351                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1352         }
1353         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1354
1355         /* oe_on */
1356         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1357         if (mux) {
1358                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1359                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1360                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1361         }
1362         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1363
1364         /* access */
1365         /* XXX: any scope for improvement ?, by combining oe_on
1366          * and clk_activation, need to check whether
1367          * access = clk_activation + round to sync clk ?
1368          */
1369         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1370         temp += gpmc_t->clk_activation;
1371         if (dev_t->cyc_oe)
1372                 temp = max_t(u32, temp, gpmc_t->oe_on +
1373                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1374         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1375
1376         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1377         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1378
1379         /* rd_cycle */
1380         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1381         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1382                                                         gpmc_t->access;
1383         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1384         if (dev_t->t_ce_rdyz)
1385                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1386         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1387
1388         return 0;
1389 }
1390
1391 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1392                                         struct gpmc_device_timings *dev_t,
1393                                         bool mux)
1394 {
1395         u32 temp;
1396
1397         /* adv_wr_off */
1398         temp = dev_t->t_avdp_w;
1399         if (mux) {
1400                 temp = max_t(u32, temp,
1401                         gpmc_t->clk_activation + dev_t->t_avdh);
1402                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1403         }
1404         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1405
1406         /* wr_data_mux_bus */
1407         temp = max_t(u32, dev_t->t_weasu,
1408                         gpmc_t->clk_activation + dev_t->t_rdyo);
1409         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1410          * and in that case remember to handle we_on properly
1411          */
1412         if (mux) {
1413                 temp = max_t(u32, temp,
1414                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1415                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1416                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1417         }
1418         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1419
1420         /* we_on */
1421         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1422                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1423         else
1424                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1425
1426         /* wr_access */
1427         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1428         gpmc_t->wr_access = gpmc_t->access;
1429
1430         /* we_off */
1431         temp = gpmc_t->we_on + dev_t->t_wpl;
1432         temp = max_t(u32, temp,
1433                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1434         temp = max_t(u32, temp,
1435                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1436         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1437
1438         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1439                                                         dev_t->t_wph);
1440
1441         /* wr_cycle */
1442         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1443         temp += gpmc_t->wr_access;
1444         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1445         if (dev_t->t_ce_rdyz)
1446                 temp = max_t(u32, temp,
1447                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1448         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1449
1450         return 0;
1451 }
1452
1453 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1454                                         struct gpmc_device_timings *dev_t,
1455                                         bool mux)
1456 {
1457         u32 temp;
1458
1459         /* adv_rd_off */
1460         temp = dev_t->t_avdp_r;
1461         if (mux)
1462                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1463         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1464
1465         /* oe_on */
1466         temp = dev_t->t_oeasu;
1467         if (mux)
1468                 temp = max_t(u32, temp,
1469                         gpmc_t->adv_rd_off + dev_t->t_aavdh);
1470         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1471
1472         /* access */
1473         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1474                                 gpmc_t->oe_on + dev_t->t_oe);
1475         temp = max_t(u32, temp,
1476                                 gpmc_t->cs_on + dev_t->t_ce);
1477         temp = max_t(u32, temp,
1478                                 gpmc_t->adv_on + dev_t->t_aa);
1479         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1480
1481         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1482         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1483
1484         /* rd_cycle */
1485         temp = max_t(u32, dev_t->t_rd_cycle,
1486                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1487         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1488         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1489
1490         return 0;
1491 }
1492
1493 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1494                                          struct gpmc_device_timings *dev_t,
1495                                          bool mux)
1496 {
1497         u32 temp;
1498
1499         /* adv_wr_off */
1500         temp = dev_t->t_avdp_w;
1501         if (mux)
1502                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1503         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1504
1505         /* wr_data_mux_bus */
1506         temp = dev_t->t_weasu;
1507         if (mux) {
1508                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1509                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1510                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1511         }
1512         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1513
1514         /* we_on */
1515         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1516                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1517         else
1518                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1519
1520         /* we_off */
1521         temp = gpmc_t->we_on + dev_t->t_wpl;
1522         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1523
1524         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1525                                                         dev_t->t_wph);
1526
1527         /* wr_cycle */
1528         temp = max_t(u32, dev_t->t_wr_cycle,
1529                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1530         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1531
1532         return 0;
1533 }
1534
1535 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1536                         struct gpmc_device_timings *dev_t)
1537 {
1538         u32 temp;
1539
1540         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1541                                                 gpmc_get_fclk_period();
1542
1543         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1544                                         dev_t->t_bacc,
1545                                         gpmc_t->sync_clk);
1546
1547         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1548         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1549
1550         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1551                 return 0;
1552
1553         if (dev_t->ce_xdelay)
1554                 gpmc_t->bool_timings.cs_extra_delay = true;
1555         if (dev_t->avd_xdelay)
1556                 gpmc_t->bool_timings.adv_extra_delay = true;
1557         if (dev_t->oe_xdelay)
1558                 gpmc_t->bool_timings.oe_extra_delay = true;
1559         if (dev_t->we_xdelay)
1560                 gpmc_t->bool_timings.we_extra_delay = true;
1561
1562         return 0;
1563 }
1564
1565 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1566                                     struct gpmc_device_timings *dev_t,
1567                                     bool sync)
1568 {
1569         u32 temp;
1570
1571         /* cs_on */
1572         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1573
1574         /* adv_on */
1575         temp = dev_t->t_avdasu;
1576         if (dev_t->t_ce_avd)
1577                 temp = max_t(u32, temp,
1578                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1579         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1580
1581         if (sync)
1582                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1583
1584         return 0;
1585 }
1586
1587 /* TODO: remove this function once all peripherals are confirmed to
1588  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1589  * has to be modified to handle timings in ps instead of ns
1590 */
1591 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1592 {
1593         t->cs_on /= 1000;
1594         t->cs_rd_off /= 1000;
1595         t->cs_wr_off /= 1000;
1596         t->adv_on /= 1000;
1597         t->adv_rd_off /= 1000;
1598         t->adv_wr_off /= 1000;
1599         t->we_on /= 1000;
1600         t->we_off /= 1000;
1601         t->oe_on /= 1000;
1602         t->oe_off /= 1000;
1603         t->page_burst_access /= 1000;
1604         t->access /= 1000;
1605         t->rd_cycle /= 1000;
1606         t->wr_cycle /= 1000;
1607         t->bus_turnaround /= 1000;
1608         t->cycle2cycle_delay /= 1000;
1609         t->wait_monitoring /= 1000;
1610         t->clk_activation /= 1000;
1611         t->wr_access /= 1000;
1612         t->wr_data_mux_bus /= 1000;
1613 }
1614
1615 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1616                       struct gpmc_settings *gpmc_s,
1617                       struct gpmc_device_timings *dev_t)
1618 {
1619         bool mux = false, sync = false;
1620
1621         if (gpmc_s) {
1622                 mux = gpmc_s->mux_add_data ? true : false;
1623                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1624         }
1625
1626         memset(gpmc_t, 0, sizeof(*gpmc_t));
1627
1628         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1629
1630         if (gpmc_s && gpmc_s->sync_read)
1631                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1632         else
1633                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1634
1635         if (gpmc_s && gpmc_s->sync_write)
1636                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1637         else
1638                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1639
1640         /* TODO: remove, see function definition */
1641         gpmc_convert_ps_to_ns(gpmc_t);
1642
1643         return 0;
1644 }
1645
1646 /**
1647  * gpmc_cs_program_settings - programs non-timing related settings
1648  * @cs:         GPMC chip-select to program
1649  * @p:          pointer to GPMC settings structure
1650  *
1651  * Programs non-timing related settings for a GPMC chip-select, such as
1652  * bus-width, burst configuration, etc. Function should be called once
1653  * for each chip-select that is being used and must be called before
1654  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1655  * register will be initialised to zero by this function. Returns 0 on
1656  * success and appropriate negative error code on failure.
1657  */
1658 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1659 {
1660         u32 config1;
1661
1662         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1663                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1664                 return -EINVAL;
1665         }
1666
1667         /* Address-data multiplexing not supported for NAND devices */
1668         if (p->device_nand && p->mux_add_data) {
1669                 pr_err("%s: invalid configuration!\n", __func__);
1670                 return -EINVAL;
1671         }
1672
1673         if ((p->mux_add_data > GPMC_MUX_AD) ||
1674             ((p->mux_add_data == GPMC_MUX_AAD) &&
1675              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1676                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1677                 return -EINVAL;
1678         }
1679
1680         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1681         if (p->burst_read || p->burst_write) {
1682                 switch (p->burst_len) {
1683                 case GPMC_BURST_4:
1684                 case GPMC_BURST_8:
1685                 case GPMC_BURST_16:
1686                         break;
1687                 default:
1688                         pr_err("%s: invalid page/burst-length (%d)\n",
1689                                __func__, p->burst_len);
1690                         return -EINVAL;
1691                 }
1692         }
1693
1694         if (p->wait_pin > gpmc_nr_waitpins) {
1695                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1696                 return -EINVAL;
1697         }
1698
1699         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1700
1701         if (p->sync_read)
1702                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1703         if (p->sync_write)
1704                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1705         if (p->wait_on_read)
1706                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1707         if (p->wait_on_write)
1708                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1709         if (p->wait_on_read || p->wait_on_write)
1710                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1711         if (p->device_nand)
1712                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1713         if (p->mux_add_data)
1714                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1715         if (p->burst_read)
1716                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1717         if (p->burst_write)
1718                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1719         if (p->burst_read || p->burst_write) {
1720                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1721                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1722         }
1723
1724         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1725
1726         return 0;
1727 }
1728
1729 #ifdef CONFIG_OF
1730 static const struct of_device_id gpmc_dt_ids[] = {
1731         { .compatible = "ti,omap2420-gpmc" },
1732         { .compatible = "ti,omap2430-gpmc" },
1733         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1734         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1735         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1736         { }
1737 };
1738 MODULE_DEVICE_TABLE(of, gpmc_dt_ids);
1739
1740 /**
1741  * gpmc_read_settings_dt - read gpmc settings from device-tree
1742  * @np:         pointer to device-tree node for a gpmc child device
1743  * @p:          pointer to gpmc settings structure
1744  *
1745  * Reads the GPMC settings for a GPMC child device from device-tree and
1746  * stores them in the GPMC settings structure passed. The GPMC settings
1747  * structure is initialised to zero by this function and so any
1748  * previously stored settings will be cleared.
1749  */
1750 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1751 {
1752         memset(p, 0, sizeof(struct gpmc_settings));
1753
1754         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1755         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1756         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1757         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1758
1759         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1760                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1761                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1762                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1763                 if (!p->burst_read && !p->burst_write)
1764                         pr_warn("%s: page/burst-length set but not used!\n",
1765                                 __func__);
1766         }
1767
1768         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1769                 p->wait_on_read = of_property_read_bool(np,
1770                                                         "gpmc,wait-on-read");
1771                 p->wait_on_write = of_property_read_bool(np,
1772                                                          "gpmc,wait-on-write");
1773                 if (!p->wait_on_read && !p->wait_on_write)
1774                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1775                                  __func__);
1776         }
1777 }
1778
1779 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1780                                                 struct gpmc_timings *gpmc_t)
1781 {
1782         struct gpmc_bool_timings *p;
1783
1784         if (!np || !gpmc_t)
1785                 return;
1786
1787         memset(gpmc_t, 0, sizeof(*gpmc_t));
1788
1789         /* minimum clock period for syncronous mode */
1790         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1791
1792         /* chip select timtings */
1793         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1794         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1795         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1796
1797         /* ADV signal timings */
1798         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1799         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1800         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1801         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1802                              &gpmc_t->adv_aad_mux_on);
1803         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1804                              &gpmc_t->adv_aad_mux_rd_off);
1805         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1806                              &gpmc_t->adv_aad_mux_wr_off);
1807
1808         /* WE signal timings */
1809         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1810         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1811
1812         /* OE signal timings */
1813         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1814         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1815         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1816                              &gpmc_t->oe_aad_mux_on);
1817         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1818                              &gpmc_t->oe_aad_mux_off);
1819
1820         /* access and cycle timings */
1821         of_property_read_u32(np, "gpmc,page-burst-access-ns",
1822                              &gpmc_t->page_burst_access);
1823         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1824         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1825         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1826         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1827                              &gpmc_t->bus_turnaround);
1828         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1829                              &gpmc_t->cycle2cycle_delay);
1830         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
1831                              &gpmc_t->wait_monitoring);
1832         of_property_read_u32(np, "gpmc,clk-activation-ns",
1833                              &gpmc_t->clk_activation);
1834
1835         /* only applicable to OMAP3+ */
1836         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
1837         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
1838                              &gpmc_t->wr_data_mux_bus);
1839
1840         /* bool timing parameters */
1841         p = &gpmc_t->bool_timings;
1842
1843         p->cycle2cyclediffcsen =
1844                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
1845         p->cycle2cyclesamecsen =
1846                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
1847         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
1848         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
1849         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
1850         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
1851         p->time_para_granularity =
1852                 of_property_read_bool(np, "gpmc,time-para-granularity");
1853 }
1854
1855 #if IS_ENABLED(CONFIG_MTD_NAND)
1856
1857 static const char * const nand_xfer_types[] = {
1858         [NAND_OMAP_PREFETCH_POLLED]             = "prefetch-polled",
1859         [NAND_OMAP_POLLED]                      = "polled",
1860         [NAND_OMAP_PREFETCH_DMA]                = "prefetch-dma",
1861         [NAND_OMAP_PREFETCH_IRQ]                = "prefetch-irq",
1862 };
1863
1864 static int gpmc_probe_nand_child(struct platform_device *pdev,
1865                                  struct device_node *child)
1866 {
1867         u32 val;
1868         const char *s;
1869         struct gpmc_timings gpmc_t;
1870         struct omap_nand_platform_data *gpmc_nand_data;
1871
1872         if (of_property_read_u32(child, "reg", &val) < 0) {
1873                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1874                         child->full_name);
1875                 return -ENODEV;
1876         }
1877
1878         gpmc_nand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_nand_data),
1879                                       GFP_KERNEL);
1880         if (!gpmc_nand_data)
1881                 return -ENOMEM;
1882
1883         gpmc_nand_data->cs = val;
1884         gpmc_nand_data->of_node = child;
1885
1886         /* Detect availability of ELM module */
1887         gpmc_nand_data->elm_of_node = of_parse_phandle(child, "ti,elm-id", 0);
1888         if (gpmc_nand_data->elm_of_node == NULL)
1889                 gpmc_nand_data->elm_of_node =
1890                                         of_parse_phandle(child, "elm_id", 0);
1891
1892         /* select ecc-scheme for NAND */
1893         if (of_property_read_string(child, "ti,nand-ecc-opt", &s)) {
1894                 pr_err("%s: ti,nand-ecc-opt not found\n", __func__);
1895                 return -ENODEV;
1896         }
1897
1898         if (!strcmp(s, "sw"))
1899                 gpmc_nand_data->ecc_opt = OMAP_ECC_HAM1_CODE_SW;
1900         else if (!strcmp(s, "ham1") ||
1901                  !strcmp(s, "hw") || !strcmp(s, "hw-romcode"))
1902                 gpmc_nand_data->ecc_opt =
1903                                 OMAP_ECC_HAM1_CODE_HW;
1904         else if (!strcmp(s, "bch4"))
1905                 if (gpmc_nand_data->elm_of_node)
1906                         gpmc_nand_data->ecc_opt =
1907                                 OMAP_ECC_BCH4_CODE_HW;
1908                 else
1909                         gpmc_nand_data->ecc_opt =
1910                                 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW;
1911         else if (!strcmp(s, "bch8"))
1912                 if (gpmc_nand_data->elm_of_node)
1913                         gpmc_nand_data->ecc_opt =
1914                                 OMAP_ECC_BCH8_CODE_HW;
1915                 else
1916                         gpmc_nand_data->ecc_opt =
1917                                 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW;
1918         else if (!strcmp(s, "bch16"))
1919                 if (gpmc_nand_data->elm_of_node)
1920                         gpmc_nand_data->ecc_opt =
1921                                 OMAP_ECC_BCH16_CODE_HW;
1922                 else
1923                         pr_err("%s: BCH16 requires ELM support\n", __func__);
1924         else
1925                 pr_err("%s: ti,nand-ecc-opt invalid value\n", __func__);
1926
1927         /* select data transfer mode for NAND controller */
1928         if (!of_property_read_string(child, "ti,nand-xfer-type", &s))
1929                 for (val = 0; val < ARRAY_SIZE(nand_xfer_types); val++)
1930                         if (!strcasecmp(s, nand_xfer_types[val])) {
1931                                 gpmc_nand_data->xfer_type = val;
1932                                 break;
1933                         }
1934
1935         gpmc_nand_data->flash_bbt = of_get_nand_on_flash_bbt(child);
1936
1937         val = of_get_nand_bus_width(child);
1938         if (val == 16)
1939                 gpmc_nand_data->devsize = NAND_BUSWIDTH_16;
1940
1941         gpmc_read_timings_dt(child, &gpmc_t);
1942         gpmc_nand_init(gpmc_nand_data, &gpmc_t);
1943
1944         return 0;
1945 }
1946 #else
1947 static int gpmc_probe_nand_child(struct platform_device *pdev,
1948                                  struct device_node *child)
1949 {
1950         return 0;
1951 }
1952 #endif
1953
1954 #if IS_ENABLED(CONFIG_MTD_ONENAND)
1955 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1956                                  struct device_node *child)
1957 {
1958         u32 val;
1959         struct omap_onenand_platform_data *gpmc_onenand_data;
1960
1961         if (of_property_read_u32(child, "reg", &val) < 0) {
1962                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
1963                         child->full_name);
1964                 return -ENODEV;
1965         }
1966
1967         gpmc_onenand_data = devm_kzalloc(&pdev->dev, sizeof(*gpmc_onenand_data),
1968                                          GFP_KERNEL);
1969         if (!gpmc_onenand_data)
1970                 return -ENOMEM;
1971
1972         gpmc_onenand_data->cs = val;
1973         gpmc_onenand_data->of_node = child;
1974         gpmc_onenand_data->dma_channel = -1;
1975
1976         if (!of_property_read_u32(child, "dma-channel", &val))
1977                 gpmc_onenand_data->dma_channel = val;
1978
1979         gpmc_onenand_init(gpmc_onenand_data);
1980
1981         return 0;
1982 }
1983 #else
1984 static int gpmc_probe_onenand_child(struct platform_device *pdev,
1985                                     struct device_node *child)
1986 {
1987         return 0;
1988 }
1989 #endif
1990
1991 /**
1992  * gpmc_probe_generic_child - configures the gpmc for a child device
1993  * @pdev:       pointer to gpmc platform device
1994  * @child:      pointer to device-tree node for child device
1995  *
1996  * Allocates and configures a GPMC chip-select for a child device.
1997  * Returns 0 on success and appropriate negative error code on failure.
1998  */
1999 static int gpmc_probe_generic_child(struct platform_device *pdev,
2000                                 struct device_node *child)
2001 {
2002         struct gpmc_settings gpmc_s;
2003         struct gpmc_timings gpmc_t;
2004         struct resource res;
2005         unsigned long base;
2006         const char *name;
2007         int ret, cs;
2008         u32 val;
2009
2010         if (of_property_read_u32(child, "reg", &cs) < 0) {
2011                 dev_err(&pdev->dev, "%s has no 'reg' property\n",
2012                         child->full_name);
2013                 return -ENODEV;
2014         }
2015
2016         if (of_address_to_resource(child, 0, &res) < 0) {
2017                 dev_err(&pdev->dev, "%s has malformed 'reg' property\n",
2018                         child->full_name);
2019                 return -ENODEV;
2020         }
2021
2022         /*
2023          * Check if we have multiple instances of the same device
2024          * on a single chip select. If so, use the already initialized
2025          * timings.
2026          */
2027         name = gpmc_cs_get_name(cs);
2028         if (name && child->name && of_node_cmp(child->name, name) == 0)
2029                         goto no_timings;
2030
2031         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2032         if (ret < 0) {
2033                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2034                 return ret;
2035         }
2036         gpmc_cs_set_name(cs, child->name);
2037
2038         gpmc_read_settings_dt(child, &gpmc_s);
2039         gpmc_read_timings_dt(child, &gpmc_t);
2040
2041         /*
2042          * For some GPMC devices we still need to rely on the bootloader
2043          * timings because the devices can be connected via FPGA.
2044          * REVISIT: Add timing support from slls644g.pdf.
2045          */
2046         if (!gpmc_t.cs_rd_off) {
2047                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2048                         cs);
2049                 gpmc_cs_show_timings(cs,
2050                                      "please add GPMC bootloader timings to .dts");
2051                 goto no_timings;
2052         }
2053
2054         /* CS must be disabled while making changes to gpmc configuration */
2055         gpmc_cs_disable_mem(cs);
2056
2057         /*
2058          * FIXME: gpmc_cs_request() will map the CS to an arbitary
2059          * location in the gpmc address space. When booting with
2060          * device-tree we want the NOR flash to be mapped to the
2061          * location specified in the device-tree blob. So remap the
2062          * CS to this location. Once DT migration is complete should
2063          * just make gpmc_cs_request() map a specific address.
2064          */
2065         ret = gpmc_cs_remap(cs, res.start);
2066         if (ret < 0) {
2067                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2068                         cs, &res.start);
2069                 goto err;
2070         }
2071
2072         ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
2073         if (ret < 0)
2074                 goto err;
2075
2076         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2077         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2078         if (ret < 0)
2079                 goto err;
2080
2081         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2082         if (ret) {
2083                 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2084                         child->name);
2085                 goto err;
2086         }
2087
2088         /* Clear limited address i.e. enable A26-A11 */
2089         val = gpmc_read_reg(GPMC_CONFIG);
2090         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2091         gpmc_write_reg(GPMC_CONFIG, val);
2092
2093         /* Enable CS region */
2094         gpmc_cs_enable_mem(cs);
2095
2096 no_timings:
2097
2098         /* create platform device, NULL on error or when disabled */
2099         if (!of_platform_device_create(child, NULL, &pdev->dev))
2100                 goto err_child_fail;
2101
2102         /* is child a common bus? */
2103         if (of_match_node(of_default_bus_match_table, child))
2104                 /* create children and other common bus children */
2105                 if (of_platform_populate(child, of_default_bus_match_table,
2106                                          NULL, &pdev->dev))
2107                         goto err_child_fail;
2108
2109         return 0;
2110
2111 err_child_fail:
2112
2113         dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2114         ret = -ENODEV;
2115
2116 err:
2117         gpmc_cs_free(cs);
2118
2119         return ret;
2120 }
2121
2122 static int gpmc_probe_dt(struct platform_device *pdev)
2123 {
2124         int ret;
2125         struct device_node *child;
2126         const struct of_device_id *of_id =
2127                 of_match_device(gpmc_dt_ids, &pdev->dev);
2128
2129         if (!of_id)
2130                 return 0;
2131
2132         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2133                                    &gpmc_cs_num);
2134         if (ret < 0) {
2135                 pr_err("%s: number of chip-selects not defined\n", __func__);
2136                 return ret;
2137         } else if (gpmc_cs_num < 1) {
2138                 pr_err("%s: all chip-selects are disabled\n", __func__);
2139                 return -EINVAL;
2140         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2141                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2142                                          __func__, GPMC_CS_NUM);
2143                 return -EINVAL;
2144         }
2145
2146         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2147                                    &gpmc_nr_waitpins);
2148         if (ret < 0) {
2149                 pr_err("%s: number of wait pins not found!\n", __func__);
2150                 return ret;
2151         }
2152
2153         for_each_available_child_of_node(pdev->dev.of_node, child) {
2154
2155                 if (!child->name)
2156                         continue;
2157
2158                 if (of_node_cmp(child->name, "nand") == 0)
2159                         ret = gpmc_probe_nand_child(pdev, child);
2160                 else if (of_node_cmp(child->name, "onenand") == 0)
2161                         ret = gpmc_probe_onenand_child(pdev, child);
2162                 else
2163                         ret = gpmc_probe_generic_child(pdev, child);
2164         }
2165
2166         return 0;
2167 }
2168 #else
2169 static int gpmc_probe_dt(struct platform_device *pdev)
2170 {
2171         return 0;
2172 }
2173 #endif
2174
2175 static int gpmc_probe(struct platform_device *pdev)
2176 {
2177         int rc;
2178         u32 l;
2179         struct resource *res;
2180         struct gpmc_device *gpmc;
2181
2182         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2183         if (!gpmc)
2184                 return -ENOMEM;
2185
2186         gpmc->dev = &pdev->dev;
2187         platform_set_drvdata(pdev, gpmc);
2188
2189         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2190         if (res == NULL)
2191                 return -ENOENT;
2192
2193         phys_base = res->start;
2194         mem_size = resource_size(res);
2195
2196         gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2197         if (IS_ERR(gpmc_base))
2198                 return PTR_ERR(gpmc_base);
2199
2200         res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2201         if (!res) {
2202                 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2203                 return -ENOENT;
2204         }
2205
2206         gpmc->irq = res->start;
2207
2208         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2209         if (IS_ERR(gpmc_l3_clk)) {
2210                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2211                 return PTR_ERR(gpmc_l3_clk);
2212         }
2213
2214         if (!clk_get_rate(gpmc_l3_clk)) {
2215                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2216                 return -EINVAL;
2217         }
2218
2219         pm_runtime_enable(&pdev->dev);
2220         pm_runtime_get_sync(&pdev->dev);
2221
2222         l = gpmc_read_reg(GPMC_REVISION);
2223
2224         /*
2225          * FIXME: Once device-tree migration is complete the below flags
2226          * should be populated based upon the device-tree compatible
2227          * string. For now just use the IP revision. OMAP3+ devices have
2228          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2229          * devices support the addr-addr-data multiplex protocol.
2230          *
2231          * GPMC IP revisions:
2232          * - OMAP24xx                   = 2.0
2233          * - OMAP3xxx                   = 5.0
2234          * - OMAP44xx/54xx/AM335x       = 6.0
2235          */
2236         if (GPMC_REVISION_MAJOR(l) > 0x4)
2237                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2238         if (GPMC_REVISION_MAJOR(l) > 0x5)
2239                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2240         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2241                  GPMC_REVISION_MINOR(l));
2242
2243         gpmc_mem_init();
2244
2245         rc = gpmc_setup_irq(gpmc);
2246         if (rc) {
2247                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2248                 goto fail;
2249         }
2250
2251         if (!pdev->dev.of_node) {
2252                 gpmc_cs_num      = GPMC_CS_NUM;
2253                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2254         }
2255
2256         rc = gpmc_probe_dt(pdev);
2257         if (rc < 0) {
2258                 dev_err(gpmc->dev, "failed to probe DT parameters\n");
2259                 gpmc_free_irq(gpmc);
2260                 goto fail;
2261         }
2262
2263         return 0;
2264
2265 fail:
2266         pm_runtime_put_sync(&pdev->dev);
2267         return rc;
2268 }
2269
2270 static int gpmc_remove(struct platform_device *pdev)
2271 {
2272         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2273
2274         gpmc_free_irq(gpmc);
2275         gpmc_mem_exit();
2276         pm_runtime_put_sync(&pdev->dev);
2277         pm_runtime_disable(&pdev->dev);
2278
2279         return 0;
2280 }
2281
2282 #ifdef CONFIG_PM_SLEEP
2283 static int gpmc_suspend(struct device *dev)
2284 {
2285         omap3_gpmc_save_context();
2286         pm_runtime_put_sync(dev);
2287         return 0;
2288 }
2289
2290 static int gpmc_resume(struct device *dev)
2291 {
2292         pm_runtime_get_sync(dev);
2293         omap3_gpmc_restore_context();
2294         return 0;
2295 }
2296 #endif
2297
2298 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2299
2300 static struct platform_driver gpmc_driver = {
2301         .probe          = gpmc_probe,
2302         .remove         = gpmc_remove,
2303         .driver         = {
2304                 .name   = DEVICE_NAME,
2305                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2306                 .pm     = &gpmc_pm_ops,
2307         },
2308 };
2309
2310 static __init int gpmc_init(void)
2311 {
2312         return platform_driver_register(&gpmc_driver);
2313 }
2314
2315 static __exit void gpmc_exit(void)
2316 {
2317         platform_driver_unregister(&gpmc_driver);
2318
2319 }
2320
2321 postcore_initcall(gpmc_init);
2322 module_exit(gpmc_exit);
2323
2324 static struct omap3_gpmc_regs gpmc_context;
2325
2326 void omap3_gpmc_save_context(void)
2327 {
2328         int i;
2329
2330         if (!gpmc_base)
2331                 return;
2332
2333         gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2334         gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2335         gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2336         gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2337         gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2338         gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2339         gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2340         for (i = 0; i < gpmc_cs_num; i++) {
2341                 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2342                 if (gpmc_context.cs_context[i].is_valid) {
2343                         gpmc_context.cs_context[i].config1 =
2344                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2345                         gpmc_context.cs_context[i].config2 =
2346                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2347                         gpmc_context.cs_context[i].config3 =
2348                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2349                         gpmc_context.cs_context[i].config4 =
2350                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2351                         gpmc_context.cs_context[i].config5 =
2352                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2353                         gpmc_context.cs_context[i].config6 =
2354                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2355                         gpmc_context.cs_context[i].config7 =
2356                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2357                 }
2358         }
2359 }
2360
2361 void omap3_gpmc_restore_context(void)
2362 {
2363         int i;
2364
2365         if (!gpmc_base)
2366                 return;
2367
2368         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2369         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2370         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2371         gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2372         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2373         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2374         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2375         for (i = 0; i < gpmc_cs_num; i++) {
2376                 if (gpmc_context.cs_context[i].is_valid) {
2377                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2378                                 gpmc_context.cs_context[i].config1);
2379                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2380                                 gpmc_context.cs_context[i].config2);
2381                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2382                                 gpmc_context.cs_context[i].config3);
2383                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2384                                 gpmc_context.cs_context[i].config4);
2385                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2386                                 gpmc_context.cs_context[i].config5);
2387                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2388                                 gpmc_context.cs_context[i].config6);
2389                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2390                                 gpmc_context.cs_context[i].config7);
2391                 }
2392         }
2393 }