drivers/mmc/host/dw_mmc.c

   1 /*
   2  * Synopsys DesignWare Multimedia Card Interface driver
   3  *  (Based on NXP driver for lpc 31xx)
   4  *
   5  * Copyright (C) 2009 NXP Semiconductors
   6  * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/blkdev.h>
  15 #include <linux/clk.h>
  16 #include <linux/debugfs.h>
  17 #include <linux/device.h>
  18 #include <linux/dma-mapping.h>
  19 #include <linux/err.h>
  20 #include <linux/init.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/ioport.h>
  24 #include <linux/module.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/slab.h>
  29 #include <linux/stat.h>
  30 #include <linux/delay.h>
  31 #include <linux/irq.h>
  32 #include <linux/mmc/card.h>
  33 #include <linux/mmc/host.h>
  34 #include <linux/mmc/mmc.h>
  35 #include <linux/mmc/sd.h>
  36 #include <linux/mmc/sdio.h>
  37 #include <linux/bitops.h>
  38 #include <linux/regulator/consumer.h>
  39 #include <linux/of.h>
  40 #include <linux/of_gpio.h>
  41 #include <linux/mmc/slot-gpio.h>
  42
  43 #include "dw_mmc.h"
  44
  45 /* Common flag combinations */
  46 #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  47                                  SDMMC_INT_HTO | SDMMC_INT_SBE  | \
  48                                  SDMMC_INT_EBE | SDMMC_INT_HLE)
  49 #define DW_MCI_CMD_ERROR_FLAGS  (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  50                                  SDMMC_INT_RESP_ERR | SDMMC_INT_HLE)
  51 #define DW_MCI_ERROR_FLAGS      (DW_MCI_DATA_ERROR_FLAGS | \
  52                                  DW_MCI_CMD_ERROR_FLAGS)
  53 #define DW_MCI_SEND_STATUS      1
  54 #define DW_MCI_RECV_STATUS      2
  55 #define DW_MCI_DMA_THRESHOLD    16
  56
  57 #define DW_MCI_FREQ_MAX 200000000       /* unit: HZ */
  58 #define DW_MCI_FREQ_MIN 100000          /* unit: HZ */
  59
  60 #define IDMAC_INT_CLR           (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  61                                  SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  62                                  SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  63                                  SDMMC_IDMAC_INT_TI)
  64
  65 #define DESC_RING_BUF_SZ        PAGE_SIZE
  66
  67 struct idmac_desc_64addr {
  68         u32             des0;   /* Control Descriptor */
  69 #define IDMAC_OWN_CLR64(x) \
  70         !((x) & cpu_to_le32(IDMAC_DES0_OWN))
  71
  72         u32             des1;   /* Reserved */
  73
  74         u32             des2;   /*Buffer sizes */
  75 #define IDMAC_64ADDR_SET_BUFFER1_SIZE(d, s) \
  76         ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
  77          ((cpu_to_le32(s)) & cpu_to_le32(0x1fff)))
  78
  79         u32             des3;   /* Reserved */
  80
  81         u32             des4;   /* Lower 32-bits of Buffer Address Pointer 1*/
  82         u32             des5;   /* Upper 32-bits of Buffer Address Pointer 1*/
  83
  84         u32             des6;   /* Lower 32-bits of Next Descriptor Address */
  85         u32             des7;   /* Upper 32-bits of Next Descriptor Address */
  86 };
  87
  88 struct idmac_desc {
  89         __le32          des0;   /* Control Descriptor */
  90 #define IDMAC_DES0_DIC  BIT(1)
  91 #define IDMAC_DES0_LD   BIT(2)
  92 #define IDMAC_DES0_FD   BIT(3)
  93 #define IDMAC_DES0_CH   BIT(4)
  94 #define IDMAC_DES0_ER   BIT(5)
  95 #define IDMAC_DES0_CES  BIT(30)
  96 #define IDMAC_DES0_OWN  BIT(31)
  97
  98         __le32          des1;   /* Buffer sizes */
  99 #define IDMAC_SET_BUFFER1_SIZE(d, s) \
 100         ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
 101
 102         __le32          des2;   /* buffer 1 physical address */
 103
 104         __le32          des3;   /* buffer 2 physical address */
 105 };
 106
 107 /* Each descriptor can transfer up to 4KB of data in chained mode */
 108 #define DW_MCI_DESC_DATA_LENGTH 0x1000
 109
 110 #if defined(CONFIG_DEBUG_FS)
 111 static int dw_mci_req_show(struct seq_file *s, void *v)
 112 {
 113         struct dw_mci_slot *slot = s->private;
 114         struct mmc_request *mrq;
 115         struct mmc_command *cmd;
 116         struct mmc_command *stop;
 117         struct mmc_data *data;
 118
 119         /* Make sure we get a consistent snapshot */
 120         spin_lock_bh(&slot->host->lock);
 121         mrq = slot->mrq;
 122
 123         if (mrq) {
 124                 cmd = mrq->cmd;
 125                 data = mrq->data;
 126                 stop = mrq->stop;
 127
 128                 if (cmd)
 129                         seq_printf(s,
 130                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 131                                    cmd->opcode, cmd->arg, cmd->flags,
 132                                    cmd->resp[0], cmd->resp[1], cmd->resp[2],
 133                                    cmd->resp[2], cmd->error);
 134                 if (data)
 135                         seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
 136                                    data->bytes_xfered, data->blocks,
 137                                    data->blksz, data->flags, data->error);
 138                 if (stop)
 139                         seq_printf(s,
 140                                    "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
 141                                    stop->opcode, stop->arg, stop->flags,
 142                                    stop->resp[0], stop->resp[1], stop->resp[2],
 143                                    stop->resp[2], stop->error);
 144         }
 145
 146         spin_unlock_bh(&slot->host->lock);
 147
 148         return 0;
 149 }
 150
 151 static int dw_mci_req_open(struct inode *inode, struct file *file)
 152 {
 153         return single_open(file, dw_mci_req_show, inode->i_private);
 154 }
 155
 156 static const struct file_operations dw_mci_req_fops = {
 157         .owner          = THIS_MODULE,
 158         .open           = dw_mci_req_open,
 159         .read           = seq_read,
 160         .llseek         = seq_lseek,
 161         .release        = single_release,
 162 };
 163
 164 static int dw_mci_regs_show(struct seq_file *s, void *v)
 165 {
 166         struct dw_mci *host = s->private;
 167
 168         seq_printf(s, "STATUS:\t0x%08x\n", mci_readl(host, STATUS));
 169         seq_printf(s, "RINTSTS:\t0x%08x\n", mci_readl(host, RINTSTS));
 170         seq_printf(s, "CMD:\t0x%08x\n", mci_readl(host, CMD));
 171         seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL));
 172         seq_printf(s, "INTMASK:\t0x%08x\n", mci_readl(host, INTMASK));
 173         seq_printf(s, "CLKENA:\t0x%08x\n", mci_readl(host, CLKENA));
 174
 175         return 0;
 176 }
 177
 178 static int dw_mci_regs_open(struct inode *inode, struct file *file)
 179 {
 180         return single_open(file, dw_mci_regs_show, inode->i_private);
 181 }
 182
 183 static const struct file_operations dw_mci_regs_fops = {
 184         .owner          = THIS_MODULE,
 185         .open           = dw_mci_regs_open,
 186         .read           = seq_read,
 187         .llseek         = seq_lseek,
 188         .release        = single_release,
 189 };
 190
 191 static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
 192 {
 193         struct mmc_host *mmc = slot->mmc;
 194         struct dw_mci *host = slot->host;
 195         struct dentry *root;
 196         struct dentry *node;
 197
 198         root = mmc->debugfs_root;
 199         if (!root)
 200                 return;
 201
 202         node = debugfs_create_file("regs", S_IRUSR, root, host,
 203                                    &dw_mci_regs_fops);
 204         if (!node)
 205                 goto err;
 206
 207         node = debugfs_create_file("req", S_IRUSR, root, slot,
 208                                    &dw_mci_req_fops);
 209         if (!node)
 210                 goto err;
 211
 212         node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
 213         if (!node)
 214                 goto err;
 215
 216         node = debugfs_create_x32("pending_events", S_IRUSR, root,
 217                                   (u32 *)&host->pending_events);
 218         if (!node)
 219                 goto err;
 220
 221         node = debugfs_create_x32("completed_events", S_IRUSR, root,
 222                                   (u32 *)&host->completed_events);
 223         if (!node)
 224                 goto err;
 225
 226         return;
 227
 228 err:
 229         dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
 230 }
 231 #endif /* defined(CONFIG_DEBUG_FS) */
 232
 233 static bool dw_mci_ctrl_reset(struct dw_mci *host, u32 reset)
 234 {
 235         u32 ctrl;
 236
 237         ctrl = mci_readl(host, CTRL);
 238         ctrl |= reset;
 239         mci_writel(host, CTRL, ctrl);
 240
 241         /* wait till resets clear */
 242         if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl,
 243                                       !(ctrl & reset),
 244                                       1, 500 * USEC_PER_MSEC)) {
 245                 dev_err(host->dev,
 246                         "Timeout resetting block (ctrl reset %#x)\n",
 247                         ctrl & reset);
 248                 return false;
 249         }
 250
 251         return true;
 252 }
 253
 254 static void dw_mci_wait_while_busy(struct dw_mci *host, u32 cmd_flags)
 255 {
 256         u32 status;
 257
 258         /*
 259          * Databook says that before issuing a new data transfer command
 260          * we need to check to see if the card is busy.  Data transfer commands
 261          * all have SDMMC_CMD_PRV_DAT_WAIT set, so we'll key off that.
 262          *
 263          * ...also allow sending for SDMMC_CMD_VOLT_SWITCH where busy is
 264          * expected.
 265          */
 266         if ((cmd_flags & SDMMC_CMD_PRV_DAT_WAIT) &&
 267             !(cmd_flags & SDMMC_CMD_VOLT_SWITCH)) {
 268                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
 269                                               status,
 270                                               !(status & SDMMC_STATUS_BUSY),
 271                                               10, 500 * USEC_PER_MSEC))
 272                         dev_err(host->dev, "Busy; trying anyway\n");
 273         }
 274 }
 275
 276 static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
 277 {
 278         struct dw_mci *host = slot->host;
 279         unsigned int cmd_status = 0;
 280
 281         mci_writel(host, CMDARG, arg);
 282         wmb(); /* drain writebuffer */
 283         dw_mci_wait_while_busy(host, cmd);
 284         mci_writel(host, CMD, SDMMC_CMD_START | cmd);
 285
 286         if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status,
 287                                       !(cmd_status & SDMMC_CMD_START),
 288                                       1, 500 * USEC_PER_MSEC))
 289                 dev_err(&slot->mmc->class_dev,
 290                         "Timeout sending command (cmd %#x arg %#x status %#x)\n",
 291                         cmd, arg, cmd_status);
 292 }
 293
 294 static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
 295 {
 296         struct dw_mci_slot *slot = mmc_priv(mmc);
 297         struct dw_mci *host = slot->host;
 298         u32 cmdr;
 299
 300         cmd->error = -EINPROGRESS;
 301         cmdr = cmd->opcode;
 302
 303         if (cmd->opcode == MMC_STOP_TRANSMISSION ||
 304             cmd->opcode == MMC_GO_IDLE_STATE ||
 305             cmd->opcode == MMC_GO_INACTIVE_STATE ||
 306             (cmd->opcode == SD_IO_RW_DIRECT &&
 307              ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT))
 308                 cmdr |= SDMMC_CMD_STOP;
 309         else if (cmd->opcode != MMC_SEND_STATUS && cmd->data)
 310                 cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
 311
 312         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
 313                 u32 clk_en_a;
 314
 315                 /* Special bit makes CMD11 not die */
 316                 cmdr |= SDMMC_CMD_VOLT_SWITCH;
 317
 318                 /* Change state to continue to handle CMD11 weirdness */
 319                 WARN_ON(slot->host->state != STATE_SENDING_CMD);
 320                 slot->host->state = STATE_SENDING_CMD11;
 321
 322                 /*
 323                  * We need to disable low power mode (automatic clock stop)
 324                  * while doing voltage switch so we don't confuse the card,
 325                  * since stopping the clock is a specific part of the UHS
 326                  * voltage change dance.
 327                  *
 328                  * Note that low power mode (SDMMC_CLKEN_LOW_PWR) will be
 329                  * unconditionally turned back on in dw_mci_setup_bus() if it's
 330                  * ever called with a non-zero clock.  That shouldn't happen
 331                  * until the voltage change is all done.
 332                  */
 333                 clk_en_a = mci_readl(host, CLKENA);
 334                 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id);
 335                 mci_writel(host, CLKENA, clk_en_a);
 336                 mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
 337                              SDMMC_CMD_PRV_DAT_WAIT, 0);
 338         }
 339
 340         if (cmd->flags & MMC_RSP_PRESENT) {
 341                 /* We expect a response, so set this bit */
 342                 cmdr |= SDMMC_CMD_RESP_EXP;
 343                 if (cmd->flags & MMC_RSP_136)
 344                         cmdr |= SDMMC_CMD_RESP_LONG;
 345         }
 346
 347         if (cmd->flags & MMC_RSP_CRC)
 348                 cmdr |= SDMMC_CMD_RESP_CRC;
 349
 350         if (cmd->data) {
 351                 cmdr |= SDMMC_CMD_DAT_EXP;
 352                 if (cmd->data->flags & MMC_DATA_WRITE)
 353                         cmdr |= SDMMC_CMD_DAT_WR;
 354         }
 355
 356         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags))
 357                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 358
 359         return cmdr;
 360 }
 361
 362 static u32 dw_mci_prep_stop_abort(struct dw_mci *host, struct mmc_command *cmd)
 363 {
 364         struct mmc_command *stop;
 365         u32 cmdr;
 366
 367         if (!cmd->data)
 368                 return 0;
 369
 370         stop = &host->stop_abort;
 371         cmdr = cmd->opcode;
 372         memset(stop, 0, sizeof(struct mmc_command));
 373
 374         if (cmdr == MMC_READ_SINGLE_BLOCK ||
 375             cmdr == MMC_READ_MULTIPLE_BLOCK ||
 376             cmdr == MMC_WRITE_BLOCK ||
 377             cmdr == MMC_WRITE_MULTIPLE_BLOCK ||
 378             cmdr == MMC_SEND_TUNING_BLOCK ||
 379             cmdr == MMC_SEND_TUNING_BLOCK_HS200) {
 380                 stop->opcode = MMC_STOP_TRANSMISSION;
 381                 stop->arg = 0;
 382                 stop->flags = MMC_RSP_R1B | MMC_CMD_AC;
 383         } else if (cmdr == SD_IO_RW_EXTENDED) {
 384                 stop->opcode = SD_IO_RW_DIRECT;
 385                 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) |
 386                              ((cmd->arg >> 28) & 0x7);
 387                 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC;
 388         } else {
 389                 return 0;
 390         }
 391
 392         cmdr = stop->opcode | SDMMC_CMD_STOP |
 393                 SDMMC_CMD_RESP_CRC | SDMMC_CMD_RESP_EXP;
 394
 395         if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags))
 396                 cmdr |= SDMMC_CMD_USE_HOLD_REG;
 397
 398         return cmdr;
 399 }
 400
 401 static void dw_mci_start_command(struct dw_mci *host,
 402                                  struct mmc_command *cmd, u32 cmd_flags)
 403 {
 404         host->cmd = cmd;
 405         dev_vdbg(host->dev,
 406                  "start command: ARGR=0x%08x CMDR=0x%08x\n",
 407                  cmd->arg, cmd_flags);
 408
 409         mci_writel(host, CMDARG, cmd->arg);
 410         wmb(); /* drain writebuffer */
 411         dw_mci_wait_while_busy(host, cmd_flags);
 412
 413         mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
 414 }
 415
 416 static inline void send_stop_abort(struct dw_mci *host, struct mmc_data *data)
 417 {
 418         struct mmc_command *stop = &host->stop_abort;
 419
 420         dw_mci_start_command(host, stop, host->stop_cmdr);
 421 }
 422
 423 /* DMA interface functions */
 424 static void dw_mci_stop_dma(struct dw_mci *host)
 425 {
 426         if (host->using_dma) {
 427                 host->dma_ops->stop(host);
 428                 host->dma_ops->cleanup(host);
 429         }
 430
 431         /* Data transfer was stopped by the interrupt handler */
 432         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 433 }
 434
 435 static void dw_mci_dma_cleanup(struct dw_mci *host)
 436 {
 437         struct mmc_data *data = host->data;
 438
 439         if (data && data->host_cookie == COOKIE_MAPPED) {
 440                 dma_unmap_sg(host->dev,
 441                              data->sg,
 442                              data->sg_len,
 443                              mmc_get_dma_dir(data));
 444                 data->host_cookie = COOKIE_UNMAPPED;
 445         }
 446 }
 447
 448 static void dw_mci_idmac_reset(struct dw_mci *host)
 449 {
 450         u32 bmod = mci_readl(host, BMOD);
 451         /* Software reset of DMA */
 452         bmod |= SDMMC_IDMAC_SWRESET;
 453         mci_writel(host, BMOD, bmod);
 454 }
 455
 456 static void dw_mci_idmac_stop_dma(struct dw_mci *host)
 457 {
 458         u32 temp;
 459
 460         /* Disable and reset the IDMAC interface */
 461         temp = mci_readl(host, CTRL);
 462         temp &= ~SDMMC_CTRL_USE_IDMAC;
 463         temp |= SDMMC_CTRL_DMA_RESET;
 464         mci_writel(host, CTRL, temp);
 465
 466         /* Stop the IDMAC running */
 467         temp = mci_readl(host, BMOD);
 468         temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
 469         temp |= SDMMC_IDMAC_SWRESET;
 470         mci_writel(host, BMOD, temp);
 471 }
 472
 473 static void dw_mci_dmac_complete_dma(void *arg)
 474 {
 475         struct dw_mci *host = arg;
 476         struct mmc_data *data = host->data;
 477
 478         dev_vdbg(host->dev, "DMA complete\n");
 479
 480         if ((host->use_dma == TRANS_MODE_EDMAC) &&
 481             data && (data->flags & MMC_DATA_READ))
 482                 /* Invalidate cache after read */
 483                 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc),
 484                                     data->sg,
 485                                     data->sg_len,
 486                                     DMA_FROM_DEVICE);
 487
 488         host->dma_ops->cleanup(host);
 489
 490         /*
 491          * If the card was removed, data will be NULL. No point in trying to
 492          * send the stop command or waiting for NBUSY in this case.
 493          */
 494         if (data) {
 495                 set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
 496                 tasklet_schedule(&host->tasklet);
 497         }
 498 }
 499
 500 static int dw_mci_idmac_init(struct dw_mci *host)
 501 {
 502         int i;
 503
 504         if (host->dma_64bit_address == 1) {
 505                 struct idmac_desc_64addr *p;
 506                 /* Number of descriptors in the ring buffer */
 507                 host->ring_size =
 508                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc_64addr);
 509
 510                 /* Forward link the descriptor list */
 511                 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1;
 512                                                                 i++, p++) {
 513                         p->des6 = (host->sg_dma +
 514                                         (sizeof(struct idmac_desc_64addr) *
 515                                                         (i + 1))) & 0xffffffff;
 516
 517                         p->des7 = (u64)(host->sg_dma +
 518                                         (sizeof(struct idmac_desc_64addr) *
 519                                                         (i + 1))) >> 32;
 520                         /* Initialize reserved and buffer size fields to "0" */
 521                         p->des1 = 0;
 522                         p->des2 = 0;
 523                         p->des3 = 0;
 524                 }
 525
 526                 /* Set the last descriptor as the end-of-ring descriptor */
 527                 p->des6 = host->sg_dma & 0xffffffff;
 528                 p->des7 = (u64)host->sg_dma >> 32;
 529                 p->des0 = IDMAC_DES0_ER;
 530
 531         } else {
 532                 struct idmac_desc *p;
 533                 /* Number of descriptors in the ring buffer */
 534                 host->ring_size =
 535                         DESC_RING_BUF_SZ / sizeof(struct idmac_desc);
 536
 537                 /* Forward link the descriptor list */
 538                 for (i = 0, p = host->sg_cpu;
 539                      i < host->ring_size - 1;
 540                      i++, p++) {
 541                         p->des3 = cpu_to_le32(host->sg_dma +
 542                                         (sizeof(struct idmac_desc) * (i + 1)));
 543                         p->des1 = 0;
 544                 }
 545
 546                 /* Set the last descriptor as the end-of-ring descriptor */
 547                 p->des3 = cpu_to_le32(host->sg_dma);
 548                 p->des0 = cpu_to_le32(IDMAC_DES0_ER);
 549         }
 550
 551         dw_mci_idmac_reset(host);
 552
 553         if (host->dma_64bit_address == 1) {
 554                 /* Mask out interrupts - get Tx & Rx complete only */
 555                 mci_writel(host, IDSTS64, IDMAC_INT_CLR);
 556                 mci_writel(host, IDINTEN64, SDMMC_IDMAC_INT_NI |
 557                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 558
 559                 /* Set the descriptor base address */
 560                 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff);
 561                 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32);
 562
 563         } else {
 564                 /* Mask out interrupts - get Tx & Rx complete only */
 565                 mci_writel(host, IDSTS, IDMAC_INT_CLR);
 566                 mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI |
 567                                 SDMMC_IDMAC_INT_RI | SDMMC_IDMAC_INT_TI);
 568
 569                 /* Set the descriptor base address */
 570                 mci_writel(host, DBADDR, host->sg_dma);
 571         }
 572
 573         return 0;
 574 }
 575
 576 static inline int dw_mci_prepare_desc64(struct dw_mci *host,
 577                                          struct mmc_data *data,
 578                                          unsigned int sg_len)
 579 {
 580         unsigned int desc_len;
 581         struct idmac_desc_64addr *desc_first, *desc_last, *desc;
 582         u32 val;
 583         int i;
 584
 585         desc_first = desc_last = desc = host->sg_cpu;
 586
 587         for (i = 0; i < sg_len; i++) {
 588                 unsigned int length = sg_dma_len(&data->sg[i]);
 589
 590                 u64 mem_addr = sg_dma_address(&data->sg[i]);
 591
 592                 for ( ; length ; desc++) {
 593                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 594                                    length : DW_MCI_DESC_DATA_LENGTH;
 595
 596                         length -= desc_len;
 597
 598                         /*
 599                          * Wait for the former clear OWN bit operation
 600                          * of IDMAC to make sure that this descriptor
 601                          * isn't still owned by IDMAC as IDMAC's write
 602                          * ops and CPU's read ops are asynchronous.
 603                          */
 604                         if (readl_poll_timeout_atomic(&desc->des0, val,
 605                                                 !(val & IDMAC_DES0_OWN),
 606                                                 10, 100 * USEC_PER_MSEC))
 607                                 goto err_own_bit;
 608
 609                         /*
 610                          * Set the OWN bit and disable interrupts
 611                          * for this descriptor
 612                          */
 613                         desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
 614                                                 IDMAC_DES0_CH;
 615
 616                         /* Buffer length */
 617                         IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
 618
 619                         /* Physical address to DMA to/from */
 620                         desc->des4 = mem_addr & 0xffffffff;
 621                         desc->des5 = mem_addr >> 32;
 622
 623                         /* Update physical address for the next desc */
 624                         mem_addr += desc_len;
 625
 626                         /* Save pointer to the last descriptor */
 627                         desc_last = desc;
 628                 }
 629         }
 630
 631         /* Set first descriptor */
 632         desc_first->des0 |= IDMAC_DES0_FD;
 633
 634         /* Set last descriptor */
 635         desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
 636         desc_last->des0 |= IDMAC_DES0_LD;
 637
 638         return 0;
 639 err_own_bit:
 640         /* restore the descriptor chain as it's polluted */
 641         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 642         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 643         dw_mci_idmac_init(host);
 644         return -EINVAL;
 645 }
 646
 647
 648 static inline int dw_mci_prepare_desc32(struct dw_mci *host,
 649                                          struct mmc_data *data,
 650                                          unsigned int sg_len)
 651 {
 652         unsigned int desc_len;
 653         struct idmac_desc *desc_first, *desc_last, *desc;
 654         u32 val;
 655         int i;
 656
 657         desc_first = desc_last = desc = host->sg_cpu;
 658
 659         for (i = 0; i < sg_len; i++) {
 660                 unsigned int length = sg_dma_len(&data->sg[i]);
 661
 662                 u32 mem_addr = sg_dma_address(&data->sg[i]);
 663
 664                 for ( ; length ; desc++) {
 665                         desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
 666                                    length : DW_MCI_DESC_DATA_LENGTH;
 667
 668                         length -= desc_len;
 669
 670                         /*
 671                          * Wait for the former clear OWN bit operation
 672                          * of IDMAC to make sure that this descriptor
 673                          * isn't still owned by IDMAC as IDMAC's write
 674                          * ops and CPU's read ops are asynchronous.
 675                          */
 676                         if (readl_poll_timeout_atomic(&desc->des0, val,
 677                                                       IDMAC_OWN_CLR64(val),
 678                                                       10,
 679                                                       100 * USEC_PER_MSEC))
 680                                 goto err_own_bit;
 681
 682                         /*
 683                          * Set the OWN bit and disable interrupts
 684                          * for this descriptor
 685                          */
 686                         desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
 687                                                  IDMAC_DES0_DIC |
 688                                                  IDMAC_DES0_CH);
 689
 690                         /* Buffer length */
 691                         IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
 692
 693                         /* Physical address to DMA to/from */
 694                         desc->des2 = cpu_to_le32(mem_addr);
 695
 696                         /* Update physical address for the next desc */
 697                         mem_addr += desc_len;
 698
 699                         /* Save pointer to the last descriptor */
 700                         desc_last = desc;
 701                 }
 702         }
 703
 704         /* Set first descriptor */
 705         desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
 706
 707         /* Set last descriptor */
 708         desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
 709                                        IDMAC_DES0_DIC));
 710         desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
 711
 712         return 0;
 713 err_own_bit:
 714         /* restore the descriptor chain as it's polluted */
 715         dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n");
 716         memset(host->sg_cpu, 0, DESC_RING_BUF_SZ);
 717         dw_mci_idmac_init(host);
 718         return -EINVAL;
 719 }
 720
 721 static int dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
 722 {
 723         u32 temp;
 724         int ret;
 725
 726         if (host->dma_64bit_address == 1)
 727                 ret = dw_mci_prepare_desc64(host, host->data, sg_len);
 728         else
 729                 ret = dw_mci_prepare_desc32(host, host->data, sg_len);
 730
 731         if (ret)
 732                 goto out;
 733
 734         /* drain writebuffer */
 735         wmb();
 736
 737         /* Make sure to reset DMA in case we did PIO before this */
 738         dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET);
 739         dw_mci_idmac_reset(host);
 740
 741         /* Select IDMAC interface */
 742         temp = mci_readl(host, CTRL);
 743         temp |= SDMMC_CTRL_USE_IDMAC;
 744         mci_writel(host, CTRL, temp);
 745
 746         /* drain writebuffer */
 747         wmb();
 748
 749         /* Enable the IDMAC */
 750         temp = mci_readl(host, BMOD);
 751         temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
 752         mci_writel(host, BMOD, temp);
 753
 754         /* Start it running */
 755         mci_writel(host, PLDMND, 1);
 756
 757 out:
 758         return ret;
 759 }
 760
 761 static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
 762         .init = dw_mci_idmac_init,
 763         .start = dw_mci_idmac_start_dma,
 764         .stop = dw_mci_idmac_stop_dma,
 765         .complete = dw_mci_dmac_complete_dma,
 766         .cleanup = dw_mci_dma_cleanup,
 767 };
 768
 769 static void dw_mci_edmac_stop_dma(struct dw_mci *host)
 770 {
 771         dmaengine_terminate_async(host->dms->ch);
 772 }
 773
 774 static int dw_mci_edmac_start_dma(struct dw_mci *host,
 775                                             unsigned int sg_len)
 776 {
 777         struct dma_slave_config cfg;
 778         struct dma_async_tx_descriptor *desc = NULL;
 779         struct scatterlist *sgl = host->data->sg;
 780         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 781         u32 sg_elems = host->data->sg_len;
 782         u32 fifoth_val;
 783         u32 fifo_offset = host->fifo_reg - host->regs;
 784         int ret = 0;
 785
 786         /* Set external dma config: burst size, burst width */
 787         cfg.dst_addr = host->phy_regs + fifo_offset;
 788         cfg.src_addr = cfg.dst_addr;
 789         cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 790         cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 791
 792         /* Match burst msize with external dma config */
 793         fifoth_val = mci_readl(host, FIFOTH);
 794         cfg.dst_maxburst = mszs[(fifoth_val >> 28) & 0x7];
 795         cfg.src_maxburst = cfg.dst_maxburst;
 796
 797         if (host->data->flags & MMC_DATA_WRITE)
 798                 cfg.direction = DMA_MEM_TO_DEV;
 799         else
 800                 cfg.direction = DMA_DEV_TO_MEM;
 801
 802         ret = dmaengine_slave_config(host->dms->ch, &cfg);
 803         if (ret) {
 804                 dev_err(host->dev, "Failed to config edmac.\n");
 805                 return -EBUSY;
 806         }
 807
 808         desc = dmaengine_prep_slave_sg(host->dms->ch, sgl,
 809                                        sg_len, cfg.direction,
 810                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
 811         if (!desc) {
 812                 dev_err(host->dev, "Can't prepare slave sg.\n");
 813                 return -EBUSY;
 814         }
 815
 816         /* Set dw_mci_dmac_complete_dma as callback */
 817         desc->callback = dw_mci_dmac_complete_dma;
 818         desc->callback_param = (void *)host;
 819         dmaengine_submit(desc);
 820
 821         /* Flush cache before write */
 822         if (host->data->flags & MMC_DATA_WRITE)
 823                 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl,
 824                                        sg_elems, DMA_TO_DEVICE);
 825
 826         dma_async_issue_pending(host->dms->ch);
 827
 828         return 0;
 829 }
 830
 831 static int dw_mci_edmac_init(struct dw_mci *host)
 832 {
 833         /* Request external dma channel */
 834         host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL);
 835         if (!host->dms)
 836                 return -ENOMEM;
 837
 838         host->dms->ch = dma_request_slave_channel(host->dev, "rx-tx");
 839         if (!host->dms->ch) {
 840                 dev_err(host->dev, "Failed to get external DMA channel.\n");
 841                 kfree(host->dms);
 842                 host->dms = NULL;
 843                 return -ENXIO;
 844         }
 845
 846         return 0;
 847 }
 848
 849 static void dw_mci_edmac_exit(struct dw_mci *host)
 850 {
 851         if (host->dms) {
 852                 if (host->dms->ch) {
 853                         dma_release_channel(host->dms->ch);
 854                         host->dms->ch = NULL;
 855                 }
 856                 kfree(host->dms);
 857                 host->dms = NULL;
 858         }
 859 }
 860
 861 static const struct dw_mci_dma_ops dw_mci_edmac_ops = {
 862         .init = dw_mci_edmac_init,
 863         .exit = dw_mci_edmac_exit,
 864         .start = dw_mci_edmac_start_dma,
 865         .stop = dw_mci_edmac_stop_dma,
 866         .complete = dw_mci_dmac_complete_dma,
 867         .cleanup = dw_mci_dma_cleanup,
 868 };
 869
 870 static int dw_mci_pre_dma_transfer(struct dw_mci *host,
 871                                    struct mmc_data *data,
 872                                    int cookie)
 873 {
 874         struct scatterlist *sg;
 875         unsigned int i, sg_len;
 876
 877         if (data->host_cookie == COOKIE_PRE_MAPPED)
 878                 return data->sg_len;
 879
 880         /*
 881          * We don't do DMA on "complex" transfers, i.e. with
 882          * non-word-aligned buffers or lengths. Also, we don't bother
 883          * with all the DMA setup overhead for short transfers.
 884          */
 885         if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
 886                 return -EINVAL;
 887
 888         if (data->blksz & 3)
 889                 return -EINVAL;
 890
 891         for_each_sg(data->sg, sg, data->sg_len, i) {
 892                 if (sg->offset & 3 || sg->length & 3)
 893                         return -EINVAL;
 894         }
 895
 896         sg_len = dma_map_sg(host->dev,
 897                             data->sg,
 898                             data->sg_len,
 899                             mmc_get_dma_dir(data));
 900         if (sg_len == 0)
 901                 return -EINVAL;
 902
 903         data->host_cookie = cookie;
 904
 905         return sg_len;
 906 }
 907
 908 static void dw_mci_pre_req(struct mmc_host *mmc,
 909                            struct mmc_request *mrq)
 910 {
 911         struct dw_mci_slot *slot = mmc_priv(mmc);
 912         struct mmc_data *data = mrq->data;
 913
 914         if (!slot->host->use_dma || !data)
 915                 return;
 916
 917         /* This data might be unmapped at this time */
 918         data->host_cookie = COOKIE_UNMAPPED;
 919
 920         if (dw_mci_pre_dma_transfer(slot->host, mrq->data,
 921                                 COOKIE_PRE_MAPPED) < 0)
 922                 data->host_cookie = COOKIE_UNMAPPED;
 923 }
 924
 925 static void dw_mci_post_req(struct mmc_host *mmc,
 926                             struct mmc_request *mrq,
 927                             int err)
 928 {
 929         struct dw_mci_slot *slot = mmc_priv(mmc);
 930         struct mmc_data *data = mrq->data;
 931
 932         if (!slot->host->use_dma || !data)
 933                 return;
 934
 935         if (data->host_cookie != COOKIE_UNMAPPED)
 936                 dma_unmap_sg(slot->host->dev,
 937                              data->sg,
 938                              data->sg_len,
 939                              mmc_get_dma_dir(data));
 940         data->host_cookie = COOKIE_UNMAPPED;
 941 }
 942
 943 static int dw_mci_get_cd(struct mmc_host *mmc)
 944 {
 945         int present;
 946         struct dw_mci_slot *slot = mmc_priv(mmc);
 947         struct dw_mci *host = slot->host;
 948         int gpio_cd = mmc_gpio_get_cd(mmc);
 949
 950         /* Use platform get_cd function, else try onboard card detect */
 951         if (((mmc->caps & MMC_CAP_NEEDS_POLL)
 952                                 || !mmc_card_is_removable(mmc))) {
 953                 present = 1;
 954
 955                 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
 956                         if (mmc->caps & MMC_CAP_NEEDS_POLL) {
 957                                 dev_info(&mmc->class_dev,
 958                                         "card is polling.\n");
 959                         } else {
 960                                 dev_info(&mmc->class_dev,
 961                                         "card is non-removable.\n");
 962                         }
 963                         set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
 964                 }
 965
 966                 return present;
 967         } else if (gpio_cd >= 0)
 968                 present = gpio_cd;
 969         else
 970                 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
 971                         == 0 ? 1 : 0;
 972
 973         spin_lock_bh(&host->lock);
 974         if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 975                 dev_dbg(&mmc->class_dev, "card is present\n");
 976         else if (!present &&
 977                         !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags))
 978                 dev_dbg(&mmc->class_dev, "card is not present\n");
 979         spin_unlock_bh(&host->lock);
 980
 981         return present;
 982 }
 983
 984 static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
 985 {
 986         unsigned int blksz = data->blksz;
 987         const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
 988         u32 fifo_width = 1 << host->data_shift;
 989         u32 blksz_depth = blksz / fifo_width, fifoth_val;
 990         u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
 991         int idx = ARRAY_SIZE(mszs) - 1;
 992
 993         /* pio should ship this scenario */
 994         if (!host->use_dma)
 995                 return;
 996
 997         tx_wmark = (host->fifo_depth) / 2;
 998         tx_wmark_invers = host->fifo_depth - tx_wmark;
 999
1000         /*
1001          * MSIZE is '1',
1002          * if blksz is not a multiple of the FIFO width
1003          */
1004         if (blksz % fifo_width)
1005                 goto done;
1006
1007         do {
1008                 if (!((blksz_depth % mszs[idx]) ||
1009                      (tx_wmark_invers % mszs[idx]))) {
1010                         msize = idx;
1011                         rx_wmark = mszs[idx] - 1;
1012                         break;
1013                 }
1014         } while (--idx > 0);
1015         /*
1016          * If idx is '0', it won't be tried
1017          * Thus, initial values are uesed
1018          */
1019 done:
1020         fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
1021         mci_writel(host, FIFOTH, fifoth_val);
1022 }
1023
1024 static void dw_mci_ctrl_thld(struct dw_mci *host, struct mmc_data *data)
1025 {
1026         unsigned int blksz = data->blksz;
1027         u32 blksz_depth, fifo_depth;
1028         u16 thld_size;
1029         u8 enable;
1030
1031         /*
1032          * CDTHRCTL doesn't exist prior to 240A (in fact that register offset is
1033          * in the FIFO region, so we really shouldn't access it).
1034          */
1035         if (host->verid < DW_MMC_240A ||
1036                 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE))
1037                 return;
1038
1039         /*
1040          * Card write Threshold is introduced since 2.80a
1041          * It's used when HS400 mode is enabled.
1042          */
1043         if (data->flags & MMC_DATA_WRITE &&
1044                 !(host->timing != MMC_TIMING_MMC_HS400))
1045                 return;
1046
1047         if (data->flags & MMC_DATA_WRITE)
1048                 enable = SDMMC_CARD_WR_THR_EN;
1049         else
1050                 enable = SDMMC_CARD_RD_THR_EN;
1051
1052         if (host->timing != MMC_TIMING_MMC_HS200 &&
1053             host->timing != MMC_TIMING_UHS_SDR104)
1054                 goto disable;
1055
1056         blksz_depth = blksz / (1 << host->data_shift);
1057         fifo_depth = host->fifo_depth;
1058
1059         if (blksz_depth > fifo_depth)
1060                 goto disable;
1061
1062         /*
1063          * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
1064          * If (blksz_depth) <  (fifo_depth >> 1), should be thld_size = blksz
1065          * Currently just choose blksz.
1066          */
1067         thld_size = blksz;
1068         mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(thld_size, enable));
1069         return;
1070
1071 disable:
1072         mci_writel(host, CDTHRCTL, 0);
1073 }
1074
1075 static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
1076 {
1077         unsigned long irqflags;
1078         int sg_len;
1079         u32 temp;
1080
1081         host->using_dma = 0;
1082
1083         /* If we don't have a channel, we can't do DMA */
1084         if (!host->use_dma)
1085                 return -ENODEV;
1086
1087         sg_len = dw_mci_pre_dma_transfer(host, data, COOKIE_MAPPED);
1088         if (sg_len < 0) {
1089                 host->dma_ops->stop(host);
1090                 return sg_len;
1091         }
1092
1093         host->using_dma = 1;
1094
1095         if (host->use_dma == TRANS_MODE_IDMAC)
1096                 dev_vdbg(host->dev,
1097                          "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
1098                          (unsigned long)host->sg_cpu,
1099                          (unsigned long)host->sg_dma,
1100                          sg_len);
1101
1102         /*
1103          * Decide the MSIZE and RX/TX Watermark.
1104          * If current block size is same with previous size,
1105          * no need to update fifoth.
1106          */
1107         if (host->prev_blksz != data->blksz)
1108                 dw_mci_adjust_fifoth(host, data);
1109
1110         /* Enable the DMA interface */
1111         temp = mci_readl(host, CTRL);
1112         temp |= SDMMC_CTRL_DMA_ENABLE;
1113         mci_writel(host, CTRL, temp);
1114
1115         /* Disable RX/TX IRQs, let DMA handle it */
1116         spin_lock_irqsave(&host->irq_lock, irqflags);
1117         temp = mci_readl(host, INTMASK);
1118         temp  &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
1119         mci_writel(host, INTMASK, temp);
1120         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1121
1122         if (host->dma_ops->start(host, sg_len)) {
1123                 host->dma_ops->stop(host);
1124                 /* We can't do DMA, try PIO for this one */
1125                 dev_dbg(host->dev,
1126                         "%s: fall back to PIO mode for current transfer\n",
1127                         __func__);
1128                 return -ENODEV;
1129         }
1130
1131         return 0;
1132 }
1133
1134 static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
1135 {
1136         unsigned long irqflags;
1137         int flags = SG_MITER_ATOMIC;
1138         u32 temp;
1139
1140         data->error = -EINPROGRESS;
1141
1142         WARN_ON(host->data);
1143         host->sg = NULL;
1144         host->data = data;
1145
1146         if (data->flags & MMC_DATA_READ)
1147                 host->dir_status = DW_MCI_RECV_STATUS;
1148         else
1149                 host->dir_status = DW_MCI_SEND_STATUS;
1150
1151         dw_mci_ctrl_thld(host, data);
1152
1153         if (dw_mci_submit_data_dma(host, data)) {
1154                 if (host->data->flags & MMC_DATA_READ)
1155                         flags |= SG_MITER_TO_SG;
1156                 else
1157                         flags |= SG_MITER_FROM_SG;
1158
1159                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
1160                 host->sg = data->sg;
1161                 host->part_buf_start = 0;
1162                 host->part_buf_count = 0;
1163
1164                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
1165
1166                 spin_lock_irqsave(&host->irq_lock, irqflags);
1167                 temp = mci_readl(host, INTMASK);
1168                 temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
1169                 mci_writel(host, INTMASK, temp);
1170                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1171
1172                 temp = mci_readl(host, CTRL);
1173                 temp &= ~SDMMC_CTRL_DMA_ENABLE;
1174                 mci_writel(host, CTRL, temp);
1175
1176                 /*
1177                  * Use the initial fifoth_val for PIO mode. If wm_algined
1178                  * is set, we set watermark same as data size.
1179                  * If next issued data may be transfered by DMA mode,
1180                  * prev_blksz should be invalidated.
1181                  */
1182                 if (host->wm_aligned)
1183                         dw_mci_adjust_fifoth(host, data);
1184                 else
1185                         mci_writel(host, FIFOTH, host->fifoth_val);
1186                 host->prev_blksz = 0;
1187         } else {
1188                 /*
1189                  * Keep the current block size.
1190                  * It will be used to decide whether to update
1191                  * fifoth register next time.
1192                  */
1193                 host->prev_blksz = data->blksz;
1194         }
1195 }
1196
1197 static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
1198 {
1199         struct dw_mci *host = slot->host;
1200         unsigned int clock = slot->clock;
1201         u32 div;
1202         u32 clk_en_a;
1203         u32 sdmmc_cmd_bits = SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT;
1204
1205         /* We must continue to set bit 28 in CMD until the change is complete */
1206         if (host->state == STATE_WAITING_CMD11_DONE)
1207                 sdmmc_cmd_bits |= SDMMC_CMD_VOLT_SWITCH;
1208
1209         if (!clock) {
1210                 mci_writel(host, CLKENA, 0);
1211                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1212         } else if (clock != host->current_speed || force_clkinit) {
1213                 div = host->bus_hz / clock;
1214                 if (host->bus_hz % clock && host->bus_hz > clock)
1215                         /*
1216                          * move the + 1 after the divide to prevent
1217                          * over-clocking the card.
1218                          */
1219                         div += 1;
1220
1221                 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
1222
1223                 if ((clock != slot->__clk_old &&
1224                         !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) ||
1225                         force_clkinit) {
1226                         /* Silent the verbose log if calling from PM context */
1227                         if (!force_clkinit)
1228                                 dev_info(&slot->mmc->class_dev,
1229                                          "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
1230                                          slot->id, host->bus_hz, clock,
1231                                          div ? ((host->bus_hz / div) >> 1) :
1232                                          host->bus_hz, div);
1233
1234                         /*
1235                          * If card is polling, display the message only
1236                          * one time at boot time.
1237                          */
1238                         if (slot->mmc->caps & MMC_CAP_NEEDS_POLL &&
1239                                         slot->mmc->f_min == clock)
1240                                 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags);
1241                 }
1242
1243                 /* disable clock */
1244                 mci_writel(host, CLKENA, 0);
1245                 mci_writel(host, CLKSRC, 0);
1246
1247                 /* inform CIU */
1248                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1249
1250                 /* set clock to desired speed */
1251                 mci_writel(host, CLKDIV, div);
1252
1253                 /* inform CIU */
1254                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1255
1256                 /* enable clock; only low power if no SDIO */
1257                 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
1258                 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags))
1259                         clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
1260                 mci_writel(host, CLKENA, clk_en_a);
1261
1262                 /* inform CIU */
1263                 mci_send_cmd(slot, sdmmc_cmd_bits, 0);
1264
1265                 /* keep the last clock value that was requested from core */
1266                 slot->__clk_old = clock;
1267         }
1268
1269         host->current_speed = clock;
1270
1271         /* Set the current slot bus width */
1272         mci_writel(host, CTYPE, (slot->ctype << slot->id));
1273 }
1274
1275 static void __dw_mci_start_request(struct dw_mci *host,
1276                                    struct dw_mci_slot *slot,
1277                                    struct mmc_command *cmd)
1278 {
1279         struct mmc_request *mrq;
1280         struct mmc_data *data;
1281         u32 cmdflags;
1282
1283         mrq = slot->mrq;
1284
1285         host->mrq = mrq;
1286
1287         host->pending_events = 0;
1288         host->completed_events = 0;
1289         host->cmd_status = 0;
1290         host->data_status = 0;
1291         host->dir_status = 0;
1292
1293         data = cmd->data;
1294         if (data) {
1295                 mci_writel(host, TMOUT, 0xFFFFFFFF);
1296                 mci_writel(host, BYTCNT, data->blksz*data->blocks);
1297                 mci_writel(host, BLKSIZ, data->blksz);
1298         }
1299
1300         cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
1301
1302         /* this is the first command, send the initialization clock */
1303         if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
1304                 cmdflags |= SDMMC_CMD_INIT;
1305
1306         if (data) {
1307                 dw_mci_submit_data(host, data);
1308                 wmb(); /* drain writebuffer */
1309         }
1310
1311         dw_mci_start_command(host, cmd, cmdflags);
1312
1313         if (cmd->opcode == SD_SWITCH_VOLTAGE) {
1314                 unsigned long irqflags;
1315
1316                 /*
1317                  * Databook says to fail after 2ms w/ no response, but evidence
1318                  * shows that sometimes the cmd11 interrupt takes over 130ms.
1319                  * We'll set to 500ms, plus an extra jiffy just in case jiffies
1320                  * is just about to roll over.
1321                  *
1322                  * We do this whole thing under spinlock and only if the
1323                  * command hasn't already completed (indicating the the irq
1324                  * already ran so we don't want the timeout).
1325                  */
1326                 spin_lock_irqsave(&host->irq_lock, irqflags);
1327                 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events))
1328                         mod_timer(&host->cmd11_timer,
1329                                 jiffies + msecs_to_jiffies(500) + 1);
1330                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
1331         }
1332
1333         host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd);
1334 }
1335
1336 static void dw_mci_start_request(struct dw_mci *host,
1337                                  struct dw_mci_slot *slot)
1338 {
1339         struct mmc_request *mrq = slot->mrq;
1340         struct mmc_command *cmd;
1341
1342         cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
1343         __dw_mci_start_request(host, slot, cmd);
1344 }
1345
1346 /* must be called with host->lock held */
1347 static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
1348                                  struct mmc_request *mrq)
1349 {
1350         dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
1351                  host->state);
1352
1353         slot->mrq = mrq;
1354
1355         if (host->state == STATE_WAITING_CMD11_DONE) {
1356                 dev_warn(&slot->mmc->class_dev,
1357                          "Voltage change didn't complete\n");
1358                 /*
1359                  * this case isn't expected to happen, so we can
1360                  * either crash here or just try to continue on
1361                  * in the closest possible state
1362                  */
1363                 host->state = STATE_IDLE;
1364         }
1365
1366         if (host->state == STATE_IDLE) {
1367                 host->state = STATE_SENDING_CMD;
1368                 dw_mci_start_request(host, slot);
1369         } else {
1370                 list_add_tail(&slot->queue_node, &host->queue);
1371         }
1372 }
1373
1374 static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1375 {
1376         struct dw_mci_slot *slot = mmc_priv(mmc);
1377         struct dw_mci *host = slot->host;
1378
1379         WARN_ON(slot->mrq);
1380
1381         /*
1382          * The check for card presence and queueing of the request must be
1383          * atomic, otherwise the card could be removed in between and the
1384          * request wouldn't fail until another card was inserted.
1385          */
1386
1387         if (!dw_mci_get_cd(mmc)) {
1388                 mrq->cmd->error = -ENOMEDIUM;
1389                 mmc_request_done(mmc, mrq);
1390                 return;
1391         }
1392
1393         spin_lock_bh(&host->lock);
1394
1395         dw_mci_queue_request(host, slot, mrq);
1396
1397         spin_unlock_bh(&host->lock);
1398 }
1399
1400 static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1401 {
1402         struct dw_mci_slot *slot = mmc_priv(mmc);
1403         const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
1404         u32 regs;
1405         int ret;
1406
1407         switch (ios->bus_width) {
1408         case MMC_BUS_WIDTH_4:
1409                 slot->ctype = SDMMC_CTYPE_4BIT;
1410                 break;
1411         case MMC_BUS_WIDTH_8:
1412                 slot->ctype = SDMMC_CTYPE_8BIT;
1413                 break;
1414         default:
1415                 /* set default 1 bit mode */
1416                 slot->ctype = SDMMC_CTYPE_1BIT;
1417         }
1418
1419         regs = mci_readl(slot->host, UHS_REG);
1420
1421         /* DDR mode set */
1422         if (ios->timing == MMC_TIMING_MMC_DDR52 ||
1423             ios->timing == MMC_TIMING_UHS_DDR50 ||
1424             ios->timing == MMC_TIMING_MMC_HS400)
1425                 regs |= ((0x1 << slot->id) << 16);
1426         else
1427                 regs &= ~((0x1 << slot->id) << 16);
1428
1429         mci_writel(slot->host, UHS_REG, regs);
1430         slot->host->timing = ios->timing;
1431
1432         /*
1433          * Use mirror of ios->clock to prevent race with mmc
1434          * core ios update when finding the minimum.
1435          */
1436         slot->clock = ios->clock;
1437
1438         if (drv_data && drv_data->set_ios)
1439                 drv_data->set_ios(slot->host, ios);
1440
1441         switch (ios->power_mode) {
1442         case MMC_POWER_UP:
1443                 if (!IS_ERR(mmc->supply.vmmc)) {
1444                         ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1445                                         ios->vdd);
1446                         if (ret) {
1447                                 dev_err(slot->host->dev,
1448                                         "failed to enable vmmc regulator\n");
1449                                 /*return, if failed turn on vmmc*/
1450                                 return;
1451                         }
1452                 }
1453                 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
1454                 regs = mci_readl(slot->host, PWREN);
1455                 regs |= (1 << slot->id);
1456                 mci_writel(slot->host, PWREN, regs);
1457                 break;
1458         case MMC_POWER_ON:
1459                 if (!slot->host->vqmmc_enabled) {
1460                         if (!IS_ERR(mmc->supply.vqmmc)) {
1461                                 ret = regulator_enable(mmc->supply.vqmmc);
1462                                 if (ret < 0)
1463                                         dev_err(slot->host->dev,
1464                                                 "failed to enable vqmmc\n");
1465                                 else
1466                                         slot->host->vqmmc_enabled = true;
1467
1468                         } else {
1469                                 /* Keep track so we don't reset again */
1470                                 slot->host->vqmmc_enabled = true;
1471                         }
1472
1473                         /* Reset our state machine after powering on */
1474                         dw_mci_ctrl_reset(slot->host,
1475                                           SDMMC_CTRL_ALL_RESET_FLAGS);
1476                 }
1477
1478                 /* Adjust clock / bus width after power is up */
1479                 dw_mci_setup_bus(slot, false);
1480
1481                 break;
1482         case MMC_POWER_OFF:
1483                 /* Turn clock off before power goes down */
1484                 dw_mci_setup_bus(slot, false);
1485
1486                 if (!IS_ERR(mmc->supply.vmmc))
1487                         mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1488
1489                 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled)
1490                         regulator_disable(mmc->supply.vqmmc);
1491                 slot->host->vqmmc_enabled = false;
1492
1493                 regs = mci_readl(slot->host, PWREN);
1494                 regs &= ~(1 << slot->id);
1495                 mci_writel(slot->host, PWREN, regs);
1496                 break;
1497         default:
1498                 break;
1499         }
1500
1501         if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0)
1502                 slot->host->state = STATE_IDLE;
1503 }
1504
1505 static int dw_mci_card_busy(struct mmc_host *mmc)
1506 {
1507         struct dw_mci_slot *slot = mmc_priv(mmc);
1508         u32 status;
1509
1510         /*
1511          * Check the busy bit which is low when DAT[3:0]
1512          * (the data lines) are 0000
1513          */
1514         status = mci_readl(slot->host, STATUS);
1515
1516         return !!(status & SDMMC_STATUS_BUSY);
1517 }
1518
1519 static int dw_mci_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios)
1520 {
1521         struct dw_mci_slot *slot = mmc_priv(mmc);
1522         struct dw_mci *host = slot->host;
1523         const struct dw_mci_drv_data *drv_data = host->drv_data;
1524         u32 uhs;
1525         u32 v18 = SDMMC_UHS_18V << slot->id;
1526         int ret;
1527
1528         if (drv_data && drv_data->switch_voltage)
1529                 return drv_data->switch_voltage(mmc, ios);
1530
1531         /*
1532          * Program the voltage.  Note that some instances of dw_mmc may use
1533          * the UHS_REG for this.  For other instances (like exynos) the UHS_REG
1534          * does no harm but you need to set the regulator directly.  Try both.
1535          */
1536         uhs = mci_readl(host, UHS_REG);
1537         if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1538                 uhs &= ~v18;
1539         else
1540                 uhs |= v18;
1541
1542         if (!IS_ERR(mmc->supply.vqmmc)) {
1543                 ret = mmc_regulator_set_vqmmc(mmc, ios);
1544
1545                 if (ret) {
1546                         dev_dbg(&mmc->class_dev,
1547                                          "Regulator set error %d - %s V\n",
1548                                          ret, uhs & v18 ? "1.8" : "3.3");
1549                         return ret;
1550                 }
1551         }
1552         mci_writel(host, UHS_REG, uhs);
1553
1554         return 0;
1555 }
1556
1557 static int dw_mci_get_ro(struct mmc_host *mmc)
1558 {
1559         int read_only;
1560         struct dw_mci_slot *slot = mmc_priv(mmc);
1561         int gpio_ro = mmc_gpio_get_ro(mmc);
1562
1563         /* Use platform get_ro function, else try on board write protect */
1564         if (gpio_ro >= 0)
1565                 read_only = gpio_ro;
1566         else
1567                 read_only =
1568                         mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
1569
1570         dev_dbg(&mmc->class_dev, "card is %s\n",
1571                 read_only ? "read-only" : "read-write");
1572
1573         return read_only;
1574 }
1575
1576 static void dw_mci_hw_reset(struct mmc_host *mmc)
1577 {
1578         struct dw_mci_slot *slot = mmc_priv(mmc);
1579         struct dw_mci *host = slot->host;
1580         int reset;
1581
1582         if (host->use_dma == TRANS_MODE_IDMAC)
1583                 dw_mci_idmac_reset(host);
1584
1585         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_DMA_RESET |
1586                                      SDMMC_CTRL_FIFO_RESET))
1587                 return;
1588
1589         /*
1590          * According to eMMC spec, card reset procedure:
1591          * tRstW >= 1us:   RST_n pulse width
1592          * tRSCA >= 200us: RST_n to Command time
1593          * tRSTH >= 1us:   RST_n high period
1594          */
1595         reset = mci_readl(host, RST_N);
1596         reset &= ~(SDMMC_RST_HWACTIVE << slot->id);
1597         mci_writel(host, RST_N, reset);
1598         usleep_range(1, 2);
1599         reset |= SDMMC_RST_HWACTIVE << slot->id;
1600         mci_writel(host, RST_N, reset);
1601         usleep_range(200, 300);
1602 }
1603
1604 static void dw_mci_init_card(struct mmc_host *mmc, struct mmc_card *card)
1605 {
1606         struct dw_mci_slot *slot = mmc_priv(mmc);
1607         struct dw_mci *host = slot->host;
1608
1609         /*
1610          * Low power mode will stop the card clock when idle.  According to the
1611          * description of the CLKENA register we should disable low power mode
1612          * for SDIO cards if we need SDIO interrupts to work.
1613          */
1614         if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1615                 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
1616                 u32 clk_en_a_old;
1617                 u32 clk_en_a;
1618
1619                 clk_en_a_old = mci_readl(host, CLKENA);
1620
1621                 if (card->type == MMC_TYPE_SDIO ||
1622                     card->type == MMC_TYPE_SD_COMBO) {
1623                         set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1624                         clk_en_a = clk_en_a_old & ~clken_low_pwr;
1625                 } else {
1626                         clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags);
1627                         clk_en_a = clk_en_a_old | clken_low_pwr;
1628                 }
1629
1630                 if (clk_en_a != clk_en_a_old) {
1631                         mci_writel(host, CLKENA, clk_en_a);
1632                         mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
1633                                      SDMMC_CMD_PRV_DAT_WAIT, 0);
1634                 }
1635         }
1636 }
1637
1638 static void __dw_mci_enable_sdio_irq(struct dw_mci_slot *slot, int enb)
1639 {
1640         struct dw_mci *host = slot->host;
1641         unsigned long irqflags;
1642         u32 int_mask;
1643
1644         spin_lock_irqsave(&host->irq_lock, irqflags);
1645
1646         /* Enable/disable Slot Specific SDIO interrupt */
1647         int_mask = mci_readl(host, INTMASK);
1648         if (enb)
1649                 int_mask |= SDMMC_INT_SDIO(slot->sdio_id);
1650         else
1651                 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id);
1652         mci_writel(host, INTMASK, int_mask);
1653
1654         spin_unlock_irqrestore(&host->irq_lock, irqflags);
1655 }
1656
1657 static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
1658 {
1659         struct dw_mci_slot *slot = mmc_priv(mmc);
1660         struct dw_mci *host = slot->host;
1661
1662         __dw_mci_enable_sdio_irq(slot, enb);
1663
1664         /* Avoid runtime suspending the device when SDIO IRQ is enabled */
1665         if (enb)
1666                 pm_runtime_get_noresume(host->dev);
1667         else
1668                 pm_runtime_put_noidle(host->dev);
1669 }
1670
1671 static void dw_mci_ack_sdio_irq(struct mmc_host *mmc)
1672 {
1673         struct dw_mci_slot *slot = mmc_priv(mmc);
1674
1675         __dw_mci_enable_sdio_irq(slot, 1);
1676 }
1677
1678 static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1679 {
1680         struct dw_mci_slot *slot = mmc_priv(mmc);
1681         struct dw_mci *host = slot->host;
1682         const struct dw_mci_drv_data *drv_data = host->drv_data;
1683         int err = -EINVAL;
1684
1685         if (drv_data && drv_data->execute_tuning)
1686                 err = drv_data->execute_tuning(slot, opcode);
1687         return err;
1688 }
1689
1690 static int dw_mci_prepare_hs400_tuning(struct mmc_host *mmc,
1691                                        struct mmc_ios *ios)
1692 {
1693         struct dw_mci_slot *slot = mmc_priv(mmc);
1694         struct dw_mci *host = slot->host;
1695         const struct dw_mci_drv_data *drv_data = host->drv_data;
1696
1697         if (drv_data && drv_data->prepare_hs400_tuning)
1698                 return drv_data->prepare_hs400_tuning(host, ios);
1699
1700         return 0;
1701 }
1702
1703 static bool dw_mci_reset(struct dw_mci *host)
1704 {
1705         u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
1706         bool ret = false;
1707         u32 status = 0;
1708
1709         /*
1710          * Resetting generates a block interrupt, hence setting
1711          * the scatter-gather pointer to NULL.
1712          */
1713         if (host->sg) {
1714                 sg_miter_stop(&host->sg_miter);
1715                 host->sg = NULL;
1716         }
1717
1718         if (host->use_dma)
1719                 flags |= SDMMC_CTRL_DMA_RESET;
1720
1721         if (dw_mci_ctrl_reset(host, flags)) {
1722                 /*
1723                  * In all cases we clear the RAWINTS
1724                  * register to clear any interrupts.
1725                  */
1726                 mci_writel(host, RINTSTS, 0xFFFFFFFF);
1727
1728                 if (!host->use_dma) {
1729                         ret = true;
1730                         goto ciu_out;
1731                 }
1732
1733                 /* Wait for dma_req to be cleared */
1734                 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
1735                                               status,
1736                                               !(status & SDMMC_STATUS_DMA_REQ),
1737                                               1, 500 * USEC_PER_MSEC)) {
1738                         dev_err(host->dev,
1739                                 "%s: Timeout waiting for dma_req to be cleared\n",
1740                                 __func__);
1741                         goto ciu_out;
1742                 }
1743
1744                 /* when using DMA next we reset the fifo again */
1745                 if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
1746                         goto ciu_out;
1747         } else {
1748                 /* if the controller reset bit did clear, then set clock regs */
1749                 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
1750                         dev_err(host->dev,
1751                                 "%s: fifo/dma reset bits didn't clear but ciu was reset, doing clock update\n",
1752                                 __func__);
1753                         goto ciu_out;
1754                 }
1755         }
1756
1757         if (host->use_dma == TRANS_MODE_IDMAC)
1758                 /* It is also recommended that we reset and reprogram idmac */
1759                 dw_mci_idmac_reset(host);
1760
1761         ret = true;
1762
1763 ciu_out:
1764         /* After a CTRL reset we need to have CIU set clock registers  */
1765         mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0);
1766
1767         return ret;
1768 }
1769
1770 static const struct mmc_host_ops dw_mci_ops = {
1771         .request                = dw_mci_request,
1772         .pre_req                = dw_mci_pre_req,
1773         .post_req               = dw_mci_post_req,
1774         .set_ios                = dw_mci_set_ios,
1775         .get_ro                 = dw_mci_get_ro,
1776         .get_cd                 = dw_mci_get_cd,
1777         .hw_reset               = dw_mci_hw_reset,
1778         .enable_sdio_irq        = dw_mci_enable_sdio_irq,
1779         .ack_sdio_irq           = dw_mci_ack_sdio_irq,
1780         .execute_tuning         = dw_mci_execute_tuning,
1781         .card_busy              = dw_mci_card_busy,
1782         .start_signal_voltage_switch = dw_mci_switch_voltage,
1783         .init_card              = dw_mci_init_card,
1784         .prepare_hs400_tuning   = dw_mci_prepare_hs400_tuning,
1785 };
1786
1787 static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
1788         __releases(&host->lock)
1789         __acquires(&host->lock)
1790 {
1791         struct dw_mci_slot *slot;
1792         struct mmc_host *prev_mmc = host->slot->mmc;
1793
1794         WARN_ON(host->cmd || host->data);
1795
1796         host->slot->mrq = NULL;
1797         host->mrq = NULL;
1798         if (!list_empty(&host->queue)) {
1799                 slot = list_entry(host->queue.next,
1800                                   struct dw_mci_slot, queue_node);
1801                 list_del(&slot->queue_node);
1802                 dev_vdbg(host->dev, "list not empty: %s is next\n",
1803                          mmc_hostname(slot->mmc));
1804                 host->state = STATE_SENDING_CMD;
1805                 dw_mci_start_request(host, slot);
1806         } else {
1807                 dev_vdbg(host->dev, "list empty\n");
1808
1809                 if (host->state == STATE_SENDING_CMD11)
1810                         host->state = STATE_WAITING_CMD11_DONE;
1811                 else
1812                         host->state = STATE_IDLE;
1813         }
1814
1815         spin_unlock(&host->lock);
1816         mmc_request_done(prev_mmc, mrq);
1817         spin_lock(&host->lock);
1818 }
1819
1820 static int dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
1821 {
1822         u32 status = host->cmd_status;
1823
1824         host->cmd_status = 0;
1825
1826         /* Read the response from the card (up to 16 bytes) */
1827         if (cmd->flags & MMC_RSP_PRESENT) {
1828                 if (cmd->flags & MMC_RSP_136) {
1829                         cmd->resp[3] = mci_readl(host, RESP0);
1830                         cmd->resp[2] = mci_readl(host, RESP1);
1831                         cmd->resp[1] = mci_readl(host, RESP2);
1832                         cmd->resp[0] = mci_readl(host, RESP3);
1833                 } else {
1834                         cmd->resp[0] = mci_readl(host, RESP0);
1835                         cmd->resp[1] = 0;
1836                         cmd->resp[2] = 0;
1837                         cmd->resp[3] = 0;
1838                 }
1839         }
1840
1841         if (status & SDMMC_INT_RTO)
1842                 cmd->error = -ETIMEDOUT;
1843         else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
1844                 cmd->error = -EILSEQ;
1845         else if (status & SDMMC_INT_RESP_ERR)
1846                 cmd->error = -EIO;
1847         else
1848                 cmd->error = 0;
1849
1850         return cmd->error;
1851 }
1852
1853 static int dw_mci_data_complete(struct dw_mci *host, struct mmc_data *data)
1854 {
1855         u32 status = host->data_status;
1856
1857         if (status & DW_MCI_DATA_ERROR_FLAGS) {
1858                 if (status & SDMMC_INT_DRTO) {
1859                         data->error = -ETIMEDOUT;
1860                 } else if (status & SDMMC_INT_DCRC) {
1861                         data->error = -EILSEQ;
1862                 } else if (status & SDMMC_INT_EBE) {
1863                         if (host->dir_status ==
1864                                 DW_MCI_SEND_STATUS) {
1865                                 /*
1866                                  * No data CRC status was returned.
1867                                  * The number of bytes transferred
1868                                  * will be exaggerated in PIO mode.
1869                                  */
1870                                 data->bytes_xfered = 0;
1871                                 data->error = -ETIMEDOUT;
1872                         } else if (host->dir_status ==
1873                                         DW_MCI_RECV_STATUS) {
1874                                 data->error = -EILSEQ;
1875                         }
1876                 } else {
1877                         /* SDMMC_INT_SBE is included */
1878                         data->error = -EILSEQ;
1879                 }
1880
1881                 dev_dbg(host->dev, "data error, status 0x%08x\n", status);
1882
1883                 /*
1884                  * After an error, there may be data lingering
1885                  * in the FIFO
1886                  */
1887                 dw_mci_reset(host);
1888         } else {
1889                 data->bytes_xfered = data->blocks * data->blksz;
1890                 data->error = 0;
1891         }
1892
1893         return data->error;
1894 }
1895
1896 static void dw_mci_set_drto(struct dw_mci *host)
1897 {
1898         unsigned int drto_clks;
1899         unsigned int drto_ms;
1900
1901         drto_clks = mci_readl(host, TMOUT) >> 8;
1902         drto_ms = DIV_ROUND_UP(drto_clks, host->bus_hz / 1000);
1903
1904         /* add a bit spare time */
1905         drto_ms += 10;
1906
1907         mod_timer(&host->dto_timer, jiffies + msecs_to_jiffies(drto_ms));
1908 }
1909
1910 static void dw_mci_tasklet_func(unsigned long priv)
1911 {
1912         struct dw_mci *host = (struct dw_mci *)priv;
1913         struct mmc_data *data;
1914         struct mmc_command *cmd;
1915         struct mmc_request *mrq;
1916         enum dw_mci_state state;
1917         enum dw_mci_state prev_state;
1918         unsigned int err;
1919
1920         spin_lock(&host->lock);
1921
1922         state = host->state;
1923         data = host->data;
1924         mrq = host->mrq;
1925
1926         do {
1927                 prev_state = state;
1928
1929                 switch (state) {
1930                 case STATE_IDLE:
1931                 case STATE_WAITING_CMD11_DONE:
1932                         break;
1933
1934                 case STATE_SENDING_CMD11:
1935                 case STATE_SENDING_CMD:
1936                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
1937                                                 &host->pending_events))
1938                                 break;
1939
1940                         cmd = host->cmd;
1941                         host->cmd = NULL;
1942                         set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
1943                         err = dw_mci_command_complete(host, cmd);
1944                         if (cmd == mrq->sbc && !err) {
1945                                 prev_state = state = STATE_SENDING_CMD;
1946                                 __dw_mci_start_request(host, host->slot,
1947                                                        mrq->cmd);
1948                                 goto unlock;
1949                         }
1950
1951                         if (cmd->data && err) {
1952                                 /*
1953                                  * During UHS tuning sequence, sending the stop
1954                                  * command after the response CRC error would
1955                                  * throw the system into a confused state
1956                                  * causing all future tuning phases to report
1957                                  * failure.
1958                                  *
1959                                  * In such case controller will move into a data
1960                                  * transfer state after a response error or
1961                                  * response CRC error. Let's let that finish
1962                                  * before trying to send a stop, so we'll go to
1963                                  * STATE_SENDING_DATA.
1964                                  *
1965                                  * Although letting the data transfer take place
1966                                  * will waste a bit of time (we already know
1967                                  * the command was bad), it can't cause any
1968                                  * errors since it's possible it would have
1969                                  * taken place anyway if this tasklet got
1970                                  * delayed. Allowing the transfer to take place
1971                                  * avoids races and keeps things simple.
1972                                  */
1973                                 if ((err != -ETIMEDOUT) &&
1974                                     (cmd->opcode == MMC_SEND_TUNING_BLOCK)) {
1975                                         state = STATE_SENDING_DATA;
1976                                         continue;
1977                                 }
1978
1979                                 dw_mci_stop_dma(host);
1980                                 send_stop_abort(host, data);
1981                                 state = STATE_SENDING_STOP;
1982                                 break;
1983                         }
1984
1985                         if (!cmd->data || err) {
1986                                 dw_mci_request_end(host, mrq);
1987                                 goto unlock;
1988                         }
1989
1990                         prev_state = state = STATE_SENDING_DATA;
1991                         /* fall through */
1992
1993                 case STATE_SENDING_DATA:
1994                         /*
1995                          * We could get a data error and never a transfer
1996                          * complete so we'd better check for it here.
1997                          *
1998                          * Note that we don't really care if we also got a
1999                          * transfer complete; stopping the DMA and sending an
2000                          * abort won't hurt.
2001                          */
2002                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2003                                                &host->pending_events)) {
2004                                 dw_mci_stop_dma(host);
2005                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2006                                                            SDMMC_INT_EBE)))
2007                                         send_stop_abort(host, data);
2008                                 state = STATE_DATA_ERROR;
2009                                 break;
2010                         }
2011
2012                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2013                                                 &host->pending_events)) {
2014                                 /*
2015                                  * If all data-related interrupts don't come
2016                                  * within the given time in reading data state.
2017                                  */
2018                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2019                                         dw_mci_set_drto(host);
2020                                 break;
2021                         }
2022
2023                         set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
2024
2025                         /*
2026                          * Handle an EVENT_DATA_ERROR that might have shown up
2027                          * before the transfer completed.  This might not have
2028                          * been caught by the check above because the interrupt
2029                          * could have gone off between the previous check and
2030                          * the check for transfer complete.
2031                          *
2032                          * Technically this ought not be needed assuming we
2033                          * get a DATA_COMPLETE eventually (we'll notice the
2034                          * error and end the request), but it shouldn't hurt.
2035                          *
2036                          * This has the advantage of sending the stop command.
2037                          */
2038                         if (test_and_clear_bit(EVENT_DATA_ERROR,
2039                                                &host->pending_events)) {
2040                                 dw_mci_stop_dma(host);
2041                                 if (!(host->data_status & (SDMMC_INT_DRTO |
2042                                                            SDMMC_INT_EBE)))
2043                                         send_stop_abort(host, data);
2044                                 state = STATE_DATA_ERROR;
2045                                 break;
2046                         }
2047                         prev_state = state = STATE_DATA_BUSY;
2048
2049                         /* fall through */
2050
2051                 case STATE_DATA_BUSY:
2052                         if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
2053                                                 &host->pending_events)) {
2054                                 /*
2055                                  * If data error interrupt comes but data over
2056                                  * interrupt doesn't come within the given time.
2057                                  * in reading data state.
2058                                  */
2059                                 if (host->dir_status == DW_MCI_RECV_STATUS)
2060                                         dw_mci_set_drto(host);
2061                                 break;
2062                         }
2063
2064                         host->data = NULL;
2065                         set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
2066                         err = dw_mci_data_complete(host, data);
2067
2068                         if (!err) {
2069                                 if (!data->stop || mrq->sbc) {
2070                                         if (mrq->sbc && data->stop)
2071                                                 data->stop->error = 0;
2072                                         dw_mci_request_end(host, mrq);
2073                                         goto unlock;
2074                                 }
2075
2076                                 /* stop command for open-ended transfer*/
2077                                 if (data->stop)
2078                                         send_stop_abort(host, data);
2079                         } else {
2080                                 /*
2081                                  * If we don't have a command complete now we'll
2082                                  * never get one since we just reset everything;
2083                                  * better end the request.
2084                                  *
2085                                  * If we do have a command complete we'll fall
2086                                  * through to the SENDING_STOP command and
2087                                  * everything will be peachy keen.
2088                                  */
2089                                 if (!test_bit(EVENT_CMD_COMPLETE,
2090                                               &host->pending_events)) {
2091                                         host->cmd = NULL;
2092                                         dw_mci_request_end(host, mrq);
2093                                         goto unlock;
2094                                 }
2095                         }
2096
2097                         /*
2098                          * If err has non-zero,
2099                          * stop-abort command has been already issued.
2100                          */
2101                         prev_state = state = STATE_SENDING_STOP;
2102
2103                         /* fall through */
2104
2105                 case STATE_SENDING_STOP:
2106                         if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
2107                                                 &host->pending_events))
2108                                 break;
2109
2110                         /* CMD error in data command */
2111                         if (mrq->cmd->error && mrq->data)
2112                                 dw_mci_reset(host);
2113
2114                         host->cmd = NULL;
2115                         host->data = NULL;
2116
2117                         if (!mrq->sbc && mrq->stop)
2118                                 dw_mci_command_complete(host, mrq->stop);
2119                         else
2120                                 host->cmd_status = 0;
2121
2122                         dw_mci_request_end(host, mrq);
2123                         goto unlock;
2124
2125                 case STATE_DATA_ERROR:
2126                         if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
2127                                                 &host->pending_events))
2128                                 break;
2129
2130                         state = STATE_DATA_BUSY;
2131                         break;
2132                 }
2133         } while (state != prev_state);
2134
2135         host->state = state;
2136 unlock:
2137         spin_unlock(&host->lock);
2138
2139 }
2140
2141 /* push final bytes to part_buf, only use during push */
2142 static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
2143 {
2144         memcpy((void *)&host->part_buf, buf, cnt);
2145         host->part_buf_count = cnt;
2146 }
2147
2148 /* append bytes to part_buf, only use during push */
2149 static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
2150 {
2151         cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
2152         memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
2153         host->part_buf_count += cnt;
2154         return cnt;
2155 }
2156
2157 /* pull first bytes from part_buf, only use during pull */
2158 static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
2159 {
2160         cnt = min_t(int, cnt, host->part_buf_count);
2161         if (cnt) {
2162                 memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
2163                        cnt);
2164                 host->part_buf_count -= cnt;
2165                 host->part_buf_start += cnt;
2166         }
2167         return cnt;
2168 }
2169
2170 /* pull final bytes from the part_buf, assuming it's just been filled */
2171 static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
2172 {
2173         memcpy(buf, &host->part_buf, cnt);
2174         host->part_buf_start = cnt;
2175         host->part_buf_count = (1 << host->data_shift) - cnt;
2176 }
2177
2178 static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
2179 {
2180         struct mmc_data *data = host->data;
2181         int init_cnt = cnt;
2182
2183         /* try and push anything in the part_buf */
2184         if (unlikely(host->part_buf_count)) {
2185                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2186
2187                 buf += len;
2188                 cnt -= len;
2189                 if (host->part_buf_count == 2) {
2190                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2191                         host->part_buf_count = 0;
2192                 }
2193         }
2194 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2195         if (unlikely((unsigned long)buf & 0x1)) {
2196                 while (cnt >= 2) {
2197                         u16 aligned_buf[64];
2198                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2199                         int items = len >> 1;
2200                         int i;
2201                         /* memcpy from input buffer into aligned buffer */
2202                         memcpy(aligned_buf, buf, len);
2203                         buf += len;
2204                         cnt -= len;
2205                         /* push data from aligned buffer into fifo */
2206                         for (i = 0; i < items; ++i)
2207                                 mci_fifo_writew(host->fifo_reg, aligned_buf[i]);
2208                 }
2209         } else
2210 #endif
2211         {
2212                 u16 *pdata = buf;
2213
2214                 for (; cnt >= 2; cnt -= 2)
2215                         mci_fifo_writew(host->fifo_reg, *pdata++);
2216                 buf = pdata;
2217         }
2218         /* put anything remaining in the part_buf */
2219         if (cnt) {
2220                 dw_mci_set_part_bytes(host, buf, cnt);
2221                  /* Push data if we have reached the expected data length */
2222                 if ((data->bytes_xfered + init_cnt) ==
2223                     (data->blksz * data->blocks))
2224                         mci_fifo_writew(host->fifo_reg, host->part_buf16);
2225         }
2226 }
2227
2228 static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
2229 {
2230 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2231         if (unlikely((unsigned long)buf & 0x1)) {
2232                 while (cnt >= 2) {
2233                         /* pull data from fifo into aligned buffer */
2234                         u16 aligned_buf[64];
2235                         int len = min(cnt & -2, (int)sizeof(aligned_buf));
2236                         int items = len >> 1;
2237                         int i;
2238
2239                         for (i = 0; i < items; ++i)
2240                                 aligned_buf[i] = mci_fifo_readw(host->fifo_reg);
2241                         /* memcpy from aligned buffer into output buffer */
2242                         memcpy(buf, aligned_buf, len);
2243                         buf += len;
2244                         cnt -= len;
2245                 }
2246         } else
2247 #endif
2248         {
2249                 u16 *pdata = buf;
2250
2251                 for (; cnt >= 2; cnt -= 2)
2252                         *pdata++ = mci_fifo_readw(host->fifo_reg);
2253                 buf = pdata;
2254         }
2255         if (cnt) {
2256                 host->part_buf16 = mci_fifo_readw(host->fifo_reg);
2257                 dw_mci_pull_final_bytes(host, buf, cnt);
2258         }
2259 }
2260
2261 static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
2262 {
2263         struct mmc_data *data = host->data;
2264         int init_cnt = cnt;
2265
2266         /* try and push anything in the part_buf */
2267         if (unlikely(host->part_buf_count)) {
2268                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2269
2270                 buf += len;
2271                 cnt -= len;
2272                 if (host->part_buf_count == 4) {
2273                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2274                         host->part_buf_count = 0;
2275                 }
2276         }
2277 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2278         if (unlikely((unsigned long)buf & 0x3)) {
2279                 while (cnt >= 4) {
2280                         u32 aligned_buf[32];
2281                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2282                         int items = len >> 2;
2283                         int i;
2284                         /* memcpy from input buffer into aligned buffer */
2285                         memcpy(aligned_buf, buf, len);
2286                         buf += len;
2287                         cnt -= len;
2288                         /* push data from aligned buffer into fifo */
2289                         for (i = 0; i < items; ++i)
2290                                 mci_fifo_writel(host->fifo_reg, aligned_buf[i]);
2291                 }
2292         } else
2293 #endif
2294         {
2295                 u32 *pdata = buf;
2296
2297                 for (; cnt >= 4; cnt -= 4)
2298                         mci_fifo_writel(host->fifo_reg, *pdata++);
2299                 buf = pdata;
2300         }
2301         /* put anything remaining in the part_buf */
2302         if (cnt) {
2303                 dw_mci_set_part_bytes(host, buf, cnt);
2304                  /* Push data if we have reached the expected data length */
2305                 if ((data->bytes_xfered + init_cnt) ==
2306                     (data->blksz * data->blocks))
2307                         mci_fifo_writel(host->fifo_reg, host->part_buf32);
2308         }
2309 }
2310
2311 static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
2312 {
2313 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2314         if (unlikely((unsigned long)buf & 0x3)) {
2315                 while (cnt >= 4) {
2316                         /* pull data from fifo into aligned buffer */
2317                         u32 aligned_buf[32];
2318                         int len = min(cnt & -4, (int)sizeof(aligned_buf));
2319                         int items = len >> 2;
2320                         int i;
2321
2322                         for (i = 0; i < items; ++i)
2323                                 aligned_buf[i] = mci_fifo_readl(host->fifo_reg);
2324                         /* memcpy from aligned buffer into output buffer */
2325                         memcpy(buf, aligned_buf, len);
2326                         buf += len;
2327                         cnt -= len;
2328                 }
2329         } else
2330 #endif
2331         {
2332                 u32 *pdata = buf;
2333
2334                 for (; cnt >= 4; cnt -= 4)
2335                         *pdata++ = mci_fifo_readl(host->fifo_reg);
2336                 buf = pdata;
2337         }
2338         if (cnt) {
2339                 host->part_buf32 = mci_fifo_readl(host->fifo_reg);
2340                 dw_mci_pull_final_bytes(host, buf, cnt);
2341         }
2342 }
2343
2344 static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
2345 {
2346         struct mmc_data *data = host->data;
2347         int init_cnt = cnt;
2348
2349         /* try and push anything in the part_buf */
2350         if (unlikely(host->part_buf_count)) {
2351                 int len = dw_mci_push_part_bytes(host, buf, cnt);
2352
2353                 buf += len;
2354                 cnt -= len;
2355
2356                 if (host->part_buf_count == 8) {
2357                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2358                         host->part_buf_count = 0;
2359                 }
2360         }
2361 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2362         if (unlikely((unsigned long)buf & 0x7)) {
2363                 while (cnt >= 8) {
2364                         u64 aligned_buf[16];
2365                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2366                         int items = len >> 3;
2367                         int i;
2368                         /* memcpy from input buffer into aligned buffer */
2369                         memcpy(aligned_buf, buf, len);
2370                         buf += len;
2371                         cnt -= len;
2372                         /* push data from aligned buffer into fifo */
2373                         for (i = 0; i < items; ++i)
2374                                 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]);
2375                 }
2376         } else
2377 #endif
2378         {
2379                 u64 *pdata = buf;
2380
2381                 for (; cnt >= 8; cnt -= 8)
2382                         mci_fifo_writeq(host->fifo_reg, *pdata++);
2383                 buf = pdata;
2384         }
2385         /* put anything remaining in the part_buf */
2386         if (cnt) {
2387                 dw_mci_set_part_bytes(host, buf, cnt);
2388                 /* Push data if we have reached the expected data length */
2389                 if ((data->bytes_xfered + init_cnt) ==
2390                     (data->blksz * data->blocks))
2391                         mci_fifo_writeq(host->fifo_reg, host->part_buf);
2392         }
2393 }
2394
2395 static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
2396 {
2397 #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
2398         if (unlikely((unsigned long)buf & 0x7)) {
2399                 while (cnt >= 8) {
2400                         /* pull data from fifo into aligned buffer */
2401                         u64 aligned_buf[16];
2402                         int len = min(cnt & -8, (int)sizeof(aligned_buf));
2403                         int items = len >> 3;
2404                         int i;
2405
2406                         for (i = 0; i < items; ++i)
2407                                 aligned_buf[i] = mci_fifo_readq(host->fifo_reg);
2408
2409                         /* memcpy from aligned buffer into output buffer */
2410                         memcpy(buf, aligned_buf, len);
2411                         buf += len;
2412                         cnt -= len;
2413                 }
2414         } else
2415 #endif
2416         {
2417                 u64 *pdata = buf;
2418
2419                 for (; cnt >= 8; cnt -= 8)
2420                         *pdata++ = mci_fifo_readq(host->fifo_reg);
2421                 buf = pdata;
2422         }
2423         if (cnt) {
2424                 host->part_buf = mci_fifo_readq(host->fifo_reg);
2425                 dw_mci_pull_final_bytes(host, buf, cnt);
2426         }
2427 }
2428
2429 static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
2430 {
2431         int len;
2432
2433         /* get remaining partial bytes */
2434         len = dw_mci_pull_part_bytes(host, buf, cnt);
2435         if (unlikely(len == cnt))
2436                 return;
2437         buf += len;
2438         cnt -= len;
2439
2440         /* get the rest of the data */
2441         host->pull_data(host, buf, cnt);
2442 }
2443
2444 static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
2445 {
2446         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2447         void *buf;
2448         unsigned int offset;
2449         struct mmc_data *data = host->data;
2450         int shift = host->data_shift;
2451         u32 status;
2452         unsigned int len;
2453         unsigned int remain, fcnt;
2454
2455         do {
2456                 if (!sg_miter_next(sg_miter))
2457                         goto done;
2458
2459                 host->sg = sg_miter->piter.sg;
2460                 buf = sg_miter->addr;
2461                 remain = sg_miter->length;
2462                 offset = 0;
2463
2464                 do {
2465                         fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
2466                                         << shift) + host->part_buf_count;
2467                         len = min(remain, fcnt);
2468                         if (!len)
2469                                 break;
2470                         dw_mci_pull_data(host, (void *)(buf + offset), len);
2471                         data->bytes_xfered += len;
2472                         offset += len;
2473                         remain -= len;
2474                 } while (remain);
2475
2476                 sg_miter->consumed = offset;
2477                 status = mci_readl(host, MINTSTS);
2478                 mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2479         /* if the RXDR is ready read again */
2480         } while ((status & SDMMC_INT_RXDR) ||
2481                  (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
2482
2483         if (!remain) {
2484                 if (!sg_miter_next(sg_miter))
2485                         goto done;
2486                 sg_miter->consumed = 0;
2487         }
2488         sg_miter_stop(sg_miter);
2489         return;
2490
2491 done:
2492         sg_miter_stop(sg_miter);
2493         host->sg = NULL;
2494         smp_wmb(); /* drain writebuffer */
2495         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2496 }
2497
2498 static void dw_mci_write_data_pio(struct dw_mci *host)
2499 {
2500         struct sg_mapping_iter *sg_miter = &host->sg_miter;
2501         void *buf;
2502         unsigned int offset;
2503         struct mmc_data *data = host->data;
2504         int shift = host->data_shift;
2505         u32 status;
2506         unsigned int len;
2507         unsigned int fifo_depth = host->fifo_depth;
2508         unsigned int remain, fcnt;
2509
2510         do {
2511                 if (!sg_miter_next(sg_miter))
2512                         goto done;
2513
2514                 host->sg = sg_miter->piter.sg;
2515                 buf = sg_miter->addr;
2516                 remain = sg_miter->length;
2517                 offset = 0;
2518
2519                 do {
2520                         fcnt = ((fifo_depth -
2521                                  SDMMC_GET_FCNT(mci_readl(host, STATUS)))
2522                                         << shift) - host->part_buf_count;
2523                         len = min(remain, fcnt);
2524                         if (!len)
2525                                 break;
2526                         host->push_data(host, (void *)(buf + offset), len);
2527                         data->bytes_xfered += len;
2528                         offset += len;
2529                         remain -= len;
2530                 } while (remain);
2531
2532                 sg_miter->consumed = offset;
2533                 status = mci_readl(host, MINTSTS);
2534                 mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2535         } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
2536
2537         if (!remain) {
2538                 if (!sg_miter_next(sg_miter))
2539                         goto done;
2540                 sg_miter->consumed = 0;
2541         }
2542         sg_miter_stop(sg_miter);
2543         return;
2544
2545 done:
2546         sg_miter_stop(sg_miter);
2547         host->sg = NULL;
2548         smp_wmb(); /* drain writebuffer */
2549         set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
2550 }
2551
2552 static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
2553 {
2554         if (!host->cmd_status)
2555                 host->cmd_status = status;
2556
2557         smp_wmb(); /* drain writebuffer */
2558
2559         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2560         tasklet_schedule(&host->tasklet);
2561 }
2562
2563 static void dw_mci_handle_cd(struct dw_mci *host)
2564 {
2565         struct dw_mci_slot *slot = host->slot;
2566
2567         if (slot->mmc->ops->card_event)
2568                 slot->mmc->ops->card_event(slot->mmc);
2569         mmc_detect_change(slot->mmc,
2570                 msecs_to_jiffies(host->pdata->detect_delay_ms));
2571 }
2572
2573 static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
2574 {
2575         struct dw_mci *host = dev_id;
2576         u32 pending;
2577         struct dw_mci_slot *slot = host->slot;
2578
2579         pending = mci_readl(host, MINTSTS); /* read-only mask reg */
2580
2581         if (pending) {
2582                 /* Check volt switch first, since it can look like an error */
2583                 if ((host->state == STATE_SENDING_CMD11) &&
2584                     (pending & SDMMC_INT_VOLT_SWITCH)) {
2585                         unsigned long irqflags;
2586
2587                         mci_writel(host, RINTSTS, SDMMC_INT_VOLT_SWITCH);
2588                         pending &= ~SDMMC_INT_VOLT_SWITCH;
2589
2590                         /*
2591                          * Hold the lock; we know cmd11_timer can't be kicked
2592                          * off after the lock is released, so safe to delete.
2593                          */
2594                         spin_lock_irqsave(&host->irq_lock, irqflags);
2595                         dw_mci_cmd_interrupt(host, pending);
2596                         spin_unlock_irqrestore(&host->irq_lock, irqflags);
2597
2598                         del_timer(&host->cmd11_timer);
2599                 }
2600
2601                 if (pending & DW_MCI_CMD_ERROR_FLAGS) {
2602                         mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
2603                         host->cmd_status = pending;
2604                         smp_wmb(); /* drain writebuffer */
2605                         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2606                 }
2607
2608                 if (pending & DW_MCI_DATA_ERROR_FLAGS) {
2609                         /* if there is an error report DATA_ERROR */
2610                         mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
2611                         host->data_status = pending;
2612                         smp_wmb(); /* drain writebuffer */
2613                         set_bit(EVENT_DATA_ERROR, &host->pending_events);
2614                         tasklet_schedule(&host->tasklet);
2615                 }
2616
2617                 if (pending & SDMMC_INT_DATA_OVER) {
2618                         del_timer(&host->dto_timer);
2619
2620                         mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
2621                         if (!host->data_status)
2622                                 host->data_status = pending;
2623                         smp_wmb(); /* drain writebuffer */
2624                         if (host->dir_status == DW_MCI_RECV_STATUS) {
2625                                 if (host->sg != NULL)
2626                                         dw_mci_read_data_pio(host, true);
2627                         }
2628                         set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2629                         tasklet_schedule(&host->tasklet);
2630                 }
2631
2632                 if (pending & SDMMC_INT_RXDR) {
2633                         mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
2634                         if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
2635                                 dw_mci_read_data_pio(host, false);
2636                 }
2637
2638                 if (pending & SDMMC_INT_TXDR) {
2639                         mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
2640                         if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
2641                                 dw_mci_write_data_pio(host);
2642                 }
2643
2644                 if (pending & SDMMC_INT_CMD_DONE) {
2645                         mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
2646                         dw_mci_cmd_interrupt(host, pending);
2647                 }
2648
2649                 if (pending & SDMMC_INT_CD) {
2650                         mci_writel(host, RINTSTS, SDMMC_INT_CD);
2651                         dw_mci_handle_cd(host);
2652                 }
2653
2654                 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) {
2655                         mci_writel(host, RINTSTS,
2656                                    SDMMC_INT_SDIO(slot->sdio_id));
2657                         __dw_mci_enable_sdio_irq(slot, 0);
2658                         sdio_signal_irq(slot->mmc);
2659                 }
2660
2661         }
2662
2663         if (host->use_dma != TRANS_MODE_IDMAC)
2664                 return IRQ_HANDLED;
2665
2666         /* Handle IDMA interrupts */
2667         if (host->dma_64bit_address == 1) {
2668                 pending = mci_readl(host, IDSTS64);
2669                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2670                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_TI |
2671                                                         SDMMC_IDMAC_INT_RI);
2672                         mci_writel(host, IDSTS64, SDMMC_IDMAC_INT_NI);
2673                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2674                                 host->dma_ops->complete((void *)host);
2675                 }
2676         } else {
2677                 pending = mci_readl(host, IDSTS);
2678                 if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
2679                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI |
2680                                                         SDMMC_IDMAC_INT_RI);
2681                         mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
2682                         if (!test_bit(EVENT_DATA_ERROR, &host->pending_events))
2683                                 host->dma_ops->complete((void *)host);
2684                 }
2685         }
2686
2687         return IRQ_HANDLED;
2688 }
2689
2690 static int dw_mci_init_slot(struct dw_mci *host)
2691 {
2692         struct mmc_host *mmc;
2693         struct dw_mci_slot *slot;
2694         const struct dw_mci_drv_data *drv_data = host->drv_data;
2695         int ctrl_id, ret;
2696         u32 freq[2];
2697
2698         mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
2699         if (!mmc)
2700                 return -ENOMEM;
2701
2702         slot = mmc_priv(mmc);
2703         slot->id = 0;
2704         slot->sdio_id = host->sdio_id0 + slot->id;
2705         slot->mmc = mmc;
2706         slot->host = host;
2707         host->slot = slot;
2708
2709         mmc->ops = &dw_mci_ops;
2710         if (device_property_read_u32_array(host->dev, "clock-freq-min-max",
2711                                            freq, 2)) {
2712                 mmc->f_min = DW_MCI_FREQ_MIN;
2713                 mmc->f_max = DW_MCI_FREQ_MAX;
2714         } else {
2715                 dev_info(host->dev,
2716                         "'clock-freq-min-max' property was deprecated.\n");
2717                 mmc->f_min = freq[0];
2718                 mmc->f_max = freq[1];
2719         }
2720
2721         /*if there are external regulators, get them*/
2722         ret = mmc_regulator_get_supply(mmc);
2723         if (ret == -EPROBE_DEFER)
2724                 goto err_host_allocated;
2725
2726         if (!mmc->ocr_avail)
2727                 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
2728
2729         if (host->pdata->caps)
2730                 mmc->caps = host->pdata->caps;
2731
2732         /*
2733          * Support MMC_CAP_ERASE by default.
2734          * It needs to use trim/discard/erase commands.
2735          */
2736         mmc->caps |= MMC_CAP_ERASE;
2737
2738         if (host->pdata->pm_caps)
2739                 mmc->pm_caps = host->pdata->pm_caps;
2740
2741         if (host->dev->of_node) {
2742                 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
2743                 if (ctrl_id < 0)
2744                         ctrl_id = 0;
2745         } else {
2746                 ctrl_id = to_platform_device(host->dev)->id;
2747         }
2748         if (drv_data && drv_data->caps)
2749                 mmc->caps |= drv_data->caps[ctrl_id];
2750
2751         if (host->pdata->caps2)
2752                 mmc->caps2 = host->pdata->caps2;
2753
2754         ret = mmc_of_parse(mmc);
2755         if (ret)
2756                 goto err_host_allocated;
2757
2758         /* Process SDIO IRQs through the sdio_irq_work. */
2759         if (mmc->caps & MMC_CAP_SDIO_IRQ)
2760                 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2761
2762         /* Useful defaults if platform data is unset. */
2763         if (host->use_dma == TRANS_MODE_IDMAC) {
2764                 mmc->max_segs = host->ring_size;
2765                 mmc->max_blk_size = 65535;
2766                 mmc->max_seg_size = 0x1000;
2767                 mmc->max_req_size = mmc->max_seg_size * host->ring_size;
2768                 mmc->max_blk_count = mmc->max_req_size / 512;
2769         } else if (host->use_dma == TRANS_MODE_EDMAC) {
2770                 mmc->max_segs = 64;
2771                 mmc->max_blk_size = 65535;
2772                 mmc->max_blk_count = 65535;
2773                 mmc->max_req_size =
2774                                 mmc->max_blk_size * mmc->max_blk_count;
2775                 mmc->max_seg_size = mmc->max_req_size;
2776         } else {
2777                 /* TRANS_MODE_PIO */
2778                 mmc->max_segs = 64;
2779                 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */
2780                 mmc->max_blk_count = 512;
2781                 mmc->max_req_size = mmc->max_blk_size *
2782                                     mmc->max_blk_count;
2783                 mmc->max_seg_size = mmc->max_req_size;
2784         }
2785
2786         dw_mci_get_cd(mmc);
2787
2788         ret = mmc_add_host(mmc);
2789         if (ret)
2790                 goto err_host_allocated;
2791
2792 #if defined(CONFIG_DEBUG_FS)
2793         dw_mci_init_debugfs(slot);
2794 #endif
2795
2796         return 0;
2797
2798 err_host_allocated:
2799         mmc_free_host(mmc);
2800         return ret;
2801 }
2802
2803 static void dw_mci_cleanup_slot(struct dw_mci_slot *slot)
2804 {
2805         /* Debugfs stuff is cleaned up by mmc core */
2806         mmc_remove_host(slot->mmc);
2807         slot->host->slot = NULL;
2808         mmc_free_host(slot->mmc);
2809 }
2810
2811 static void dw_mci_init_dma(struct dw_mci *host)
2812 {
2813         int addr_config;
2814         struct device *dev = host->dev;
2815
2816         /*
2817         * Check tansfer mode from HCON[17:16]
2818         * Clear the ambiguous description of dw_mmc databook:
2819         * 2b'00: No DMA Interface -> Actually means using Internal DMA block
2820         * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block
2821         * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block
2822         * 2b'11: Non DW DMA Interface -> pio only
2823         * Compared to DesignWare DMA Interface, Generic DMA Interface has a
2824         * simpler request/acknowledge handshake mechanism and both of them
2825         * are regarded as external dma master for dw_mmc.
2826         */
2827         host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON));
2828         if (host->use_dma == DMA_INTERFACE_IDMA) {
2829                 host->use_dma = TRANS_MODE_IDMAC;
2830         } else if (host->use_dma == DMA_INTERFACE_DWDMA ||
2831                    host->use_dma == DMA_INTERFACE_GDMA) {
2832                 host->use_dma = TRANS_MODE_EDMAC;
2833         } else {
2834                 goto no_dma;
2835         }
2836
2837         /* Determine which DMA interface to use */
2838         if (host->use_dma == TRANS_MODE_IDMAC) {
2839                 /*
2840                 * Check ADDR_CONFIG bit in HCON to find
2841                 * IDMAC address bus width
2842                 */
2843                 addr_config = SDMMC_GET_ADDR_CONFIG(mci_readl(host, HCON));
2844
2845                 if (addr_config == 1) {
2846                         /* host supports IDMAC in 64-bit address mode */
2847                         host->dma_64bit_address = 1;
2848                         dev_info(host->dev,
2849                                  "IDMAC supports 64-bit address mode.\n");
2850                         if (!dma_set_mask(host->dev, DMA_BIT_MASK(64)))
2851                                 dma_set_coherent_mask(host->dev,
2852                                                       DMA_BIT_MASK(64));
2853                 } else {
2854                         /* host supports IDMAC in 32-bit address mode */
2855                         host->dma_64bit_address = 0;
2856                         dev_info(host->dev,
2857                                  "IDMAC supports 32-bit address mode.\n");
2858                 }
2859
2860                 /* Alloc memory for sg translation */
2861                 host->sg_cpu = dmam_alloc_coherent(host->dev,
2862                                                    DESC_RING_BUF_SZ,
2863                                                    &host->sg_dma, GFP_KERNEL);
2864                 if (!host->sg_cpu) {
2865                         dev_err(host->dev,
2866                                 "%s: could not alloc DMA memory\n",
2867                                 __func__);
2868                         goto no_dma;
2869                 }
2870
2871                 host->dma_ops = &dw_mci_idmac_ops;
2872                 dev_info(host->dev, "Using internal DMA controller.\n");
2873         } else {
2874                 /* TRANS_MODE_EDMAC: check dma bindings again */
2875                 if ((device_property_read_string_array(dev, "dma-names",
2876                                                        NULL, 0) < 0) ||
2877                     !device_property_present(dev, "dmas")) {
2878                         goto no_dma;
2879                 }
2880                 host->dma_ops = &dw_mci_edmac_ops;
2881                 dev_info(host->dev, "Using external DMA controller.\n");
2882         }
2883
2884         if (host->dma_ops->init && host->dma_ops->start &&
2885             host->dma_ops->stop && host->dma_ops->cleanup) {
2886                 if (host->dma_ops->init(host)) {
2887                         dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n",
2888                                 __func__);
2889                         goto no_dma;
2890                 }
2891         } else {
2892                 dev_err(host->dev, "DMA initialization not found.\n");
2893                 goto no_dma;
2894         }
2895
2896         return;
2897
2898 no_dma:
2899         dev_info(host->dev, "Using PIO mode.\n");
2900         host->use_dma = TRANS_MODE_PIO;
2901 }
2902
2903 static void dw_mci_cmd11_timer(unsigned long arg)
2904 {
2905         struct dw_mci *host = (struct dw_mci *)arg;
2906
2907         if (host->state != STATE_SENDING_CMD11) {
2908                 dev_warn(host->dev, "Unexpected CMD11 timeout\n");
2909                 return;
2910         }
2911
2912         host->cmd_status = SDMMC_INT_RTO;
2913         set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
2914         tasklet_schedule(&host->tasklet);
2915 }
2916
2917 static void dw_mci_dto_timer(unsigned long arg)
2918 {
2919         struct dw_mci *host = (struct dw_mci *)arg;
2920
2921         switch (host->state) {
2922         case STATE_SENDING_DATA:
2923         case STATE_DATA_BUSY:
2924                 /*
2925                  * If DTO interrupt does NOT come in sending data state,
2926                  * we should notify the driver to terminate current transfer
2927                  * and report a data timeout to the core.
2928                  */
2929                 host->data_status = SDMMC_INT_DRTO;
2930                 set_bit(EVENT_DATA_ERROR, &host->pending_events);
2931                 set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
2932                 tasklet_schedule(&host->tasklet);
2933                 break;
2934         default:
2935                 break;
2936         }
2937 }
2938
2939 #ifdef CONFIG_OF
2940 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2941 {
2942         struct dw_mci_board *pdata;
2943         struct device *dev = host->dev;
2944         const struct dw_mci_drv_data *drv_data = host->drv_data;
2945         int ret;
2946         u32 clock_frequency;
2947
2948         pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
2949         if (!pdata)
2950                 return ERR_PTR(-ENOMEM);
2951
2952         /* find reset controller when exist */
2953         pdata->rstc = devm_reset_control_get_optional(dev, "reset");
2954         if (IS_ERR(pdata->rstc)) {
2955                 if (PTR_ERR(pdata->rstc) == -EPROBE_DEFER)
2956                         return ERR_PTR(-EPROBE_DEFER);
2957         }
2958
2959         /* find out number of slots supported */
2960         if (!device_property_read_u32(dev, "num-slots", &pdata->num_slots))
2961                 dev_info(dev, "'num-slots' was deprecated.\n");
2962
2963         if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth))
2964                 dev_info(dev,
2965                          "fifo-depth property not found, using value of FIFOTH register as default\n");
2966
2967         device_property_read_u32(dev, "card-detect-delay",
2968                                  &pdata->detect_delay_ms);
2969
2970         device_property_read_u32(dev, "data-addr", &host->data_addr_override);
2971
2972         if (device_property_present(dev, "fifo-watermark-aligned"))
2973                 host->wm_aligned = true;
2974
2975         if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency))
2976                 pdata->bus_hz = clock_frequency;
2977
2978         if (drv_data && drv_data->parse_dt) {
2979                 ret = drv_data->parse_dt(host);
2980                 if (ret)
2981                         return ERR_PTR(ret);
2982         }
2983
2984         return pdata;
2985 }
2986
2987 #else /* CONFIG_OF */
2988 static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
2989 {
2990         return ERR_PTR(-EINVAL);
2991 }
2992 #endif /* CONFIG_OF */
2993
2994 static void dw_mci_enable_cd(struct dw_mci *host)
2995 {
2996         unsigned long irqflags;
2997         u32 temp;
2998
2999         /*
3000          * No need for CD if all slots have a non-error GPIO
3001          * as well as broken card detection is found.
3002          */
3003         if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL)
3004                 return;
3005
3006         if (mmc_gpio_get_cd(host->slot->mmc) < 0) {
3007                 spin_lock_irqsave(&host->irq_lock, irqflags);
3008                 temp = mci_readl(host, INTMASK);
3009                 temp  |= SDMMC_INT_CD;
3010                 mci_writel(host, INTMASK, temp);
3011                 spin_unlock_irqrestore(&host->irq_lock, irqflags);
3012         }
3013 }
3014
3015 int dw_mci_probe(struct dw_mci *host)
3016 {
3017         const struct dw_mci_drv_data *drv_data = host->drv_data;
3018         int width, i, ret = 0;
3019         u32 fifo_size;
3020
3021         if (!host->pdata) {
3022                 host->pdata = dw_mci_parse_dt(host);
3023                 if (PTR_ERR(host->pdata) == -EPROBE_DEFER) {
3024                         return -EPROBE_DEFER;
3025                 } else if (IS_ERR(host->pdata)) {
3026                         dev_err(host->dev, "platform data not available\n");
3027                         return -EINVAL;
3028                 }
3029         }
3030
3031         host->biu_clk = devm_clk_get(host->dev, "biu");
3032         if (IS_ERR(host->biu_clk)) {
3033                 dev_dbg(host->dev, "biu clock not available\n");
3034         } else {
3035                 ret = clk_prepare_enable(host->biu_clk);
3036                 if (ret) {
3037                         dev_err(host->dev, "failed to enable biu clock\n");
3038                         return ret;
3039                 }
3040         }
3041
3042         host->ciu_clk = devm_clk_get(host->dev, "ciu");
3043         if (IS_ERR(host->ciu_clk)) {
3044                 dev_dbg(host->dev, "ciu clock not available\n");
3045                 host->bus_hz = host->pdata->bus_hz;
3046         } else {
3047                 ret = clk_prepare_enable(host->ciu_clk);
3048                 if (ret) {
3049                         dev_err(host->dev, "failed to enable ciu clock\n");
3050                         goto err_clk_biu;
3051                 }
3052
3053                 if (host->pdata->bus_hz) {
3054                         ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
3055                         if (ret)
3056                                 dev_warn(host->dev,
3057                                          "Unable to set bus rate to %uHz\n",
3058                                          host->pdata->bus_hz);
3059                 }
3060                 host->bus_hz = clk_get_rate(host->ciu_clk);
3061         }
3062
3063         if (!host->bus_hz) {
3064                 dev_err(host->dev,
3065                         "Platform data must supply bus speed\n");
3066                 ret = -ENODEV;
3067                 goto err_clk_ciu;
3068         }
3069
3070         if (drv_data && drv_data->init) {
3071                 ret = drv_data->init(host);
3072                 if (ret) {
3073                         dev_err(host->dev,
3074                                 "implementation specific init failed\n");
3075                         goto err_clk_ciu;
3076                 }
3077         }
3078
3079         if (!IS_ERR(host->pdata->rstc)) {
3080                 reset_control_assert(host->pdata->rstc);
3081                 usleep_range(10, 50);
3082                 reset_control_deassert(host->pdata->rstc);
3083         }
3084
3085         setup_timer(&host->cmd11_timer,
3086                     dw_mci_cmd11_timer, (unsigned long)host);
3087
3088         setup_timer(&host->dto_timer,
3089                     dw_mci_dto_timer, (unsigned long)host);
3090
3091         spin_lock_init(&host->lock);
3092         spin_lock_init(&host->irq_lock);
3093         INIT_LIST_HEAD(&host->queue);
3094
3095         /*
3096          * Get the host data width - this assumes that HCON has been set with
3097          * the correct values.
3098          */
3099         i = SDMMC_GET_HDATA_WIDTH(mci_readl(host, HCON));
3100         if (!i) {
3101                 host->push_data = dw_mci_push_data16;
3102                 host->pull_data = dw_mci_pull_data16;
3103                 width = 16;
3104                 host->data_shift = 1;
3105         } else if (i == 2) {
3106                 host->push_data = dw_mci_push_data64;
3107                 host->pull_data = dw_mci_pull_data64;
3108                 width = 64;
3109                 host->data_shift = 3;
3110         } else {
3111                 /* Check for a reserved value, and warn if it is */
3112                 WARN((i != 1),
3113                      "HCON reports a reserved host data width!\n"
3114                      "Defaulting to 32-bit access.\n");
3115                 host->push_data = dw_mci_push_data32;
3116                 host->pull_data = dw_mci_pull_data32;
3117                 width = 32;
3118                 host->data_shift = 2;
3119         }
3120
3121         /* Reset all blocks */
3122         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3123                 ret = -ENODEV;
3124                 goto err_clk_ciu;
3125         }
3126
3127         host->dma_ops = host->pdata->dma_ops;
3128         dw_mci_init_dma(host);
3129
3130         /* Clear the interrupts for the host controller */
3131         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3132         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3133
3134         /* Put in max timeout */
3135         mci_writel(host, TMOUT, 0xFFFFFFFF);
3136
3137         /*
3138          * FIFO threshold settings  RxMark  = fifo_size / 2 - 1,
3139          *                          Tx Mark = fifo_size / 2 DMA Size = 8
3140          */
3141         if (!host->pdata->fifo_depth) {
3142                 /*
3143                  * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
3144                  * have been overwritten by the bootloader, just like we're
3145                  * about to do, so if you know the value for your hardware, you
3146                  * should put it in the platform data.
3147                  */
3148                 fifo_size = mci_readl(host, FIFOTH);
3149                 fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
3150         } else {
3151                 fifo_size = host->pdata->fifo_depth;
3152         }
3153         host->fifo_depth = fifo_size;
3154         host->fifoth_val =
3155                 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
3156         mci_writel(host, FIFOTH, host->fifoth_val);
3157
3158         /* disable clock to CIU */
3159         mci_writel(host, CLKENA, 0);
3160         mci_writel(host, CLKSRC, 0);
3161
3162         /*
3163          * In 2.40a spec, Data offset is changed.
3164          * Need to check the version-id and set data-offset for DATA register.
3165          */
3166         host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
3167         dev_info(host->dev, "Version ID is %04x\n", host->verid);
3168
3169         if (host->data_addr_override)
3170                 host->fifo_reg = host->regs + host->data_addr_override;
3171         else if (host->verid < DW_MMC_240A)
3172                 host->fifo_reg = host->regs + DATA_OFFSET;
3173         else
3174                 host->fifo_reg = host->regs + DATA_240A_OFFSET;
3175
3176         tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
3177         ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
3178                                host->irq_flags, "dw-mci", host);
3179         if (ret)
3180                 goto err_dmaunmap;
3181
3182         /*
3183          * Enable interrupts for command done, data over, data empty,
3184          * receive ready and error such as transmit, receive timeout, crc error
3185          */
3186         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3187                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3188                    DW_MCI_ERROR_FLAGS);
3189         /* Enable mci interrupt */
3190         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3191
3192         dev_info(host->dev,
3193                  "DW MMC controller at irq %d,%d bit host data width,%u deep fifo\n",
3194                  host->irq, width, fifo_size);
3195
3196         /* We need at least one slot to succeed */
3197         ret = dw_mci_init_slot(host);
3198         if (ret) {
3199                 dev_dbg(host->dev, "slot %d init failed\n", i);
3200                 goto err_dmaunmap;
3201         }
3202
3203         /* Now that slots are all setup, we can enable card detect */
3204         dw_mci_enable_cd(host);
3205
3206         return 0;
3207
3208 err_dmaunmap:
3209         if (host->use_dma && host->dma_ops->exit)
3210                 host->dma_ops->exit(host);
3211
3212         if (!IS_ERR(host->pdata->rstc))
3213                 reset_control_assert(host->pdata->rstc);
3214
3215 err_clk_ciu:
3216         clk_disable_unprepare(host->ciu_clk);
3217
3218 err_clk_biu:
3219         clk_disable_unprepare(host->biu_clk);
3220
3221         return ret;
3222 }
3223 EXPORT_SYMBOL(dw_mci_probe);
3224
3225 void dw_mci_remove(struct dw_mci *host)
3226 {
3227         dev_dbg(host->dev, "remove slot\n");
3228         if (host->slot)
3229                 dw_mci_cleanup_slot(host->slot);
3230
3231         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3232         mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
3233
3234         /* disable clock to CIU */
3235         mci_writel(host, CLKENA, 0);
3236         mci_writel(host, CLKSRC, 0);
3237
3238         if (host->use_dma && host->dma_ops->exit)
3239                 host->dma_ops->exit(host);
3240
3241         if (!IS_ERR(host->pdata->rstc))
3242                 reset_control_assert(host->pdata->rstc);
3243
3244         clk_disable_unprepare(host->ciu_clk);
3245         clk_disable_unprepare(host->biu_clk);
3246 }
3247 EXPORT_SYMBOL(dw_mci_remove);
3248
3249
3250
3251 #ifdef CONFIG_PM
3252 int dw_mci_runtime_suspend(struct device *dev)
3253 {
3254         struct dw_mci *host = dev_get_drvdata(dev);
3255
3256         if (host->use_dma && host->dma_ops->exit)
3257                 host->dma_ops->exit(host);
3258
3259         clk_disable_unprepare(host->ciu_clk);
3260
3261         if (host->slot &&
3262             (mmc_can_gpio_cd(host->slot->mmc) ||
3263              !mmc_card_is_removable(host->slot->mmc)))
3264                 clk_disable_unprepare(host->biu_clk);
3265
3266         return 0;
3267 }
3268 EXPORT_SYMBOL(dw_mci_runtime_suspend);
3269
3270 int dw_mci_runtime_resume(struct device *dev)
3271 {
3272         int ret = 0;
3273         struct dw_mci *host = dev_get_drvdata(dev);
3274
3275         if (host->slot &&
3276             (mmc_can_gpio_cd(host->slot->mmc) ||
3277              !mmc_card_is_removable(host->slot->mmc))) {
3278                 ret = clk_prepare_enable(host->biu_clk);
3279                 if (ret)
3280                         return ret;
3281         }
3282
3283         ret = clk_prepare_enable(host->ciu_clk);
3284         if (ret)
3285                 goto err;
3286
3287         if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_ALL_RESET_FLAGS)) {
3288                 clk_disable_unprepare(host->ciu_clk);
3289                 ret = -ENODEV;
3290                 goto err;
3291         }
3292
3293         if (host->use_dma && host->dma_ops->init)
3294                 host->dma_ops->init(host);
3295
3296         /*
3297          * Restore the initial value at FIFOTH register
3298          * And Invalidate the prev_blksz with zero
3299          */
3300          mci_writel(host, FIFOTH, host->fifoth_val);
3301          host->prev_blksz = 0;
3302
3303         /* Put in max timeout */
3304         mci_writel(host, TMOUT, 0xFFFFFFFF);
3305
3306         mci_writel(host, RINTSTS, 0xFFFFFFFF);
3307         mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
3308                    SDMMC_INT_TXDR | SDMMC_INT_RXDR |
3309                    DW_MCI_ERROR_FLAGS);
3310         mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
3311
3312
3313         if (host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER)
3314                 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios);
3315
3316         /* Force setup bus to guarantee available clock output */
3317         dw_mci_setup_bus(host->slot, true);
3318
3319         /* Now that slots are all setup, we can enable card detect */
3320         dw_mci_enable_cd(host);
3321
3322         return 0;
3323
3324 err:
3325         if (host->slot &&
3326             (mmc_can_gpio_cd(host->slot->mmc) ||
3327              !mmc_card_is_removable(host->slot->mmc)))
3328                 clk_disable_unprepare(host->biu_clk);
3329
3330         return ret;
3331 }
3332 EXPORT_SYMBOL(dw_mci_runtime_resume);
3333 #endif /* CONFIG_PM */
3334
3335 static int __init dw_mci_init(void)
3336 {
3337         pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
3338         return 0;
3339 }
3340
3341 static void __exit dw_mci_exit(void)
3342 {
3343 }
3344
3345 module_init(dw_mci_init);
3346 module_exit(dw_mci_exit);
3347
3348 MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
3349 MODULE_AUTHOR("NXP Semiconductor VietNam");
3350 MODULE_AUTHOR("Imagination Technologies Ltd");
3351 MODULE_LICENSE("GPL v2");