2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver
4 * This is a driver for the SDHC controller found in Freescale MX2/MX3
5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
6 * Unlike the hardware found on MX1, this hardware just works and does
7 * not need all the quirks found in imxmmc.c, hence the separate driver.
9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
12 * derived from pxamci.c by Russell King
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License version 2 as
16 * published by the Free Software Foundation.
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/ioport.h>
23 #include <linux/platform_device.h>
24 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/blkdev.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/mmc/host.h>
29 #include <linux/mmc/card.h>
30 #include <linux/delay.h>
31 #include <linux/clk.h>
33 #include <linux/gpio.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/dmaengine.h>
36 #include <linux/types.h>
38 #include <linux/of_device.h>
39 #include <linux/of_dma.h>
40 #include <linux/of_gpio.h>
44 #include <asm/sizes.h>
45 #include <linux/platform_data/mmc-mxcmmc.h>
47 #include <linux/platform_data/dma-imx.h>
49 #define DRIVER_NAME "mxc-mmc"
50 #define MXCMCI_TIMEOUT_MS 10000
52 #define MMC_REG_STR_STP_CLK 0x00
53 #define MMC_REG_STATUS 0x04
54 #define MMC_REG_CLK_RATE 0x08
55 #define MMC_REG_CMD_DAT_CONT 0x0C
56 #define MMC_REG_RES_TO 0x10
57 #define MMC_REG_READ_TO 0x14
58 #define MMC_REG_BLK_LEN 0x18
59 #define MMC_REG_NOB 0x1C
60 #define MMC_REG_REV_NO 0x20
61 #define MMC_REG_INT_CNTR 0x24
62 #define MMC_REG_CMD 0x28
63 #define MMC_REG_ARG 0x2C
64 #define MMC_REG_RES_FIFO 0x34
65 #define MMC_REG_BUFFER_ACCESS 0x38
67 #define STR_STP_CLK_RESET (1 << 3)
68 #define STR_STP_CLK_START_CLK (1 << 1)
69 #define STR_STP_CLK_STOP_CLK (1 << 0)
71 #define STATUS_CARD_INSERTION (1 << 31)
72 #define STATUS_CARD_REMOVAL (1 << 30)
73 #define STATUS_YBUF_EMPTY (1 << 29)
74 #define STATUS_XBUF_EMPTY (1 << 28)
75 #define STATUS_YBUF_FULL (1 << 27)
76 #define STATUS_XBUF_FULL (1 << 26)
77 #define STATUS_BUF_UND_RUN (1 << 25)
78 #define STATUS_BUF_OVFL (1 << 24)
79 #define STATUS_SDIO_INT_ACTIVE (1 << 14)
80 #define STATUS_END_CMD_RESP (1 << 13)
81 #define STATUS_WRITE_OP_DONE (1 << 12)
82 #define STATUS_DATA_TRANS_DONE (1 << 11)
83 #define STATUS_READ_OP_DONE (1 << 11)
84 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
85 #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
86 #define STATUS_BUF_READ_RDY (1 << 7)
87 #define STATUS_BUF_WRITE_RDY (1 << 6)
88 #define STATUS_RESP_CRC_ERR (1 << 5)
89 #define STATUS_CRC_READ_ERR (1 << 3)
90 #define STATUS_CRC_WRITE_ERR (1 << 2)
91 #define STATUS_TIME_OUT_RESP (1 << 1)
92 #define STATUS_TIME_OUT_READ (1 << 0)
93 #define STATUS_ERR_MASK 0x2f
95 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
96 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
97 #define CMD_DAT_CONT_START_READWAIT (1 << 10)
98 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
99 #define CMD_DAT_CONT_INIT (1 << 7)
100 #define CMD_DAT_CONT_WRITE (1 << 4)
101 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
102 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
103 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
104 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
106 #define INT_SDIO_INT_WKP_EN (1 << 18)
107 #define INT_CARD_INSERTION_WKP_EN (1 << 17)
108 #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
109 #define INT_CARD_INSERTION_EN (1 << 15)
110 #define INT_CARD_REMOVAL_EN (1 << 14)
111 #define INT_SDIO_IRQ_EN (1 << 13)
112 #define INT_DAT0_EN (1 << 12)
113 #define INT_BUF_READ_EN (1 << 4)
114 #define INT_BUF_WRITE_EN (1 << 3)
115 #define INT_END_CMD_RES_EN (1 << 2)
116 #define INT_WRITE_OP_DONE_EN (1 << 1)
117 #define INT_READ_OP_EN (1 << 0)
125 struct mmc_host *mmc;
126 struct resource *res;
130 struct dma_chan *dma;
131 struct dma_async_tx_descriptor *desc;
133 int default_irq_mask;
135 unsigned int power_mode;
136 struct imxmmc_platform_data *pdata;
138 struct mmc_request *req;
139 struct mmc_command *cmd;
140 struct mmc_data *data;
142 unsigned int datasize;
143 unsigned int dma_dir;
153 struct work_struct datawork;
156 struct regulator *vcc;
160 struct dma_slave_config dma_slave_config;
161 struct imx_dma_data dma_data;
163 struct timer_list watchdog;
164 enum mxcmci_type devtype;
167 static struct platform_device_id mxcmci_devtype[] = {
170 .driver_data = IMX21_MMC,
173 .driver_data = IMX31_MMC,
178 MODULE_DEVICE_TABLE(platform, mxcmci_devtype);
180 static const struct of_device_id mxcmci_of_match[] = {
182 .compatible = "fsl,imx21-mmc",
183 .data = &mxcmci_devtype[IMX21_MMC],
185 .compatible = "fsl,imx31-mmc",
186 .data = &mxcmci_devtype[IMX31_MMC],
191 MODULE_DEVICE_TABLE(of, mxcmci_of_match);
193 static inline int is_imx31_mmc(struct mxcmci_host *host)
195 return host->devtype == IMX31_MMC;
198 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios);
200 static inline void mxcmci_init_ocr(struct mxcmci_host *host)
202 host->vcc = regulator_get(mmc_dev(host->mmc), "vmmc");
204 if (IS_ERR(host->vcc)) {
207 host->mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vcc);
208 if (host->pdata && host->pdata->ocr_avail)
209 dev_warn(mmc_dev(host->mmc),
210 "pdata->ocr_avail will not be used\n");
213 if (host->vcc == NULL) {
214 /* fall-back to platform data */
215 if (host->pdata && host->pdata->ocr_avail)
216 host->mmc->ocr_avail = host->pdata->ocr_avail;
218 host->mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
222 static inline void mxcmci_set_power(struct mxcmci_host *host,
223 unsigned char power_mode,
227 if (power_mode == MMC_POWER_UP)
228 mmc_regulator_set_ocr(host->mmc, host->vcc, vdd);
229 else if (power_mode == MMC_POWER_OFF)
230 mmc_regulator_set_ocr(host->mmc, host->vcc, 0);
233 if (host->pdata && host->pdata->setpower)
234 host->pdata->setpower(mmc_dev(host->mmc), vdd);
237 static inline int mxcmci_use_dma(struct mxcmci_host *host)
242 static void mxcmci_softreset(struct mxcmci_host *host)
246 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n");
249 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK);
250 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
251 host->base + MMC_REG_STR_STP_CLK);
253 for (i = 0; i < 8; i++)
254 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
256 writew(0xff, host->base + MMC_REG_RES_TO);
258 static int mxcmci_setup_dma(struct mmc_host *mmc);
260 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
262 unsigned int nob = data->blocks;
263 unsigned int blksz = data->blksz;
264 unsigned int datasize = nob * blksz;
265 struct scatterlist *sg;
266 enum dma_transfer_direction slave_dirn;
269 if (data->flags & MMC_DATA_STREAM)
273 data->bytes_xfered = 0;
275 writew(nob, host->base + MMC_REG_NOB);
276 writew(blksz, host->base + MMC_REG_BLK_LEN);
277 host->datasize = datasize;
279 if (!mxcmci_use_dma(host))
282 for_each_sg(data->sg, sg, data->sg_len, i) {
283 if (sg->offset & 3 || sg->length & 3 || sg->length < 512) {
289 if (data->flags & MMC_DATA_READ) {
290 host->dma_dir = DMA_FROM_DEVICE;
291 slave_dirn = DMA_DEV_TO_MEM;
293 host->dma_dir = DMA_TO_DEVICE;
294 slave_dirn = DMA_MEM_TO_DEV;
297 nents = dma_map_sg(host->dma->device->dev, data->sg,
298 data->sg_len, host->dma_dir);
299 if (nents != data->sg_len)
302 host->desc = dmaengine_prep_slave_sg(host->dma,
303 data->sg, data->sg_len, slave_dirn,
304 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
307 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
310 return 0; /* Fall back to PIO */
314 dmaengine_submit(host->desc);
315 dma_async_issue_pending(host->dma);
317 mod_timer(&host->watchdog, jiffies + msecs_to_jiffies(MXCMCI_TIMEOUT_MS));
322 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat);
323 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat);
325 static void mxcmci_dma_callback(void *data)
327 struct mxcmci_host *host = data;
330 del_timer(&host->watchdog);
332 stat = readl(host->base + MMC_REG_STATUS);
333 writel(stat & ~STATUS_DATA_TRANS_DONE, host->base + MMC_REG_STATUS);
335 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
337 if (stat & STATUS_READ_OP_DONE)
338 writel(STATUS_READ_OP_DONE, host->base + MMC_REG_STATUS);
340 mxcmci_data_done(host, stat);
343 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd,
346 u32 int_cntr = host->default_irq_mask;
349 WARN_ON(host->cmd != NULL);
352 switch (mmc_resp_type(cmd)) {
353 case MMC_RSP_R1: /* short CRC, OPCODE */
354 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */
355 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
357 case MMC_RSP_R2: /* long 136 bit + CRC */
358 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
360 case MMC_RSP_R3: /* short */
361 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
366 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n",
368 cmd->error = -EINVAL;
372 int_cntr = INT_END_CMD_RES_EN;
374 if (mxcmci_use_dma(host)) {
375 if (host->dma_dir == DMA_FROM_DEVICE) {
376 host->desc->callback = mxcmci_dma_callback;
377 host->desc->callback_param = host;
379 int_cntr |= INT_WRITE_OP_DONE_EN;
383 spin_lock_irqsave(&host->lock, flags);
385 int_cntr |= INT_SDIO_IRQ_EN;
386 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
387 spin_unlock_irqrestore(&host->lock, flags);
389 writew(cmd->opcode, host->base + MMC_REG_CMD);
390 writel(cmd->arg, host->base + MMC_REG_ARG);
391 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT);
396 static void mxcmci_finish_request(struct mxcmci_host *host,
397 struct mmc_request *req)
399 u32 int_cntr = host->default_irq_mask;
402 spin_lock_irqsave(&host->lock, flags);
404 int_cntr |= INT_SDIO_IRQ_EN;
405 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
406 spin_unlock_irqrestore(&host->lock, flags);
412 mmc_request_done(host->mmc, req);
415 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
417 struct mmc_data *data = host->data;
420 if (mxcmci_use_dma(host))
421 dma_unmap_sg(host->dma->device->dev, data->sg, data->sg_len,
424 if (stat & STATUS_ERR_MASK) {
425 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n",
427 if (stat & STATUS_CRC_READ_ERR) {
428 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__);
429 data->error = -EILSEQ;
430 } else if (stat & STATUS_CRC_WRITE_ERR) {
431 u32 err_code = (stat >> 9) & 0x3;
432 if (err_code == 2) { /* No CRC response */
433 dev_err(mmc_dev(host->mmc),
434 "%s: No CRC -ETIMEDOUT\n", __func__);
435 data->error = -ETIMEDOUT;
437 dev_err(mmc_dev(host->mmc),
438 "%s: -EILSEQ\n", __func__);
439 data->error = -EILSEQ;
441 } else if (stat & STATUS_TIME_OUT_READ) {
442 dev_err(mmc_dev(host->mmc),
443 "%s: read -ETIMEDOUT\n", __func__);
444 data->error = -ETIMEDOUT;
446 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__);
450 data->bytes_xfered = host->datasize;
453 data_error = data->error;
460 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
462 struct mmc_command *cmd = host->cmd;
469 if (stat & STATUS_TIME_OUT_RESP) {
470 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n");
471 cmd->error = -ETIMEDOUT;
472 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) {
473 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n");
474 cmd->error = -EILSEQ;
477 if (cmd->flags & MMC_RSP_PRESENT) {
478 if (cmd->flags & MMC_RSP_136) {
479 for (i = 0; i < 4; i++) {
480 a = readw(host->base + MMC_REG_RES_FIFO);
481 b = readw(host->base + MMC_REG_RES_FIFO);
482 cmd->resp[i] = a << 16 | b;
485 a = readw(host->base + MMC_REG_RES_FIFO);
486 b = readw(host->base + MMC_REG_RES_FIFO);
487 c = readw(host->base + MMC_REG_RES_FIFO);
488 cmd->resp[0] = a << 24 | b << 8 | c >> 8;
493 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
496 unsigned long timeout = jiffies + HZ;
499 stat = readl(host->base + MMC_REG_STATUS);
500 if (stat & STATUS_ERR_MASK)
502 if (time_after(jiffies, timeout)) {
503 mxcmci_softreset(host);
504 mxcmci_set_clk_rate(host, host->clock);
505 return STATUS_TIME_OUT_READ;
513 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
519 stat = mxcmci_poll_status(host,
520 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
523 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS);
531 stat = mxcmci_poll_status(host,
532 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
535 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS);
536 memcpy(b, &tmp, bytes);
542 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes)
548 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
551 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS);
559 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
563 memcpy(&tmp, b, bytes);
564 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS);
567 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
574 static int mxcmci_transfer_data(struct mxcmci_host *host)
576 struct mmc_data *data = host->req->data;
577 struct scatterlist *sg;
583 if (data->flags & MMC_DATA_READ) {
584 for_each_sg(data->sg, sg, data->sg_len, i) {
585 stat = mxcmci_pull(host, sg_virt(sg), sg->length);
588 host->datasize += sg->length;
591 for_each_sg(data->sg, sg, data->sg_len, i) {
592 stat = mxcmci_push(host, sg_virt(sg), sg->length);
595 host->datasize += sg->length;
597 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
604 static void mxcmci_datawork(struct work_struct *work)
606 struct mxcmci_host *host = container_of(work, struct mxcmci_host,
608 int datastat = mxcmci_transfer_data(host);
610 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
611 host->base + MMC_REG_STATUS);
612 mxcmci_finish_data(host, datastat);
614 if (host->req->stop) {
615 if (mxcmci_start_cmd(host, host->req->stop, 0)) {
616 mxcmci_finish_request(host, host->req);
620 mxcmci_finish_request(host, host->req);
624 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat)
626 struct mmc_request *req;
630 spin_lock_irqsave(&host->lock, flags);
633 spin_unlock_irqrestore(&host->lock, flags);
638 spin_unlock_irqrestore(&host->lock, flags);
644 host->req = NULL; /* we will handle finish req below */
646 data_error = mxcmci_finish_data(host, stat);
648 spin_unlock_irqrestore(&host->lock, flags);
650 mxcmci_read_response(host, stat);
654 if (mxcmci_start_cmd(host, req->stop, 0)) {
655 mxcmci_finish_request(host, req);
659 mxcmci_finish_request(host, req);
663 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
665 mxcmci_read_response(host, stat);
668 if (!host->data && host->req) {
669 mxcmci_finish_request(host, host->req);
673 /* For the DMA case the DMA engine handles the data transfer
674 * automatically. For non DMA we have to do it ourselves.
675 * Don't do it in interrupt context though.
677 if (!mxcmci_use_dma(host) && host->data)
678 schedule_work(&host->datawork);
682 static irqreturn_t mxcmci_irq(int irq, void *devid)
684 struct mxcmci_host *host = devid;
689 stat = readl(host->base + MMC_REG_STATUS);
690 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE |
691 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS);
693 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat);
695 spin_lock_irqsave(&host->lock, flags);
696 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio;
697 spin_unlock_irqrestore(&host->lock, flags);
699 if (mxcmci_use_dma(host) &&
700 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE)))
701 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE,
702 host->base + MMC_REG_STATUS);
705 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS);
706 mmc_signal_sdio_irq(host->mmc);
709 if (stat & STATUS_END_CMD_RESP)
710 mxcmci_cmd_done(host, stat);
712 if (mxcmci_use_dma(host) &&
713 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) {
714 del_timer(&host->watchdog);
715 mxcmci_data_done(host, stat);
718 if (host->default_irq_mask &&
719 (stat & (STATUS_CARD_INSERTION | STATUS_CARD_REMOVAL)))
720 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
725 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req)
727 struct mxcmci_host *host = mmc_priv(mmc);
728 unsigned int cmdat = host->cmdat;
731 WARN_ON(host->req != NULL);
734 host->cmdat &= ~CMD_DAT_CONT_INIT;
740 error = mxcmci_setup_data(host, req->data);
742 req->cmd->error = error;
747 cmdat |= CMD_DAT_CONT_DATA_ENABLE;
749 if (req->data->flags & MMC_DATA_WRITE)
750 cmdat |= CMD_DAT_CONT_WRITE;
753 error = mxcmci_start_cmd(host, req->cmd, cmdat);
757 mxcmci_finish_request(host, req);
760 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
762 unsigned int divider;
764 unsigned int clk_in = clk_get_rate(host->clk_per);
766 while (prescaler <= 0x800) {
767 for (divider = 1; divider <= 0xF; divider++) {
770 x = (clk_in / (divider + 1));
773 x /= (prescaler * 2);
787 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE);
789 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n",
790 prescaler, divider, clk_in, clk_ios);
793 static int mxcmci_setup_dma(struct mmc_host *mmc)
795 struct mxcmci_host *host = mmc_priv(mmc);
796 struct dma_slave_config *config = &host->dma_slave_config;
798 config->dst_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
799 config->src_addr = host->res->start + MMC_REG_BUFFER_ACCESS;
800 config->dst_addr_width = 4;
801 config->src_addr_width = 4;
802 config->dst_maxburst = host->burstlen;
803 config->src_maxburst = host->burstlen;
804 config->device_fc = false;
806 return dmaengine_slave_config(host->dma, config);
809 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
811 struct mxcmci_host *host = mmc_priv(mmc);
815 * use burstlen of 64 (16 words) in 4 bit mode (--> reg value 0)
816 * use burstlen of 16 (4 words) in 1 bit mode (--> reg value 16)
818 if (ios->bus_width == MMC_BUS_WIDTH_4)
823 if (mxcmci_use_dma(host) && burstlen != host->burstlen) {
824 host->burstlen = burstlen;
825 ret = mxcmci_setup_dma(mmc);
827 dev_err(mmc_dev(host->mmc),
828 "failed to config DMA channel. Falling back to PIO\n");
829 dma_release_channel(host->dma);
835 if (ios->bus_width == MMC_BUS_WIDTH_4)
836 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
838 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
840 if (host->power_mode != ios->power_mode) {
841 mxcmci_set_power(host, ios->power_mode, ios->vdd);
842 host->power_mode = ios->power_mode;
844 if (ios->power_mode == MMC_POWER_ON)
845 host->cmdat |= CMD_DAT_CONT_INIT;
849 mxcmci_set_clk_rate(host, ios->clock);
850 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK);
852 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK);
855 host->clock = ios->clock;
858 static irqreturn_t mxcmci_detect_irq(int irq, void *data)
860 struct mmc_host *mmc = data;
862 dev_dbg(mmc_dev(mmc), "%s\n", __func__);
864 mmc_detect_change(mmc, msecs_to_jiffies(250));
868 static int mxcmci_get_ro(struct mmc_host *mmc)
870 struct mxcmci_host *host = mmc_priv(mmc);
872 if (host->pdata && host->pdata->get_ro)
873 return !!host->pdata->get_ro(mmc_dev(mmc));
875 * Board doesn't support read only detection; let the mmc core
881 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
883 struct mxcmci_host *host = mmc_priv(mmc);
887 spin_lock_irqsave(&host->lock, flags);
888 host->use_sdio = enable;
889 int_cntr = readl(host->base + MMC_REG_INT_CNTR);
892 int_cntr |= INT_SDIO_IRQ_EN;
894 int_cntr &= ~INT_SDIO_IRQ_EN;
896 writel(int_cntr, host->base + MMC_REG_INT_CNTR);
897 spin_unlock_irqrestore(&host->lock, flags);
900 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card)
902 struct mxcmci_host *mxcmci = mmc_priv(host);
905 * MX3 SoCs have a silicon bug which corrupts CRC calculation of
906 * multi-block transfers when connected SDIO peripheral doesn't
907 * drive the BUSY line as required by the specs.
908 * One way to prevent this is to only allow 1-bit transfers.
911 if (is_imx31_mmc(mxcmci) && card->type == MMC_TYPE_SDIO)
912 host->caps &= ~MMC_CAP_4_BIT_DATA;
914 host->caps |= MMC_CAP_4_BIT_DATA;
917 static bool filter(struct dma_chan *chan, void *param)
919 struct mxcmci_host *host = param;
921 if (!imx_dma_is_general_purpose(chan))
924 chan->private = &host->dma_data;
929 static void mxcmci_watchdog(unsigned long data)
931 struct mmc_host *mmc = (struct mmc_host *)data;
932 struct mxcmci_host *host = mmc_priv(mmc);
933 struct mmc_request *req = host->req;
934 unsigned int stat = readl(host->base + MMC_REG_STATUS);
936 if (host->dma_dir == DMA_FROM_DEVICE) {
937 dmaengine_terminate_all(host->dma);
938 dev_err(mmc_dev(host->mmc),
939 "%s: read time out (status = 0x%08x)\n",
942 dev_err(mmc_dev(host->mmc),
943 "%s: write time out (status = 0x%08x)\n",
945 mxcmci_softreset(host);
948 /* Mark transfer as erroneus and inform the upper layers */
951 host->data->error = -ETIMEDOUT;
955 mmc_request_done(host->mmc, req);
958 static const struct mmc_host_ops mxcmci_ops = {
959 .request = mxcmci_request,
960 .set_ios = mxcmci_set_ios,
961 .get_ro = mxcmci_get_ro,
962 .enable_sdio_irq = mxcmci_enable_sdio_irq,
963 .init_card = mxcmci_init_card,
966 static int mxcmci_probe(struct platform_device *pdev)
968 struct mmc_host *mmc;
969 struct mxcmci_host *host = NULL;
970 struct resource *iores, *r;
972 bool dat3_card_detect = false;
974 const struct of_device_id *of_id;
975 struct imxmmc_platform_data *pdata = pdev->dev.platform_data;
977 pr_info("i.MX SDHC driver\n");
979 of_id = of_match_device(mxcmci_of_match, &pdev->dev);
981 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 irq = platform_get_irq(pdev, 0);
983 if (!iores || irq < 0)
986 r = request_mem_region(iores->start, resource_size(iores), pdev->name);
990 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev);
993 goto out_release_mem;
997 mmc->ops = &mxcmci_ops;
999 /* For devicetree parsing, the bus width is read from devicetree */
1001 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ;
1003 mmc->caps |= MMC_CAP_SDIO_IRQ;
1005 /* MMC core transfer sizes tunable parameters */
1007 mmc->max_blk_size = 2048;
1008 mmc->max_blk_count = 65535;
1009 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
1010 mmc->max_seg_size = mmc->max_req_size;
1012 host = mmc_priv(mmc);
1013 host->base = ioremap(r->start, resource_size(r));
1020 const struct platform_device_id *id_entry = of_id->data;
1021 host->devtype = id_entry->driver_data;
1023 host->devtype = pdev->id_entry->driver_data;
1026 host->pdata = pdata;
1027 spin_lock_init(&host->lock);
1030 dat3_card_detect = pdata->dat3_card_detect;
1031 else if (!(mmc->caps & MMC_CAP_NONREMOVABLE)
1032 && !of_property_read_bool(pdev->dev.of_node, "cd-gpios"))
1033 dat3_card_detect = true;
1035 mxcmci_init_ocr(host);
1037 if (dat3_card_detect)
1038 host->default_irq_mask =
1039 INT_CARD_INSERTION_EN | INT_CARD_REMOVAL_EN;
1041 host->default_irq_mask = 0;
1046 host->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1047 if (IS_ERR(host->clk_ipg)) {
1048 ret = PTR_ERR(host->clk_ipg);
1052 host->clk_per = devm_clk_get(&pdev->dev, "per");
1053 if (IS_ERR(host->clk_per)) {
1054 ret = PTR_ERR(host->clk_per);
1058 clk_prepare_enable(host->clk_per);
1059 clk_prepare_enable(host->clk_ipg);
1061 mxcmci_softreset(host);
1063 host->rev_no = readw(host->base + MMC_REG_REV_NO);
1064 if (host->rev_no != 0x400) {
1066 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n",
1071 mmc->f_min = clk_get_rate(host->clk_per) >> 16;
1072 mmc->f_max = clk_get_rate(host->clk_per) >> 1;
1074 /* recommended in data sheet */
1075 writew(0x2db4, host->base + MMC_REG_READ_TO);
1077 writel(host->default_irq_mask, host->base + MMC_REG_INT_CNTR);
1080 host->dma = dma_request_slave_channel(&pdev->dev, "rx-tx");
1082 r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
1084 host->dmareq = r->start;
1085 host->dma_data.peripheral_type = IMX_DMATYPE_SDHC;
1086 host->dma_data.priority = DMA_PRIO_LOW;
1087 host->dma_data.dma_request = host->dmareq;
1089 dma_cap_set(DMA_SLAVE, mask);
1090 host->dma = dma_request_channel(mask, filter, host);
1094 mmc->max_seg_size = dma_get_max_seg_size(
1095 host->dma->device->dev);
1097 dev_info(mmc_dev(host->mmc), "dma not available. Using PIO\n");
1099 INIT_WORK(&host->datawork, mxcmci_datawork);
1101 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host);
1105 platform_set_drvdata(pdev, mmc);
1107 if (host->pdata && host->pdata->init) {
1108 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq,
1114 init_timer(&host->watchdog);
1115 host->watchdog.function = &mxcmci_watchdog;
1116 host->watchdog.data = (unsigned long)mmc;
1123 free_irq(host->irq, host);
1126 dma_release_channel(host->dma);
1128 clk_disable_unprepare(host->clk_per);
1129 clk_disable_unprepare(host->clk_ipg);
1131 iounmap(host->base);
1135 release_mem_region(iores->start, resource_size(iores));
1139 static int mxcmci_remove(struct platform_device *pdev)
1141 struct mmc_host *mmc = platform_get_drvdata(pdev);
1142 struct mxcmci_host *host = mmc_priv(mmc);
1144 platform_set_drvdata(pdev, NULL);
1146 mmc_remove_host(mmc);
1149 regulator_put(host->vcc);
1151 if (host->pdata && host->pdata->exit)
1152 host->pdata->exit(&pdev->dev, mmc);
1154 free_irq(host->irq, host);
1155 iounmap(host->base);
1158 dma_release_channel(host->dma);
1160 clk_disable_unprepare(host->clk_per);
1161 clk_disable_unprepare(host->clk_ipg);
1163 release_mem_region(host->res->start, resource_size(host->res));
1171 static int mxcmci_suspend(struct device *dev)
1173 struct mmc_host *mmc = dev_get_drvdata(dev);
1174 struct mxcmci_host *host = mmc_priv(mmc);
1178 ret = mmc_suspend_host(mmc);
1179 clk_disable_unprepare(host->clk_per);
1180 clk_disable_unprepare(host->clk_ipg);
1185 static int mxcmci_resume(struct device *dev)
1187 struct mmc_host *mmc = dev_get_drvdata(dev);
1188 struct mxcmci_host *host = mmc_priv(mmc);
1191 clk_prepare_enable(host->clk_per);
1192 clk_prepare_enable(host->clk_ipg);
1194 ret = mmc_resume_host(mmc);
1199 static const struct dev_pm_ops mxcmci_pm_ops = {
1200 .suspend = mxcmci_suspend,
1201 .resume = mxcmci_resume,
1205 static struct platform_driver mxcmci_driver = {
1206 .probe = mxcmci_probe,
1207 .remove = mxcmci_remove,
1208 .id_table = mxcmci_devtype,
1210 .name = DRIVER_NAME,
1211 .owner = THIS_MODULE,
1213 .pm = &mxcmci_pm_ops,
1215 .of_match_table = mxcmci_of_match,
1219 module_platform_driver(mxcmci_driver);
1221 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver");
1222 MODULE_AUTHOR("Sascha Hauer, Pengutronix");
1223 MODULE_LICENSE("GPL");
1224 MODULE_ALIAS("platform:mxc-mmc");