2 * drivers/mmc/host/sdhci-msm.c - Qualcomm SDHCI Platform driver
4 * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 and
8 * only version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/delay.h>
20 #include <linux/mmc/mmc.h>
21 #include <linux/slab.h>
23 #include "sdhci-pltfm.h"
25 #define CORE_MCI_VERSION 0x50
26 #define CORE_VERSION_MAJOR_SHIFT 28
27 #define CORE_VERSION_MAJOR_MASK (0xf << CORE_VERSION_MAJOR_SHIFT)
28 #define CORE_VERSION_MINOR_MASK 0xff
30 #define CORE_HC_MODE 0x78
31 #define HC_MODE_EN 0x1
32 #define CORE_POWER 0x0
33 #define CORE_SW_RST BIT(7)
36 #define CORE_DLL_LOCK BIT(7)
37 #define CORE_DLL_EN BIT(16)
38 #define CORE_CDR_EN BIT(17)
39 #define CORE_CK_OUT_EN BIT(18)
40 #define CORE_CDR_EXT_EN BIT(19)
41 #define CORE_DLL_PDN BIT(29)
42 #define CORE_DLL_RST BIT(30)
43 #define CORE_DLL_CONFIG 0x100
44 #define CORE_DLL_STATUS 0x108
46 #define CORE_VENDOR_SPEC 0x10c
47 #define CORE_CLK_PWRSAVE BIT(1)
49 #define CORE_VENDOR_SPEC_CAPABILITIES0 0x11c
51 #define CDR_SELEXT_SHIFT 20
52 #define CDR_SELEXT_MASK (0xf << CDR_SELEXT_SHIFT)
53 #define CMUX_SHIFT_PHASE_SHIFT 24
54 #define CMUX_SHIFT_PHASE_MASK (7 << CMUX_SHIFT_PHASE_SHIFT)
56 struct sdhci_msm_host {
57 struct platform_device *pdev;
58 void __iomem *core_mem; /* MSM SDCC mapped address */
59 struct clk *clk; /* main SD/MMC bus clock */
60 struct clk *pclk; /* SDHC peripheral bus clock */
61 struct clk *bus_clk; /* SDHC bus voter clock */
65 /* Platform specific tuning */
66 static inline int msm_dll_poll_ck_out_en(struct sdhci_host *host, u8 poll)
70 struct mmc_host *mmc = host->mmc;
72 /* Poll for CK_OUT_EN bit. max. poll time = 50us */
73 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
76 while (ck_out_en != poll) {
77 if (--wait_cnt == 0) {
78 dev_err(mmc_dev(mmc), "%s: CK_OUT_EN bit is not %d\n",
79 mmc_hostname(mmc), poll);
84 ck_out_en = !!(readl_relaxed(host->ioaddr + CORE_DLL_CONFIG) &
91 static int msm_config_cm_dll_phase(struct sdhci_host *host, u8 phase)
94 static const u8 grey_coded_phase_table[] = {
95 0x0, 0x1, 0x3, 0x2, 0x6, 0x7, 0x5, 0x4,
96 0xc, 0xd, 0xf, 0xe, 0xa, 0xb, 0x9, 0x8
100 struct mmc_host *mmc = host->mmc;
102 spin_lock_irqsave(&host->lock, flags);
104 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
105 config &= ~(CORE_CDR_EN | CORE_CK_OUT_EN);
106 config |= (CORE_CDR_EXT_EN | CORE_DLL_EN);
107 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
109 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '0' */
110 rc = msm_dll_poll_ck_out_en(host, 0);
115 * Write the selected DLL clock output phase (0 ... 15)
116 * to CDR_SELEXT bit field of DLL_CONFIG register.
118 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
119 config &= ~CDR_SELEXT_MASK;
120 config |= grey_coded_phase_table[phase] << CDR_SELEXT_SHIFT;
121 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
123 /* Set CK_OUT_EN bit of DLL_CONFIG register to 1. */
124 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
125 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
127 /* Wait until CK_OUT_EN bit of DLL_CONFIG register becomes '1' */
128 rc = msm_dll_poll_ck_out_en(host, 1);
132 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
133 config |= CORE_CDR_EN;
134 config &= ~CORE_CDR_EXT_EN;
135 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
139 dev_err(mmc_dev(mmc), "%s: Failed to set DLL phase: %d\n",
140 mmc_hostname(mmc), phase);
142 spin_unlock_irqrestore(&host->lock, flags);
147 * Find out the greatest range of consecuitive selected
148 * DLL clock output phases that can be used as sampling
149 * setting for SD3.0 UHS-I card read operation (in SDR104
150 * timing mode) or for eMMC4.5 card read operation (in HS200
152 * Select the 3/4 of the range and configure the DLL with the
153 * selected DLL clock output phase.
156 static int msm_find_most_appropriate_phase(struct sdhci_host *host,
157 u8 *phase_table, u8 total_phases)
160 u8 ranges[MAX_PHASES][MAX_PHASES] = { {0}, {0} };
161 u8 phases_per_row[MAX_PHASES] = { 0 };
162 int row_index = 0, col_index = 0, selected_row_index = 0, curr_max = 0;
163 int i, cnt, phase_0_raw_index = 0, phase_15_raw_index = 0;
164 bool phase_0_found = false, phase_15_found = false;
165 struct mmc_host *mmc = host->mmc;
167 if (!total_phases || (total_phases > MAX_PHASES)) {
168 dev_err(mmc_dev(mmc), "%s: Invalid argument: total_phases=%d\n",
169 mmc_hostname(mmc), total_phases);
173 for (cnt = 0; cnt < total_phases; cnt++) {
174 ranges[row_index][col_index] = phase_table[cnt];
175 phases_per_row[row_index] += 1;
178 if ((cnt + 1) == total_phases) {
180 /* check if next phase in phase_table is consecutive or not */
181 } else if ((phase_table[cnt] + 1) != phase_table[cnt + 1]) {
187 if (row_index >= MAX_PHASES)
190 /* Check if phase-0 is present in first valid window? */
192 phase_0_found = true;
193 phase_0_raw_index = 0;
194 /* Check if cycle exist between 2 valid windows */
195 for (cnt = 1; cnt <= row_index; cnt++) {
196 if (phases_per_row[cnt]) {
197 for (i = 0; i < phases_per_row[cnt]; i++) {
198 if (ranges[cnt][i] == 15) {
199 phase_15_found = true;
200 phase_15_raw_index = cnt;
208 /* If 2 valid windows form cycle then merge them as single window */
209 if (phase_0_found && phase_15_found) {
210 /* number of phases in raw where phase 0 is present */
211 u8 phases_0 = phases_per_row[phase_0_raw_index];
212 /* number of phases in raw where phase 15 is present */
213 u8 phases_15 = phases_per_row[phase_15_raw_index];
215 if (phases_0 + phases_15 >= MAX_PHASES)
217 * If there are more than 1 phase windows then total
218 * number of phases in both the windows should not be
219 * more than or equal to MAX_PHASES.
223 /* Merge 2 cyclic windows */
225 for (cnt = 0; cnt < phases_0; cnt++) {
226 ranges[phase_15_raw_index][i] =
227 ranges[phase_0_raw_index][cnt];
228 if (++i >= MAX_PHASES)
232 phases_per_row[phase_0_raw_index] = 0;
233 phases_per_row[phase_15_raw_index] = phases_15 + phases_0;
236 for (cnt = 0; cnt <= row_index; cnt++) {
237 if (phases_per_row[cnt] > curr_max) {
238 curr_max = phases_per_row[cnt];
239 selected_row_index = cnt;
243 i = (curr_max * 3) / 4;
247 ret = ranges[selected_row_index][i];
249 if (ret >= MAX_PHASES) {
251 dev_err(mmc_dev(mmc), "%s: Invalid phase selected=%d\n",
252 mmc_hostname(mmc), ret);
258 static inline void msm_cm_dll_set_freq(struct sdhci_host *host)
260 u32 mclk_freq = 0, config;
262 /* Program the MCLK value to MCLK_FREQ bit field */
263 if (host->clock <= 112000000)
265 else if (host->clock <= 125000000)
267 else if (host->clock <= 137000000)
269 else if (host->clock <= 150000000)
271 else if (host->clock <= 162000000)
273 else if (host->clock <= 175000000)
275 else if (host->clock <= 187000000)
277 else if (host->clock <= 200000000)
280 config = readl_relaxed(host->ioaddr + CORE_DLL_CONFIG);
281 config &= ~CMUX_SHIFT_PHASE_MASK;
282 config |= mclk_freq << CMUX_SHIFT_PHASE_SHIFT;
283 writel_relaxed(config, host->ioaddr + CORE_DLL_CONFIG);
286 /* Initialize the DLL (Programmable Delay Line) */
287 static int msm_init_cm_dll(struct sdhci_host *host)
289 struct mmc_host *mmc = host->mmc;
293 spin_lock_irqsave(&host->lock, flags);
296 * Make sure that clock is always enabled when DLL
297 * tuning is in progress. Keeping PWRSAVE ON may
298 * turn off the clock.
300 writel_relaxed((readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC)
301 & ~CORE_CLK_PWRSAVE), host->ioaddr + CORE_VENDOR_SPEC);
303 /* Write 1 to DLL_RST bit of DLL_CONFIG register */
304 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
305 | CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
307 /* Write 1 to DLL_PDN bit of DLL_CONFIG register */
308 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
309 | CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
310 msm_cm_dll_set_freq(host);
312 /* Write 0 to DLL_RST bit of DLL_CONFIG register */
313 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
314 & ~CORE_DLL_RST), host->ioaddr + CORE_DLL_CONFIG);
316 /* Write 0 to DLL_PDN bit of DLL_CONFIG register */
317 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
318 & ~CORE_DLL_PDN), host->ioaddr + CORE_DLL_CONFIG);
320 /* Set DLL_EN bit to 1. */
321 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
322 | CORE_DLL_EN), host->ioaddr + CORE_DLL_CONFIG);
324 /* Set CK_OUT_EN bit to 1. */
325 writel_relaxed((readl_relaxed(host->ioaddr + CORE_DLL_CONFIG)
326 | CORE_CK_OUT_EN), host->ioaddr + CORE_DLL_CONFIG);
328 /* Wait until DLL_LOCK bit of DLL_STATUS register becomes '1' */
329 while (!(readl_relaxed(host->ioaddr + CORE_DLL_STATUS) &
331 /* max. wait for 50us sec for LOCK bit to be set */
332 if (--wait_cnt == 0) {
333 dev_err(mmc_dev(mmc), "%s: DLL failed to LOCK\n",
335 spin_unlock_irqrestore(&host->lock, flags);
341 spin_unlock_irqrestore(&host->lock, flags);
345 static int sdhci_msm_execute_tuning(struct sdhci_host *host, u32 opcode)
347 int tuning_seq_cnt = 3;
348 u8 phase, tuned_phases[16], tuned_phase_cnt = 0;
350 struct mmc_host *mmc = host->mmc;
351 struct mmc_ios ios = host->mmc->ios;
354 * Tuning is required for SDR104, HS200 and HS400 cards and
355 * if clock frequency is greater than 100MHz in these modes.
357 if (host->clock <= 100 * 1000 * 1000 ||
358 !((ios.timing == MMC_TIMING_MMC_HS200) ||
359 (ios.timing == MMC_TIMING_UHS_SDR104)))
363 /* First of all reset the tuning block */
364 rc = msm_init_cm_dll(host);
370 /* Set the phase in delay line hw block */
371 rc = msm_config_cm_dll_phase(host, phase);
375 rc = mmc_send_tuning(mmc, opcode, NULL);
377 /* Tuning is successful at this tuning point */
378 tuned_phases[tuned_phase_cnt++] = phase;
379 dev_dbg(mmc_dev(mmc), "%s: Found good phase = %d\n",
380 mmc_hostname(mmc), phase);
382 } while (++phase < ARRAY_SIZE(tuned_phases));
384 if (tuned_phase_cnt) {
385 rc = msm_find_most_appropriate_phase(host, tuned_phases,
393 * Finally set the selected phase in delay
396 rc = msm_config_cm_dll_phase(host, phase);
399 dev_dbg(mmc_dev(mmc), "%s: Setting the tuning phase to %d\n",
400 mmc_hostname(mmc), phase);
402 if (--tuning_seq_cnt)
405 dev_dbg(mmc_dev(mmc), "%s: No tuning point found\n",
413 static const struct of_device_id sdhci_msm_dt_match[] = {
414 { .compatible = "qcom,sdhci-msm-v4" },
418 MODULE_DEVICE_TABLE(of, sdhci_msm_dt_match);
420 static const struct sdhci_ops sdhci_msm_ops = {
421 .platform_execute_tuning = sdhci_msm_execute_tuning,
422 .reset = sdhci_reset,
423 .set_clock = sdhci_set_clock,
424 .set_bus_width = sdhci_set_bus_width,
425 .set_uhs_signaling = sdhci_set_uhs_signaling,
428 static const struct sdhci_pltfm_data sdhci_msm_pdata = {
429 .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
430 SDHCI_QUIRK_SINGLE_POWER_WRITE |
431 SDHCI_QUIRK_NO_CARD_NO_RESET,
432 .ops = &sdhci_msm_ops,
435 static int sdhci_msm_probe(struct platform_device *pdev)
437 struct sdhci_host *host;
438 struct sdhci_pltfm_host *pltfm_host;
439 struct sdhci_msm_host *msm_host;
440 struct resource *core_memres;
442 u16 host_version, core_minor;
443 u32 core_version, caps;
446 host = sdhci_pltfm_init(pdev, &sdhci_msm_pdata, sizeof(*msm_host));
448 return PTR_ERR(host);
450 pltfm_host = sdhci_priv(host);
451 msm_host = sdhci_pltfm_priv(pltfm_host);
452 msm_host->mmc = host->mmc;
453 msm_host->pdev = pdev;
455 ret = mmc_of_parse(host->mmc);
459 sdhci_get_of_property(pdev);
461 /* Setup SDCC bus voter clock. */
462 msm_host->bus_clk = devm_clk_get(&pdev->dev, "bus");
463 if (!IS_ERR(msm_host->bus_clk)) {
464 /* Vote for max. clk rate for max. performance */
465 ret = clk_set_rate(msm_host->bus_clk, INT_MAX);
468 ret = clk_prepare_enable(msm_host->bus_clk);
473 /* Setup main peripheral bus clock */
474 msm_host->pclk = devm_clk_get(&pdev->dev, "iface");
475 if (IS_ERR(msm_host->pclk)) {
476 ret = PTR_ERR(msm_host->pclk);
477 dev_err(&pdev->dev, "Perpheral clk setup failed (%d)\n", ret);
478 goto bus_clk_disable;
481 ret = clk_prepare_enable(msm_host->pclk);
483 goto bus_clk_disable;
485 /* Setup SDC MMC clock */
486 msm_host->clk = devm_clk_get(&pdev->dev, "core");
487 if (IS_ERR(msm_host->clk)) {
488 ret = PTR_ERR(msm_host->clk);
489 dev_err(&pdev->dev, "SDC MMC clk setup failed (%d)\n", ret);
493 /* Vote for maximum clock rate for maximum performance */
494 ret = clk_set_rate(msm_host->clk, INT_MAX);
496 dev_warn(&pdev->dev, "core clock boost failed\n");
498 ret = clk_prepare_enable(msm_host->clk);
502 core_memres = platform_get_resource(pdev, IORESOURCE_MEM, 1);
503 msm_host->core_mem = devm_ioremap_resource(&pdev->dev, core_memres);
505 if (IS_ERR(msm_host->core_mem)) {
506 dev_err(&pdev->dev, "Failed to remap registers\n");
507 ret = PTR_ERR(msm_host->core_mem);
511 /* Reset the core and Enable SDHC mode */
512 writel_relaxed(readl_relaxed(msm_host->core_mem + CORE_POWER) |
513 CORE_SW_RST, msm_host->core_mem + CORE_POWER);
515 /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
516 usleep_range(1000, 5000);
517 if (readl(msm_host->core_mem + CORE_POWER) & CORE_SW_RST) {
518 dev_err(&pdev->dev, "Stuck in reset\n");
523 /* Set HC_MODE_EN bit in HC_MODE register */
524 writel_relaxed(HC_MODE_EN, (msm_host->core_mem + CORE_HC_MODE));
526 host_version = readw_relaxed((host->ioaddr + SDHCI_HOST_VERSION));
527 dev_dbg(&pdev->dev, "Host Version: 0x%x Vendor Version 0x%x\n",
528 host_version, ((host_version & SDHCI_VENDOR_VER_MASK) >>
529 SDHCI_VENDOR_VER_SHIFT));
531 core_version = readl_relaxed(msm_host->core_mem + CORE_MCI_VERSION);
532 core_major = (core_version & CORE_VERSION_MAJOR_MASK) >>
533 CORE_VERSION_MAJOR_SHIFT;
534 core_minor = core_version & CORE_VERSION_MINOR_MASK;
535 dev_dbg(&pdev->dev, "MCI Version: 0x%08x, major: 0x%04x, minor: 0x%02x\n",
536 core_version, core_major, core_minor);
539 * Support for some capabilities is not advertised by newer
540 * controller versions and must be explicitly enabled.
542 if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
543 caps = readl_relaxed(host->ioaddr + SDHCI_CAPABILITIES);
544 caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
545 writel_relaxed(caps, host->ioaddr +
546 CORE_VENDOR_SPEC_CAPABILITIES0);
549 ret = sdhci_add_host(host);
556 clk_disable_unprepare(msm_host->clk);
558 clk_disable_unprepare(msm_host->pclk);
560 if (!IS_ERR(msm_host->bus_clk))
561 clk_disable_unprepare(msm_host->bus_clk);
563 sdhci_pltfm_free(pdev);
567 static int sdhci_msm_remove(struct platform_device *pdev)
569 struct sdhci_host *host = platform_get_drvdata(pdev);
570 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
571 struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
572 int dead = (readl_relaxed(host->ioaddr + SDHCI_INT_STATUS) ==
575 sdhci_remove_host(host, dead);
576 clk_disable_unprepare(msm_host->clk);
577 clk_disable_unprepare(msm_host->pclk);
578 if (!IS_ERR(msm_host->bus_clk))
579 clk_disable_unprepare(msm_host->bus_clk);
580 sdhci_pltfm_free(pdev);
584 static struct platform_driver sdhci_msm_driver = {
585 .probe = sdhci_msm_probe,
586 .remove = sdhci_msm_remove,
589 .of_match_table = sdhci_msm_dt_match,
593 module_platform_driver(sdhci_msm_driver);
595 MODULE_DESCRIPTION("Qualcomm Secure Digital Host Controller Interface driver");
596 MODULE_LICENSE("GPL v2");