drivers/mmc/host/sdhci.c

   1 /*
   2  *  linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
   3  *
   4  *  Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or (at
   9  * your option) any later version.
  10  *
  11  * Thanks to the following companies for their support:
  12  *
  13  *     - JMicron (hardware and technical support)
  14  */
  15
  16 #include <linux/delay.h>
  17 #include <linux/highmem.h>
  18 #include <linux/io.h>
  19 #include <linux/module.h>
  20 #include <linux/dma-mapping.h>
  21 #include <linux/slab.h>
  22 #include <linux/scatterlist.h>
  23 #include <linux/regulator/consumer.h>
  24 #include <linux/pm_runtime.h>
  25
  26 #include <linux/leds.h>
  27
  28 #include <linux/mmc/mmc.h>
  29 #include <linux/mmc/host.h>
  30 #include <linux/mmc/card.h>
  31 #include <linux/mmc/slot-gpio.h>
  32
  33 #include "sdhci.h"
  34
  35 #define DRIVER_NAME "sdhci"
  36
  37 #define DBG(f, x...) \
  38         pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
  39
  40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
  41         defined(CONFIG_MMC_SDHCI_MODULE))
  42 #define SDHCI_USE_LEDS_CLASS
  43 #endif
  44
  45 #define MAX_TUNING_LOOP 40
  46
  47 #define ADMA_SIZE       ((128 * 2 + 1) * 4)
  48
  49 static unsigned int debug_quirks = 0;
  50 static unsigned int debug_quirks2;
  51
  52 static void sdhci_finish_data(struct sdhci_host *);
  53
  54 static void sdhci_finish_command(struct sdhci_host *);
  55 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
  56 static void sdhci_tuning_timer(unsigned long data);
  57 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
  58
  59 #ifdef CONFIG_PM_RUNTIME
  60 static int sdhci_runtime_pm_get(struct sdhci_host *host);
  61 static int sdhci_runtime_pm_put(struct sdhci_host *host);
  62 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
  63 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
  64 #else
  65 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
  66 {
  67         return 0;
  68 }
  69 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
  70 {
  71         return 0;
  72 }
  73 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
  74 {
  75 }
  76 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
  77 {
  78 }
  79 #endif
  80
  81 static void sdhci_dumpregs(struct sdhci_host *host)
  82 {
  83         pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
  84                 mmc_hostname(host->mmc));
  85
  86         pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version:  0x%08x\n",
  87                 sdhci_readl(host, SDHCI_DMA_ADDRESS),
  88                 sdhci_readw(host, SDHCI_HOST_VERSION));
  89         pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt:  0x%08x\n",
  90                 sdhci_readw(host, SDHCI_BLOCK_SIZE),
  91                 sdhci_readw(host, SDHCI_BLOCK_COUNT));
  92         pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
  93                 sdhci_readl(host, SDHCI_ARGUMENT),
  94                 sdhci_readw(host, SDHCI_TRANSFER_MODE));
  95         pr_debug(DRIVER_NAME ": Present:  0x%08x | Host ctl: 0x%08x\n",
  96                 sdhci_readl(host, SDHCI_PRESENT_STATE),
  97                 sdhci_readb(host, SDHCI_HOST_CONTROL));
  98         pr_debug(DRIVER_NAME ": Power:    0x%08x | Blk gap:  0x%08x\n",
  99                 sdhci_readb(host, SDHCI_POWER_CONTROL),
 100                 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
 101         pr_debug(DRIVER_NAME ": Wake-up:  0x%08x | Clock:    0x%08x\n",
 102                 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
 103                 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
 104         pr_debug(DRIVER_NAME ": Timeout:  0x%08x | Int stat: 0x%08x\n",
 105                 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
 106                 sdhci_readl(host, SDHCI_INT_STATUS));
 107         pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
 108                 sdhci_readl(host, SDHCI_INT_ENABLE),
 109                 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
 110         pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
 111                 sdhci_readw(host, SDHCI_ACMD12_ERR),
 112                 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
 113         pr_debug(DRIVER_NAME ": Caps:     0x%08x | Caps_1:   0x%08x\n",
 114                 sdhci_readl(host, SDHCI_CAPABILITIES),
 115                 sdhci_readl(host, SDHCI_CAPABILITIES_1));
 116         pr_debug(DRIVER_NAME ": Cmd:      0x%08x | Max curr: 0x%08x\n",
 117                 sdhci_readw(host, SDHCI_COMMAND),
 118                 sdhci_readl(host, SDHCI_MAX_CURRENT));
 119         pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
 120                 sdhci_readw(host, SDHCI_HOST_CONTROL2));
 121
 122         if (host->flags & SDHCI_USE_ADMA)
 123                 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
 124                        readl(host->ioaddr + SDHCI_ADMA_ERROR),
 125                        readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
 126
 127         pr_debug(DRIVER_NAME ": ===========================================\n");
 128 }
 129
 130 /*****************************************************************************\
 131  *                                                                           *
 132  * Low level functions                                                       *
 133  *                                                                           *
 134 \*****************************************************************************/
 135
 136 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
 137 {
 138         u32 present;
 139
 140         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
 141             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
 142                 return;
 143
 144         if (enable) {
 145                 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
 146                                       SDHCI_CARD_PRESENT;
 147
 148                 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
 149                                        SDHCI_INT_CARD_INSERT;
 150         } else {
 151                 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
 152         }
 153
 154         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 155         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 156 }
 157
 158 static void sdhci_enable_card_detection(struct sdhci_host *host)
 159 {
 160         sdhci_set_card_detection(host, true);
 161 }
 162
 163 static void sdhci_disable_card_detection(struct sdhci_host *host)
 164 {
 165         sdhci_set_card_detection(host, false);
 166 }
 167
 168 void sdhci_reset(struct sdhci_host *host, u8 mask)
 169 {
 170         unsigned long timeout;
 171
 172         sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
 173
 174         if (mask & SDHCI_RESET_ALL) {
 175                 host->clock = 0;
 176                 /* Reset-all turns off SD Bus Power */
 177                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
 178                         sdhci_runtime_pm_bus_off(host);
 179         }
 180
 181         /* Wait max 100 ms */
 182         timeout = 100;
 183
 184         /* hw clears the bit when it's done */
 185         while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
 186                 if (timeout == 0) {
 187                         pr_err("%s: Reset 0x%x never completed.\n",
 188                                 mmc_hostname(host->mmc), (int)mask);
 189                         sdhci_dumpregs(host);
 190                         return;
 191                 }
 192                 timeout--;
 193                 mdelay(1);
 194         }
 195 }
 196 EXPORT_SYMBOL_GPL(sdhci_reset);
 197
 198 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
 199 {
 200         if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
 201                 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
 202                         SDHCI_CARD_PRESENT))
 203                         return;
 204         }
 205
 206         host->ops->reset(host, mask);
 207
 208         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
 209                 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
 210                         host->ops->enable_dma(host);
 211         }
 212 }
 213
 214 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
 215
 216 static void sdhci_init(struct sdhci_host *host, int soft)
 217 {
 218         if (soft)
 219                 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
 220         else
 221                 sdhci_do_reset(host, SDHCI_RESET_ALL);
 222
 223         host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
 224                     SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
 225                     SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
 226                     SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
 227                     SDHCI_INT_RESPONSE;
 228
 229         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 230         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 231
 232         if (soft) {
 233                 /* force clock reconfiguration */
 234                 host->clock = 0;
 235                 sdhci_set_ios(host->mmc, &host->mmc->ios);
 236         }
 237 }
 238
 239 static void sdhci_reinit(struct sdhci_host *host)
 240 {
 241         sdhci_init(host, 0);
 242         /*
 243          * Retuning stuffs are affected by different cards inserted and only
 244          * applicable to UHS-I cards. So reset these fields to their initial
 245          * value when card is removed.
 246          */
 247         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
 248                 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
 249
 250                 del_timer_sync(&host->tuning_timer);
 251                 host->flags &= ~SDHCI_NEEDS_RETUNING;
 252                 host->mmc->max_blk_count =
 253                         (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
 254         }
 255         sdhci_enable_card_detection(host);
 256 }
 257
 258 static void sdhci_activate_led(struct sdhci_host *host)
 259 {
 260         u8 ctrl;
 261
 262         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 263         ctrl |= SDHCI_CTRL_LED;
 264         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 265 }
 266
 267 static void sdhci_deactivate_led(struct sdhci_host *host)
 268 {
 269         u8 ctrl;
 270
 271         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 272         ctrl &= ~SDHCI_CTRL_LED;
 273         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 274 }
 275
 276 #ifdef SDHCI_USE_LEDS_CLASS
 277 static void sdhci_led_control(struct led_classdev *led,
 278         enum led_brightness brightness)
 279 {
 280         struct sdhci_host *host = container_of(led, struct sdhci_host, led);
 281         unsigned long flags;
 282
 283         spin_lock_irqsave(&host->lock, flags);
 284
 285         if (host->runtime_suspended)
 286                 goto out;
 287
 288         if (brightness == LED_OFF)
 289                 sdhci_deactivate_led(host);
 290         else
 291                 sdhci_activate_led(host);
 292 out:
 293         spin_unlock_irqrestore(&host->lock, flags);
 294 }
 295 #endif
 296
 297 /*****************************************************************************\
 298  *                                                                           *
 299  * Core functions                                                            *
 300  *                                                                           *
 301 \*****************************************************************************/
 302
 303 static void sdhci_read_block_pio(struct sdhci_host *host)
 304 {
 305         unsigned long flags;
 306         size_t blksize, len, chunk;
 307         u32 uninitialized_var(scratch);
 308         u8 *buf;
 309
 310         DBG("PIO reading\n");
 311
 312         blksize = host->data->blksz;
 313         chunk = 0;
 314
 315         local_irq_save(flags);
 316
 317         while (blksize) {
 318                 if (!sg_miter_next(&host->sg_miter))
 319                         BUG();
 320
 321                 len = min(host->sg_miter.length, blksize);
 322
 323                 blksize -= len;
 324                 host->sg_miter.consumed = len;
 325
 326                 buf = host->sg_miter.addr;
 327
 328                 while (len) {
 329                         if (chunk == 0) {
 330                                 scratch = sdhci_readl(host, SDHCI_BUFFER);
 331                                 chunk = 4;
 332                         }
 333
 334                         *buf = scratch & 0xFF;
 335
 336                         buf++;
 337                         scratch >>= 8;
 338                         chunk--;
 339                         len--;
 340                 }
 341         }
 342
 343         sg_miter_stop(&host->sg_miter);
 344
 345         local_irq_restore(flags);
 346 }
 347
 348 static void sdhci_write_block_pio(struct sdhci_host *host)
 349 {
 350         unsigned long flags;
 351         size_t blksize, len, chunk;
 352         u32 scratch;
 353         u8 *buf;
 354
 355         DBG("PIO writing\n");
 356
 357         blksize = host->data->blksz;
 358         chunk = 0;
 359         scratch = 0;
 360
 361         local_irq_save(flags);
 362
 363         while (blksize) {
 364                 if (!sg_miter_next(&host->sg_miter))
 365                         BUG();
 366
 367                 len = min(host->sg_miter.length, blksize);
 368
 369                 blksize -= len;
 370                 host->sg_miter.consumed = len;
 371
 372                 buf = host->sg_miter.addr;
 373
 374                 while (len) {
 375                         scratch |= (u32)*buf << (chunk * 8);
 376
 377                         buf++;
 378                         chunk++;
 379                         len--;
 380
 381                         if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
 382                                 sdhci_writel(host, scratch, SDHCI_BUFFER);
 383                                 chunk = 0;
 384                                 scratch = 0;
 385                         }
 386                 }
 387         }
 388
 389         sg_miter_stop(&host->sg_miter);
 390
 391         local_irq_restore(flags);
 392 }
 393
 394 static void sdhci_transfer_pio(struct sdhci_host *host)
 395 {
 396         u32 mask;
 397
 398         BUG_ON(!host->data);
 399
 400         if (host->blocks == 0)
 401                 return;
 402
 403         if (host->data->flags & MMC_DATA_READ)
 404                 mask = SDHCI_DATA_AVAILABLE;
 405         else
 406                 mask = SDHCI_SPACE_AVAILABLE;
 407
 408         /*
 409          * Some controllers (JMicron JMB38x) mess up the buffer bits
 410          * for transfers < 4 bytes. As long as it is just one block,
 411          * we can ignore the bits.
 412          */
 413         if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
 414                 (host->data->blocks == 1))
 415                 mask = ~0;
 416
 417         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 418                 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
 419                         udelay(100);
 420
 421                 if (host->data->flags & MMC_DATA_READ)
 422                         sdhci_read_block_pio(host);
 423                 else
 424                         sdhci_write_block_pio(host);
 425
 426                 host->blocks--;
 427                 if (host->blocks == 0)
 428                         break;
 429         }
 430
 431         DBG("PIO transfer complete.\n");
 432 }
 433
 434 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
 435 {
 436         local_irq_save(*flags);
 437         return kmap_atomic(sg_page(sg)) + sg->offset;
 438 }
 439
 440 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
 441 {
 442         kunmap_atomic(buffer);
 443         local_irq_restore(*flags);
 444 }
 445
 446 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
 447 {
 448         __le32 *dataddr = (__le32 __force *)(desc + 4);
 449         __le16 *cmdlen = (__le16 __force *)desc;
 450
 451         /* SDHCI specification says ADMA descriptors should be 4 byte
 452          * aligned, so using 16 or 32bit operations should be safe. */
 453
 454         cmdlen[0] = cpu_to_le16(cmd);
 455         cmdlen[1] = cpu_to_le16(len);
 456
 457         dataddr[0] = cpu_to_le32(addr);
 458 }
 459
 460 static int sdhci_adma_table_pre(struct sdhci_host *host,
 461         struct mmc_data *data)
 462 {
 463         int direction;
 464
 465         u8 *desc;
 466         u8 *align;
 467         dma_addr_t addr;
 468         dma_addr_t align_addr;
 469         int len, offset;
 470
 471         struct scatterlist *sg;
 472         int i;
 473         char *buffer;
 474         unsigned long flags;
 475
 476         /*
 477          * The spec does not specify endianness of descriptor table.
 478          * We currently guess that it is LE.
 479          */
 480
 481         if (data->flags & MMC_DATA_READ)
 482                 direction = DMA_FROM_DEVICE;
 483         else
 484                 direction = DMA_TO_DEVICE;
 485
 486         host->align_addr = dma_map_single(mmc_dev(host->mmc),
 487                 host->align_buffer, 128 * 4, direction);
 488         if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
 489                 goto fail;
 490         BUG_ON(host->align_addr & 0x3);
 491
 492         host->sg_count = dma_map_sg(mmc_dev(host->mmc),
 493                 data->sg, data->sg_len, direction);
 494         if (host->sg_count == 0)
 495                 goto unmap_align;
 496
 497         desc = host->adma_desc;
 498         align = host->align_buffer;
 499
 500         align_addr = host->align_addr;
 501
 502         for_each_sg(data->sg, sg, host->sg_count, i) {
 503                 addr = sg_dma_address(sg);
 504                 len = sg_dma_len(sg);
 505
 506                 /*
 507                  * The SDHCI specification states that ADMA
 508                  * addresses must be 32-bit aligned. If they
 509                  * aren't, then we use a bounce buffer for
 510                  * the (up to three) bytes that screw up the
 511                  * alignment.
 512                  */
 513                 offset = (4 - (addr & 0x3)) & 0x3;
 514                 if (offset) {
 515                         if (data->flags & MMC_DATA_WRITE) {
 516                                 buffer = sdhci_kmap_atomic(sg, &flags);
 517                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 518                                 memcpy(align, buffer, offset);
 519                                 sdhci_kunmap_atomic(buffer, &flags);
 520                         }
 521
 522                         /* tran, valid */
 523                         sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
 524
 525                         BUG_ON(offset > 65536);
 526
 527                         align += 4;
 528                         align_addr += 4;
 529
 530                         desc += 8;
 531
 532                         addr += offset;
 533                         len -= offset;
 534                 }
 535
 536                 BUG_ON(len > 65536);
 537
 538                 /* tran, valid */
 539                 sdhci_set_adma_desc(desc, addr, len, 0x21);
 540                 desc += 8;
 541
 542                 /*
 543                  * If this triggers then we have a calculation bug
 544                  * somewhere. :/
 545                  */
 546                 WARN_ON((desc - host->adma_desc) > ADMA_SIZE);
 547         }
 548
 549         if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
 550                 /*
 551                 * Mark the last descriptor as the terminating descriptor
 552                 */
 553                 if (desc != host->adma_desc) {
 554                         desc -= 8;
 555                         desc[0] |= 0x2; /* end */
 556                 }
 557         } else {
 558                 /*
 559                 * Add a terminating entry.
 560                 */
 561
 562                 /* nop, end, valid */
 563                 sdhci_set_adma_desc(desc, 0, 0, 0x3);
 564         }
 565
 566         /*
 567          * Resync align buffer as we might have changed it.
 568          */
 569         if (data->flags & MMC_DATA_WRITE) {
 570                 dma_sync_single_for_device(mmc_dev(host->mmc),
 571                         host->align_addr, 128 * 4, direction);
 572         }
 573
 574         return 0;
 575
 576 unmap_align:
 577         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 578                 128 * 4, direction);
 579 fail:
 580         return -EINVAL;
 581 }
 582
 583 static void sdhci_adma_table_post(struct sdhci_host *host,
 584         struct mmc_data *data)
 585 {
 586         int direction;
 587
 588         struct scatterlist *sg;
 589         int i, size;
 590         u8 *align;
 591         char *buffer;
 592         unsigned long flags;
 593         bool has_unaligned;
 594
 595         if (data->flags & MMC_DATA_READ)
 596                 direction = DMA_FROM_DEVICE;
 597         else
 598                 direction = DMA_TO_DEVICE;
 599
 600         dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
 601                 128 * 4, direction);
 602
 603         /* Do a quick scan of the SG list for any unaligned mappings */
 604         has_unaligned = false;
 605         for_each_sg(data->sg, sg, host->sg_count, i)
 606                 if (sg_dma_address(sg) & 3) {
 607                         has_unaligned = true;
 608                         break;
 609                 }
 610
 611         if (has_unaligned && data->flags & MMC_DATA_READ) {
 612                 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
 613                         data->sg_len, direction);
 614
 615                 align = host->align_buffer;
 616
 617                 for_each_sg(data->sg, sg, host->sg_count, i) {
 618                         if (sg_dma_address(sg) & 0x3) {
 619                                 size = 4 - (sg_dma_address(sg) & 0x3);
 620
 621                                 buffer = sdhci_kmap_atomic(sg, &flags);
 622                                 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
 623                                 memcpy(buffer, align, size);
 624                                 sdhci_kunmap_atomic(buffer, &flags);
 625
 626                                 align += 4;
 627                         }
 628                 }
 629         }
 630
 631         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 632                 data->sg_len, direction);
 633 }
 634
 635 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
 636 {
 637         u8 count;
 638         struct mmc_data *data = cmd->data;
 639         unsigned target_timeout, current_timeout;
 640
 641         /*
 642          * If the host controller provides us with an incorrect timeout
 643          * value, just skip the check and use 0xE.  The hardware may take
 644          * longer to time out, but that's much better than having a too-short
 645          * timeout value.
 646          */
 647         if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
 648                 return 0xE;
 649
 650         /* Unspecified timeout, assume max */
 651         if (!data && !cmd->busy_timeout)
 652                 return 0xE;
 653
 654         /* timeout in us */
 655         if (!data)
 656                 target_timeout = cmd->busy_timeout * 1000;
 657         else {
 658                 target_timeout = data->timeout_ns / 1000;
 659                 if (host->clock)
 660                         target_timeout += data->timeout_clks / host->clock;
 661         }
 662
 663         /*
 664          * Figure out needed cycles.
 665          * We do this in steps in order to fit inside a 32 bit int.
 666          * The first step is the minimum timeout, which will have a
 667          * minimum resolution of 6 bits:
 668          * (1) 2^13*1000 > 2^22,
 669          * (2) host->timeout_clk < 2^16
 670          *     =>
 671          *     (1) / (2) > 2^6
 672          */
 673         count = 0;
 674         current_timeout = (1 << 13) * 1000 / host->timeout_clk;
 675         while (current_timeout < target_timeout) {
 676                 count++;
 677                 current_timeout <<= 1;
 678                 if (count >= 0xF)
 679                         break;
 680         }
 681
 682         if (count >= 0xF) {
 683                 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
 684                     mmc_hostname(host->mmc), count, cmd->opcode);
 685                 count = 0xE;
 686         }
 687
 688         return count;
 689 }
 690
 691 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
 692 {
 693         u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
 694         u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
 695
 696         if (host->flags & SDHCI_REQ_USE_DMA)
 697                 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
 698         else
 699                 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
 700
 701         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
 702         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
 703 }
 704
 705 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
 706 {
 707         u8 count;
 708         u8 ctrl;
 709         struct mmc_data *data = cmd->data;
 710         int ret;
 711
 712         WARN_ON(host->data);
 713
 714         if (data || (cmd->flags & MMC_RSP_BUSY)) {
 715                 count = sdhci_calc_timeout(host, cmd);
 716                 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
 717         }
 718
 719         if (!data)
 720                 return;
 721
 722         /* Sanity checks */
 723         BUG_ON(data->blksz * data->blocks > 524288);
 724         BUG_ON(data->blksz > host->mmc->max_blk_size);
 725         BUG_ON(data->blocks > 65535);
 726
 727         host->data = data;
 728         host->data_early = 0;
 729         host->data->bytes_xfered = 0;
 730
 731         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
 732                 host->flags |= SDHCI_REQ_USE_DMA;
 733
 734         /*
 735          * FIXME: This doesn't account for merging when mapping the
 736          * scatterlist.
 737          */
 738         if (host->flags & SDHCI_REQ_USE_DMA) {
 739                 int broken, i;
 740                 struct scatterlist *sg;
 741
 742                 broken = 0;
 743                 if (host->flags & SDHCI_USE_ADMA) {
 744                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 745                                 broken = 1;
 746                 } else {
 747                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
 748                                 broken = 1;
 749                 }
 750
 751                 if (unlikely(broken)) {
 752                         for_each_sg(data->sg, sg, data->sg_len, i) {
 753                                 if (sg->length & 0x3) {
 754                                         DBG("Reverting to PIO because of "
 755                                                 "transfer size (%d)\n",
 756                                                 sg->length);
 757                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 758                                         break;
 759                                 }
 760                         }
 761                 }
 762         }
 763
 764         /*
 765          * The assumption here being that alignment is the same after
 766          * translation to device address space.
 767          */
 768         if (host->flags & SDHCI_REQ_USE_DMA) {
 769                 int broken, i;
 770                 struct scatterlist *sg;
 771
 772                 broken = 0;
 773                 if (host->flags & SDHCI_USE_ADMA) {
 774                         /*
 775                          * As we use 3 byte chunks to work around
 776                          * alignment problems, we need to check this
 777                          * quirk.
 778                          */
 779                         if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
 780                                 broken = 1;
 781                 } else {
 782                         if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
 783                                 broken = 1;
 784                 }
 785
 786                 if (unlikely(broken)) {
 787                         for_each_sg(data->sg, sg, data->sg_len, i) {
 788                                 if (sg->offset & 0x3) {
 789                                         DBG("Reverting to PIO because of "
 790                                                 "bad alignment\n");
 791                                         host->flags &= ~SDHCI_REQ_USE_DMA;
 792                                         break;
 793                                 }
 794                         }
 795                 }
 796         }
 797
 798         if (host->flags & SDHCI_REQ_USE_DMA) {
 799                 if (host->flags & SDHCI_USE_ADMA) {
 800                         ret = sdhci_adma_table_pre(host, data);
 801                         if (ret) {
 802                                 /*
 803                                  * This only happens when someone fed
 804                                  * us an invalid request.
 805                                  */
 806                                 WARN_ON(1);
 807                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 808                         } else {
 809                                 sdhci_writel(host, host->adma_addr,
 810                                         SDHCI_ADMA_ADDRESS);
 811                         }
 812                 } else {
 813                         int sg_cnt;
 814
 815                         sg_cnt = dma_map_sg(mmc_dev(host->mmc),
 816                                         data->sg, data->sg_len,
 817                                         (data->flags & MMC_DATA_READ) ?
 818                                                 DMA_FROM_DEVICE :
 819                                                 DMA_TO_DEVICE);
 820                         if (sg_cnt == 0) {
 821                                 /*
 822                                  * This only happens when someone fed
 823                                  * us an invalid request.
 824                                  */
 825                                 WARN_ON(1);
 826                                 host->flags &= ~SDHCI_REQ_USE_DMA;
 827                         } else {
 828                                 WARN_ON(sg_cnt != 1);
 829                                 sdhci_writel(host, sg_dma_address(data->sg),
 830                                         SDHCI_DMA_ADDRESS);
 831                         }
 832                 }
 833         }
 834
 835         /*
 836          * Always adjust the DMA selection as some controllers
 837          * (e.g. JMicron) can't do PIO properly when the selection
 838          * is ADMA.
 839          */
 840         if (host->version >= SDHCI_SPEC_200) {
 841                 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
 842                 ctrl &= ~SDHCI_CTRL_DMA_MASK;
 843                 if ((host->flags & SDHCI_REQ_USE_DMA) &&
 844                         (host->flags & SDHCI_USE_ADMA))
 845                         ctrl |= SDHCI_CTRL_ADMA32;
 846                 else
 847                         ctrl |= SDHCI_CTRL_SDMA;
 848                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
 849         }
 850
 851         if (!(host->flags & SDHCI_REQ_USE_DMA)) {
 852                 int flags;
 853
 854                 flags = SG_MITER_ATOMIC;
 855                 if (host->data->flags & MMC_DATA_READ)
 856                         flags |= SG_MITER_TO_SG;
 857                 else
 858                         flags |= SG_MITER_FROM_SG;
 859                 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
 860                 host->blocks = data->blocks;
 861         }
 862
 863         sdhci_set_transfer_irqs(host);
 864
 865         /* Set the DMA boundary value and block size */
 866         sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
 867                 data->blksz), SDHCI_BLOCK_SIZE);
 868         sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
 869 }
 870
 871 static void sdhci_set_transfer_mode(struct sdhci_host *host,
 872         struct mmc_command *cmd)
 873 {
 874         u16 mode;
 875         struct mmc_data *data = cmd->data;
 876
 877         if (data == NULL) {
 878                 /* clear Auto CMD settings for no data CMDs */
 879                 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
 880                 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
 881                                 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
 882                 return;
 883         }
 884
 885         WARN_ON(!host->data);
 886
 887         mode = SDHCI_TRNS_BLK_CNT_EN;
 888         if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
 889                 mode |= SDHCI_TRNS_MULTI;
 890                 /*
 891                  * If we are sending CMD23, CMD12 never gets sent
 892                  * on successful completion (so no Auto-CMD12).
 893                  */
 894                 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
 895                         mode |= SDHCI_TRNS_AUTO_CMD12;
 896                 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
 897                         mode |= SDHCI_TRNS_AUTO_CMD23;
 898                         sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
 899                 }
 900         }
 901
 902         if (data->flags & MMC_DATA_READ)
 903                 mode |= SDHCI_TRNS_READ;
 904         if (host->flags & SDHCI_REQ_USE_DMA)
 905                 mode |= SDHCI_TRNS_DMA;
 906
 907         sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
 908 }
 909
 910 static void sdhci_finish_data(struct sdhci_host *host)
 911 {
 912         struct mmc_data *data;
 913
 914         BUG_ON(!host->data);
 915
 916         data = host->data;
 917         host->data = NULL;
 918
 919         if (host->flags & SDHCI_REQ_USE_DMA) {
 920                 if (host->flags & SDHCI_USE_ADMA)
 921                         sdhci_adma_table_post(host, data);
 922                 else {
 923                         dma_unmap_sg(mmc_dev(host->mmc), data->sg,
 924                                 data->sg_len, (data->flags & MMC_DATA_READ) ?
 925                                         DMA_FROM_DEVICE : DMA_TO_DEVICE);
 926                 }
 927         }
 928
 929         /*
 930          * The specification states that the block count register must
 931          * be updated, but it does not specify at what point in the
 932          * data flow. That makes the register entirely useless to read
 933          * back so we have to assume that nothing made it to the card
 934          * in the event of an error.
 935          */
 936         if (data->error)
 937                 data->bytes_xfered = 0;
 938         else
 939                 data->bytes_xfered = data->blksz * data->blocks;
 940
 941         /*
 942          * Need to send CMD12 if -
 943          * a) open-ended multiblock transfer (no CMD23)
 944          * b) error in multiblock transfer
 945          */
 946         if (data->stop &&
 947             (data->error ||
 948              !host->mrq->sbc)) {
 949
 950                 /*
 951                  * The controller needs a reset of internal state machines
 952                  * upon error conditions.
 953                  */
 954                 if (data->error) {
 955                         sdhci_do_reset(host, SDHCI_RESET_CMD);
 956                         sdhci_do_reset(host, SDHCI_RESET_DATA);
 957                 }
 958
 959                 sdhci_send_command(host, data->stop);
 960         } else
 961                 tasklet_schedule(&host->finish_tasklet);
 962 }
 963
 964 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
 965 {
 966         int flags;
 967         u32 mask;
 968         unsigned long timeout;
 969
 970         WARN_ON(host->cmd);
 971
 972         /* Wait max 10 ms */
 973         timeout = 10;
 974
 975         mask = SDHCI_CMD_INHIBIT;
 976         if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
 977                 mask |= SDHCI_DATA_INHIBIT;
 978
 979         /* We shouldn't wait for data inihibit for stop commands, even
 980            though they might use busy signaling */
 981         if (host->mrq->data && (cmd == host->mrq->data->stop))
 982                 mask &= ~SDHCI_DATA_INHIBIT;
 983
 984         while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
 985                 if (timeout == 0) {
 986                         pr_err("%s: Controller never released "
 987                                 "inhibit bit(s).\n", mmc_hostname(host->mmc));
 988                         sdhci_dumpregs(host);
 989                         cmd->error = -EIO;
 990                         tasklet_schedule(&host->finish_tasklet);
 991                         return;
 992                 }
 993                 timeout--;
 994                 mdelay(1);
 995         }
 996
 997         timeout = jiffies;
 998         if (!cmd->data && cmd->busy_timeout > 9000)
 999                 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1000         else
1001                 timeout += 10 * HZ;
1002         mod_timer(&host->timer, timeout);
1003
1004         host->cmd = cmd;
1005
1006         sdhci_prepare_data(host, cmd);
1007
1008         sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1009
1010         sdhci_set_transfer_mode(host, cmd);
1011
1012         if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1013                 pr_err("%s: Unsupported response type!\n",
1014                         mmc_hostname(host->mmc));
1015                 cmd->error = -EINVAL;
1016                 tasklet_schedule(&host->finish_tasklet);
1017                 return;
1018         }
1019
1020         if (!(cmd->flags & MMC_RSP_PRESENT))
1021                 flags = SDHCI_CMD_RESP_NONE;
1022         else if (cmd->flags & MMC_RSP_136)
1023                 flags = SDHCI_CMD_RESP_LONG;
1024         else if (cmd->flags & MMC_RSP_BUSY)
1025                 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1026         else
1027                 flags = SDHCI_CMD_RESP_SHORT;
1028
1029         if (cmd->flags & MMC_RSP_CRC)
1030                 flags |= SDHCI_CMD_CRC;
1031         if (cmd->flags & MMC_RSP_OPCODE)
1032                 flags |= SDHCI_CMD_INDEX;
1033
1034         /* CMD19 is special in that the Data Present Select should be set */
1035         if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1036             cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1037                 flags |= SDHCI_CMD_DATA;
1038
1039         sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1040 }
1041 EXPORT_SYMBOL_GPL(sdhci_send_command);
1042
1043 static void sdhci_finish_command(struct sdhci_host *host)
1044 {
1045         int i;
1046
1047         BUG_ON(host->cmd == NULL);
1048
1049         if (host->cmd->flags & MMC_RSP_PRESENT) {
1050                 if (host->cmd->flags & MMC_RSP_136) {
1051                         /* CRC is stripped so we need to do some shifting. */
1052                         for (i = 0;i < 4;i++) {
1053                                 host->cmd->resp[i] = sdhci_readl(host,
1054                                         SDHCI_RESPONSE + (3-i)*4) << 8;
1055                                 if (i != 3)
1056                                         host->cmd->resp[i] |=
1057                                                 sdhci_readb(host,
1058                                                 SDHCI_RESPONSE + (3-i)*4-1);
1059                         }
1060                 } else {
1061                         host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1062                 }
1063         }
1064
1065         host->cmd->error = 0;
1066
1067         /* Finished CMD23, now send actual command. */
1068         if (host->cmd == host->mrq->sbc) {
1069                 host->cmd = NULL;
1070                 sdhci_send_command(host, host->mrq->cmd);
1071         } else {
1072
1073                 /* Processed actual command. */
1074                 if (host->data && host->data_early)
1075                         sdhci_finish_data(host);
1076
1077                 if (!host->cmd->data)
1078                         tasklet_schedule(&host->finish_tasklet);
1079
1080                 host->cmd = NULL;
1081         }
1082 }
1083
1084 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1085 {
1086         u16 preset = 0;
1087
1088         switch (host->timing) {
1089         case MMC_TIMING_UHS_SDR12:
1090                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1091                 break;
1092         case MMC_TIMING_UHS_SDR25:
1093                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1094                 break;
1095         case MMC_TIMING_UHS_SDR50:
1096                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1097                 break;
1098         case MMC_TIMING_UHS_SDR104:
1099         case MMC_TIMING_MMC_HS200:
1100                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1101                 break;
1102         case MMC_TIMING_UHS_DDR50:
1103                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1104                 break;
1105         default:
1106                 pr_warn("%s: Invalid UHS-I mode selected\n",
1107                         mmc_hostname(host->mmc));
1108                 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1109                 break;
1110         }
1111         return preset;
1112 }
1113
1114 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1115 {
1116         int div = 0; /* Initialized for compiler warning */
1117         int real_div = div, clk_mul = 1;
1118         u16 clk = 0;
1119         unsigned long timeout;
1120
1121         host->mmc->actual_clock = 0;
1122
1123         sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1124
1125         if (clock == 0)
1126                 return;
1127
1128         if (host->version >= SDHCI_SPEC_300) {
1129                 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1130                         SDHCI_CTRL_PRESET_VAL_ENABLE) {
1131                         u16 pre_val;
1132
1133                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1134                         pre_val = sdhci_get_preset_value(host);
1135                         div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1136                                 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1137                         if (host->clk_mul &&
1138                                 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1139                                 clk = SDHCI_PROG_CLOCK_MODE;
1140                                 real_div = div + 1;
1141                                 clk_mul = host->clk_mul;
1142                         } else {
1143                                 real_div = max_t(int, 1, div << 1);
1144                         }
1145                         goto clock_set;
1146                 }
1147
1148                 /*
1149                  * Check if the Host Controller supports Programmable Clock
1150                  * Mode.
1151                  */
1152                 if (host->clk_mul) {
1153                         for (div = 1; div <= 1024; div++) {
1154                                 if ((host->max_clk * host->clk_mul / div)
1155                                         <= clock)
1156                                         break;
1157                         }
1158                         /*
1159                          * Set Programmable Clock Mode in the Clock
1160                          * Control register.
1161                          */
1162                         clk = SDHCI_PROG_CLOCK_MODE;
1163                         real_div = div;
1164                         clk_mul = host->clk_mul;
1165                         div--;
1166                 } else {
1167                         /* Version 3.00 divisors must be a multiple of 2. */
1168                         if (host->max_clk <= clock)
1169                                 div = 1;
1170                         else {
1171                                 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1172                                      div += 2) {
1173                                         if ((host->max_clk / div) <= clock)
1174                                                 break;
1175                                 }
1176                         }
1177                         real_div = div;
1178                         div >>= 1;
1179                 }
1180         } else {
1181                 /* Version 2.00 divisors must be a power of 2. */
1182                 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1183                         if ((host->max_clk / div) <= clock)
1184                                 break;
1185                 }
1186                 real_div = div;
1187                 div >>= 1;
1188         }
1189
1190 clock_set:
1191         if (real_div)
1192                 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1193
1194         clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1195         clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1196                 << SDHCI_DIVIDER_HI_SHIFT;
1197         clk |= SDHCI_CLOCK_INT_EN;
1198         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1199
1200         /* Wait max 20 ms */
1201         timeout = 20;
1202         while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1203                 & SDHCI_CLOCK_INT_STABLE)) {
1204                 if (timeout == 0) {
1205                         pr_err("%s: Internal clock never "
1206                                 "stabilised.\n", mmc_hostname(host->mmc));
1207                         sdhci_dumpregs(host);
1208                         return;
1209                 }
1210                 timeout--;
1211                 mdelay(1);
1212         }
1213
1214         clk |= SDHCI_CLOCK_CARD_EN;
1215         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1216 }
1217 EXPORT_SYMBOL_GPL(sdhci_set_clock);
1218
1219 static void sdhci_set_power(struct sdhci_host *host, unsigned char mode,
1220                             unsigned short vdd)
1221 {
1222         u8 pwr = 0;
1223
1224         if (mode != MMC_POWER_OFF) {
1225                 switch (1 << vdd) {
1226                 case MMC_VDD_165_195:
1227                         pwr = SDHCI_POWER_180;
1228                         break;
1229                 case MMC_VDD_29_30:
1230                 case MMC_VDD_30_31:
1231                         pwr = SDHCI_POWER_300;
1232                         break;
1233                 case MMC_VDD_32_33:
1234                 case MMC_VDD_33_34:
1235                         pwr = SDHCI_POWER_330;
1236                         break;
1237                 default:
1238                         BUG();
1239                 }
1240         }
1241
1242         if (host->pwr == pwr)
1243                 return;
1244
1245         host->pwr = pwr;
1246
1247         if (pwr == 0) {
1248                 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1249                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1250                         sdhci_runtime_pm_bus_off(host);
1251                 vdd = 0;
1252         } else {
1253                 /*
1254                  * Spec says that we should clear the power reg before setting
1255                  * a new value. Some controllers don't seem to like this though.
1256                  */
1257                 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1258                         sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1259
1260                 /*
1261                  * At least the Marvell CaFe chip gets confused if we set the
1262                  * voltage and set turn on power at the same time, so set the
1263                  * voltage first.
1264                  */
1265                 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1266                         sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1267
1268                 pwr |= SDHCI_POWER_ON;
1269
1270                 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1271
1272                 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1273                         sdhci_runtime_pm_bus_on(host);
1274
1275                 /*
1276                  * Some controllers need an extra 10ms delay of 10ms before
1277                  * they can apply clock after applying power
1278                  */
1279                 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1280                         mdelay(10);
1281         }
1282
1283         if (host->vmmc) {
1284                 spin_unlock_irq(&host->lock);
1285                 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd);
1286                 spin_lock_irq(&host->lock);
1287         }
1288 }
1289
1290 /*****************************************************************************\
1291  *                                                                           *
1292  * MMC callbacks                                                             *
1293  *                                                                           *
1294 \*****************************************************************************/
1295
1296 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1297 {
1298         struct sdhci_host *host;
1299         int present;
1300         unsigned long flags;
1301         u32 tuning_opcode;
1302
1303         host = mmc_priv(mmc);
1304
1305         sdhci_runtime_pm_get(host);
1306
1307         spin_lock_irqsave(&host->lock, flags);
1308
1309         WARN_ON(host->mrq != NULL);
1310
1311 #ifndef SDHCI_USE_LEDS_CLASS
1312         sdhci_activate_led(host);
1313 #endif
1314
1315         /*
1316          * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1317          * requests if Auto-CMD12 is enabled.
1318          */
1319         if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1320                 if (mrq->stop) {
1321                         mrq->data->stop = NULL;
1322                         mrq->stop = NULL;
1323                 }
1324         }
1325
1326         host->mrq = mrq;
1327
1328         /*
1329          * Firstly check card presence from cd-gpio.  The return could
1330          * be one of the following possibilities:
1331          *     negative: cd-gpio is not available
1332          *     zero: cd-gpio is used, and card is removed
1333          *     one: cd-gpio is used, and card is present
1334          */
1335         present = mmc_gpio_get_cd(host->mmc);
1336         if (present < 0) {
1337                 /* If polling, assume that the card is always present. */
1338                 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1339                         present = 1;
1340                 else
1341                         present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1342                                         SDHCI_CARD_PRESENT;
1343         }
1344
1345         if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1346                 host->mrq->cmd->error = -ENOMEDIUM;
1347                 tasklet_schedule(&host->finish_tasklet);
1348         } else {
1349                 u32 present_state;
1350
1351                 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1352                 /*
1353                  * Check if the re-tuning timer has already expired and there
1354                  * is no on-going data transfer. If so, we need to execute
1355                  * tuning procedure before sending command.
1356                  */
1357                 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1358                     !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1359                         if (mmc->card) {
1360                                 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1361                                 tuning_opcode =
1362                                         mmc->card->type == MMC_TYPE_MMC ?
1363                                         MMC_SEND_TUNING_BLOCK_HS200 :
1364                                         MMC_SEND_TUNING_BLOCK;
1365
1366                                 /* Here we need to set the host->mrq to NULL,
1367                                  * in case the pending finish_tasklet
1368                                  * finishes it incorrectly.
1369                                  */
1370                                 host->mrq = NULL;
1371
1372                                 spin_unlock_irqrestore(&host->lock, flags);
1373                                 sdhci_execute_tuning(mmc, tuning_opcode);
1374                                 spin_lock_irqsave(&host->lock, flags);
1375
1376                                 /* Restore original mmc_request structure */
1377                                 host->mrq = mrq;
1378                         }
1379                 }
1380
1381                 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1382                         sdhci_send_command(host, mrq->sbc);
1383                 else
1384                         sdhci_send_command(host, mrq->cmd);
1385         }
1386
1387         mmiowb();
1388         spin_unlock_irqrestore(&host->lock, flags);
1389 }
1390
1391 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1392 {
1393         u8 ctrl;
1394
1395         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1396         if (width == MMC_BUS_WIDTH_8) {
1397                 ctrl &= ~SDHCI_CTRL_4BITBUS;
1398                 if (host->version >= SDHCI_SPEC_300)
1399                         ctrl |= SDHCI_CTRL_8BITBUS;
1400         } else {
1401                 if (host->version >= SDHCI_SPEC_300)
1402                         ctrl &= ~SDHCI_CTRL_8BITBUS;
1403                 if (width == MMC_BUS_WIDTH_4)
1404                         ctrl |= SDHCI_CTRL_4BITBUS;
1405                 else
1406                         ctrl &= ~SDHCI_CTRL_4BITBUS;
1407         }
1408         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1409 }
1410 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1411
1412 void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
1413 {
1414         u16 ctrl_2;
1415
1416         ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1417         /* Select Bus Speed Mode for host */
1418         ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1419         if ((timing == MMC_TIMING_MMC_HS200) ||
1420             (timing == MMC_TIMING_UHS_SDR104))
1421                 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1422         else if (timing == MMC_TIMING_UHS_SDR12)
1423                 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1424         else if (timing == MMC_TIMING_UHS_SDR25)
1425                 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1426         else if (timing == MMC_TIMING_UHS_SDR50)
1427                 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1428         else if ((timing == MMC_TIMING_UHS_DDR50) ||
1429                  (timing == MMC_TIMING_MMC_DDR52))
1430                 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1431         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1432 }
1433 EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling);
1434
1435 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1436 {
1437         unsigned long flags;
1438         u8 ctrl;
1439
1440         spin_lock_irqsave(&host->lock, flags);
1441
1442         if (host->flags & SDHCI_DEVICE_DEAD) {
1443                 spin_unlock_irqrestore(&host->lock, flags);
1444                 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1445                         mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1446                 return;
1447         }
1448
1449         /*
1450          * Reset the chip on each power off.
1451          * Should clear out any weird states.
1452          */
1453         if (ios->power_mode == MMC_POWER_OFF) {
1454                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1455                 sdhci_reinit(host);
1456         }
1457
1458         if (host->version >= SDHCI_SPEC_300 &&
1459                 (ios->power_mode == MMC_POWER_UP) &&
1460                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1461                 sdhci_enable_preset_value(host, false);
1462
1463         if (!ios->clock || ios->clock != host->clock) {
1464                 host->ops->set_clock(host, ios->clock);
1465                 host->clock = ios->clock;
1466         }
1467
1468         sdhci_set_power(host, ios->power_mode, ios->vdd);
1469
1470         if (host->ops->platform_send_init_74_clocks)
1471                 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1472
1473         host->ops->set_bus_width(host, ios->bus_width);
1474
1475         ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1476
1477         if ((ios->timing == MMC_TIMING_SD_HS ||
1478              ios->timing == MMC_TIMING_MMC_HS)
1479             && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1480                 ctrl |= SDHCI_CTRL_HISPD;
1481         else
1482                 ctrl &= ~SDHCI_CTRL_HISPD;
1483
1484         if (host->version >= SDHCI_SPEC_300) {
1485                 u16 clk, ctrl_2;
1486
1487                 /* In case of UHS-I modes, set High Speed Enable */
1488                 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1489                     (ios->timing == MMC_TIMING_MMC_DDR52) ||
1490                     (ios->timing == MMC_TIMING_UHS_SDR50) ||
1491                     (ios->timing == MMC_TIMING_UHS_SDR104) ||
1492                     (ios->timing == MMC_TIMING_UHS_DDR50) ||
1493                     (ios->timing == MMC_TIMING_UHS_SDR25))
1494                         ctrl |= SDHCI_CTRL_HISPD;
1495
1496                 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1497                 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1498                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1499                         /*
1500                          * We only need to set Driver Strength if the
1501                          * preset value enable is not set.
1502                          */
1503                         ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1504                         if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1505                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1506                         else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1507                                 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1508
1509                         sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1510                 } else {
1511                         /*
1512                          * According to SDHC Spec v3.00, if the Preset Value
1513                          * Enable in the Host Control 2 register is set, we
1514                          * need to reset SD Clock Enable before changing High
1515                          * Speed Enable to avoid generating clock gliches.
1516                          */
1517
1518                         /* Reset SD Clock Enable */
1519                         clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1520                         clk &= ~SDHCI_CLOCK_CARD_EN;
1521                         sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1522
1523                         sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1524
1525                         /* Re-enable SD Clock */
1526                         host->ops->set_clock(host, host->clock);
1527                 }
1528
1529
1530                 /* Reset SD Clock Enable */
1531                 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1532                 clk &= ~SDHCI_CLOCK_CARD_EN;
1533                 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1534
1535                 host->ops->set_uhs_signaling(host, ios->timing);
1536                 host->timing = ios->timing;
1537
1538                 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1539                                 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1540                                  (ios->timing == MMC_TIMING_UHS_SDR25) ||
1541                                  (ios->timing == MMC_TIMING_UHS_SDR50) ||
1542                                  (ios->timing == MMC_TIMING_UHS_SDR104) ||
1543                                  (ios->timing == MMC_TIMING_UHS_DDR50))) {
1544                         u16 preset;
1545
1546                         sdhci_enable_preset_value(host, true);
1547                         preset = sdhci_get_preset_value(host);
1548                         ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1549                                 >> SDHCI_PRESET_DRV_SHIFT;
1550                 }
1551
1552                 /* Re-enable SD Clock */
1553                 host->ops->set_clock(host, host->clock);
1554         } else
1555                 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1556
1557         /*
1558          * Some (ENE) controllers go apeshit on some ios operation,
1559          * signalling timeout and CRC errors even on CMD0. Resetting
1560          * it on each ios seems to solve the problem.
1561          */
1562         if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1563                 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1564
1565         mmiowb();
1566         spin_unlock_irqrestore(&host->lock, flags);
1567 }
1568
1569 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1570 {
1571         struct sdhci_host *host = mmc_priv(mmc);
1572
1573         sdhci_runtime_pm_get(host);
1574         sdhci_do_set_ios(host, ios);
1575         sdhci_runtime_pm_put(host);
1576 }
1577
1578 static int sdhci_do_get_cd(struct sdhci_host *host)
1579 {
1580         int gpio_cd = mmc_gpio_get_cd(host->mmc);
1581
1582         if (host->flags & SDHCI_DEVICE_DEAD)
1583                 return 0;
1584
1585         /* If polling/nonremovable, assume that the card is always present. */
1586         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1587             (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1588                 return 1;
1589
1590         /* Try slot gpio detect */
1591         if (!IS_ERR_VALUE(gpio_cd))
1592                 return !!gpio_cd;
1593
1594         /* Host native card detect */
1595         return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1596 }
1597
1598 static int sdhci_get_cd(struct mmc_host *mmc)
1599 {
1600         struct sdhci_host *host = mmc_priv(mmc);
1601         int ret;
1602
1603         sdhci_runtime_pm_get(host);
1604         ret = sdhci_do_get_cd(host);
1605         sdhci_runtime_pm_put(host);
1606         return ret;
1607 }
1608
1609 static int sdhci_check_ro(struct sdhci_host *host)
1610 {
1611         unsigned long flags;
1612         int is_readonly;
1613
1614         spin_lock_irqsave(&host->lock, flags);
1615
1616         if (host->flags & SDHCI_DEVICE_DEAD)
1617                 is_readonly = 0;
1618         else if (host->ops->get_ro)
1619                 is_readonly = host->ops->get_ro(host);
1620         else
1621                 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1622                                 & SDHCI_WRITE_PROTECT);
1623
1624         spin_unlock_irqrestore(&host->lock, flags);
1625
1626         /* This quirk needs to be replaced by a callback-function later */
1627         return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1628                 !is_readonly : is_readonly;
1629 }
1630
1631 #define SAMPLE_COUNT    5
1632
1633 static int sdhci_do_get_ro(struct sdhci_host *host)
1634 {
1635         int i, ro_count;
1636
1637         if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1638                 return sdhci_check_ro(host);
1639
1640         ro_count = 0;
1641         for (i = 0; i < SAMPLE_COUNT; i++) {
1642                 if (sdhci_check_ro(host)) {
1643                         if (++ro_count > SAMPLE_COUNT / 2)
1644                                 return 1;
1645                 }
1646                 msleep(30);
1647         }
1648         return 0;
1649 }
1650
1651 static void sdhci_hw_reset(struct mmc_host *mmc)
1652 {
1653         struct sdhci_host *host = mmc_priv(mmc);
1654
1655         if (host->ops && host->ops->hw_reset)
1656                 host->ops->hw_reset(host);
1657 }
1658
1659 static int sdhci_get_ro(struct mmc_host *mmc)
1660 {
1661         struct sdhci_host *host = mmc_priv(mmc);
1662         int ret;
1663
1664         sdhci_runtime_pm_get(host);
1665         ret = sdhci_do_get_ro(host);
1666         sdhci_runtime_pm_put(host);
1667         return ret;
1668 }
1669
1670 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1671 {
1672         if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1673                 if (enable)
1674                         host->ier |= SDHCI_INT_CARD_INT;
1675                 else
1676                         host->ier &= ~SDHCI_INT_CARD_INT;
1677
1678                 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1679                 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1680                 mmiowb();
1681         }
1682 }
1683
1684 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1685 {
1686         struct sdhci_host *host = mmc_priv(mmc);
1687         unsigned long flags;
1688
1689         sdhci_runtime_pm_get(host);
1690
1691         spin_lock_irqsave(&host->lock, flags);
1692         if (enable)
1693                 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1694         else
1695                 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1696
1697         sdhci_enable_sdio_irq_nolock(host, enable);
1698         spin_unlock_irqrestore(&host->lock, flags);
1699
1700         sdhci_runtime_pm_put(host);
1701 }
1702
1703 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1704                                                 struct mmc_ios *ios)
1705 {
1706         u16 ctrl;
1707         int ret;
1708
1709         /*
1710          * Signal Voltage Switching is only applicable for Host Controllers
1711          * v3.00 and above.
1712          */
1713         if (host->version < SDHCI_SPEC_300)
1714                 return 0;
1715
1716         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1717
1718         switch (ios->signal_voltage) {
1719         case MMC_SIGNAL_VOLTAGE_330:
1720                 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1721                 ctrl &= ~SDHCI_CTRL_VDD_180;
1722                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1723
1724                 if (host->vqmmc) {
1725                         ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1726                         if (ret) {
1727                                 pr_warning("%s: Switching to 3.3V signalling voltage "
1728                                                 " failed\n", mmc_hostname(host->mmc));
1729                                 return -EIO;
1730                         }
1731                 }
1732                 /* Wait for 5ms */
1733                 usleep_range(5000, 5500);
1734
1735                 /* 3.3V regulator output should be stable within 5 ms */
1736                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1737                 if (!(ctrl & SDHCI_CTRL_VDD_180))
1738                         return 0;
1739
1740                 pr_warning("%s: 3.3V regulator output did not became stable\n",
1741                                 mmc_hostname(host->mmc));
1742
1743                 return -EAGAIN;
1744         case MMC_SIGNAL_VOLTAGE_180:
1745                 if (host->vqmmc) {
1746                         ret = regulator_set_voltage(host->vqmmc,
1747                                         1700000, 1950000);
1748                         if (ret) {
1749                                 pr_warning("%s: Switching to 1.8V signalling voltage "
1750                                                 " failed\n", mmc_hostname(host->mmc));
1751                                 return -EIO;
1752                         }
1753                 }
1754
1755                 /*
1756                  * Enable 1.8V Signal Enable in the Host Control2
1757                  * register
1758                  */
1759                 ctrl |= SDHCI_CTRL_VDD_180;
1760                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1761
1762                 /* Wait for 5ms */
1763                 usleep_range(5000, 5500);
1764
1765                 /* 1.8V regulator output should be stable within 5 ms */
1766                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1767                 if (ctrl & SDHCI_CTRL_VDD_180)
1768                         return 0;
1769
1770                 pr_warning("%s: 1.8V regulator output did not became stable\n",
1771                                 mmc_hostname(host->mmc));
1772
1773                 return -EAGAIN;
1774         case MMC_SIGNAL_VOLTAGE_120:
1775                 if (host->vqmmc) {
1776                         ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1777                         if (ret) {
1778                                 pr_warning("%s: Switching to 1.2V signalling voltage "
1779                                                 " failed\n", mmc_hostname(host->mmc));
1780                                 return -EIO;
1781                         }
1782                 }
1783                 return 0;
1784         default:
1785                 /* No signal voltage switch required */
1786                 return 0;
1787         }
1788 }
1789
1790 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1791         struct mmc_ios *ios)
1792 {
1793         struct sdhci_host *host = mmc_priv(mmc);
1794         int err;
1795
1796         if (host->version < SDHCI_SPEC_300)
1797                 return 0;
1798         sdhci_runtime_pm_get(host);
1799         err = sdhci_do_start_signal_voltage_switch(host, ios);
1800         sdhci_runtime_pm_put(host);
1801         return err;
1802 }
1803
1804 static int sdhci_card_busy(struct mmc_host *mmc)
1805 {
1806         struct sdhci_host *host = mmc_priv(mmc);
1807         u32 present_state;
1808
1809         sdhci_runtime_pm_get(host);
1810         /* Check whether DAT[3:0] is 0000 */
1811         present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1812         sdhci_runtime_pm_put(host);
1813
1814         return !(present_state & SDHCI_DATA_LVL_MASK);
1815 }
1816
1817 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1818 {
1819         struct sdhci_host *host = mmc_priv(mmc);
1820         u16 ctrl;
1821         int tuning_loop_counter = MAX_TUNING_LOOP;
1822         unsigned long timeout;
1823         int err = 0;
1824         unsigned long flags;
1825
1826         sdhci_runtime_pm_get(host);
1827         spin_lock_irqsave(&host->lock, flags);
1828
1829         /*
1830          * The Host Controller needs tuning only in case of SDR104 mode
1831          * and for SDR50 mode when Use Tuning for SDR50 is set in the
1832          * Capabilities register.
1833          * If the Host Controller supports the HS200 mode then the
1834          * tuning function has to be executed.
1835          */
1836         switch (host->timing) {
1837         case MMC_TIMING_MMC_HS200:
1838         case MMC_TIMING_UHS_SDR104:
1839                 break;
1840
1841         case MMC_TIMING_UHS_SDR50:
1842                 if (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1843                     host->flags & SDHCI_SDR104_NEEDS_TUNING)
1844                         break;
1845                 /* FALLTHROUGH */
1846
1847         default:
1848                 spin_unlock_irqrestore(&host->lock, flags);
1849                 sdhci_runtime_pm_put(host);
1850                 return 0;
1851         }
1852
1853         if (host->ops->platform_execute_tuning) {
1854                 spin_unlock_irqrestore(&host->lock, flags);
1855                 err = host->ops->platform_execute_tuning(host, opcode);
1856                 sdhci_runtime_pm_put(host);
1857                 return err;
1858         }
1859
1860         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1861         ctrl |= SDHCI_CTRL_EXEC_TUNING;
1862         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1863
1864         /*
1865          * As per the Host Controller spec v3.00, tuning command
1866          * generates Buffer Read Ready interrupt, so enable that.
1867          *
1868          * Note: The spec clearly says that when tuning sequence
1869          * is being performed, the controller does not generate
1870          * interrupts other than Buffer Read Ready interrupt. But
1871          * to make sure we don't hit a controller bug, we _only_
1872          * enable Buffer Read Ready interrupt here.
1873          */
1874         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1875         sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1876
1877         /*
1878          * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1879          * of loops reaches 40 times or a timeout of 150ms occurs.
1880          */
1881         timeout = 150;
1882         do {
1883                 struct mmc_command cmd = {0};
1884                 struct mmc_request mrq = {NULL};
1885
1886                 if (!tuning_loop_counter && !timeout)
1887                         break;
1888
1889                 cmd.opcode = opcode;
1890                 cmd.arg = 0;
1891                 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1892                 cmd.retries = 0;
1893                 cmd.data = NULL;
1894                 cmd.error = 0;
1895
1896                 mrq.cmd = &cmd;
1897                 host->mrq = &mrq;
1898
1899                 /*
1900                  * In response to CMD19, the card sends 64 bytes of tuning
1901                  * block to the Host Controller. So we set the block size
1902                  * to 64 here.
1903                  */
1904                 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1905                         if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1906                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1907                                              SDHCI_BLOCK_SIZE);
1908                         else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1909                                 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1910                                              SDHCI_BLOCK_SIZE);
1911                 } else {
1912                         sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1913                                      SDHCI_BLOCK_SIZE);
1914                 }
1915
1916                 /*
1917                  * The tuning block is sent by the card to the host controller.
1918                  * So we set the TRNS_READ bit in the Transfer Mode register.
1919                  * This also takes care of setting DMA Enable and Multi Block
1920                  * Select in the same register to 0.
1921                  */
1922                 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1923
1924                 sdhci_send_command(host, &cmd);
1925
1926                 host->cmd = NULL;
1927                 host->mrq = NULL;
1928
1929                 spin_unlock_irqrestore(&host->lock, flags);
1930                 /* Wait for Buffer Read Ready interrupt */
1931                 wait_event_interruptible_timeout(host->buf_ready_int,
1932                                         (host->tuning_done == 1),
1933                                         msecs_to_jiffies(50));
1934                 spin_lock_irqsave(&host->lock, flags);
1935
1936                 if (!host->tuning_done) {
1937                         pr_info(DRIVER_NAME ": Timeout waiting for "
1938                                 "Buffer Read Ready interrupt during tuning "
1939                                 "procedure, falling back to fixed sampling "
1940                                 "clock\n");
1941                         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1942                         ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1943                         ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1944                         sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1945
1946                         err = -EIO;
1947                         goto out;
1948                 }
1949
1950                 host->tuning_done = 0;
1951
1952                 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1953                 tuning_loop_counter--;
1954                 timeout--;
1955
1956                 /* eMMC spec does not require a delay between tuning cycles */
1957                 if (opcode == MMC_SEND_TUNING_BLOCK)
1958                         mdelay(1);
1959         } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1960
1961         /*
1962          * The Host Driver has exhausted the maximum number of loops allowed,
1963          * so use fixed sampling frequency.
1964          */
1965         if (!tuning_loop_counter || !timeout) {
1966                 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1967                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1968                 err = -EIO;
1969         } else {
1970                 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
1971                         pr_info(DRIVER_NAME ": Tuning procedure"
1972                                 " failed, falling back to fixed sampling"
1973                                 " clock\n");
1974                         err = -EIO;
1975                 }
1976         }
1977
1978 out:
1979         /*
1980          * If this is the very first time we are here, we start the retuning
1981          * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
1982          * flag won't be set, we check this condition before actually starting
1983          * the timer.
1984          */
1985         if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
1986             (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
1987                 host->flags |= SDHCI_USING_RETUNING_TIMER;
1988                 mod_timer(&host->tuning_timer, jiffies +
1989                         host->tuning_count * HZ);
1990                 /* Tuning mode 1 limits the maximum data length to 4MB */
1991                 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
1992         } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
1993                 host->flags &= ~SDHCI_NEEDS_RETUNING;
1994                 /* Reload the new initial value for timer */
1995                 mod_timer(&host->tuning_timer, jiffies +
1996                           host->tuning_count * HZ);
1997         }
1998
1999         /*
2000          * In case tuning fails, host controllers which support re-tuning can
2001          * try tuning again at a later time, when the re-tuning timer expires.
2002          * So for these controllers, we return 0. Since there might be other
2003          * controllers who do not have this capability, we return error for
2004          * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2005          * a retuning timer to do the retuning for the card.
2006          */
2007         if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2008                 err = 0;
2009
2010         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2011         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2012         spin_unlock_irqrestore(&host->lock, flags);
2013         sdhci_runtime_pm_put(host);
2014
2015         return err;
2016 }
2017
2018
2019 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2020 {
2021         u16 ctrl;
2022
2023         /* Host Controller v3.00 defines preset value registers */
2024         if (host->version < SDHCI_SPEC_300)
2025                 return;
2026
2027         ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2028
2029         /*
2030          * We only enable or disable Preset Value if they are not already
2031          * enabled or disabled respectively. Otherwise, we bail out.
2032          */
2033         if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2034                 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2035                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2036                 host->flags |= SDHCI_PV_ENABLED;
2037         } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2038                 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2039                 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2040                 host->flags &= ~SDHCI_PV_ENABLED;
2041         }
2042 }
2043
2044 static void sdhci_card_event(struct mmc_host *mmc)
2045 {
2046         struct sdhci_host *host = mmc_priv(mmc);
2047         unsigned long flags;
2048
2049         /* First check if client has provided their own card event */
2050         if (host->ops->card_event)
2051                 host->ops->card_event(host);
2052
2053         spin_lock_irqsave(&host->lock, flags);
2054
2055         /* Check host->mrq first in case we are runtime suspended */
2056         if (host->mrq && !sdhci_do_get_cd(host)) {
2057                 pr_err("%s: Card removed during transfer!\n",
2058                         mmc_hostname(host->mmc));
2059                 pr_err("%s: Resetting controller.\n",
2060                         mmc_hostname(host->mmc));
2061
2062                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2063                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2064
2065                 host->mrq->cmd->error = -ENOMEDIUM;
2066                 tasklet_schedule(&host->finish_tasklet);
2067         }
2068
2069         spin_unlock_irqrestore(&host->lock, flags);
2070 }
2071
2072 static const struct mmc_host_ops sdhci_ops = {
2073         .request        = sdhci_request,
2074         .set_ios        = sdhci_set_ios,
2075         .get_cd         = sdhci_get_cd,
2076         .get_ro         = sdhci_get_ro,
2077         .hw_reset       = sdhci_hw_reset,
2078         .enable_sdio_irq = sdhci_enable_sdio_irq,
2079         .start_signal_voltage_switch    = sdhci_start_signal_voltage_switch,
2080         .execute_tuning                 = sdhci_execute_tuning,
2081         .card_event                     = sdhci_card_event,
2082         .card_busy      = sdhci_card_busy,
2083 };
2084
2085 /*****************************************************************************\
2086  *                                                                           *
2087  * Tasklets                                                                  *
2088  *                                                                           *
2089 \*****************************************************************************/
2090
2091 static void sdhci_tasklet_finish(unsigned long param)
2092 {
2093         struct sdhci_host *host;
2094         unsigned long flags;
2095         struct mmc_request *mrq;
2096
2097         host = (struct sdhci_host*)param;
2098
2099         spin_lock_irqsave(&host->lock, flags);
2100
2101         /*
2102          * If this tasklet gets rescheduled while running, it will
2103          * be run again afterwards but without any active request.
2104          */
2105         if (!host->mrq) {
2106                 spin_unlock_irqrestore(&host->lock, flags);
2107                 return;
2108         }
2109
2110         del_timer(&host->timer);
2111
2112         mrq = host->mrq;
2113
2114         /*
2115          * The controller needs a reset of internal state machines
2116          * upon error conditions.
2117          */
2118         if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2119             ((mrq->cmd && mrq->cmd->error) ||
2120                  (mrq->data && (mrq->data->error ||
2121                   (mrq->data->stop && mrq->data->stop->error))) ||
2122                    (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2123
2124                 /* Some controllers need this kick or reset won't work here */
2125                 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2126                         /* This is to force an update */
2127                         host->ops->set_clock(host, host->clock);
2128
2129                 /* Spec says we should do both at the same time, but Ricoh
2130                    controllers do not like that. */
2131                 sdhci_do_reset(host, SDHCI_RESET_CMD);
2132                 sdhci_do_reset(host, SDHCI_RESET_DATA);
2133         }
2134
2135         host->mrq = NULL;
2136         host->cmd = NULL;
2137         host->data = NULL;
2138
2139 #ifndef SDHCI_USE_LEDS_CLASS
2140         sdhci_deactivate_led(host);
2141 #endif
2142
2143         mmiowb();
2144         spin_unlock_irqrestore(&host->lock, flags);
2145
2146         mmc_request_done(host->mmc, mrq);
2147         sdhci_runtime_pm_put(host);
2148 }
2149
2150 static void sdhci_timeout_timer(unsigned long data)
2151 {
2152         struct sdhci_host *host;
2153         unsigned long flags;
2154
2155         host = (struct sdhci_host*)data;
2156
2157         spin_lock_irqsave(&host->lock, flags);
2158
2159         if (host->mrq) {
2160                 pr_err("%s: Timeout waiting for hardware "
2161                         "interrupt.\n", mmc_hostname(host->mmc));
2162                 sdhci_dumpregs(host);
2163
2164                 if (host->data) {
2165                         host->data->error = -ETIMEDOUT;
2166                         sdhci_finish_data(host);
2167                 } else {
2168                         if (host->cmd)
2169                                 host->cmd->error = -ETIMEDOUT;
2170                         else
2171                                 host->mrq->cmd->error = -ETIMEDOUT;
2172
2173                         tasklet_schedule(&host->finish_tasklet);
2174                 }
2175         }
2176
2177         mmiowb();
2178         spin_unlock_irqrestore(&host->lock, flags);
2179 }
2180
2181 static void sdhci_tuning_timer(unsigned long data)
2182 {
2183         struct sdhci_host *host;
2184         unsigned long flags;
2185
2186         host = (struct sdhci_host *)data;
2187
2188         spin_lock_irqsave(&host->lock, flags);
2189
2190         host->flags |= SDHCI_NEEDS_RETUNING;
2191
2192         spin_unlock_irqrestore(&host->lock, flags);
2193 }
2194
2195 /*****************************************************************************\
2196  *                                                                           *
2197  * Interrupt handling                                                        *
2198  *                                                                           *
2199 \*****************************************************************************/
2200
2201 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2202 {
2203         BUG_ON(intmask == 0);
2204
2205         if (!host->cmd) {
2206                 pr_err("%s: Got command interrupt 0x%08x even "
2207                         "though no command operation was in progress.\n",
2208                         mmc_hostname(host->mmc), (unsigned)intmask);
2209                 sdhci_dumpregs(host);
2210                 return;
2211         }
2212
2213         if (intmask & SDHCI_INT_TIMEOUT)
2214                 host->cmd->error = -ETIMEDOUT;
2215         else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2216                         SDHCI_INT_INDEX))
2217                 host->cmd->error = -EILSEQ;
2218
2219         if (host->cmd->error) {
2220                 tasklet_schedule(&host->finish_tasklet);
2221                 return;
2222         }
2223
2224         /*
2225          * The host can send and interrupt when the busy state has
2226          * ended, allowing us to wait without wasting CPU cycles.
2227          * Unfortunately this is overloaded on the "data complete"
2228          * interrupt, so we need to take some care when handling
2229          * it.
2230          *
2231          * Note: The 1.0 specification is a bit ambiguous about this
2232          *       feature so there might be some problems with older
2233          *       controllers.
2234          */
2235         if (host->cmd->flags & MMC_RSP_BUSY) {
2236                 if (host->cmd->data)
2237                         DBG("Cannot wait for busy signal when also "
2238                                 "doing a data transfer");
2239                 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2240                         return;
2241
2242                 /* The controller does not support the end-of-busy IRQ,
2243                  * fall through and take the SDHCI_INT_RESPONSE */
2244         }
2245
2246         if (intmask & SDHCI_INT_RESPONSE)
2247                 sdhci_finish_command(host);
2248 }
2249
2250 #ifdef CONFIG_MMC_DEBUG
2251 static void sdhci_show_adma_error(struct sdhci_host *host)
2252 {
2253         const char *name = mmc_hostname(host->mmc);
2254         u8 *desc = host->adma_desc;
2255         __le32 *dma;
2256         __le16 *len;
2257         u8 attr;
2258
2259         sdhci_dumpregs(host);
2260
2261         while (true) {
2262                 dma = (__le32 *)(desc + 4);
2263                 len = (__le16 *)(desc + 2);
2264                 attr = *desc;
2265
2266                 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2267                     name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2268
2269                 desc += 8;
2270
2271                 if (attr & 2)
2272                         break;
2273         }
2274 }
2275 #else
2276 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2277 #endif
2278
2279 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2280 {
2281         u32 command;
2282         BUG_ON(intmask == 0);
2283
2284         /* CMD19 generates _only_ Buffer Read Ready interrupt */
2285         if (intmask & SDHCI_INT_DATA_AVAIL) {
2286                 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2287                 if (command == MMC_SEND_TUNING_BLOCK ||
2288                     command == MMC_SEND_TUNING_BLOCK_HS200) {
2289                         host->tuning_done = 1;
2290                         wake_up(&host->buf_ready_int);
2291                         return;
2292                 }
2293         }
2294
2295         if (!host->data) {
2296                 /*
2297                  * The "data complete" interrupt is also used to
2298                  * indicate that a busy state has ended. See comment
2299                  * above in sdhci_cmd_irq().
2300                  */
2301                 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2302                         if (intmask & SDHCI_INT_DATA_END) {
2303                                 sdhci_finish_command(host);
2304                                 return;
2305                         }
2306                 }
2307
2308                 pr_err("%s: Got data interrupt 0x%08x even "
2309                         "though no data operation was in progress.\n",
2310                         mmc_hostname(host->mmc), (unsigned)intmask);
2311                 sdhci_dumpregs(host);
2312
2313                 return;
2314         }
2315
2316         if (intmask & SDHCI_INT_DATA_TIMEOUT)
2317                 host->data->error = -ETIMEDOUT;
2318         else if (intmask & SDHCI_INT_DATA_END_BIT)
2319                 host->data->error = -EILSEQ;
2320         else if ((intmask & SDHCI_INT_DATA_CRC) &&
2321                 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2322                         != MMC_BUS_TEST_R)
2323                 host->data->error = -EILSEQ;
2324         else if (intmask & SDHCI_INT_ADMA_ERROR) {
2325                 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2326                 sdhci_show_adma_error(host);
2327                 host->data->error = -EIO;
2328                 if (host->ops->adma_workaround)
2329                         host->ops->adma_workaround(host, intmask);
2330         }
2331
2332         if (host->data->error)
2333                 sdhci_finish_data(host);
2334         else {
2335                 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2336                         sdhci_transfer_pio(host);
2337
2338                 /*
2339                  * We currently don't do anything fancy with DMA
2340                  * boundaries, but as we can't disable the feature
2341                  * we need to at least restart the transfer.
2342                  *
2343                  * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2344                  * should return a valid address to continue from, but as
2345                  * some controllers are faulty, don't trust them.
2346                  */
2347                 if (intmask & SDHCI_INT_DMA_END) {
2348                         u32 dmastart, dmanow;
2349                         dmastart = sg_dma_address(host->data->sg);
2350                         dmanow = dmastart + host->data->bytes_xfered;
2351                         /*
2352                          * Force update to the next DMA block boundary.
2353                          */
2354                         dmanow = (dmanow &
2355                                 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2356                                 SDHCI_DEFAULT_BOUNDARY_SIZE;
2357                         host->data->bytes_xfered = dmanow - dmastart;
2358                         DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2359                                 " next 0x%08x\n",
2360                                 mmc_hostname(host->mmc), dmastart,
2361                                 host->data->bytes_xfered, dmanow);
2362                         sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2363                 }
2364
2365                 if (intmask & SDHCI_INT_DATA_END) {
2366                         if (host->cmd) {
2367                                 /*
2368                                  * Data managed to finish before the
2369                                  * command completed. Make sure we do
2370                                  * things in the proper order.
2371                                  */
2372                                 host->data_early = 1;
2373                         } else {
2374                                 sdhci_finish_data(host);
2375                         }
2376                 }
2377         }
2378 }
2379
2380 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2381 {
2382         irqreturn_t result = IRQ_NONE;
2383         struct sdhci_host *host = dev_id;
2384         u32 intmask, mask, unexpected = 0;
2385         int max_loops = 16;
2386
2387         spin_lock(&host->lock);
2388
2389         if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2390                 spin_unlock(&host->lock);
2391                 return IRQ_NONE;
2392         }
2393
2394         intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2395         if (!intmask || intmask == 0xffffffff) {
2396                 result = IRQ_NONE;
2397                 goto out;
2398         }
2399
2400         do {
2401                 /* Clear selected interrupts. */
2402                 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2403                                   SDHCI_INT_BUS_POWER);
2404                 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2405
2406                 DBG("*** %s got interrupt: 0x%08x\n",
2407                         mmc_hostname(host->mmc), intmask);
2408
2409                 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2410                         u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2411                                       SDHCI_CARD_PRESENT;
2412
2413                         /*
2414                          * There is a observation on i.mx esdhc.  INSERT
2415                          * bit will be immediately set again when it gets
2416                          * cleared, if a card is inserted.  We have to mask
2417                          * the irq to prevent interrupt storm which will
2418                          * freeze the system.  And the REMOVE gets the
2419                          * same situation.
2420                          *
2421                          * More testing are needed here to ensure it works
2422                          * for other platforms though.
2423                          */
2424                         host->ier &= ~(SDHCI_INT_CARD_INSERT |
2425                                        SDHCI_INT_CARD_REMOVE);
2426                         host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2427                                                SDHCI_INT_CARD_INSERT;
2428                         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2429                         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2430
2431                         sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2432                                      SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2433
2434                         host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2435                                                        SDHCI_INT_CARD_REMOVE);
2436                         result = IRQ_WAKE_THREAD;
2437                 }
2438
2439                 if (intmask & SDHCI_INT_CMD_MASK)
2440                         sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2441
2442                 if (intmask & SDHCI_INT_DATA_MASK)
2443                         sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2444
2445                 if (intmask & SDHCI_INT_BUS_POWER)
2446                         pr_err("%s: Card is consuming too much power!\n",
2447                                 mmc_hostname(host->mmc));
2448
2449                 if (intmask & SDHCI_INT_CARD_INT) {
2450                         sdhci_enable_sdio_irq_nolock(host, false);
2451                         host->thread_isr |= SDHCI_INT_CARD_INT;
2452                         result = IRQ_WAKE_THREAD;
2453                 }
2454
2455                 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2456                              SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2457                              SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2458                              SDHCI_INT_CARD_INT);
2459
2460                 if (intmask) {
2461                         unexpected |= intmask;
2462                         sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2463                 }
2464
2465                 if (result == IRQ_NONE)
2466                         result = IRQ_HANDLED;
2467
2468                 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2469         } while (intmask && --max_loops);
2470 out:
2471         spin_unlock(&host->lock);
2472
2473         if (unexpected) {
2474                 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2475                            mmc_hostname(host->mmc), unexpected);
2476                 sdhci_dumpregs(host);
2477         }
2478
2479         return result;
2480 }
2481
2482 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2483 {
2484         struct sdhci_host *host = dev_id;
2485         unsigned long flags;
2486         u32 isr;
2487
2488         spin_lock_irqsave(&host->lock, flags);
2489         isr = host->thread_isr;
2490         host->thread_isr = 0;
2491         spin_unlock_irqrestore(&host->lock, flags);
2492
2493         if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2494                 sdhci_card_event(host->mmc);
2495                 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2496         }
2497
2498         if (isr & SDHCI_INT_CARD_INT) {
2499                 sdio_run_irqs(host->mmc);
2500
2501                 spin_lock_irqsave(&host->lock, flags);
2502                 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2503                         sdhci_enable_sdio_irq_nolock(host, true);
2504                 spin_unlock_irqrestore(&host->lock, flags);
2505         }
2506
2507         return isr ? IRQ_HANDLED : IRQ_NONE;
2508 }
2509
2510 /*****************************************************************************\
2511  *                                                                           *
2512  * Suspend/resume                                                            *
2513  *                                                                           *
2514 \*****************************************************************************/
2515
2516 #ifdef CONFIG_PM
2517 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2518 {
2519         u8 val;
2520         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2521                         | SDHCI_WAKE_ON_INT;
2522
2523         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2524         val |= mask ;
2525         /* Avoid fake wake up */
2526         if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2527                 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2528         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2529 }
2530 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2531
2532 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2533 {
2534         u8 val;
2535         u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2536                         | SDHCI_WAKE_ON_INT;
2537
2538         val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2539         val &= ~mask;
2540         sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2541 }
2542 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2543
2544 int sdhci_suspend_host(struct sdhci_host *host)
2545 {
2546         sdhci_disable_card_detection(host);
2547
2548         /* Disable tuning since we are suspending */
2549         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2550                 del_timer_sync(&host->tuning_timer);
2551                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2552         }
2553
2554         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2555                 host->ier = 0;
2556                 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2557                 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2558                 free_irq(host->irq, host);
2559         } else {
2560                 sdhci_enable_irq_wakeups(host);
2561                 enable_irq_wake(host->irq);
2562         }
2563         return 0;
2564 }
2565
2566 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2567
2568 int sdhci_resume_host(struct sdhci_host *host)
2569 {
2570         int ret = 0;
2571
2572         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2573                 if (host->ops->enable_dma)
2574                         host->ops->enable_dma(host);
2575         }
2576
2577         if (!device_may_wakeup(mmc_dev(host->mmc))) {
2578                 ret = request_threaded_irq(host->irq, sdhci_irq,
2579                                            sdhci_thread_irq, IRQF_SHARED,
2580                                            mmc_hostname(host->mmc), host);
2581                 if (ret)
2582                         return ret;
2583         } else {
2584                 sdhci_disable_irq_wakeups(host);
2585                 disable_irq_wake(host->irq);
2586         }
2587
2588         if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2589             (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2590                 /* Card keeps power but host controller does not */
2591                 sdhci_init(host, 0);
2592                 host->pwr = 0;
2593                 host->clock = 0;
2594                 sdhci_do_set_ios(host, &host->mmc->ios);
2595         } else {
2596                 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2597                 mmiowb();
2598         }
2599
2600         sdhci_enable_card_detection(host);
2601
2602         /* Set the re-tuning expiration flag */
2603         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2604                 host->flags |= SDHCI_NEEDS_RETUNING;
2605
2606         return ret;
2607 }
2608
2609 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2610 #endif /* CONFIG_PM */
2611
2612 #ifdef CONFIG_PM_RUNTIME
2613
2614 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2615 {
2616         return pm_runtime_get_sync(host->mmc->parent);
2617 }
2618
2619 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2620 {
2621         pm_runtime_mark_last_busy(host->mmc->parent);
2622         return pm_runtime_put_autosuspend(host->mmc->parent);
2623 }
2624
2625 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2626 {
2627         if (host->runtime_suspended || host->bus_on)
2628                 return;
2629         host->bus_on = true;
2630         pm_runtime_get_noresume(host->mmc->parent);
2631 }
2632
2633 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2634 {
2635         if (host->runtime_suspended || !host->bus_on)
2636                 return;
2637         host->bus_on = false;
2638         pm_runtime_put_noidle(host->mmc->parent);
2639 }
2640
2641 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2642 {
2643         unsigned long flags;
2644         int ret = 0;
2645
2646         /* Disable tuning since we are suspending */
2647         if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2648                 del_timer_sync(&host->tuning_timer);
2649                 host->flags &= ~SDHCI_NEEDS_RETUNING;
2650         }
2651
2652         spin_lock_irqsave(&host->lock, flags);
2653         host->ier &= SDHCI_INT_CARD_INT;
2654         sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2655         sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2656         spin_unlock_irqrestore(&host->lock, flags);
2657
2658         synchronize_hardirq(host->irq);
2659
2660         spin_lock_irqsave(&host->lock, flags);
2661         host->runtime_suspended = true;
2662         spin_unlock_irqrestore(&host->lock, flags);
2663
2664         return ret;
2665 }
2666 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2667
2668 int sdhci_runtime_resume_host(struct sdhci_host *host)
2669 {
2670         unsigned long flags;
2671         int ret = 0, host_flags = host->flags;
2672
2673         if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2674                 if (host->ops->enable_dma)
2675                         host->ops->enable_dma(host);
2676         }
2677
2678         sdhci_init(host, 0);
2679
2680         /* Force clock and power re-program */
2681         host->pwr = 0;
2682         host->clock = 0;
2683         sdhci_do_set_ios(host, &host->mmc->ios);
2684
2685         sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2686         if ((host_flags & SDHCI_PV_ENABLED) &&
2687                 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2688                 spin_lock_irqsave(&host->lock, flags);
2689                 sdhci_enable_preset_value(host, true);
2690                 spin_unlock_irqrestore(&host->lock, flags);
2691         }
2692
2693         /* Set the re-tuning expiration flag */
2694         if (host->flags & SDHCI_USING_RETUNING_TIMER)
2695                 host->flags |= SDHCI_NEEDS_RETUNING;
2696
2697         spin_lock_irqsave(&host->lock, flags);
2698
2699         host->runtime_suspended = false;
2700
2701         /* Enable SDIO IRQ */
2702         if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2703                 sdhci_enable_sdio_irq_nolock(host, true);
2704
2705         /* Enable Card Detection */
2706         sdhci_enable_card_detection(host);
2707
2708         spin_unlock_irqrestore(&host->lock, flags);
2709
2710         return ret;
2711 }
2712 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2713
2714 #endif
2715
2716 /*****************************************************************************\
2717  *                                                                           *
2718  * Device allocation/registration                                            *
2719  *                                                                           *
2720 \*****************************************************************************/
2721
2722 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2723         size_t priv_size)
2724 {
2725         struct mmc_host *mmc;
2726         struct sdhci_host *host;
2727
2728         WARN_ON(dev == NULL);
2729
2730         mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2731         if (!mmc)
2732                 return ERR_PTR(-ENOMEM);
2733
2734         host = mmc_priv(mmc);
2735         host->mmc = mmc;
2736
2737         return host;
2738 }
2739
2740 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2741
2742 int sdhci_add_host(struct sdhci_host *host)
2743 {
2744         struct mmc_host *mmc;
2745         u32 caps[2] = {0, 0};
2746         u32 max_current_caps;
2747         unsigned int ocr_avail;
2748         int ret;
2749
2750         WARN_ON(host == NULL);
2751         if (host == NULL)
2752                 return -EINVAL;
2753
2754         mmc = host->mmc;
2755
2756         if (debug_quirks)
2757                 host->quirks = debug_quirks;
2758         if (debug_quirks2)
2759                 host->quirks2 = debug_quirks2;
2760
2761         sdhci_do_reset(host, SDHCI_RESET_ALL);
2762
2763         host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2764         host->version = (host->version & SDHCI_SPEC_VER_MASK)
2765                                 >> SDHCI_SPEC_VER_SHIFT;
2766         if (host->version > SDHCI_SPEC_300) {
2767                 pr_err("%s: Unknown controller version (%d). "
2768                         "You may experience problems.\n", mmc_hostname(mmc),
2769                         host->version);
2770         }
2771
2772         caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2773                 sdhci_readl(host, SDHCI_CAPABILITIES);
2774
2775         if (host->version >= SDHCI_SPEC_300)
2776                 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2777                         host->caps1 :
2778                         sdhci_readl(host, SDHCI_CAPABILITIES_1);
2779
2780         if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2781                 host->flags |= SDHCI_USE_SDMA;
2782         else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2783                 DBG("Controller doesn't have SDMA capability\n");
2784         else
2785                 host->flags |= SDHCI_USE_SDMA;
2786
2787         if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2788                 (host->flags & SDHCI_USE_SDMA)) {
2789                 DBG("Disabling DMA as it is marked broken\n");
2790                 host->flags &= ~SDHCI_USE_SDMA;
2791         }
2792
2793         if ((host->version >= SDHCI_SPEC_200) &&
2794                 (caps[0] & SDHCI_CAN_DO_ADMA2))
2795                 host->flags |= SDHCI_USE_ADMA;
2796
2797         if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2798                 (host->flags & SDHCI_USE_ADMA)) {
2799                 DBG("Disabling ADMA as it is marked broken\n");
2800                 host->flags &= ~SDHCI_USE_ADMA;
2801         }
2802
2803         if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2804                 if (host->ops->enable_dma) {
2805                         if (host->ops->enable_dma(host)) {
2806                                 pr_warning("%s: No suitable DMA "
2807                                         "available. Falling back to PIO.\n",
2808                                         mmc_hostname(mmc));
2809                                 host->flags &=
2810                                         ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2811                         }
2812                 }
2813         }
2814
2815         if (host->flags & SDHCI_USE_ADMA) {
2816                 /*
2817                  * We need to allocate descriptors for all sg entries
2818                  * (128) and potentially one alignment transfer for
2819                  * each of those entries.
2820                  */
2821                 host->adma_desc = dma_alloc_coherent(mmc_dev(host->mmc),
2822                                                      ADMA_SIZE, &host->adma_addr,
2823                                                      GFP_KERNEL);
2824                 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2825                 if (!host->adma_desc || !host->align_buffer) {
2826                         dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2827                                           host->adma_desc, host->adma_addr);
2828                         kfree(host->align_buffer);
2829                         pr_warning("%s: Unable to allocate ADMA "
2830                                 "buffers. Falling back to standard DMA.\n",
2831                                 mmc_hostname(mmc));
2832                         host->flags &= ~SDHCI_USE_ADMA;
2833                         host->adma_desc = NULL;
2834                         host->align_buffer = NULL;
2835                 } else if (host->adma_addr & 3) {
2836                         pr_warning("%s: unable to allocate aligned ADMA descriptor\n",
2837                                    mmc_hostname(mmc));
2838                         host->flags &= ~SDHCI_USE_ADMA;
2839                         dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
2840                                           host->adma_desc, host->adma_addr);
2841                         kfree(host->align_buffer);
2842                         host->adma_desc = NULL;
2843                         host->align_buffer = NULL;
2844                 }
2845         }
2846
2847         /*
2848          * If we use DMA, then it's up to the caller to set the DMA
2849          * mask, but PIO does not need the hw shim so we set a new
2850          * mask here in that case.
2851          */
2852         if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2853                 host->dma_mask = DMA_BIT_MASK(64);
2854                 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2855         }
2856
2857         if (host->version >= SDHCI_SPEC_300)
2858                 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2859                         >> SDHCI_CLOCK_BASE_SHIFT;
2860         else
2861                 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2862                         >> SDHCI_CLOCK_BASE_SHIFT;
2863
2864         host->max_clk *= 1000000;
2865         if (host->max_clk == 0 || host->quirks &
2866                         SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2867                 if (!host->ops->get_max_clock) {
2868                         pr_err("%s: Hardware doesn't specify base clock "
2869                                "frequency.\n", mmc_hostname(mmc));
2870                         return -ENODEV;
2871                 }
2872                 host->max_clk = host->ops->get_max_clock(host);
2873         }
2874
2875         /*
2876          * In case of Host Controller v3.00, find out whether clock
2877          * multiplier is supported.
2878          */
2879         host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2880                         SDHCI_CLOCK_MUL_SHIFT;
2881
2882         /*
2883          * In case the value in Clock Multiplier is 0, then programmable
2884          * clock mode is not supported, otherwise the actual clock
2885          * multiplier is one more than the value of Clock Multiplier
2886          * in the Capabilities Register.
2887          */
2888         if (host->clk_mul)
2889                 host->clk_mul += 1;
2890
2891         /*
2892          * Set host parameters.
2893          */
2894         mmc->ops = &sdhci_ops;
2895         mmc->f_max = host->max_clk;
2896         if (host->ops->get_min_clock)
2897                 mmc->f_min = host->ops->get_min_clock(host);
2898         else if (host->version >= SDHCI_SPEC_300) {
2899                 if (host->clk_mul) {
2900                         mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2901                         mmc->f_max = host->max_clk * host->clk_mul;
2902                 } else
2903                         mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2904         } else
2905                 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2906
2907         host->timeout_clk =
2908                 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2909         if (host->timeout_clk == 0) {
2910                 if (host->ops->get_timeout_clock) {
2911                         host->timeout_clk = host->ops->get_timeout_clock(host);
2912                 } else if (!(host->quirks &
2913                                 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2914                         pr_err("%s: Hardware doesn't specify timeout clock "
2915                                "frequency.\n", mmc_hostname(mmc));
2916                         return -ENODEV;
2917                 }
2918         }
2919         if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2920                 host->timeout_clk *= 1000;
2921
2922         if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2923                 host->timeout_clk = mmc->f_max / 1000;
2924
2925         mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
2926
2927         mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2928         mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2929
2930         if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2931                 host->flags |= SDHCI_AUTO_CMD12;
2932
2933         /* Auto-CMD23 stuff only works in ADMA or PIO. */
2934         if ((host->version >= SDHCI_SPEC_300) &&
2935             ((host->flags & SDHCI_USE_ADMA) ||
2936              !(host->flags & SDHCI_USE_SDMA))) {
2937                 host->flags |= SDHCI_AUTO_CMD23;
2938                 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2939         } else {
2940                 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2941         }
2942
2943         /*
2944          * A controller may support 8-bit width, but the board itself
2945          * might not have the pins brought out.  Boards that support
2946          * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2947          * their platform code before calling sdhci_add_host(), and we
2948          * won't assume 8-bit width for hosts without that CAP.
2949          */
2950         if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2951                 mmc->caps |= MMC_CAP_4_BIT_DATA;
2952
2953         if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2954                 mmc->caps &= ~MMC_CAP_CMD23;
2955
2956         if (caps[0] & SDHCI_CAN_DO_HISPD)
2957                 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2958
2959         if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2960             !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2961                 mmc->caps |= MMC_CAP_NEEDS_POLL;
2962
2963         /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2964         host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
2965         if (IS_ERR_OR_NULL(host->vqmmc)) {
2966                 if (PTR_ERR(host->vqmmc) < 0) {
2967                         pr_info("%s: no vqmmc regulator found\n",
2968                                 mmc_hostname(mmc));
2969                         host->vqmmc = NULL;
2970                 }
2971         } else {
2972                 ret = regulator_enable(host->vqmmc);
2973                 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2974                         1950000))
2975                         caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
2976                                         SDHCI_SUPPORT_SDR50 |
2977                                         SDHCI_SUPPORT_DDR50);
2978                 if (ret) {
2979                         pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
2980                                 mmc_hostname(mmc), ret);
2981                         host->vqmmc = NULL;
2982                 }
2983         }
2984
2985         if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
2986                 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2987                        SDHCI_SUPPORT_DDR50);
2988
2989         /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
2990         if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
2991                        SDHCI_SUPPORT_DDR50))
2992                 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
2993
2994         /* SDR104 supports also implies SDR50 support */
2995         if (caps[1] & SDHCI_SUPPORT_SDR104) {
2996                 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
2997                 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
2998                  * field can be promoted to support HS200.
2999                  */
3000                 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3001                         mmc->caps2 |= MMC_CAP2_HS200;
3002         } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3003                 mmc->caps |= MMC_CAP_UHS_SDR50;
3004
3005         if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3006                 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3007                 mmc->caps |= MMC_CAP_UHS_DDR50;
3008
3009         /* Does the host need tuning for SDR50? */
3010         if (caps[1] & SDHCI_USE_SDR50_TUNING)
3011                 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3012
3013         /* Does the host need tuning for SDR104 / HS200? */
3014         if (mmc->caps2 & MMC_CAP2_HS200)
3015                 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3016
3017         /* Driver Type(s) (A, C, D) supported by the host */
3018         if (caps[1] & SDHCI_DRIVER_TYPE_A)
3019                 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3020         if (caps[1] & SDHCI_DRIVER_TYPE_C)
3021                 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3022         if (caps[1] & SDHCI_DRIVER_TYPE_D)
3023                 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3024
3025         /* Initial value for re-tuning timer count */
3026         host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3027                               SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3028
3029         /*
3030          * In case Re-tuning Timer is not disabled, the actual value of
3031          * re-tuning timer will be 2 ^ (n - 1).
3032          */
3033         if (host->tuning_count)
3034                 host->tuning_count = 1 << (host->tuning_count - 1);
3035
3036         /* Re-tuning mode supported by the Host Controller */
3037         host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3038                              SDHCI_RETUNING_MODE_SHIFT;
3039
3040         ocr_avail = 0;
3041
3042         host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
3043         if (IS_ERR_OR_NULL(host->vmmc)) {
3044                 if (PTR_ERR(host->vmmc) < 0) {
3045                         pr_info("%s: no vmmc regulator found\n",
3046                                 mmc_hostname(mmc));
3047                         host->vmmc = NULL;
3048                 }
3049         }
3050
3051 #ifdef CONFIG_REGULATOR
3052         /*
3053          * Voltage range check makes sense only if regulator reports
3054          * any voltage value.
3055          */
3056         if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3057                 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3058                         3600000);
3059                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3060                         caps[0] &= ~SDHCI_CAN_VDD_330;
3061                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3062                         caps[0] &= ~SDHCI_CAN_VDD_300;
3063                 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3064                         1950000);
3065                 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3066                         caps[0] &= ~SDHCI_CAN_VDD_180;
3067         }
3068 #endif /* CONFIG_REGULATOR */
3069
3070         /*
3071          * According to SD Host Controller spec v3.00, if the Host System
3072          * can afford more than 150mA, Host Driver should set XPC to 1. Also
3073          * the value is meaningful only if Voltage Support in the Capabilities
3074          * register is set. The actual current value is 4 times the register
3075          * value.
3076          */
3077         max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3078         if (!max_current_caps && host->vmmc) {
3079                 u32 curr = regulator_get_current_limit(host->vmmc);
3080                 if (curr > 0) {
3081
3082                         /* convert to SDHCI_MAX_CURRENT format */
3083                         curr = curr/1000;  /* convert to mA */
3084                         curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3085
3086                         curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3087                         max_current_caps =
3088                                 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3089                                 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3090                                 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3091                 }
3092         }
3093
3094         if (caps[0] & SDHCI_CAN_VDD_330) {
3095                 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3096
3097                 mmc->max_current_330 = ((max_current_caps &
3098                                    SDHCI_MAX_CURRENT_330_MASK) >>
3099                                    SDHCI_MAX_CURRENT_330_SHIFT) *
3100                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3101         }
3102         if (caps[0] & SDHCI_CAN_VDD_300) {
3103                 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3104
3105                 mmc->max_current_300 = ((max_current_caps &
3106                                    SDHCI_MAX_CURRENT_300_MASK) >>
3107                                    SDHCI_MAX_CURRENT_300_SHIFT) *
3108                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3109         }
3110         if (caps[0] & SDHCI_CAN_VDD_180) {
3111                 ocr_avail |= MMC_VDD_165_195;
3112
3113                 mmc->max_current_180 = ((max_current_caps &
3114                                    SDHCI_MAX_CURRENT_180_MASK) >>
3115                                    SDHCI_MAX_CURRENT_180_SHIFT) *
3116                                    SDHCI_MAX_CURRENT_MULTIPLIER;
3117         }
3118
3119         if (host->ocr_mask)
3120                 ocr_avail = host->ocr_mask;
3121
3122         mmc->ocr_avail = ocr_avail;
3123         mmc->ocr_avail_sdio = ocr_avail;
3124         if (host->ocr_avail_sdio)
3125                 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3126         mmc->ocr_avail_sd = ocr_avail;
3127         if (host->ocr_avail_sd)
3128                 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3129         else /* normal SD controllers don't support 1.8V */
3130                 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3131         mmc->ocr_avail_mmc = ocr_avail;
3132         if (host->ocr_avail_mmc)
3133                 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3134
3135         if (mmc->ocr_avail == 0) {
3136                 pr_err("%s: Hardware doesn't report any "
3137                         "support voltages.\n", mmc_hostname(mmc));
3138                 return -ENODEV;
3139         }
3140
3141         spin_lock_init(&host->lock);
3142
3143         /*
3144          * Maximum number of segments. Depends on if the hardware
3145          * can do scatter/gather or not.
3146          */
3147         if (host->flags & SDHCI_USE_ADMA)
3148                 mmc->max_segs = 128;
3149         else if (host->flags & SDHCI_USE_SDMA)
3150                 mmc->max_segs = 1;
3151         else /* PIO */
3152                 mmc->max_segs = 128;
3153
3154         /*
3155          * Maximum number of sectors in one transfer. Limited by DMA boundary
3156          * size (512KiB).
3157          */
3158         mmc->max_req_size = 524288;
3159
3160         /*
3161          * Maximum segment size. Could be one segment with the maximum number
3162          * of bytes. When doing hardware scatter/gather, each entry cannot
3163          * be larger than 64 KiB though.
3164          */
3165         if (host->flags & SDHCI_USE_ADMA) {
3166                 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3167                         mmc->max_seg_size = 65535;
3168                 else
3169                         mmc->max_seg_size = 65536;
3170         } else {
3171                 mmc->max_seg_size = mmc->max_req_size;
3172         }
3173
3174         /*
3175          * Maximum block size. This varies from controller to controller and
3176          * is specified in the capabilities register.
3177          */
3178         if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3179                 mmc->max_blk_size = 2;
3180         } else {
3181                 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3182                                 SDHCI_MAX_BLOCK_SHIFT;
3183                 if (mmc->max_blk_size >= 3) {
3184                         pr_warning("%s: Invalid maximum block size, "
3185                                 "assuming 512 bytes\n", mmc_hostname(mmc));
3186                         mmc->max_blk_size = 0;
3187                 }
3188         }
3189
3190         mmc->max_blk_size = 512 << mmc->max_blk_size;
3191
3192         /*
3193          * Maximum block count.
3194          */
3195         mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3196
3197         /*
3198          * Init tasklets.
3199          */
3200         tasklet_init(&host->finish_tasklet,
3201                 sdhci_tasklet_finish, (unsigned long)host);
3202
3203         setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3204
3205         if (host->version >= SDHCI_SPEC_300) {
3206                 init_waitqueue_head(&host->buf_ready_int);
3207
3208                 /* Initialize re-tuning timer */
3209                 init_timer(&host->tuning_timer);
3210                 host->tuning_timer.data = (unsigned long)host;
3211                 host->tuning_timer.function = sdhci_tuning_timer;
3212         }
3213
3214         sdhci_init(host, 0);
3215
3216         ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3217                                    IRQF_SHARED, mmc_hostname(mmc), host);
3218         if (ret) {
3219                 pr_err("%s: Failed to request IRQ %d: %d\n",
3220                        mmc_hostname(mmc), host->irq, ret);
3221                 goto untasklet;
3222         }
3223
3224 #ifdef CONFIG_MMC_DEBUG
3225         sdhci_dumpregs(host);
3226 #endif
3227
3228 #ifdef SDHCI_USE_LEDS_CLASS
3229         snprintf(host->led_name, sizeof(host->led_name),
3230                 "%s::", mmc_hostname(mmc));
3231         host->led.name = host->led_name;
3232         host->led.brightness = LED_OFF;
3233         host->led.default_trigger = mmc_hostname(mmc);
3234         host->led.brightness_set = sdhci_led_control;
3235
3236         ret = led_classdev_register(mmc_dev(mmc), &host->led);
3237         if (ret) {
3238                 pr_err("%s: Failed to register LED device: %d\n",
3239                        mmc_hostname(mmc), ret);
3240                 goto reset;
3241         }
3242 #endif
3243
3244         mmiowb();
3245
3246         mmc_add_host(mmc);
3247
3248         pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3249                 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3250                 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3251                 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3252
3253         sdhci_enable_card_detection(host);
3254
3255         return 0;
3256
3257 #ifdef SDHCI_USE_LEDS_CLASS
3258 reset:
3259         sdhci_do_reset(host, SDHCI_RESET_ALL);
3260         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3261         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3262         free_irq(host->irq, host);
3263 #endif
3264 untasklet:
3265         tasklet_kill(&host->finish_tasklet);
3266
3267         return ret;
3268 }
3269
3270 EXPORT_SYMBOL_GPL(sdhci_add_host);
3271
3272 void sdhci_remove_host(struct sdhci_host *host, int dead)
3273 {
3274         unsigned long flags;
3275
3276         if (dead) {
3277                 spin_lock_irqsave(&host->lock, flags);
3278
3279                 host->flags |= SDHCI_DEVICE_DEAD;
3280
3281                 if (host->mrq) {
3282                         pr_err("%s: Controller removed during "
3283                                 " transfer!\n", mmc_hostname(host->mmc));
3284
3285                         host->mrq->cmd->error = -ENOMEDIUM;
3286                         tasklet_schedule(&host->finish_tasklet);
3287                 }
3288
3289                 spin_unlock_irqrestore(&host->lock, flags);
3290         }
3291
3292         sdhci_disable_card_detection(host);
3293
3294         mmc_remove_host(host->mmc);
3295
3296 #ifdef SDHCI_USE_LEDS_CLASS
3297         led_classdev_unregister(&host->led);
3298 #endif
3299
3300         if (!dead)
3301                 sdhci_do_reset(host, SDHCI_RESET_ALL);
3302
3303         sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3304         sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3305         free_irq(host->irq, host);
3306
3307         del_timer_sync(&host->timer);
3308
3309         tasklet_kill(&host->finish_tasklet);
3310
3311         if (host->vmmc) {
3312                 regulator_disable(host->vmmc);
3313                 regulator_put(host->vmmc);
3314         }
3315
3316         if (host->vqmmc) {
3317                 regulator_disable(host->vqmmc);
3318                 regulator_put(host->vqmmc);
3319         }
3320
3321         if (host->adma_desc)
3322                 dma_free_coherent(mmc_dev(host->mmc), ADMA_SIZE,
3323                                   host->adma_desc, host->adma_addr);
3324         kfree(host->align_buffer);
3325
3326         host->adma_desc = NULL;
3327         host->align_buffer = NULL;
3328 }
3329
3330 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3331
3332 void sdhci_free_host(struct sdhci_host *host)
3333 {
3334         mmc_free_host(host->mmc);
3335 }
3336
3337 EXPORT_SYMBOL_GPL(sdhci_free_host);
3338
3339 /*****************************************************************************\
3340  *                                                                           *
3341  * Driver init/exit                                                          *
3342  *                                                                           *
3343 \*****************************************************************************/
3344
3345 static int __init sdhci_drv_init(void)
3346 {
3347         pr_info(DRIVER_NAME
3348                 ": Secure Digital Host Controller Interface driver\n");
3349         pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3350
3351         return 0;
3352 }
3353
3354 static void __exit sdhci_drv_exit(void)
3355 {
3356 }
3357
3358 module_init(sdhci_drv_init);
3359 module_exit(sdhci_drv_exit);
3360
3361 module_param(debug_quirks, uint, 0444);
3362 module_param(debug_quirks2, uint, 0444);
3363
3364 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3365 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3366 MODULE_LICENSE("GPL");
3367
3368 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3369 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");