2 * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver
4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or (at
9 * your option) any later version.
11 * Thanks to the following companies for their support:
13 * - JMicron (hardware and technical support)
16 #include <linux/delay.h>
17 #include <linux/highmem.h>
19 #include <linux/module.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/slab.h>
22 #include <linux/scatterlist.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/pm_runtime.h>
26 #include <linux/leds.h>
28 #include <linux/mmc/mmc.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/card.h>
31 #include <linux/mmc/slot-gpio.h>
35 #define DRIVER_NAME "sdhci"
37 #define DBG(f, x...) \
38 pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x)
40 #if defined(CONFIG_LEDS_CLASS) || (defined(CONFIG_LEDS_CLASS_MODULE) && \
41 defined(CONFIG_MMC_SDHCI_MODULE))
42 #define SDHCI_USE_LEDS_CLASS
45 #define MAX_TUNING_LOOP 40
47 static unsigned int debug_quirks = 0;
48 static unsigned int debug_quirks2;
50 static void sdhci_finish_data(struct sdhci_host *);
52 static void sdhci_finish_command(struct sdhci_host *);
53 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
54 static void sdhci_tuning_timer(unsigned long data);
55 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable);
57 #ifdef CONFIG_PM_RUNTIME
58 static int sdhci_runtime_pm_get(struct sdhci_host *host);
59 static int sdhci_runtime_pm_put(struct sdhci_host *host);
60 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host);
61 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host);
63 static inline int sdhci_runtime_pm_get(struct sdhci_host *host)
67 static inline int sdhci_runtime_pm_put(struct sdhci_host *host)
71 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
74 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
79 static void sdhci_dumpregs(struct sdhci_host *host)
81 pr_debug(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n",
82 mmc_hostname(host->mmc));
84 pr_debug(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n",
85 sdhci_readl(host, SDHCI_DMA_ADDRESS),
86 sdhci_readw(host, SDHCI_HOST_VERSION));
87 pr_debug(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n",
88 sdhci_readw(host, SDHCI_BLOCK_SIZE),
89 sdhci_readw(host, SDHCI_BLOCK_COUNT));
90 pr_debug(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n",
91 sdhci_readl(host, SDHCI_ARGUMENT),
92 sdhci_readw(host, SDHCI_TRANSFER_MODE));
93 pr_debug(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n",
94 sdhci_readl(host, SDHCI_PRESENT_STATE),
95 sdhci_readb(host, SDHCI_HOST_CONTROL));
96 pr_debug(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n",
97 sdhci_readb(host, SDHCI_POWER_CONTROL),
98 sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL));
99 pr_debug(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n",
100 sdhci_readb(host, SDHCI_WAKE_UP_CONTROL),
101 sdhci_readw(host, SDHCI_CLOCK_CONTROL));
102 pr_debug(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n",
103 sdhci_readb(host, SDHCI_TIMEOUT_CONTROL),
104 sdhci_readl(host, SDHCI_INT_STATUS));
105 pr_debug(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n",
106 sdhci_readl(host, SDHCI_INT_ENABLE),
107 sdhci_readl(host, SDHCI_SIGNAL_ENABLE));
108 pr_debug(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n",
109 sdhci_readw(host, SDHCI_ACMD12_ERR),
110 sdhci_readw(host, SDHCI_SLOT_INT_STATUS));
111 pr_debug(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n",
112 sdhci_readl(host, SDHCI_CAPABILITIES),
113 sdhci_readl(host, SDHCI_CAPABILITIES_1));
114 pr_debug(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
115 sdhci_readw(host, SDHCI_COMMAND),
116 sdhci_readl(host, SDHCI_MAX_CURRENT));
117 pr_debug(DRIVER_NAME ": Host ctl2: 0x%08x\n",
118 sdhci_readw(host, SDHCI_HOST_CONTROL2));
120 if (host->flags & SDHCI_USE_ADMA)
121 pr_debug(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
122 readl(host->ioaddr + SDHCI_ADMA_ERROR),
123 readl(host->ioaddr + SDHCI_ADMA_ADDRESS));
125 pr_debug(DRIVER_NAME ": ===========================================\n");
128 /*****************************************************************************\
130 * Low level functions *
132 \*****************************************************************************/
134 static void sdhci_set_card_detection(struct sdhci_host *host, bool enable)
138 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
139 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
143 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
146 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
147 SDHCI_INT_CARD_INSERT;
149 host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
152 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
153 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
156 static void sdhci_enable_card_detection(struct sdhci_host *host)
158 sdhci_set_card_detection(host, true);
161 static void sdhci_disable_card_detection(struct sdhci_host *host)
163 sdhci_set_card_detection(host, false);
166 void sdhci_reset(struct sdhci_host *host, u8 mask)
168 unsigned long timeout;
170 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
172 if (mask & SDHCI_RESET_ALL) {
174 /* Reset-all turns off SD Bus Power */
175 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
176 sdhci_runtime_pm_bus_off(host);
179 /* Wait max 100 ms */
182 /* hw clears the bit when it's done */
183 while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
185 pr_err("%s: Reset 0x%x never completed.\n",
186 mmc_hostname(host->mmc), (int)mask);
187 sdhci_dumpregs(host);
194 EXPORT_SYMBOL_GPL(sdhci_reset);
196 static void sdhci_do_reset(struct sdhci_host *host, u8 mask)
198 if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) {
199 if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
204 host->ops->reset(host, mask);
206 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
207 if ((host->ops->enable_dma) && (mask & SDHCI_RESET_ALL))
208 host->ops->enable_dma(host);
212 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios);
214 static void sdhci_init(struct sdhci_host *host, int soft)
217 sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA);
219 sdhci_do_reset(host, SDHCI_RESET_ALL);
221 host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT |
222 SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT |
223 SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC |
224 SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END |
227 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
228 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
231 /* force clock reconfiguration */
233 sdhci_set_ios(host->mmc, &host->mmc->ios);
237 static void sdhci_reinit(struct sdhci_host *host)
241 * Retuning stuffs are affected by different cards inserted and only
242 * applicable to UHS-I cards. So reset these fields to their initial
243 * value when card is removed.
245 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
246 host->flags &= ~SDHCI_USING_RETUNING_TIMER;
248 del_timer_sync(&host->tuning_timer);
249 host->flags &= ~SDHCI_NEEDS_RETUNING;
250 host->mmc->max_blk_count =
251 (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
253 sdhci_enable_card_detection(host);
256 static void sdhci_activate_led(struct sdhci_host *host)
260 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
261 ctrl |= SDHCI_CTRL_LED;
262 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
265 static void sdhci_deactivate_led(struct sdhci_host *host)
269 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
270 ctrl &= ~SDHCI_CTRL_LED;
271 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
274 #ifdef SDHCI_USE_LEDS_CLASS
275 static void sdhci_led_control(struct led_classdev *led,
276 enum led_brightness brightness)
278 struct sdhci_host *host = container_of(led, struct sdhci_host, led);
281 spin_lock_irqsave(&host->lock, flags);
283 if (host->runtime_suspended)
286 if (brightness == LED_OFF)
287 sdhci_deactivate_led(host);
289 sdhci_activate_led(host);
291 spin_unlock_irqrestore(&host->lock, flags);
295 /*****************************************************************************\
299 \*****************************************************************************/
301 static void sdhci_read_block_pio(struct sdhci_host *host)
304 size_t blksize, len, chunk;
305 u32 uninitialized_var(scratch);
308 DBG("PIO reading\n");
310 blksize = host->data->blksz;
313 local_irq_save(flags);
316 if (!sg_miter_next(&host->sg_miter))
319 len = min(host->sg_miter.length, blksize);
322 host->sg_miter.consumed = len;
324 buf = host->sg_miter.addr;
328 scratch = sdhci_readl(host, SDHCI_BUFFER);
332 *buf = scratch & 0xFF;
341 sg_miter_stop(&host->sg_miter);
343 local_irq_restore(flags);
346 static void sdhci_write_block_pio(struct sdhci_host *host)
349 size_t blksize, len, chunk;
353 DBG("PIO writing\n");
355 blksize = host->data->blksz;
359 local_irq_save(flags);
362 if (!sg_miter_next(&host->sg_miter))
365 len = min(host->sg_miter.length, blksize);
368 host->sg_miter.consumed = len;
370 buf = host->sg_miter.addr;
373 scratch |= (u32)*buf << (chunk * 8);
379 if ((chunk == 4) || ((len == 0) && (blksize == 0))) {
380 sdhci_writel(host, scratch, SDHCI_BUFFER);
387 sg_miter_stop(&host->sg_miter);
389 local_irq_restore(flags);
392 static void sdhci_transfer_pio(struct sdhci_host *host)
398 if (host->blocks == 0)
401 if (host->data->flags & MMC_DATA_READ)
402 mask = SDHCI_DATA_AVAILABLE;
404 mask = SDHCI_SPACE_AVAILABLE;
407 * Some controllers (JMicron JMB38x) mess up the buffer bits
408 * for transfers < 4 bytes. As long as it is just one block,
409 * we can ignore the bits.
411 if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) &&
412 (host->data->blocks == 1))
415 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
416 if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY)
419 if (host->data->flags & MMC_DATA_READ)
420 sdhci_read_block_pio(host);
422 sdhci_write_block_pio(host);
425 if (host->blocks == 0)
429 DBG("PIO transfer complete.\n");
432 static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags)
434 local_irq_save(*flags);
435 return kmap_atomic(sg_page(sg)) + sg->offset;
438 static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags)
440 kunmap_atomic(buffer);
441 local_irq_restore(*flags);
444 static void sdhci_set_adma_desc(u8 *desc, u32 addr, int len, unsigned cmd)
446 __le32 *dataddr = (__le32 __force *)(desc + 4);
447 __le16 *cmdlen = (__le16 __force *)desc;
449 /* SDHCI specification says ADMA descriptors should be 4 byte
450 * aligned, so using 16 or 32bit operations should be safe. */
452 cmdlen[0] = cpu_to_le16(cmd);
453 cmdlen[1] = cpu_to_le16(len);
455 dataddr[0] = cpu_to_le32(addr);
458 static int sdhci_adma_table_pre(struct sdhci_host *host,
459 struct mmc_data *data)
466 dma_addr_t align_addr;
469 struct scatterlist *sg;
475 * The spec does not specify endianness of descriptor table.
476 * We currently guess that it is LE.
479 if (data->flags & MMC_DATA_READ)
480 direction = DMA_FROM_DEVICE;
482 direction = DMA_TO_DEVICE;
485 * The ADMA descriptor table is mapped further down as we
486 * need to fill it with data first.
489 host->align_addr = dma_map_single(mmc_dev(host->mmc),
490 host->align_buffer, 128 * 4, direction);
491 if (dma_mapping_error(mmc_dev(host->mmc), host->align_addr))
493 BUG_ON(host->align_addr & 0x3);
495 host->sg_count = dma_map_sg(mmc_dev(host->mmc),
496 data->sg, data->sg_len, direction);
497 if (host->sg_count == 0)
500 desc = host->adma_desc;
501 align = host->align_buffer;
503 align_addr = host->align_addr;
505 for_each_sg(data->sg, sg, host->sg_count, i) {
506 addr = sg_dma_address(sg);
507 len = sg_dma_len(sg);
510 * The SDHCI specification states that ADMA
511 * addresses must be 32-bit aligned. If they
512 * aren't, then we use a bounce buffer for
513 * the (up to three) bytes that screw up the
516 offset = (4 - (addr & 0x3)) & 0x3;
518 if (data->flags & MMC_DATA_WRITE) {
519 buffer = sdhci_kmap_atomic(sg, &flags);
520 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
521 memcpy(align, buffer, offset);
522 sdhci_kunmap_atomic(buffer, &flags);
526 sdhci_set_adma_desc(desc, align_addr, offset, 0x21);
528 BUG_ON(offset > 65536);
542 sdhci_set_adma_desc(desc, addr, len, 0x21);
546 * If this triggers then we have a calculation bug
549 WARN_ON((desc - host->adma_desc) > (128 * 2 + 1) * 4);
552 if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) {
554 * Mark the last descriptor as the terminating descriptor
556 if (desc != host->adma_desc) {
558 desc[0] |= 0x2; /* end */
562 * Add a terminating entry.
565 /* nop, end, valid */
566 sdhci_set_adma_desc(desc, 0, 0, 0x3);
570 * Resync align buffer as we might have changed it.
572 if (data->flags & MMC_DATA_WRITE) {
573 dma_sync_single_for_device(mmc_dev(host->mmc),
574 host->align_addr, 128 * 4, direction);
577 host->adma_addr = dma_map_single(mmc_dev(host->mmc),
578 host->adma_desc, (128 * 2 + 1) * 4, DMA_TO_DEVICE);
579 if (dma_mapping_error(mmc_dev(host->mmc), host->adma_addr))
581 BUG_ON(host->adma_addr & 0x3);
586 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
587 data->sg_len, direction);
589 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
595 static void sdhci_adma_table_post(struct sdhci_host *host,
596 struct mmc_data *data)
600 struct scatterlist *sg;
607 if (data->flags & MMC_DATA_READ)
608 direction = DMA_FROM_DEVICE;
610 direction = DMA_TO_DEVICE;
612 dma_unmap_single(mmc_dev(host->mmc), host->adma_addr,
613 (128 * 2 + 1) * 4, DMA_TO_DEVICE);
615 dma_unmap_single(mmc_dev(host->mmc), host->align_addr,
618 /* Do a quick scan of the SG list for any unaligned mappings */
619 has_unaligned = false;
620 for_each_sg(data->sg, sg, host->sg_count, i)
621 if (sg_dma_address(sg) & 3) {
622 has_unaligned = true;
626 if (has_unaligned && data->flags & MMC_DATA_READ) {
627 dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg,
628 data->sg_len, direction);
630 align = host->align_buffer;
632 for_each_sg(data->sg, sg, host->sg_count, i) {
633 if (sg_dma_address(sg) & 0x3) {
634 size = 4 - (sg_dma_address(sg) & 0x3);
636 buffer = sdhci_kmap_atomic(sg, &flags);
637 WARN_ON(((long)buffer & PAGE_MASK) > (PAGE_SIZE - 3));
638 memcpy(buffer, align, size);
639 sdhci_kunmap_atomic(buffer, &flags);
646 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
647 data->sg_len, direction);
650 static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
653 struct mmc_data *data = cmd->data;
654 unsigned target_timeout, current_timeout;
657 * If the host controller provides us with an incorrect timeout
658 * value, just skip the check and use 0xE. The hardware may take
659 * longer to time out, but that's much better than having a too-short
662 if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
665 /* Unspecified timeout, assume max */
666 if (!data && !cmd->busy_timeout)
671 target_timeout = cmd->busy_timeout * 1000;
673 target_timeout = data->timeout_ns / 1000;
675 target_timeout += data->timeout_clks / host->clock;
679 * Figure out needed cycles.
680 * We do this in steps in order to fit inside a 32 bit int.
681 * The first step is the minimum timeout, which will have a
682 * minimum resolution of 6 bits:
683 * (1) 2^13*1000 > 2^22,
684 * (2) host->timeout_clk < 2^16
689 current_timeout = (1 << 13) * 1000 / host->timeout_clk;
690 while (current_timeout < target_timeout) {
692 current_timeout <<= 1;
698 DBG("%s: Too large timeout 0x%x requested for CMD%d!\n",
699 mmc_hostname(host->mmc), count, cmd->opcode);
706 static void sdhci_set_transfer_irqs(struct sdhci_host *host)
708 u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL;
709 u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR;
711 if (host->flags & SDHCI_REQ_USE_DMA)
712 host->ier = (host->ier & ~pio_irqs) | dma_irqs;
714 host->ier = (host->ier & ~dma_irqs) | pio_irqs;
716 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
717 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
720 static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
724 struct mmc_data *data = cmd->data;
729 if (data || (cmd->flags & MMC_RSP_BUSY)) {
730 count = sdhci_calc_timeout(host, cmd);
731 sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
738 BUG_ON(data->blksz * data->blocks > 524288);
739 BUG_ON(data->blksz > host->mmc->max_blk_size);
740 BUG_ON(data->blocks > 65535);
743 host->data_early = 0;
744 host->data->bytes_xfered = 0;
746 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
747 host->flags |= SDHCI_REQ_USE_DMA;
750 * FIXME: This doesn't account for merging when mapping the
753 if (host->flags & SDHCI_REQ_USE_DMA) {
755 struct scatterlist *sg;
758 if (host->flags & SDHCI_USE_ADMA) {
759 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
762 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE)
766 if (unlikely(broken)) {
767 for_each_sg(data->sg, sg, data->sg_len, i) {
768 if (sg->length & 0x3) {
769 DBG("Reverting to PIO because of "
770 "transfer size (%d)\n",
772 host->flags &= ~SDHCI_REQ_USE_DMA;
780 * The assumption here being that alignment is the same after
781 * translation to device address space.
783 if (host->flags & SDHCI_REQ_USE_DMA) {
785 struct scatterlist *sg;
788 if (host->flags & SDHCI_USE_ADMA) {
790 * As we use 3 byte chunks to work around
791 * alignment problems, we need to check this
794 if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE)
797 if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR)
801 if (unlikely(broken)) {
802 for_each_sg(data->sg, sg, data->sg_len, i) {
803 if (sg->offset & 0x3) {
804 DBG("Reverting to PIO because of "
806 host->flags &= ~SDHCI_REQ_USE_DMA;
813 if (host->flags & SDHCI_REQ_USE_DMA) {
814 if (host->flags & SDHCI_USE_ADMA) {
815 ret = sdhci_adma_table_pre(host, data);
818 * This only happens when someone fed
819 * us an invalid request.
822 host->flags &= ~SDHCI_REQ_USE_DMA;
824 sdhci_writel(host, host->adma_addr,
830 sg_cnt = dma_map_sg(mmc_dev(host->mmc),
831 data->sg, data->sg_len,
832 (data->flags & MMC_DATA_READ) ?
837 * This only happens when someone fed
838 * us an invalid request.
841 host->flags &= ~SDHCI_REQ_USE_DMA;
843 WARN_ON(sg_cnt != 1);
844 sdhci_writel(host, sg_dma_address(data->sg),
851 * Always adjust the DMA selection as some controllers
852 * (e.g. JMicron) can't do PIO properly when the selection
855 if (host->version >= SDHCI_SPEC_200) {
856 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
857 ctrl &= ~SDHCI_CTRL_DMA_MASK;
858 if ((host->flags & SDHCI_REQ_USE_DMA) &&
859 (host->flags & SDHCI_USE_ADMA))
860 ctrl |= SDHCI_CTRL_ADMA32;
862 ctrl |= SDHCI_CTRL_SDMA;
863 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
866 if (!(host->flags & SDHCI_REQ_USE_DMA)) {
869 flags = SG_MITER_ATOMIC;
870 if (host->data->flags & MMC_DATA_READ)
871 flags |= SG_MITER_TO_SG;
873 flags |= SG_MITER_FROM_SG;
874 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
875 host->blocks = data->blocks;
878 sdhci_set_transfer_irqs(host);
880 /* Set the DMA boundary value and block size */
881 sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
882 data->blksz), SDHCI_BLOCK_SIZE);
883 sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
886 static void sdhci_set_transfer_mode(struct sdhci_host *host,
887 struct mmc_command *cmd)
890 struct mmc_data *data = cmd->data;
893 /* clear Auto CMD settings for no data CMDs */
894 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE);
895 sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 |
896 SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE);
900 WARN_ON(!host->data);
902 mode = SDHCI_TRNS_BLK_CNT_EN;
903 if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
904 mode |= SDHCI_TRNS_MULTI;
906 * If we are sending CMD23, CMD12 never gets sent
907 * on successful completion (so no Auto-CMD12).
909 if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
910 mode |= SDHCI_TRNS_AUTO_CMD12;
911 else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
912 mode |= SDHCI_TRNS_AUTO_CMD23;
913 sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
917 if (data->flags & MMC_DATA_READ)
918 mode |= SDHCI_TRNS_READ;
919 if (host->flags & SDHCI_REQ_USE_DMA)
920 mode |= SDHCI_TRNS_DMA;
922 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
925 static void sdhci_finish_data(struct sdhci_host *host)
927 struct mmc_data *data;
934 if (host->flags & SDHCI_REQ_USE_DMA) {
935 if (host->flags & SDHCI_USE_ADMA)
936 sdhci_adma_table_post(host, data);
938 dma_unmap_sg(mmc_dev(host->mmc), data->sg,
939 data->sg_len, (data->flags & MMC_DATA_READ) ?
940 DMA_FROM_DEVICE : DMA_TO_DEVICE);
945 * The specification states that the block count register must
946 * be updated, but it does not specify at what point in the
947 * data flow. That makes the register entirely useless to read
948 * back so we have to assume that nothing made it to the card
949 * in the event of an error.
952 data->bytes_xfered = 0;
954 data->bytes_xfered = data->blksz * data->blocks;
957 * Need to send CMD12 if -
958 * a) open-ended multiblock transfer (no CMD23)
959 * b) error in multiblock transfer
966 * The controller needs a reset of internal state machines
967 * upon error conditions.
970 sdhci_do_reset(host, SDHCI_RESET_CMD);
971 sdhci_do_reset(host, SDHCI_RESET_DATA);
974 sdhci_send_command(host, data->stop);
976 tasklet_schedule(&host->finish_tasklet);
979 void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
983 unsigned long timeout;
990 mask = SDHCI_CMD_INHIBIT;
991 if ((cmd->data != NULL) || (cmd->flags & MMC_RSP_BUSY))
992 mask |= SDHCI_DATA_INHIBIT;
994 /* We shouldn't wait for data inihibit for stop commands, even
995 though they might use busy signaling */
996 if (host->mrq->data && (cmd == host->mrq->data->stop))
997 mask &= ~SDHCI_DATA_INHIBIT;
999 while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
1001 pr_err("%s: Controller never released "
1002 "inhibit bit(s).\n", mmc_hostname(host->mmc));
1003 sdhci_dumpregs(host);
1005 tasklet_schedule(&host->finish_tasklet);
1013 if (!cmd->data && cmd->busy_timeout > 9000)
1014 timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ;
1017 mod_timer(&host->timer, timeout);
1021 sdhci_prepare_data(host, cmd);
1023 sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
1025 sdhci_set_transfer_mode(host, cmd);
1027 if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
1028 pr_err("%s: Unsupported response type!\n",
1029 mmc_hostname(host->mmc));
1030 cmd->error = -EINVAL;
1031 tasklet_schedule(&host->finish_tasklet);
1035 if (!(cmd->flags & MMC_RSP_PRESENT))
1036 flags = SDHCI_CMD_RESP_NONE;
1037 else if (cmd->flags & MMC_RSP_136)
1038 flags = SDHCI_CMD_RESP_LONG;
1039 else if (cmd->flags & MMC_RSP_BUSY)
1040 flags = SDHCI_CMD_RESP_SHORT_BUSY;
1042 flags = SDHCI_CMD_RESP_SHORT;
1044 if (cmd->flags & MMC_RSP_CRC)
1045 flags |= SDHCI_CMD_CRC;
1046 if (cmd->flags & MMC_RSP_OPCODE)
1047 flags |= SDHCI_CMD_INDEX;
1049 /* CMD19 is special in that the Data Present Select should be set */
1050 if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK ||
1051 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200)
1052 flags |= SDHCI_CMD_DATA;
1054 sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
1056 EXPORT_SYMBOL_GPL(sdhci_send_command);
1058 static void sdhci_finish_command(struct sdhci_host *host)
1062 BUG_ON(host->cmd == NULL);
1064 if (host->cmd->flags & MMC_RSP_PRESENT) {
1065 if (host->cmd->flags & MMC_RSP_136) {
1066 /* CRC is stripped so we need to do some shifting. */
1067 for (i = 0;i < 4;i++) {
1068 host->cmd->resp[i] = sdhci_readl(host,
1069 SDHCI_RESPONSE + (3-i)*4) << 8;
1071 host->cmd->resp[i] |=
1073 SDHCI_RESPONSE + (3-i)*4-1);
1076 host->cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE);
1080 host->cmd->error = 0;
1082 /* Finished CMD23, now send actual command. */
1083 if (host->cmd == host->mrq->sbc) {
1085 sdhci_send_command(host, host->mrq->cmd);
1088 /* Processed actual command. */
1089 if (host->data && host->data_early)
1090 sdhci_finish_data(host);
1092 if (!host->cmd->data)
1093 tasklet_schedule(&host->finish_tasklet);
1099 static u16 sdhci_get_preset_value(struct sdhci_host *host)
1101 u16 ctrl, preset = 0;
1103 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1105 switch (ctrl & SDHCI_CTRL_UHS_MASK) {
1106 case SDHCI_CTRL_UHS_SDR12:
1107 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1109 case SDHCI_CTRL_UHS_SDR25:
1110 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25);
1112 case SDHCI_CTRL_UHS_SDR50:
1113 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50);
1115 case SDHCI_CTRL_UHS_SDR104:
1116 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104);
1118 case SDHCI_CTRL_UHS_DDR50:
1119 preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50);
1122 pr_warn("%s: Invalid UHS-I mode selected\n",
1123 mmc_hostname(host->mmc));
1124 preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12);
1130 static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
1132 int div = 0; /* Initialized for compiler warning */
1133 int real_div = div, clk_mul = 1;
1135 unsigned long timeout;
1137 if (clock && clock == host->clock)
1140 host->mmc->actual_clock = 0;
1142 if (host->ops->set_clock) {
1143 host->ops->set_clock(host, clock);
1144 if (host->quirks & SDHCI_QUIRK_NONSTANDARD_CLOCK)
1148 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
1153 if (host->version >= SDHCI_SPEC_300) {
1154 if (sdhci_readw(host, SDHCI_HOST_CONTROL2) &
1155 SDHCI_CTRL_PRESET_VAL_ENABLE) {
1158 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1159 pre_val = sdhci_get_preset_value(host);
1160 div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK)
1161 >> SDHCI_PRESET_SDCLK_FREQ_SHIFT;
1162 if (host->clk_mul &&
1163 (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) {
1164 clk = SDHCI_PROG_CLOCK_MODE;
1166 clk_mul = host->clk_mul;
1168 real_div = max_t(int, 1, div << 1);
1174 * Check if the Host Controller supports Programmable Clock
1177 if (host->clk_mul) {
1178 for (div = 1; div <= 1024; div++) {
1179 if ((host->max_clk * host->clk_mul / div)
1184 * Set Programmable Clock Mode in the Clock
1187 clk = SDHCI_PROG_CLOCK_MODE;
1189 clk_mul = host->clk_mul;
1192 /* Version 3.00 divisors must be a multiple of 2. */
1193 if (host->max_clk <= clock)
1196 for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
1198 if ((host->max_clk / div) <= clock)
1206 /* Version 2.00 divisors must be a power of 2. */
1207 for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
1208 if ((host->max_clk / div) <= clock)
1217 host->mmc->actual_clock = (host->max_clk * clk_mul) / real_div;
1219 clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
1220 clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
1221 << SDHCI_DIVIDER_HI_SHIFT;
1222 clk |= SDHCI_CLOCK_INT_EN;
1223 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1225 /* Wait max 20 ms */
1227 while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
1228 & SDHCI_CLOCK_INT_STABLE)) {
1230 pr_err("%s: Internal clock never "
1231 "stabilised.\n", mmc_hostname(host->mmc));
1232 sdhci_dumpregs(host);
1239 clk |= SDHCI_CLOCK_CARD_EN;
1240 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1243 host->clock = clock;
1246 static inline void sdhci_update_clock(struct sdhci_host *host)
1250 clock = host->clock;
1252 sdhci_set_clock(host, clock);
1255 static int sdhci_set_power(struct sdhci_host *host, unsigned short power)
1259 if (power != (unsigned short)-1) {
1260 switch (1 << power) {
1261 case MMC_VDD_165_195:
1262 pwr = SDHCI_POWER_180;
1266 pwr = SDHCI_POWER_300;
1270 pwr = SDHCI_POWER_330;
1277 if (host->pwr == pwr)
1283 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1284 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1285 sdhci_runtime_pm_bus_off(host);
1290 * Spec says that we should clear the power reg before setting
1291 * a new value. Some controllers don't seem to like this though.
1293 if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE))
1294 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
1297 * At least the Marvell CaFe chip gets confused if we set the voltage
1298 * and set turn on power at the same time, so set the voltage first.
1300 if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER)
1301 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1303 pwr |= SDHCI_POWER_ON;
1305 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
1307 if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON)
1308 sdhci_runtime_pm_bus_on(host);
1311 * Some controllers need an extra 10ms delay of 10ms before they
1312 * can apply clock after applying power
1314 if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER)
1320 /*****************************************************************************\
1324 \*****************************************************************************/
1326 static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1328 struct sdhci_host *host;
1330 unsigned long flags;
1333 host = mmc_priv(mmc);
1335 sdhci_runtime_pm_get(host);
1337 spin_lock_irqsave(&host->lock, flags);
1339 WARN_ON(host->mrq != NULL);
1341 #ifndef SDHCI_USE_LEDS_CLASS
1342 sdhci_activate_led(host);
1346 * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
1347 * requests if Auto-CMD12 is enabled.
1349 if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
1351 mrq->data->stop = NULL;
1359 * Firstly check card presence from cd-gpio. The return could
1360 * be one of the following possibilities:
1361 * negative: cd-gpio is not available
1362 * zero: cd-gpio is used, and card is removed
1363 * one: cd-gpio is used, and card is present
1365 present = mmc_gpio_get_cd(host->mmc);
1367 /* If polling, assume that the card is always present. */
1368 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
1371 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
1375 if (!present || host->flags & SDHCI_DEVICE_DEAD) {
1376 host->mrq->cmd->error = -ENOMEDIUM;
1377 tasklet_schedule(&host->finish_tasklet);
1381 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1383 * Check if the re-tuning timer has already expired and there
1384 * is no on-going data transfer. If so, we need to execute
1385 * tuning procedure before sending command.
1387 if ((host->flags & SDHCI_NEEDS_RETUNING) &&
1388 !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
1390 /* eMMC uses cmd21 but sd and sdio use cmd19 */
1392 mmc->card->type == MMC_TYPE_MMC ?
1393 MMC_SEND_TUNING_BLOCK_HS200 :
1394 MMC_SEND_TUNING_BLOCK;
1396 /* Here we need to set the host->mrq to NULL,
1397 * in case the pending finish_tasklet
1398 * finishes it incorrectly.
1402 spin_unlock_irqrestore(&host->lock, flags);
1403 sdhci_execute_tuning(mmc, tuning_opcode);
1404 spin_lock_irqsave(&host->lock, flags);
1406 /* Restore original mmc_request structure */
1411 if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
1412 sdhci_send_command(host, mrq->sbc);
1414 sdhci_send_command(host, mrq->cmd);
1418 spin_unlock_irqrestore(&host->lock, flags);
1421 void sdhci_set_bus_width(struct sdhci_host *host, int width)
1425 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1426 if (width == MMC_BUS_WIDTH_8) {
1427 ctrl &= ~SDHCI_CTRL_4BITBUS;
1428 if (host->version >= SDHCI_SPEC_300)
1429 ctrl |= SDHCI_CTRL_8BITBUS;
1431 if (host->version >= SDHCI_SPEC_300)
1432 ctrl &= ~SDHCI_CTRL_8BITBUS;
1433 if (width == MMC_BUS_WIDTH_4)
1434 ctrl |= SDHCI_CTRL_4BITBUS;
1436 ctrl &= ~SDHCI_CTRL_4BITBUS;
1438 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1440 EXPORT_SYMBOL_GPL(sdhci_set_bus_width);
1442 static void sdhci_do_set_ios(struct sdhci_host *host, struct mmc_ios *ios)
1444 unsigned long flags;
1448 spin_lock_irqsave(&host->lock, flags);
1450 if (host->flags & SDHCI_DEVICE_DEAD) {
1451 spin_unlock_irqrestore(&host->lock, flags);
1452 if (host->vmmc && ios->power_mode == MMC_POWER_OFF)
1453 mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
1458 * Reset the chip on each power off.
1459 * Should clear out any weird states.
1461 if (ios->power_mode == MMC_POWER_OFF) {
1462 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
1466 if (host->version >= SDHCI_SPEC_300 &&
1467 (ios->power_mode == MMC_POWER_UP) &&
1468 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN))
1469 sdhci_enable_preset_value(host, false);
1471 sdhci_set_clock(host, ios->clock);
1473 if (ios->power_mode == MMC_POWER_OFF)
1474 vdd_bit = sdhci_set_power(host, -1);
1476 vdd_bit = sdhci_set_power(host, ios->vdd);
1478 if (host->vmmc && vdd_bit != -1) {
1479 spin_unlock_irqrestore(&host->lock, flags);
1480 mmc_regulator_set_ocr(host->mmc, host->vmmc, vdd_bit);
1481 spin_lock_irqsave(&host->lock, flags);
1484 if (host->ops->platform_send_init_74_clocks)
1485 host->ops->platform_send_init_74_clocks(host, ios->power_mode);
1487 host->ops->set_bus_width(host, ios->bus_width);
1489 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
1491 if ((ios->timing == MMC_TIMING_SD_HS ||
1492 ios->timing == MMC_TIMING_MMC_HS)
1493 && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT))
1494 ctrl |= SDHCI_CTRL_HISPD;
1496 ctrl &= ~SDHCI_CTRL_HISPD;
1498 if (host->version >= SDHCI_SPEC_300) {
1501 /* In case of UHS-I modes, set High Speed Enable */
1502 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1503 (ios->timing == MMC_TIMING_MMC_DDR52) ||
1504 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1505 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1506 (ios->timing == MMC_TIMING_UHS_DDR50) ||
1507 (ios->timing == MMC_TIMING_UHS_SDR25))
1508 ctrl |= SDHCI_CTRL_HISPD;
1510 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1511 if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
1512 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1514 * We only need to set Driver Strength if the
1515 * preset value enable is not set.
1517 ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
1518 if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
1519 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
1520 else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
1521 ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
1523 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1526 * According to SDHC Spec v3.00, if the Preset Value
1527 * Enable in the Host Control 2 register is set, we
1528 * need to reset SD Clock Enable before changing High
1529 * Speed Enable to avoid generating clock gliches.
1532 /* Reset SD Clock Enable */
1533 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1534 clk &= ~SDHCI_CLOCK_CARD_EN;
1535 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1537 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1539 /* Re-enable SD Clock */
1540 sdhci_update_clock(host);
1544 /* Reset SD Clock Enable */
1545 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1546 clk &= ~SDHCI_CLOCK_CARD_EN;
1547 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
1549 if (host->ops->set_uhs_signaling)
1550 host->ops->set_uhs_signaling(host, ios->timing);
1552 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1553 /* Select Bus Speed Mode for host */
1554 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1555 if ((ios->timing == MMC_TIMING_MMC_HS200) ||
1556 (ios->timing == MMC_TIMING_UHS_SDR104))
1557 ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1558 else if (ios->timing == MMC_TIMING_UHS_SDR12)
1559 ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1560 else if (ios->timing == MMC_TIMING_UHS_SDR25)
1561 ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1562 else if (ios->timing == MMC_TIMING_UHS_SDR50)
1563 ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1564 else if ((ios->timing == MMC_TIMING_UHS_DDR50) ||
1565 (ios->timing == MMC_TIMING_MMC_DDR52))
1566 ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1567 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1570 if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) &&
1571 ((ios->timing == MMC_TIMING_UHS_SDR12) ||
1572 (ios->timing == MMC_TIMING_UHS_SDR25) ||
1573 (ios->timing == MMC_TIMING_UHS_SDR50) ||
1574 (ios->timing == MMC_TIMING_UHS_SDR104) ||
1575 (ios->timing == MMC_TIMING_UHS_DDR50))) {
1578 sdhci_enable_preset_value(host, true);
1579 preset = sdhci_get_preset_value(host);
1580 ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK)
1581 >> SDHCI_PRESET_DRV_SHIFT;
1584 /* Re-enable SD Clock */
1585 sdhci_update_clock(host);
1587 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
1590 * Some (ENE) controllers go apeshit on some ios operation,
1591 * signalling timeout and CRC errors even on CMD0. Resetting
1592 * it on each ios seems to solve the problem.
1594 if(host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS)
1595 sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
1598 spin_unlock_irqrestore(&host->lock, flags);
1601 static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1603 struct sdhci_host *host = mmc_priv(mmc);
1605 sdhci_runtime_pm_get(host);
1606 sdhci_do_set_ios(host, ios);
1607 sdhci_runtime_pm_put(host);
1610 static int sdhci_do_get_cd(struct sdhci_host *host)
1612 int gpio_cd = mmc_gpio_get_cd(host->mmc);
1614 if (host->flags & SDHCI_DEVICE_DEAD)
1617 /* If polling/nonremovable, assume that the card is always present. */
1618 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) ||
1619 (host->mmc->caps & MMC_CAP_NONREMOVABLE))
1622 /* Try slot gpio detect */
1623 if (!IS_ERR_VALUE(gpio_cd))
1626 /* Host native card detect */
1627 return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT);
1630 static int sdhci_get_cd(struct mmc_host *mmc)
1632 struct sdhci_host *host = mmc_priv(mmc);
1635 sdhci_runtime_pm_get(host);
1636 ret = sdhci_do_get_cd(host);
1637 sdhci_runtime_pm_put(host);
1641 static int sdhci_check_ro(struct sdhci_host *host)
1643 unsigned long flags;
1646 spin_lock_irqsave(&host->lock, flags);
1648 if (host->flags & SDHCI_DEVICE_DEAD)
1650 else if (host->ops->get_ro)
1651 is_readonly = host->ops->get_ro(host);
1653 is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE)
1654 & SDHCI_WRITE_PROTECT);
1656 spin_unlock_irqrestore(&host->lock, flags);
1658 /* This quirk needs to be replaced by a callback-function later */
1659 return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ?
1660 !is_readonly : is_readonly;
1663 #define SAMPLE_COUNT 5
1665 static int sdhci_do_get_ro(struct sdhci_host *host)
1669 if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
1670 return sdhci_check_ro(host);
1673 for (i = 0; i < SAMPLE_COUNT; i++) {
1674 if (sdhci_check_ro(host)) {
1675 if (++ro_count > SAMPLE_COUNT / 2)
1683 static void sdhci_hw_reset(struct mmc_host *mmc)
1685 struct sdhci_host *host = mmc_priv(mmc);
1687 if (host->ops && host->ops->hw_reset)
1688 host->ops->hw_reset(host);
1691 static int sdhci_get_ro(struct mmc_host *mmc)
1693 struct sdhci_host *host = mmc_priv(mmc);
1696 sdhci_runtime_pm_get(host);
1697 ret = sdhci_do_get_ro(host);
1698 sdhci_runtime_pm_put(host);
1702 static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable)
1704 if (!(host->flags & SDHCI_DEVICE_DEAD)) {
1706 host->ier |= SDHCI_INT_CARD_INT;
1708 host->ier &= ~SDHCI_INT_CARD_INT;
1710 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
1711 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
1716 static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1718 struct sdhci_host *host = mmc_priv(mmc);
1719 unsigned long flags;
1721 sdhci_runtime_pm_get(host);
1723 spin_lock_irqsave(&host->lock, flags);
1725 host->flags |= SDHCI_SDIO_IRQ_ENABLED;
1727 host->flags &= ~SDHCI_SDIO_IRQ_ENABLED;
1729 sdhci_enable_sdio_irq_nolock(host, enable);
1730 spin_unlock_irqrestore(&host->lock, flags);
1732 sdhci_runtime_pm_put(host);
1735 static int sdhci_do_start_signal_voltage_switch(struct sdhci_host *host,
1736 struct mmc_ios *ios)
1742 * Signal Voltage Switching is only applicable for Host Controllers
1745 if (host->version < SDHCI_SPEC_300)
1748 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1750 switch (ios->signal_voltage) {
1751 case MMC_SIGNAL_VOLTAGE_330:
1752 /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
1753 ctrl &= ~SDHCI_CTRL_VDD_180;
1754 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1757 ret = regulator_set_voltage(host->vqmmc, 2700000, 3600000);
1759 pr_warning("%s: Switching to 3.3V signalling voltage "
1760 " failed\n", mmc_hostname(host->mmc));
1765 usleep_range(5000, 5500);
1767 /* 3.3V regulator output should be stable within 5 ms */
1768 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1769 if (!(ctrl & SDHCI_CTRL_VDD_180))
1772 pr_warning("%s: 3.3V regulator output did not became stable\n",
1773 mmc_hostname(host->mmc));
1776 case MMC_SIGNAL_VOLTAGE_180:
1778 ret = regulator_set_voltage(host->vqmmc,
1781 pr_warning("%s: Switching to 1.8V signalling voltage "
1782 " failed\n", mmc_hostname(host->mmc));
1788 * Enable 1.8V Signal Enable in the Host Control2
1791 ctrl |= SDHCI_CTRL_VDD_180;
1792 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1795 usleep_range(5000, 5500);
1797 /* 1.8V regulator output should be stable within 5 ms */
1798 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1799 if (ctrl & SDHCI_CTRL_VDD_180)
1802 pr_warning("%s: 1.8V regulator output did not became stable\n",
1803 mmc_hostname(host->mmc));
1806 case MMC_SIGNAL_VOLTAGE_120:
1808 ret = regulator_set_voltage(host->vqmmc, 1100000, 1300000);
1810 pr_warning("%s: Switching to 1.2V signalling voltage "
1811 " failed\n", mmc_hostname(host->mmc));
1817 /* No signal voltage switch required */
1822 static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
1823 struct mmc_ios *ios)
1825 struct sdhci_host *host = mmc_priv(mmc);
1828 if (host->version < SDHCI_SPEC_300)
1830 sdhci_runtime_pm_get(host);
1831 err = sdhci_do_start_signal_voltage_switch(host, ios);
1832 sdhci_runtime_pm_put(host);
1836 static int sdhci_card_busy(struct mmc_host *mmc)
1838 struct sdhci_host *host = mmc_priv(mmc);
1841 sdhci_runtime_pm_get(host);
1842 /* Check whether DAT[3:0] is 0000 */
1843 present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
1844 sdhci_runtime_pm_put(host);
1846 return !(present_state & SDHCI_DATA_LVL_MASK);
1849 static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode)
1851 struct sdhci_host *host;
1853 int tuning_loop_counter = MAX_TUNING_LOOP;
1854 unsigned long timeout;
1856 bool requires_tuning_nonuhs = false;
1857 unsigned long flags;
1859 host = mmc_priv(mmc);
1861 sdhci_runtime_pm_get(host);
1862 spin_lock_irqsave(&host->lock, flags);
1864 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1867 * The Host Controller needs tuning only in case of SDR104 mode
1868 * and for SDR50 mode when Use Tuning for SDR50 is set in the
1869 * Capabilities register.
1870 * If the Host Controller supports the HS200 mode then the
1871 * tuning function has to be executed.
1873 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
1874 (host->flags & SDHCI_SDR50_NEEDS_TUNING ||
1875 host->flags & SDHCI_SDR104_NEEDS_TUNING))
1876 requires_tuning_nonuhs = true;
1878 if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
1879 requires_tuning_nonuhs)
1880 ctrl |= SDHCI_CTRL_EXEC_TUNING;
1882 spin_unlock_irqrestore(&host->lock, flags);
1883 sdhci_runtime_pm_put(host);
1887 if (host->ops->platform_execute_tuning) {
1888 spin_unlock_irqrestore(&host->lock, flags);
1889 err = host->ops->platform_execute_tuning(host, opcode);
1890 sdhci_runtime_pm_put(host);
1894 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1897 * As per the Host Controller spec v3.00, tuning command
1898 * generates Buffer Read Ready interrupt, so enable that.
1900 * Note: The spec clearly says that when tuning sequence
1901 * is being performed, the controller does not generate
1902 * interrupts other than Buffer Read Ready interrupt. But
1903 * to make sure we don't hit a controller bug, we _only_
1904 * enable Buffer Read Ready interrupt here.
1906 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
1907 sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
1910 * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
1911 * of loops reaches 40 times or a timeout of 150ms occurs.
1915 struct mmc_command cmd = {0};
1916 struct mmc_request mrq = {NULL};
1918 if (!tuning_loop_counter && !timeout)
1921 cmd.opcode = opcode;
1923 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
1932 * In response to CMD19, the card sends 64 bytes of tuning
1933 * block to the Host Controller. So we set the block size
1936 if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) {
1937 if (mmc->ios.bus_width == MMC_BUS_WIDTH_8)
1938 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128),
1940 else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4)
1941 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1944 sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64),
1949 * The tuning block is sent by the card to the host controller.
1950 * So we set the TRNS_READ bit in the Transfer Mode register.
1951 * This also takes care of setting DMA Enable and Multi Block
1952 * Select in the same register to 0.
1954 sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
1956 sdhci_send_command(host, &cmd);
1961 spin_unlock_irqrestore(&host->lock, flags);
1962 /* Wait for Buffer Read Ready interrupt */
1963 wait_event_interruptible_timeout(host->buf_ready_int,
1964 (host->tuning_done == 1),
1965 msecs_to_jiffies(50));
1966 spin_lock_irqsave(&host->lock, flags);
1968 if (!host->tuning_done) {
1969 pr_info(DRIVER_NAME ": Timeout waiting for "
1970 "Buffer Read Ready interrupt during tuning "
1971 "procedure, falling back to fixed sampling "
1973 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1974 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1975 ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
1976 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
1982 host->tuning_done = 0;
1984 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1985 tuning_loop_counter--;
1988 /* eMMC spec does not require a delay between tuning cycles */
1989 if (opcode == MMC_SEND_TUNING_BLOCK)
1991 } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
1994 * The Host Driver has exhausted the maximum number of loops allowed,
1995 * so use fixed sampling frequency.
1997 if (!tuning_loop_counter || !timeout) {
1998 ctrl &= ~SDHCI_CTRL_TUNED_CLK;
1999 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2002 if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
2003 pr_info(DRIVER_NAME ": Tuning procedure"
2004 " failed, falling back to fixed sampling"
2012 * If this is the very first time we are here, we start the retuning
2013 * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
2014 * flag won't be set, we check this condition before actually starting
2017 if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
2018 (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
2019 host->flags |= SDHCI_USING_RETUNING_TIMER;
2020 mod_timer(&host->tuning_timer, jiffies +
2021 host->tuning_count * HZ);
2022 /* Tuning mode 1 limits the maximum data length to 4MB */
2023 mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
2024 } else if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2025 host->flags &= ~SDHCI_NEEDS_RETUNING;
2026 /* Reload the new initial value for timer */
2027 mod_timer(&host->tuning_timer, jiffies +
2028 host->tuning_count * HZ);
2032 * In case tuning fails, host controllers which support re-tuning can
2033 * try tuning again at a later time, when the re-tuning timer expires.
2034 * So for these controllers, we return 0. Since there might be other
2035 * controllers who do not have this capability, we return error for
2036 * them. SDHCI_USING_RETUNING_TIMER means the host is currently using
2037 * a retuning timer to do the retuning for the card.
2039 if (err && (host->flags & SDHCI_USING_RETUNING_TIMER))
2042 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2043 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2044 spin_unlock_irqrestore(&host->lock, flags);
2045 sdhci_runtime_pm_put(host);
2051 static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable)
2055 /* Host Controller v3.00 defines preset value registers */
2056 if (host->version < SDHCI_SPEC_300)
2059 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
2062 * We only enable or disable Preset Value if they are not already
2063 * enabled or disabled respectively. Otherwise, we bail out.
2065 if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2066 ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
2067 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2068 host->flags |= SDHCI_PV_ENABLED;
2069 } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
2070 ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
2071 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
2072 host->flags &= ~SDHCI_PV_ENABLED;
2076 static void sdhci_card_event(struct mmc_host *mmc)
2078 struct sdhci_host *host = mmc_priv(mmc);
2079 unsigned long flags;
2081 /* First check if client has provided their own card event */
2082 if (host->ops->card_event)
2083 host->ops->card_event(host);
2085 spin_lock_irqsave(&host->lock, flags);
2087 /* Check host->mrq first in case we are runtime suspended */
2088 if (host->mrq && !sdhci_do_get_cd(host)) {
2089 pr_err("%s: Card removed during transfer!\n",
2090 mmc_hostname(host->mmc));
2091 pr_err("%s: Resetting controller.\n",
2092 mmc_hostname(host->mmc));
2094 sdhci_do_reset(host, SDHCI_RESET_CMD);
2095 sdhci_do_reset(host, SDHCI_RESET_DATA);
2097 host->mrq->cmd->error = -ENOMEDIUM;
2098 tasklet_schedule(&host->finish_tasklet);
2101 spin_unlock_irqrestore(&host->lock, flags);
2104 static const struct mmc_host_ops sdhci_ops = {
2105 .request = sdhci_request,
2106 .set_ios = sdhci_set_ios,
2107 .get_cd = sdhci_get_cd,
2108 .get_ro = sdhci_get_ro,
2109 .hw_reset = sdhci_hw_reset,
2110 .enable_sdio_irq = sdhci_enable_sdio_irq,
2111 .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
2112 .execute_tuning = sdhci_execute_tuning,
2113 .card_event = sdhci_card_event,
2114 .card_busy = sdhci_card_busy,
2117 /*****************************************************************************\
2121 \*****************************************************************************/
2123 static void sdhci_tasklet_finish(unsigned long param)
2125 struct sdhci_host *host;
2126 unsigned long flags;
2127 struct mmc_request *mrq;
2129 host = (struct sdhci_host*)param;
2131 spin_lock_irqsave(&host->lock, flags);
2134 * If this tasklet gets rescheduled while running, it will
2135 * be run again afterwards but without any active request.
2138 spin_unlock_irqrestore(&host->lock, flags);
2142 del_timer(&host->timer);
2147 * The controller needs a reset of internal state machines
2148 * upon error conditions.
2150 if (!(host->flags & SDHCI_DEVICE_DEAD) &&
2151 ((mrq->cmd && mrq->cmd->error) ||
2152 (mrq->data && (mrq->data->error ||
2153 (mrq->data->stop && mrq->data->stop->error))) ||
2154 (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))) {
2156 /* Some controllers need this kick or reset won't work here */
2157 if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET)
2158 /* This is to force an update */
2159 sdhci_update_clock(host);
2161 /* Spec says we should do both at the same time, but Ricoh
2162 controllers do not like that. */
2163 sdhci_do_reset(host, SDHCI_RESET_CMD);
2164 sdhci_do_reset(host, SDHCI_RESET_DATA);
2171 #ifndef SDHCI_USE_LEDS_CLASS
2172 sdhci_deactivate_led(host);
2176 spin_unlock_irqrestore(&host->lock, flags);
2178 mmc_request_done(host->mmc, mrq);
2179 sdhci_runtime_pm_put(host);
2182 static void sdhci_timeout_timer(unsigned long data)
2184 struct sdhci_host *host;
2185 unsigned long flags;
2187 host = (struct sdhci_host*)data;
2189 spin_lock_irqsave(&host->lock, flags);
2192 pr_err("%s: Timeout waiting for hardware "
2193 "interrupt.\n", mmc_hostname(host->mmc));
2194 sdhci_dumpregs(host);
2197 host->data->error = -ETIMEDOUT;
2198 sdhci_finish_data(host);
2201 host->cmd->error = -ETIMEDOUT;
2203 host->mrq->cmd->error = -ETIMEDOUT;
2205 tasklet_schedule(&host->finish_tasklet);
2210 spin_unlock_irqrestore(&host->lock, flags);
2213 static void sdhci_tuning_timer(unsigned long data)
2215 struct sdhci_host *host;
2216 unsigned long flags;
2218 host = (struct sdhci_host *)data;
2220 spin_lock_irqsave(&host->lock, flags);
2222 host->flags |= SDHCI_NEEDS_RETUNING;
2224 spin_unlock_irqrestore(&host->lock, flags);
2227 /*****************************************************************************\
2229 * Interrupt handling *
2231 \*****************************************************************************/
2233 static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask)
2235 BUG_ON(intmask == 0);
2238 pr_err("%s: Got command interrupt 0x%08x even "
2239 "though no command operation was in progress.\n",
2240 mmc_hostname(host->mmc), (unsigned)intmask);
2241 sdhci_dumpregs(host);
2245 if (intmask & SDHCI_INT_TIMEOUT)
2246 host->cmd->error = -ETIMEDOUT;
2247 else if (intmask & (SDHCI_INT_CRC | SDHCI_INT_END_BIT |
2249 host->cmd->error = -EILSEQ;
2251 if (host->cmd->error) {
2252 tasklet_schedule(&host->finish_tasklet);
2257 * The host can send and interrupt when the busy state has
2258 * ended, allowing us to wait without wasting CPU cycles.
2259 * Unfortunately this is overloaded on the "data complete"
2260 * interrupt, so we need to take some care when handling
2263 * Note: The 1.0 specification is a bit ambiguous about this
2264 * feature so there might be some problems with older
2267 if (host->cmd->flags & MMC_RSP_BUSY) {
2268 if (host->cmd->data)
2269 DBG("Cannot wait for busy signal when also "
2270 "doing a data transfer");
2271 else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ))
2274 /* The controller does not support the end-of-busy IRQ,
2275 * fall through and take the SDHCI_INT_RESPONSE */
2278 if (intmask & SDHCI_INT_RESPONSE)
2279 sdhci_finish_command(host);
2282 #ifdef CONFIG_MMC_DEBUG
2283 static void sdhci_show_adma_error(struct sdhci_host *host)
2285 const char *name = mmc_hostname(host->mmc);
2286 u8 *desc = host->adma_desc;
2291 sdhci_dumpregs(host);
2294 dma = (__le32 *)(desc + 4);
2295 len = (__le16 *)(desc + 2);
2298 DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n",
2299 name, desc, le32_to_cpu(*dma), le16_to_cpu(*len), attr);
2308 static void sdhci_show_adma_error(struct sdhci_host *host) { }
2311 static void sdhci_data_irq(struct sdhci_host *host, u32 intmask)
2314 BUG_ON(intmask == 0);
2316 /* CMD19 generates _only_ Buffer Read Ready interrupt */
2317 if (intmask & SDHCI_INT_DATA_AVAIL) {
2318 command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND));
2319 if (command == MMC_SEND_TUNING_BLOCK ||
2320 command == MMC_SEND_TUNING_BLOCK_HS200) {
2321 host->tuning_done = 1;
2322 wake_up(&host->buf_ready_int);
2329 * The "data complete" interrupt is also used to
2330 * indicate that a busy state has ended. See comment
2331 * above in sdhci_cmd_irq().
2333 if (host->cmd && (host->cmd->flags & MMC_RSP_BUSY)) {
2334 if (intmask & SDHCI_INT_DATA_END) {
2335 sdhci_finish_command(host);
2340 pr_err("%s: Got data interrupt 0x%08x even "
2341 "though no data operation was in progress.\n",
2342 mmc_hostname(host->mmc), (unsigned)intmask);
2343 sdhci_dumpregs(host);
2348 if (intmask & SDHCI_INT_DATA_TIMEOUT)
2349 host->data->error = -ETIMEDOUT;
2350 else if (intmask & SDHCI_INT_DATA_END_BIT)
2351 host->data->error = -EILSEQ;
2352 else if ((intmask & SDHCI_INT_DATA_CRC) &&
2353 SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND))
2355 host->data->error = -EILSEQ;
2356 else if (intmask & SDHCI_INT_ADMA_ERROR) {
2357 pr_err("%s: ADMA error\n", mmc_hostname(host->mmc));
2358 sdhci_show_adma_error(host);
2359 host->data->error = -EIO;
2360 if (host->ops->adma_workaround)
2361 host->ops->adma_workaround(host, intmask);
2364 if (host->data->error)
2365 sdhci_finish_data(host);
2367 if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL))
2368 sdhci_transfer_pio(host);
2371 * We currently don't do anything fancy with DMA
2372 * boundaries, but as we can't disable the feature
2373 * we need to at least restart the transfer.
2375 * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
2376 * should return a valid address to continue from, but as
2377 * some controllers are faulty, don't trust them.
2379 if (intmask & SDHCI_INT_DMA_END) {
2380 u32 dmastart, dmanow;
2381 dmastart = sg_dma_address(host->data->sg);
2382 dmanow = dmastart + host->data->bytes_xfered;
2384 * Force update to the next DMA block boundary.
2387 ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
2388 SDHCI_DEFAULT_BOUNDARY_SIZE;
2389 host->data->bytes_xfered = dmanow - dmastart;
2390 DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
2392 mmc_hostname(host->mmc), dmastart,
2393 host->data->bytes_xfered, dmanow);
2394 sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
2397 if (intmask & SDHCI_INT_DATA_END) {
2400 * Data managed to finish before the
2401 * command completed. Make sure we do
2402 * things in the proper order.
2404 host->data_early = 1;
2406 sdhci_finish_data(host);
2412 static irqreturn_t sdhci_irq(int irq, void *dev_id)
2414 irqreturn_t result = IRQ_NONE;
2415 struct sdhci_host *host = dev_id;
2416 u32 intmask, mask, unexpected = 0;
2419 spin_lock(&host->lock);
2421 if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) {
2422 spin_unlock(&host->lock);
2426 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2427 if (!intmask || intmask == 0xffffffff) {
2433 /* Clear selected interrupts. */
2434 mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2435 SDHCI_INT_BUS_POWER);
2436 sdhci_writel(host, mask, SDHCI_INT_STATUS);
2438 DBG("*** %s got interrupt: 0x%08x\n",
2439 mmc_hostname(host->mmc), intmask);
2441 if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2442 u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) &
2446 * There is a observation on i.mx esdhc. INSERT
2447 * bit will be immediately set again when it gets
2448 * cleared, if a card is inserted. We have to mask
2449 * the irq to prevent interrupt storm which will
2450 * freeze the system. And the REMOVE gets the
2453 * More testing are needed here to ensure it works
2454 * for other platforms though.
2456 host->ier &= ~(SDHCI_INT_CARD_INSERT |
2457 SDHCI_INT_CARD_REMOVE);
2458 host->ier |= present ? SDHCI_INT_CARD_REMOVE :
2459 SDHCI_INT_CARD_INSERT;
2460 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2461 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2463 sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT |
2464 SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS);
2466 host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT |
2467 SDHCI_INT_CARD_REMOVE);
2468 result = IRQ_WAKE_THREAD;
2471 if (intmask & SDHCI_INT_CMD_MASK)
2472 sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
2474 if (intmask & SDHCI_INT_DATA_MASK)
2475 sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
2477 if (intmask & SDHCI_INT_BUS_POWER)
2478 pr_err("%s: Card is consuming too much power!\n",
2479 mmc_hostname(host->mmc));
2481 if (intmask & SDHCI_INT_CARD_INT) {
2482 sdhci_enable_sdio_irq_nolock(host, false);
2483 host->thread_isr |= SDHCI_INT_CARD_INT;
2484 result = IRQ_WAKE_THREAD;
2487 intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE |
2488 SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK |
2489 SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER |
2490 SDHCI_INT_CARD_INT);
2493 unexpected |= intmask;
2494 sdhci_writel(host, intmask, SDHCI_INT_STATUS);
2497 if (result == IRQ_NONE)
2498 result = IRQ_HANDLED;
2500 intmask = sdhci_readl(host, SDHCI_INT_STATUS);
2501 } while (intmask && --max_loops);
2503 spin_unlock(&host->lock);
2506 pr_err("%s: Unexpected interrupt 0x%08x.\n",
2507 mmc_hostname(host->mmc), unexpected);
2508 sdhci_dumpregs(host);
2514 static irqreturn_t sdhci_thread_irq(int irq, void *dev_id)
2516 struct sdhci_host *host = dev_id;
2517 unsigned long flags;
2520 spin_lock_irqsave(&host->lock, flags);
2521 isr = host->thread_isr;
2522 host->thread_isr = 0;
2523 spin_unlock_irqrestore(&host->lock, flags);
2525 if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) {
2526 sdhci_card_event(host->mmc);
2527 mmc_detect_change(host->mmc, msecs_to_jiffies(200));
2530 if (isr & SDHCI_INT_CARD_INT) {
2531 sdio_run_irqs(host->mmc);
2533 spin_lock_irqsave(&host->lock, flags);
2534 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2535 sdhci_enable_sdio_irq_nolock(host, true);
2536 spin_unlock_irqrestore(&host->lock, flags);
2539 return isr ? IRQ_HANDLED : IRQ_NONE;
2542 /*****************************************************************************\
2546 \*****************************************************************************/
2549 void sdhci_enable_irq_wakeups(struct sdhci_host *host)
2552 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2553 | SDHCI_WAKE_ON_INT;
2555 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2557 /* Avoid fake wake up */
2558 if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION)
2559 val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE);
2560 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2562 EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups);
2564 void sdhci_disable_irq_wakeups(struct sdhci_host *host)
2567 u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE
2568 | SDHCI_WAKE_ON_INT;
2570 val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL);
2572 sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL);
2574 EXPORT_SYMBOL_GPL(sdhci_disable_irq_wakeups);
2576 int sdhci_suspend_host(struct sdhci_host *host)
2578 if (host->ops->platform_suspend)
2579 host->ops->platform_suspend(host);
2581 sdhci_disable_card_detection(host);
2583 /* Disable tuning since we are suspending */
2584 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2585 del_timer_sync(&host->tuning_timer);
2586 host->flags &= ~SDHCI_NEEDS_RETUNING;
2589 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2591 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
2592 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
2593 free_irq(host->irq, host);
2595 sdhci_enable_irq_wakeups(host);
2596 enable_irq_wake(host->irq);
2601 EXPORT_SYMBOL_GPL(sdhci_suspend_host);
2603 int sdhci_resume_host(struct sdhci_host *host)
2607 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2608 if (host->ops->enable_dma)
2609 host->ops->enable_dma(host);
2612 if (!device_may_wakeup(mmc_dev(host->mmc))) {
2613 ret = request_threaded_irq(host->irq, sdhci_irq,
2614 sdhci_thread_irq, IRQF_SHARED,
2615 mmc_hostname(host->mmc), host);
2619 sdhci_disable_irq_wakeups(host);
2620 disable_irq_wake(host->irq);
2623 if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) &&
2624 (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) {
2625 /* Card keeps power but host controller does not */
2626 sdhci_init(host, 0);
2629 sdhci_do_set_ios(host, &host->mmc->ios);
2631 sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER));
2635 sdhci_enable_card_detection(host);
2637 if (host->ops->platform_resume)
2638 host->ops->platform_resume(host);
2640 /* Set the re-tuning expiration flag */
2641 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2642 host->flags |= SDHCI_NEEDS_RETUNING;
2647 EXPORT_SYMBOL_GPL(sdhci_resume_host);
2648 #endif /* CONFIG_PM */
2650 #ifdef CONFIG_PM_RUNTIME
2652 static int sdhci_runtime_pm_get(struct sdhci_host *host)
2654 return pm_runtime_get_sync(host->mmc->parent);
2657 static int sdhci_runtime_pm_put(struct sdhci_host *host)
2659 pm_runtime_mark_last_busy(host->mmc->parent);
2660 return pm_runtime_put_autosuspend(host->mmc->parent);
2663 static void sdhci_runtime_pm_bus_on(struct sdhci_host *host)
2665 if (host->runtime_suspended || host->bus_on)
2667 host->bus_on = true;
2668 pm_runtime_get_noresume(host->mmc->parent);
2671 static void sdhci_runtime_pm_bus_off(struct sdhci_host *host)
2673 if (host->runtime_suspended || !host->bus_on)
2675 host->bus_on = false;
2676 pm_runtime_put_noidle(host->mmc->parent);
2679 int sdhci_runtime_suspend_host(struct sdhci_host *host)
2681 unsigned long flags;
2684 /* Disable tuning since we are suspending */
2685 if (host->flags & SDHCI_USING_RETUNING_TIMER) {
2686 del_timer_sync(&host->tuning_timer);
2687 host->flags &= ~SDHCI_NEEDS_RETUNING;
2690 spin_lock_irqsave(&host->lock, flags);
2691 host->ier &= SDHCI_INT_CARD_INT;
2692 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
2693 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
2694 spin_unlock_irqrestore(&host->lock, flags);
2696 synchronize_hardirq(host->irq);
2698 spin_lock_irqsave(&host->lock, flags);
2699 host->runtime_suspended = true;
2700 spin_unlock_irqrestore(&host->lock, flags);
2704 EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host);
2706 int sdhci_runtime_resume_host(struct sdhci_host *host)
2708 unsigned long flags;
2709 int ret = 0, host_flags = host->flags;
2711 if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2712 if (host->ops->enable_dma)
2713 host->ops->enable_dma(host);
2716 sdhci_init(host, 0);
2718 /* Force clock and power re-program */
2721 sdhci_do_set_ios(host, &host->mmc->ios);
2723 sdhci_do_start_signal_voltage_switch(host, &host->mmc->ios);
2724 if ((host_flags & SDHCI_PV_ENABLED) &&
2725 !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) {
2726 spin_lock_irqsave(&host->lock, flags);
2727 sdhci_enable_preset_value(host, true);
2728 spin_unlock_irqrestore(&host->lock, flags);
2731 /* Set the re-tuning expiration flag */
2732 if (host->flags & SDHCI_USING_RETUNING_TIMER)
2733 host->flags |= SDHCI_NEEDS_RETUNING;
2735 spin_lock_irqsave(&host->lock, flags);
2737 host->runtime_suspended = false;
2739 /* Enable SDIO IRQ */
2740 if (host->flags & SDHCI_SDIO_IRQ_ENABLED)
2741 sdhci_enable_sdio_irq_nolock(host, true);
2743 /* Enable Card Detection */
2744 sdhci_enable_card_detection(host);
2746 spin_unlock_irqrestore(&host->lock, flags);
2750 EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host);
2754 /*****************************************************************************\
2756 * Device allocation/registration *
2758 \*****************************************************************************/
2760 struct sdhci_host *sdhci_alloc_host(struct device *dev,
2763 struct mmc_host *mmc;
2764 struct sdhci_host *host;
2766 WARN_ON(dev == NULL);
2768 mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev);
2770 return ERR_PTR(-ENOMEM);
2772 host = mmc_priv(mmc);
2778 EXPORT_SYMBOL_GPL(sdhci_alloc_host);
2780 int sdhci_add_host(struct sdhci_host *host)
2782 struct mmc_host *mmc;
2783 u32 caps[2] = {0, 0};
2784 u32 max_current_caps;
2785 unsigned int ocr_avail;
2788 WARN_ON(host == NULL);
2795 host->quirks = debug_quirks;
2797 host->quirks2 = debug_quirks2;
2799 sdhci_do_reset(host, SDHCI_RESET_ALL);
2801 host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
2802 host->version = (host->version & SDHCI_SPEC_VER_MASK)
2803 >> SDHCI_SPEC_VER_SHIFT;
2804 if (host->version > SDHCI_SPEC_300) {
2805 pr_err("%s: Unknown controller version (%d). "
2806 "You may experience problems.\n", mmc_hostname(mmc),
2810 caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
2811 sdhci_readl(host, SDHCI_CAPABILITIES);
2813 if (host->version >= SDHCI_SPEC_300)
2814 caps[1] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ?
2816 sdhci_readl(host, SDHCI_CAPABILITIES_1);
2818 if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
2819 host->flags |= SDHCI_USE_SDMA;
2820 else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
2821 DBG("Controller doesn't have SDMA capability\n");
2823 host->flags |= SDHCI_USE_SDMA;
2825 if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) &&
2826 (host->flags & SDHCI_USE_SDMA)) {
2827 DBG("Disabling DMA as it is marked broken\n");
2828 host->flags &= ~SDHCI_USE_SDMA;
2831 if ((host->version >= SDHCI_SPEC_200) &&
2832 (caps[0] & SDHCI_CAN_DO_ADMA2))
2833 host->flags |= SDHCI_USE_ADMA;
2835 if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
2836 (host->flags & SDHCI_USE_ADMA)) {
2837 DBG("Disabling ADMA as it is marked broken\n");
2838 host->flags &= ~SDHCI_USE_ADMA;
2841 if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) {
2842 if (host->ops->enable_dma) {
2843 if (host->ops->enable_dma(host)) {
2844 pr_warning("%s: No suitable DMA "
2845 "available. Falling back to PIO.\n",
2848 ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA);
2853 if (host->flags & SDHCI_USE_ADMA) {
2855 * We need to allocate descriptors for all sg entries
2856 * (128) and potentially one alignment transfer for
2857 * each of those entries.
2859 host->adma_desc = kmalloc((128 * 2 + 1) * 4, GFP_KERNEL);
2860 host->align_buffer = kmalloc(128 * 4, GFP_KERNEL);
2861 if (!host->adma_desc || !host->align_buffer) {
2862 kfree(host->adma_desc);
2863 kfree(host->align_buffer);
2864 pr_warning("%s: Unable to allocate ADMA "
2865 "buffers. Falling back to standard DMA.\n",
2867 host->flags &= ~SDHCI_USE_ADMA;
2872 * If we use DMA, then it's up to the caller to set the DMA
2873 * mask, but PIO does not need the hw shim so we set a new
2874 * mask here in that case.
2876 if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) {
2877 host->dma_mask = DMA_BIT_MASK(64);
2878 mmc_dev(host->mmc)->dma_mask = &host->dma_mask;
2881 if (host->version >= SDHCI_SPEC_300)
2882 host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
2883 >> SDHCI_CLOCK_BASE_SHIFT;
2885 host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
2886 >> SDHCI_CLOCK_BASE_SHIFT;
2888 host->max_clk *= 1000000;
2889 if (host->max_clk == 0 || host->quirks &
2890 SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) {
2891 if (!host->ops->get_max_clock) {
2892 pr_err("%s: Hardware doesn't specify base clock "
2893 "frequency.\n", mmc_hostname(mmc));
2896 host->max_clk = host->ops->get_max_clock(host);
2900 * In case of Host Controller v3.00, find out whether clock
2901 * multiplier is supported.
2903 host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
2904 SDHCI_CLOCK_MUL_SHIFT;
2907 * In case the value in Clock Multiplier is 0, then programmable
2908 * clock mode is not supported, otherwise the actual clock
2909 * multiplier is one more than the value of Clock Multiplier
2910 * in the Capabilities Register.
2916 * Set host parameters.
2918 mmc->ops = &sdhci_ops;
2919 mmc->f_max = host->max_clk;
2920 if (host->ops->get_min_clock)
2921 mmc->f_min = host->ops->get_min_clock(host);
2922 else if (host->version >= SDHCI_SPEC_300) {
2923 if (host->clk_mul) {
2924 mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
2925 mmc->f_max = host->max_clk * host->clk_mul;
2927 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
2929 mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
2932 (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
2933 if (host->timeout_clk == 0) {
2934 if (host->ops->get_timeout_clock) {
2935 host->timeout_clk = host->ops->get_timeout_clock(host);
2936 } else if (!(host->quirks &
2937 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) {
2938 pr_err("%s: Hardware doesn't specify timeout clock "
2939 "frequency.\n", mmc_hostname(mmc));
2943 if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
2944 host->timeout_clk *= 1000;
2946 if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
2947 host->timeout_clk = mmc->f_max / 1000;
2949 mmc->max_busy_timeout = (1 << 27) / host->timeout_clk;
2951 mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
2952 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2954 if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
2955 host->flags |= SDHCI_AUTO_CMD12;
2957 /* Auto-CMD23 stuff only works in ADMA or PIO. */
2958 if ((host->version >= SDHCI_SPEC_300) &&
2959 ((host->flags & SDHCI_USE_ADMA) ||
2960 !(host->flags & SDHCI_USE_SDMA))) {
2961 host->flags |= SDHCI_AUTO_CMD23;
2962 DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
2964 DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
2968 * A controller may support 8-bit width, but the board itself
2969 * might not have the pins brought out. Boards that support
2970 * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in
2971 * their platform code before calling sdhci_add_host(), and we
2972 * won't assume 8-bit width for hosts without that CAP.
2974 if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
2975 mmc->caps |= MMC_CAP_4_BIT_DATA;
2977 if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23)
2978 mmc->caps &= ~MMC_CAP_CMD23;
2980 if (caps[0] & SDHCI_CAN_DO_HISPD)
2981 mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
2983 if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
2984 !(host->mmc->caps & MMC_CAP_NONREMOVABLE))
2985 mmc->caps |= MMC_CAP_NEEDS_POLL;
2987 /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */
2988 host->vqmmc = regulator_get_optional(mmc_dev(mmc), "vqmmc");
2989 if (IS_ERR_OR_NULL(host->vqmmc)) {
2990 if (PTR_ERR(host->vqmmc) < 0) {
2991 pr_info("%s: no vqmmc regulator found\n",
2996 ret = regulator_enable(host->vqmmc);
2997 if (!regulator_is_supported_voltage(host->vqmmc, 1700000,
2999 caps[1] &= ~(SDHCI_SUPPORT_SDR104 |
3000 SDHCI_SUPPORT_SDR50 |
3001 SDHCI_SUPPORT_DDR50);
3003 pr_warn("%s: Failed to enable vqmmc regulator: %d\n",
3004 mmc_hostname(mmc), ret);
3009 if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V)
3010 caps[1] &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3011 SDHCI_SUPPORT_DDR50);
3013 /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */
3014 if (caps[1] & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
3015 SDHCI_SUPPORT_DDR50))
3016 mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
3018 /* SDR104 supports also implies SDR50 support */
3019 if (caps[1] & SDHCI_SUPPORT_SDR104) {
3020 mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
3021 /* SD3.0: SDR104 is supported so (for eMMC) the caps2
3022 * field can be promoted to support HS200.
3024 if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200))
3025 mmc->caps2 |= MMC_CAP2_HS200;
3026 } else if (caps[1] & SDHCI_SUPPORT_SDR50)
3027 mmc->caps |= MMC_CAP_UHS_SDR50;
3029 if ((caps[1] & SDHCI_SUPPORT_DDR50) &&
3030 !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50))
3031 mmc->caps |= MMC_CAP_UHS_DDR50;
3033 /* Does the host need tuning for SDR50? */
3034 if (caps[1] & SDHCI_USE_SDR50_TUNING)
3035 host->flags |= SDHCI_SDR50_NEEDS_TUNING;
3037 /* Does the host need tuning for SDR104 / HS200? */
3038 if (mmc->caps2 & MMC_CAP2_HS200)
3039 host->flags |= SDHCI_SDR104_NEEDS_TUNING;
3041 /* Driver Type(s) (A, C, D) supported by the host */
3042 if (caps[1] & SDHCI_DRIVER_TYPE_A)
3043 mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
3044 if (caps[1] & SDHCI_DRIVER_TYPE_C)
3045 mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
3046 if (caps[1] & SDHCI_DRIVER_TYPE_D)
3047 mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
3049 /* Initial value for re-tuning timer count */
3050 host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
3051 SDHCI_RETUNING_TIMER_COUNT_SHIFT;
3054 * In case Re-tuning Timer is not disabled, the actual value of
3055 * re-tuning timer will be 2 ^ (n - 1).
3057 if (host->tuning_count)
3058 host->tuning_count = 1 << (host->tuning_count - 1);
3060 /* Re-tuning mode supported by the Host Controller */
3061 host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
3062 SDHCI_RETUNING_MODE_SHIFT;
3066 host->vmmc = regulator_get_optional(mmc_dev(mmc), "vmmc");
3067 if (IS_ERR_OR_NULL(host->vmmc)) {
3068 if (PTR_ERR(host->vmmc) < 0) {
3069 pr_info("%s: no vmmc regulator found\n",
3075 #ifdef CONFIG_REGULATOR
3077 * Voltage range check makes sense only if regulator reports
3078 * any voltage value.
3080 if (host->vmmc && regulator_get_voltage(host->vmmc) > 0) {
3081 ret = regulator_is_supported_voltage(host->vmmc, 2700000,
3083 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_330)))
3084 caps[0] &= ~SDHCI_CAN_VDD_330;
3085 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_300)))
3086 caps[0] &= ~SDHCI_CAN_VDD_300;
3087 ret = regulator_is_supported_voltage(host->vmmc, 1700000,
3089 if ((ret <= 0) || (!(caps[0] & SDHCI_CAN_VDD_180)))
3090 caps[0] &= ~SDHCI_CAN_VDD_180;
3092 #endif /* CONFIG_REGULATOR */
3095 * According to SD Host Controller spec v3.00, if the Host System
3096 * can afford more than 150mA, Host Driver should set XPC to 1. Also
3097 * the value is meaningful only if Voltage Support in the Capabilities
3098 * register is set. The actual current value is 4 times the register
3101 max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
3102 if (!max_current_caps && host->vmmc) {
3103 u32 curr = regulator_get_current_limit(host->vmmc);
3106 /* convert to SDHCI_MAX_CURRENT format */
3107 curr = curr/1000; /* convert to mA */
3108 curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER;
3110 curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT);
3112 (curr << SDHCI_MAX_CURRENT_330_SHIFT) |
3113 (curr << SDHCI_MAX_CURRENT_300_SHIFT) |
3114 (curr << SDHCI_MAX_CURRENT_180_SHIFT);
3118 if (caps[0] & SDHCI_CAN_VDD_330) {
3119 ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
3121 mmc->max_current_330 = ((max_current_caps &
3122 SDHCI_MAX_CURRENT_330_MASK) >>
3123 SDHCI_MAX_CURRENT_330_SHIFT) *
3124 SDHCI_MAX_CURRENT_MULTIPLIER;
3126 if (caps[0] & SDHCI_CAN_VDD_300) {
3127 ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
3129 mmc->max_current_300 = ((max_current_caps &
3130 SDHCI_MAX_CURRENT_300_MASK) >>
3131 SDHCI_MAX_CURRENT_300_SHIFT) *
3132 SDHCI_MAX_CURRENT_MULTIPLIER;
3134 if (caps[0] & SDHCI_CAN_VDD_180) {
3135 ocr_avail |= MMC_VDD_165_195;
3137 mmc->max_current_180 = ((max_current_caps &
3138 SDHCI_MAX_CURRENT_180_MASK) >>
3139 SDHCI_MAX_CURRENT_180_SHIFT) *
3140 SDHCI_MAX_CURRENT_MULTIPLIER;
3144 ocr_avail = host->ocr_mask;
3146 mmc->ocr_avail = ocr_avail;
3147 mmc->ocr_avail_sdio = ocr_avail;
3148 if (host->ocr_avail_sdio)
3149 mmc->ocr_avail_sdio &= host->ocr_avail_sdio;
3150 mmc->ocr_avail_sd = ocr_avail;
3151 if (host->ocr_avail_sd)
3152 mmc->ocr_avail_sd &= host->ocr_avail_sd;
3153 else /* normal SD controllers don't support 1.8V */
3154 mmc->ocr_avail_sd &= ~MMC_VDD_165_195;
3155 mmc->ocr_avail_mmc = ocr_avail;
3156 if (host->ocr_avail_mmc)
3157 mmc->ocr_avail_mmc &= host->ocr_avail_mmc;
3159 if (mmc->ocr_avail == 0) {
3160 pr_err("%s: Hardware doesn't report any "
3161 "support voltages.\n", mmc_hostname(mmc));
3165 spin_lock_init(&host->lock);
3168 * Maximum number of segments. Depends on if the hardware
3169 * can do scatter/gather or not.
3171 if (host->flags & SDHCI_USE_ADMA)
3172 mmc->max_segs = 128;
3173 else if (host->flags & SDHCI_USE_SDMA)
3176 mmc->max_segs = 128;
3179 * Maximum number of sectors in one transfer. Limited by DMA boundary
3182 mmc->max_req_size = 524288;
3185 * Maximum segment size. Could be one segment with the maximum number
3186 * of bytes. When doing hardware scatter/gather, each entry cannot
3187 * be larger than 64 KiB though.
3189 if (host->flags & SDHCI_USE_ADMA) {
3190 if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC)
3191 mmc->max_seg_size = 65535;
3193 mmc->max_seg_size = 65536;
3195 mmc->max_seg_size = mmc->max_req_size;
3199 * Maximum block size. This varies from controller to controller and
3200 * is specified in the capabilities register.
3202 if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
3203 mmc->max_blk_size = 2;
3205 mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
3206 SDHCI_MAX_BLOCK_SHIFT;
3207 if (mmc->max_blk_size >= 3) {
3208 pr_warning("%s: Invalid maximum block size, "
3209 "assuming 512 bytes\n", mmc_hostname(mmc));
3210 mmc->max_blk_size = 0;
3214 mmc->max_blk_size = 512 << mmc->max_blk_size;
3217 * Maximum block count.
3219 mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535;
3224 tasklet_init(&host->finish_tasklet,
3225 sdhci_tasklet_finish, (unsigned long)host);
3227 setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
3229 if (host->version >= SDHCI_SPEC_300) {
3230 init_waitqueue_head(&host->buf_ready_int);
3232 /* Initialize re-tuning timer */
3233 init_timer(&host->tuning_timer);
3234 host->tuning_timer.data = (unsigned long)host;
3235 host->tuning_timer.function = sdhci_tuning_timer;
3238 sdhci_init(host, 0);
3240 ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq,
3241 IRQF_SHARED, mmc_hostname(mmc), host);
3243 pr_err("%s: Failed to request IRQ %d: %d\n",
3244 mmc_hostname(mmc), host->irq, ret);
3248 #ifdef CONFIG_MMC_DEBUG
3249 sdhci_dumpregs(host);
3252 #ifdef SDHCI_USE_LEDS_CLASS
3253 snprintf(host->led_name, sizeof(host->led_name),
3254 "%s::", mmc_hostname(mmc));
3255 host->led.name = host->led_name;
3256 host->led.brightness = LED_OFF;
3257 host->led.default_trigger = mmc_hostname(mmc);
3258 host->led.brightness_set = sdhci_led_control;
3260 ret = led_classdev_register(mmc_dev(mmc), &host->led);
3262 pr_err("%s: Failed to register LED device: %d\n",
3263 mmc_hostname(mmc), ret);
3272 pr_info("%s: SDHCI controller on %s [%s] using %s\n",
3273 mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)),
3274 (host->flags & SDHCI_USE_ADMA) ? "ADMA" :
3275 (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO");
3277 sdhci_enable_card_detection(host);
3281 #ifdef SDHCI_USE_LEDS_CLASS
3283 sdhci_do_reset(host, SDHCI_RESET_ALL);
3284 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3285 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3286 free_irq(host->irq, host);
3289 tasklet_kill(&host->finish_tasklet);
3294 EXPORT_SYMBOL_GPL(sdhci_add_host);
3296 void sdhci_remove_host(struct sdhci_host *host, int dead)
3298 unsigned long flags;
3301 spin_lock_irqsave(&host->lock, flags);
3303 host->flags |= SDHCI_DEVICE_DEAD;
3306 pr_err("%s: Controller removed during "
3307 " transfer!\n", mmc_hostname(host->mmc));
3309 host->mrq->cmd->error = -ENOMEDIUM;
3310 tasklet_schedule(&host->finish_tasklet);
3313 spin_unlock_irqrestore(&host->lock, flags);
3316 sdhci_disable_card_detection(host);
3318 mmc_remove_host(host->mmc);
3320 #ifdef SDHCI_USE_LEDS_CLASS
3321 led_classdev_unregister(&host->led);
3325 sdhci_do_reset(host, SDHCI_RESET_ALL);
3327 sdhci_writel(host, 0, SDHCI_INT_ENABLE);
3328 sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE);
3329 free_irq(host->irq, host);
3331 del_timer_sync(&host->timer);
3333 tasklet_kill(&host->finish_tasklet);
3336 regulator_disable(host->vmmc);
3337 regulator_put(host->vmmc);
3341 regulator_disable(host->vqmmc);
3342 regulator_put(host->vqmmc);
3345 kfree(host->adma_desc);
3346 kfree(host->align_buffer);
3348 host->adma_desc = NULL;
3349 host->align_buffer = NULL;
3352 EXPORT_SYMBOL_GPL(sdhci_remove_host);
3354 void sdhci_free_host(struct sdhci_host *host)
3356 mmc_free_host(host->mmc);
3359 EXPORT_SYMBOL_GPL(sdhci_free_host);
3361 /*****************************************************************************\
3363 * Driver init/exit *
3365 \*****************************************************************************/
3367 static int __init sdhci_drv_init(void)
3370 ": Secure Digital Host Controller Interface driver\n");
3371 pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n");
3376 static void __exit sdhci_drv_exit(void)
3380 module_init(sdhci_drv_init);
3381 module_exit(sdhci_drv_exit);
3383 module_param(debug_quirks, uint, 0444);
3384 module_param(debug_quirks2, uint, 0444);
3386 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>");
3387 MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver");
3388 MODULE_LICENSE("GPL");
3390 MODULE_PARM_DESC(debug_quirks, "Force certain quirks.");
3391 MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks.");