drivers/mtd/nand/atmel/nand-controller.c

   1 /*
   2  * Copyright 2017 ATMEL
   3  * Copyright 2017 Free Electrons
   4  *
   5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
   6  *
   7  * Derived from the atmel_nand.c driver which contained the following
   8  * copyrights:
   9  *
  10  *   Copyright 2003 Rick Bronson
  11  *
  12  *   Derived from drivers/mtd/nand/autcpu12.c
  13  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
  14  *
  15  *   Derived from drivers/mtd/spia.c
  16  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
  17  *
  18  *
  19  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
  20  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
  21  *
  22  *   Derived from Das U-Boot source code
  23  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
  24  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
  25  *
  26  *   Add Programmable Multibit ECC support for various AT91 SoC
  27  *      Copyright 2012 ATMEL, Hong Xu
  28  *
  29  *   Add Nand Flash Controller support for SAMA5 SoC
  30  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
  31  *
  32  * This program is free software; you can redistribute it and/or modify
  33  * it under the terms of the GNU General Public License version 2 as
  34  * published by the Free Software Foundation.
  35  *
  36  * A few words about the naming convention in this file. This convention
  37  * applies to structure and function names.
  38  *
  39  * Prefixes:
  40  *
  41  * - atmel_nand_: all generic structures/functions
  42  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
  43  *                    (at91sam9 and avr32 SoCs)
  44  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
  45  *                     (sama5 SoCs and later)
  46  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
  47  *               that is available in the HSMC block
  48  * - <soc>_nand_: all SoC specific structures/functions
  49  */
  50
  51 #include <linux/clk.h>
  52 #include <linux/dma-mapping.h>
  53 #include <linux/dmaengine.h>
  54 #include <linux/genalloc.h>
  55 #include <linux/gpio.h>
  56 #include <linux/gpio/consumer.h>
  57 #include <linux/interrupt.h>
  58 #include <linux/mfd/syscon.h>
  59 #include <linux/mfd/syscon/atmel-matrix.h>
  60 #include <linux/module.h>
  61 #include <linux/mtd/nand.h>
  62 #include <linux/of_address.h>
  63 #include <linux/of_irq.h>
  64 #include <linux/of_platform.h>
  65 #include <linux/iopoll.h>
  66 #include <linux/platform_device.h>
  67 #include <linux/platform_data/atmel.h>
  68 #include <linux/regmap.h>
  69
  70 #include "pmecc.h"
  71
  72 #define ATMEL_HSMC_NFC_CFG                      0x0
  73 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
  74 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
  75 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
  76 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
  77 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
  78 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
  79 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
  80 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
  81 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
  82 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
  83
  84 #define ATMEL_HSMC_NFC_CTRL                     0x4
  85 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
  86 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
  87
  88 #define ATMEL_HSMC_NFC_SR                       0x8
  89 #define ATMEL_HSMC_NFC_IER                      0xc
  90 #define ATMEL_HSMC_NFC_IDR                      0x10
  91 #define ATMEL_HSMC_NFC_IMR                      0x14
  92 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
  93 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
  94 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
  95 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
  96 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
  97 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
  98 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
  99 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
 100 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
 101 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
 102 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
 103 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
 104 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
 105                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
 106                                                  ATMEL_HSMC_NFC_SR_AWB | \
 107                                                  ATMEL_HSMC_NFC_SR_NFCASE)
 108 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
 109
 110 #define ATMEL_HSMC_NFC_ADDR                     0x18
 111 #define ATMEL_HSMC_NFC_BANK                     0x1c
 112
 113 #define ATMEL_NFC_MAX_RB_ID                     7
 114
 115 #define ATMEL_NFC_SRAM_SIZE                     0x2400
 116
 117 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
 118 #define ATMEL_NFC_VCMD2                         BIT(18)
 119 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
 120 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
 121 #define ATMEL_NFC_DATAEN                        BIT(25)
 122 #define ATMEL_NFC_NFCWR                         BIT(26)
 123
 124 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
 125
 126 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
 127 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
 128
 129 #define DEFAULT_TIMEOUT_MS                      1000
 130 #define MIN_DMA_LEN                             128
 131
 132 enum atmel_nand_rb_type {
 133         ATMEL_NAND_NO_RB,
 134         ATMEL_NAND_NATIVE_RB,
 135         ATMEL_NAND_GPIO_RB,
 136 };
 137
 138 struct atmel_nand_rb {
 139         enum atmel_nand_rb_type type;
 140         union {
 141                 struct gpio_desc *gpio;
 142                 int id;
 143         };
 144 };
 145
 146 struct atmel_nand_cs {
 147         int id;
 148         struct atmel_nand_rb rb;
 149         struct gpio_desc *csgpio;
 150         struct {
 151                 void __iomem *virt;
 152                 dma_addr_t dma;
 153         } io;
 154 };
 155
 156 struct atmel_nand {
 157         struct list_head node;
 158         struct device *dev;
 159         struct nand_chip base;
 160         struct atmel_nand_cs *activecs;
 161         struct atmel_pmecc_user *pmecc;
 162         struct gpio_desc *cdgpio;
 163         int numcs;
 164         struct atmel_nand_cs cs[];
 165 };
 166
 167 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
 168 {
 169         return container_of(chip, struct atmel_nand, base);
 170 }
 171
 172 enum atmel_nfc_data_xfer {
 173         ATMEL_NFC_NO_DATA,
 174         ATMEL_NFC_READ_DATA,
 175         ATMEL_NFC_WRITE_DATA,
 176 };
 177
 178 struct atmel_nfc_op {
 179         u8 cs;
 180         u8 ncmds;
 181         u8 cmds[2];
 182         u8 naddrs;
 183         u8 addrs[5];
 184         enum atmel_nfc_data_xfer data;
 185         u32 wait;
 186         u32 errors;
 187 };
 188
 189 struct atmel_nand_controller;
 190 struct atmel_nand_controller_caps;
 191
 192 struct atmel_nand_controller_ops {
 193         int (*probe)(struct platform_device *pdev,
 194                      const struct atmel_nand_controller_caps *caps);
 195         int (*remove)(struct atmel_nand_controller *nc);
 196         void (*nand_init)(struct atmel_nand_controller *nc,
 197                           struct atmel_nand *nand);
 198         int (*ecc_init)(struct atmel_nand *nand);
 199 };
 200
 201 struct atmel_nand_controller_caps {
 202         bool has_dma;
 203         bool legacy_of_bindings;
 204         u32 ale_offs;
 205         u32 cle_offs;
 206         const struct atmel_nand_controller_ops *ops;
 207 };
 208
 209 struct atmel_nand_controller {
 210         struct nand_hw_control base;
 211         const struct atmel_nand_controller_caps *caps;
 212         struct device *dev;
 213         struct regmap *smc;
 214         struct dma_chan *dmac;
 215         struct atmel_pmecc *pmecc;
 216         struct list_head chips;
 217         struct clk *mck;
 218 };
 219
 220 static inline struct atmel_nand_controller *
 221 to_nand_controller(struct nand_hw_control *ctl)
 222 {
 223         return container_of(ctl, struct atmel_nand_controller, base);
 224 }
 225
 226 struct atmel_smc_nand_controller {
 227         struct atmel_nand_controller base;
 228         struct regmap *matrix;
 229         unsigned int ebi_csa_offs;
 230 };
 231
 232 static inline struct atmel_smc_nand_controller *
 233 to_smc_nand_controller(struct nand_hw_control *ctl)
 234 {
 235         return container_of(to_nand_controller(ctl),
 236                             struct atmel_smc_nand_controller, base);
 237 }
 238
 239 struct atmel_hsmc_nand_controller {
 240         struct atmel_nand_controller base;
 241         struct {
 242                 struct gen_pool *pool;
 243                 void __iomem *virt;
 244                 dma_addr_t dma;
 245         } sram;
 246         struct regmap *io;
 247         struct atmel_nfc_op op;
 248         struct completion complete;
 249         int irq;
 250
 251         /* Only used when instantiating from legacy DT bindings. */
 252         struct clk *clk;
 253 };
 254
 255 static inline struct atmel_hsmc_nand_controller *
 256 to_hsmc_nand_controller(struct nand_hw_control *ctl)
 257 {
 258         return container_of(to_nand_controller(ctl),
 259                             struct atmel_hsmc_nand_controller, base);
 260 }
 261
 262 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
 263 {
 264         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
 265         op->wait ^= status & op->wait;
 266
 267         return !op->wait || op->errors;
 268 }
 269
 270 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
 271 {
 272         struct atmel_hsmc_nand_controller *nc = data;
 273         u32 sr, rcvd;
 274         bool done;
 275
 276         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
 277
 278         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 279         done = atmel_nfc_op_done(&nc->op, sr);
 280
 281         if (rcvd)
 282                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
 283
 284         if (done)
 285                 complete(&nc->complete);
 286
 287         return rcvd ? IRQ_HANDLED : IRQ_NONE;
 288 }
 289
 290 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
 291                           unsigned int timeout_ms)
 292 {
 293         int ret;
 294
 295         if (!timeout_ms)
 296                 timeout_ms = DEFAULT_TIMEOUT_MS;
 297
 298         if (poll) {
 299                 u32 status;
 300
 301                 ret = regmap_read_poll_timeout(nc->base.smc,
 302                                                ATMEL_HSMC_NFC_SR, status,
 303                                                atmel_nfc_op_done(&nc->op,
 304                                                                  status),
 305                                                0, timeout_ms * 1000);
 306         } else {
 307                 init_completion(&nc->complete);
 308                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
 309                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
 310                 ret = wait_for_completion_timeout(&nc->complete,
 311                                                 msecs_to_jiffies(timeout_ms));
 312                 if (!ret)
 313                         ret = -ETIMEDOUT;
 314                 else
 315                         ret = 0;
 316
 317                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
 318         }
 319
 320         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
 321                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
 322                 ret = -ETIMEDOUT;
 323         }
 324
 325         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
 326                 dev_err(nc->base.dev, "Access to an undefined area\n");
 327                 ret = -EIO;
 328         }
 329
 330         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
 331                 dev_err(nc->base.dev, "Access while busy\n");
 332                 ret = -EIO;
 333         }
 334
 335         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
 336                 dev_err(nc->base.dev, "Wrong access size\n");
 337                 ret = -EIO;
 338         }
 339
 340         return ret;
 341 }
 342
 343 static void atmel_nand_dma_transfer_finished(void *data)
 344 {
 345         struct completion *finished = data;
 346
 347         complete(finished);
 348 }
 349
 350 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
 351                                    void *buf, dma_addr_t dev_dma, size_t len,
 352                                    enum dma_data_direction dir)
 353 {
 354         DECLARE_COMPLETION_ONSTACK(finished);
 355         dma_addr_t src_dma, dst_dma, buf_dma;
 356         struct dma_async_tx_descriptor *tx;
 357         dma_cookie_t cookie;
 358
 359         buf_dma = dma_map_single(nc->dev, buf, len, dir);
 360         if (dma_mapping_error(nc->dev, dev_dma)) {
 361                 dev_err(nc->dev,
 362                         "Failed to prepare a buffer for DMA access\n");
 363                 goto err;
 364         }
 365
 366         if (dir == DMA_FROM_DEVICE) {
 367                 src_dma = dev_dma;
 368                 dst_dma = buf_dma;
 369         } else {
 370                 src_dma = buf_dma;
 371                 dst_dma = dev_dma;
 372         }
 373
 374         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
 375                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
 376         if (!tx) {
 377                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
 378                 goto err_unmap;
 379         }
 380
 381         tx->callback = atmel_nand_dma_transfer_finished;
 382         tx->callback_param = &finished;
 383
 384         cookie = dmaengine_submit(tx);
 385         if (dma_submit_error(cookie)) {
 386                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
 387                 goto err_unmap;
 388         }
 389
 390         dma_async_issue_pending(nc->dmac);
 391         wait_for_completion(&finished);
 392
 393         return 0;
 394
 395 err_unmap:
 396         dma_unmap_single(nc->dev, buf_dma, len, dir);
 397
 398 err:
 399         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
 400
 401         return -EIO;
 402 }
 403
 404 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
 405 {
 406         struct nand_chip *chip = mtd_to_nand(mtd);
 407         struct atmel_nand *nand = to_atmel_nand(chip);
 408
 409         return ioread8(nand->activecs->io.virt);
 410 }
 411
 412 static u16 atmel_nand_read_word(struct mtd_info *mtd)
 413 {
 414         struct nand_chip *chip = mtd_to_nand(mtd);
 415         struct atmel_nand *nand = to_atmel_nand(chip);
 416
 417         return ioread16(nand->activecs->io.virt);
 418 }
 419
 420 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
 421 {
 422         struct nand_chip *chip = mtd_to_nand(mtd);
 423         struct atmel_nand *nand = to_atmel_nand(chip);
 424
 425         if (chip->options & NAND_BUSWIDTH_16)
 426                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
 427         else
 428                 iowrite8(byte, nand->activecs->io.virt);
 429 }
 430
 431 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 432 {
 433         struct nand_chip *chip = mtd_to_nand(mtd);
 434         struct atmel_nand *nand = to_atmel_nand(chip);
 435         struct atmel_nand_controller *nc;
 436
 437         nc = to_nand_controller(chip->controller);
 438
 439         /*
 440          * If the controller supports DMA, the buffer address is DMA-able and
 441          * len is long enough to make DMA transfers profitable, let's trigger
 442          * a DMA transfer. If it fails, fallback to PIO mode.
 443          */
 444         if (nc->dmac && virt_addr_valid(buf) &&
 445             len >= MIN_DMA_LEN &&
 446             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
 447                                      DMA_FROM_DEVICE))
 448                 return;
 449
 450         if (chip->options & NAND_BUSWIDTH_16)
 451                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
 452         else
 453                 ioread8_rep(nand->activecs->io.virt, buf, len);
 454 }
 455
 456 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 457 {
 458         struct nand_chip *chip = mtd_to_nand(mtd);
 459         struct atmel_nand *nand = to_atmel_nand(chip);
 460         struct atmel_nand_controller *nc;
 461
 462         nc = to_nand_controller(chip->controller);
 463
 464         /*
 465          * If the controller supports DMA, the buffer address is DMA-able and
 466          * len is long enough to make DMA transfers profitable, let's trigger
 467          * a DMA transfer. If it fails, fallback to PIO mode.
 468          */
 469         if (nc->dmac && virt_addr_valid(buf) &&
 470             len >= MIN_DMA_LEN &&
 471             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
 472                                      len, DMA_TO_DEVICE))
 473                 return;
 474
 475         if (chip->options & NAND_BUSWIDTH_16)
 476                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
 477         else
 478                 iowrite8_rep(nand->activecs->io.virt, buf, len);
 479 }
 480
 481 static int atmel_nand_dev_ready(struct mtd_info *mtd)
 482 {
 483         struct nand_chip *chip = mtd_to_nand(mtd);
 484         struct atmel_nand *nand = to_atmel_nand(chip);
 485
 486         return gpiod_get_value(nand->activecs->rb.gpio);
 487 }
 488
 489 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
 490 {
 491         struct nand_chip *chip = mtd_to_nand(mtd);
 492         struct atmel_nand *nand = to_atmel_nand(chip);
 493
 494         if (cs < 0 || cs >= nand->numcs) {
 495                 nand->activecs = NULL;
 496                 chip->dev_ready = NULL;
 497                 return;
 498         }
 499
 500         nand->activecs = &nand->cs[cs];
 501
 502         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
 503                 chip->dev_ready = atmel_nand_dev_ready;
 504 }
 505
 506 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
 507 {
 508         struct nand_chip *chip = mtd_to_nand(mtd);
 509         struct atmel_nand *nand = to_atmel_nand(chip);
 510         struct atmel_hsmc_nand_controller *nc;
 511         u32 status;
 512
 513         nc = to_hsmc_nand_controller(chip->controller);
 514
 515         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
 516
 517         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
 518 }
 519
 520 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
 521 {
 522         struct nand_chip *chip = mtd_to_nand(mtd);
 523         struct atmel_nand *nand = to_atmel_nand(chip);
 524         struct atmel_hsmc_nand_controller *nc;
 525
 526         nc = to_hsmc_nand_controller(chip->controller);
 527
 528         atmel_nand_select_chip(mtd, cs);
 529
 530         if (!nand->activecs) {
 531                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 532                              ATMEL_HSMC_NFC_CTRL_DIS);
 533                 return;
 534         }
 535
 536         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
 537                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
 538
 539         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
 540                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
 541                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
 542                            ATMEL_HSMC_NFC_CFG_RSPARE |
 543                            ATMEL_HSMC_NFC_CFG_WSPARE,
 544                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
 545                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
 546                            ATMEL_HSMC_NFC_CFG_RSPARE);
 547         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
 548                      ATMEL_HSMC_NFC_CTRL_EN);
 549 }
 550
 551 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
 552 {
 553         u8 *addrs = nc->op.addrs;
 554         unsigned int op = 0;
 555         u32 addr, val;
 556         int i, ret;
 557
 558         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
 559
 560         for (i = 0; i < nc->op.ncmds; i++)
 561                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
 562
 563         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 564                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
 565
 566         op |= ATMEL_NFC_CSID(nc->op.cs) |
 567               ATMEL_NFC_ACYCLE(nc->op.naddrs);
 568
 569         if (nc->op.ncmds > 1)
 570                 op |= ATMEL_NFC_VCMD2;
 571
 572         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
 573                (addrs[3] << 24);
 574
 575         if (nc->op.data != ATMEL_NFC_NO_DATA) {
 576                 op |= ATMEL_NFC_DATAEN;
 577                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
 578
 579                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
 580                         op |= ATMEL_NFC_NFCWR;
 581         }
 582
 583         /* Clear all flags. */
 584         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
 585
 586         /* Send the command. */
 587         regmap_write(nc->io, op, addr);
 588
 589         ret = atmel_nfc_wait(nc, poll, 0);
 590         if (ret)
 591                 dev_err(nc->base.dev,
 592                         "Failed to send NAND command (err = %d)!",
 593                         ret);
 594
 595         /* Reset the op state. */
 596         memset(&nc->op, 0, sizeof(nc->op));
 597
 598         return ret;
 599 }
 600
 601 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
 602                                      unsigned int ctrl)
 603 {
 604         struct nand_chip *chip = mtd_to_nand(mtd);
 605         struct atmel_nand *nand = to_atmel_nand(chip);
 606         struct atmel_hsmc_nand_controller *nc;
 607
 608         nc = to_hsmc_nand_controller(chip->controller);
 609
 610         if (ctrl & NAND_ALE) {
 611                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
 612                         return;
 613
 614                 nc->op.addrs[nc->op.naddrs++] = dat;
 615         } else if (ctrl & NAND_CLE) {
 616                 if (nc->op.ncmds > 1)
 617                         return;
 618
 619                 nc->op.cmds[nc->op.ncmds++] = dat;
 620         }
 621
 622         if (dat == NAND_CMD_NONE) {
 623                 nc->op.cs = nand->activecs->id;
 624                 atmel_nfc_exec_op(nc, true);
 625         }
 626 }
 627
 628 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 629                                 unsigned int ctrl)
 630 {
 631         struct nand_chip *chip = mtd_to_nand(mtd);
 632         struct atmel_nand *nand = to_atmel_nand(chip);
 633         struct atmel_nand_controller *nc;
 634
 635         nc = to_nand_controller(chip->controller);
 636
 637         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
 638                 if (ctrl & NAND_NCE)
 639                         gpiod_set_value(nand->activecs->csgpio, 0);
 640                 else
 641                         gpiod_set_value(nand->activecs->csgpio, 1);
 642         }
 643
 644         if (ctrl & NAND_ALE)
 645                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
 646         else if (ctrl & NAND_CLE)
 647                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
 648 }
 649
 650 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
 651                                    bool oob_required)
 652 {
 653         struct mtd_info *mtd = nand_to_mtd(chip);
 654         struct atmel_hsmc_nand_controller *nc;
 655         int ret = -EIO;
 656
 657         nc = to_hsmc_nand_controller(chip->controller);
 658
 659         if (nc->base.dmac)
 660                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
 661                                               nc->sram.dma, mtd->writesize,
 662                                               DMA_TO_DEVICE);
 663
 664         /* Falling back to CPU copy. */
 665         if (ret)
 666                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
 667
 668         if (oob_required)
 669                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
 670                             mtd->oobsize);
 671 }
 672
 673 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
 674                                      bool oob_required)
 675 {
 676         struct mtd_info *mtd = nand_to_mtd(chip);
 677         struct atmel_hsmc_nand_controller *nc;
 678         int ret = -EIO;
 679
 680         nc = to_hsmc_nand_controller(chip->controller);
 681
 682         if (nc->base.dmac)
 683                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
 684                                               mtd->writesize, DMA_FROM_DEVICE);
 685
 686         /* Falling back to CPU copy. */
 687         if (ret)
 688                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
 689
 690         if (oob_required)
 691                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
 692                               mtd->oobsize);
 693 }
 694
 695 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
 696 {
 697         struct mtd_info *mtd = nand_to_mtd(chip);
 698         struct atmel_hsmc_nand_controller *nc;
 699
 700         nc = to_hsmc_nand_controller(chip->controller);
 701
 702         if (column >= 0) {
 703                 nc->op.addrs[nc->op.naddrs++] = column;
 704
 705                 /*
 706                  * 2 address cycles for the column offset on large page NANDs.
 707                  */
 708                 if (mtd->writesize > 512)
 709                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
 710         }
 711
 712         if (page >= 0) {
 713                 nc->op.addrs[nc->op.naddrs++] = page;
 714                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
 715
 716                 if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
 717                     (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
 718                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
 719         }
 720 }
 721
 722 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
 723 {
 724         struct atmel_nand *nand = to_atmel_nand(chip);
 725         struct atmel_nand_controller *nc;
 726         int ret;
 727
 728         nc = to_nand_controller(chip->controller);
 729
 730         if (raw)
 731                 return 0;
 732
 733         ret = atmel_pmecc_enable(nand->pmecc, op);
 734         if (ret)
 735                 dev_err(nc->dev,
 736                         "Failed to enable ECC engine (err = %d)\n", ret);
 737
 738         return ret;
 739 }
 740
 741 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
 742 {
 743         struct atmel_nand *nand = to_atmel_nand(chip);
 744
 745         if (!raw)
 746                 atmel_pmecc_disable(nand->pmecc);
 747 }
 748
 749 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
 750 {
 751         struct atmel_nand *nand = to_atmel_nand(chip);
 752         struct mtd_info *mtd = nand_to_mtd(chip);
 753         struct atmel_nand_controller *nc;
 754         struct mtd_oob_region oobregion;
 755         void *eccbuf;
 756         int ret, i;
 757
 758         nc = to_nand_controller(chip->controller);
 759
 760         if (raw)
 761                 return 0;
 762
 763         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 764         if (ret) {
 765                 dev_err(nc->dev,
 766                         "Failed to transfer NAND page data (err = %d)\n",
 767                         ret);
 768                 return ret;
 769         }
 770
 771         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 772         eccbuf = chip->oob_poi + oobregion.offset;
 773
 774         for (i = 0; i < chip->ecc.steps; i++) {
 775                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
 776                                                    eccbuf);
 777                 eccbuf += chip->ecc.bytes;
 778         }
 779
 780         return 0;
 781 }
 782
 783 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
 784                                          bool raw)
 785 {
 786         struct atmel_nand *nand = to_atmel_nand(chip);
 787         struct mtd_info *mtd = nand_to_mtd(chip);
 788         struct atmel_nand_controller *nc;
 789         struct mtd_oob_region oobregion;
 790         int ret, i, max_bitflips = 0;
 791         void *databuf, *eccbuf;
 792
 793         nc = to_nand_controller(chip->controller);
 794
 795         if (raw)
 796                 return 0;
 797
 798         ret = atmel_pmecc_wait_rdy(nand->pmecc);
 799         if (ret) {
 800                 dev_err(nc->dev,
 801                         "Failed to read NAND page data (err = %d)\n",
 802                         ret);
 803                 return ret;
 804         }
 805
 806         mtd_ooblayout_ecc(mtd, 0, &oobregion);
 807         eccbuf = chip->oob_poi + oobregion.offset;
 808         databuf = buf;
 809
 810         for (i = 0; i < chip->ecc.steps; i++) {
 811                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
 812                                                  eccbuf);
 813                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
 814                         ret = nand_check_erased_ecc_chunk(databuf,
 815                                                           chip->ecc.size,
 816                                                           eccbuf,
 817                                                           chip->ecc.bytes,
 818                                                           NULL, 0,
 819                                                           chip->ecc.strength);
 820
 821                 if (ret >= 0)
 822                         max_bitflips = max(ret, max_bitflips);
 823                 else
 824                         mtd->ecc_stats.failed++;
 825
 826                 databuf += chip->ecc.size;
 827                 eccbuf += chip->ecc.bytes;
 828         }
 829
 830         return max_bitflips;
 831 }
 832
 833 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
 834                                      bool oob_required, int page, bool raw)
 835 {
 836         struct mtd_info *mtd = nand_to_mtd(chip);
 837         struct atmel_nand *nand = to_atmel_nand(chip);
 838         int ret;
 839
 840         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 841         if (ret)
 842                 return ret;
 843
 844         atmel_nand_write_buf(mtd, buf, mtd->writesize);
 845
 846         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 847         if (ret) {
 848                 atmel_pmecc_disable(nand->pmecc);
 849                 return ret;
 850         }
 851
 852         atmel_nand_pmecc_disable(chip, raw);
 853
 854         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 855
 856         return 0;
 857 }
 858
 859 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
 860                                        struct nand_chip *chip, const u8 *buf,
 861                                        int oob_required, int page)
 862 {
 863         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
 864 }
 865
 866 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 867                                            struct nand_chip *chip,
 868                                            const u8 *buf, int oob_required,
 869                                            int page)
 870 {
 871         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
 872 }
 873
 874 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 875                                     bool oob_required, int page, bool raw)
 876 {
 877         struct mtd_info *mtd = nand_to_mtd(chip);
 878         int ret;
 879
 880         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
 881         if (ret)
 882                 return ret;
 883
 884         atmel_nand_read_buf(mtd, buf, mtd->writesize);
 885         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
 886
 887         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
 888
 889         atmel_nand_pmecc_disable(chip, raw);
 890
 891         return ret;
 892 }
 893
 894 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
 895                                       struct nand_chip *chip, u8 *buf,
 896                                       int oob_required, int page)
 897 {
 898         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
 899 }
 900
 901 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
 902                                           struct nand_chip *chip, u8 *buf,
 903                                           int oob_required, int page)
 904 {
 905         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
 906 }
 907
 908 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
 909                                           const u8 *buf, bool oob_required,
 910                                           int page, bool raw)
 911 {
 912         struct mtd_info *mtd = nand_to_mtd(chip);
 913         struct atmel_nand *nand = to_atmel_nand(chip);
 914         struct atmel_hsmc_nand_controller *nc;
 915         int ret;
 916
 917         nc = to_hsmc_nand_controller(chip->controller);
 918
 919         atmel_nfc_copy_to_sram(chip, buf, false);
 920
 921         nc->op.cmds[0] = NAND_CMD_SEQIN;
 922         nc->op.ncmds = 1;
 923         atmel_nfc_set_op_addr(chip, page, 0x0);
 924         nc->op.cs = nand->activecs->id;
 925         nc->op.data = ATMEL_NFC_WRITE_DATA;
 926
 927         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
 928         if (ret)
 929                 return ret;
 930
 931         ret = atmel_nfc_exec_op(nc, false);
 932         if (ret) {
 933                 atmel_nand_pmecc_disable(chip, raw);
 934                 dev_err(nc->base.dev,
 935                         "Failed to transfer NAND page data (err = %d)\n",
 936                         ret);
 937                 return ret;
 938         }
 939
 940         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
 941
 942         atmel_nand_pmecc_disable(chip, raw);
 943
 944         if (ret)
 945                 return ret;
 946
 947         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
 948
 949         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
 950         nc->op.ncmds = 1;
 951         nc->op.cs = nand->activecs->id;
 952         ret = atmel_nfc_exec_op(nc, false);
 953         if (ret)
 954                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
 955                         ret);
 956
 957         return ret;
 958 }
 959
 960 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
 961                                             struct nand_chip *chip,
 962                                             const u8 *buf, int oob_required,
 963                                             int page)
 964 {
 965         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 966                                               false);
 967 }
 968
 969 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
 970                                                 struct nand_chip *chip,
 971                                                 const u8 *buf,
 972                                                 int oob_required, int page)
 973 {
 974         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
 975                                               true);
 976 }
 977
 978 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
 979                                          bool oob_required, int page,
 980                                          bool raw)
 981 {
 982         struct mtd_info *mtd = nand_to_mtd(chip);
 983         struct atmel_nand *nand = to_atmel_nand(chip);
 984         struct atmel_hsmc_nand_controller *nc;
 985         int ret;
 986
 987         nc = to_hsmc_nand_controller(chip->controller);
 988
 989         /*
 990          * Optimized read page accessors only work when the NAND R/B pin is
 991          * connected to a native SoC R/B pin. If that's not the case, fallback
 992          * to the non-optimized one.
 993          */
 994         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
 995                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
 996
 997                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
 998                                                 raw);
 999         }
1000
1001         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1002
1003         if (mtd->writesize > 512)
1004                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1005
1006         atmel_nfc_set_op_addr(chip, page, 0x0);
1007         nc->op.cs = nand->activecs->id;
1008         nc->op.data = ATMEL_NFC_READ_DATA;
1009
1010         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1011         if (ret)
1012                 return ret;
1013
1014         ret = atmel_nfc_exec_op(nc, false);
1015         if (ret) {
1016                 atmel_nand_pmecc_disable(chip, raw);
1017                 dev_err(nc->base.dev,
1018                         "Failed to load NAND page data (err = %d)\n",
1019                         ret);
1020                 return ret;
1021         }
1022
1023         atmel_nfc_copy_from_sram(chip, buf, true);
1024
1025         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1026
1027         atmel_nand_pmecc_disable(chip, raw);
1028
1029         return ret;
1030 }
1031
1032 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1033                                            struct nand_chip *chip, u8 *buf,
1034                                            int oob_required, int page)
1035 {
1036         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1037                                              false);
1038 }
1039
1040 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1041                                                struct nand_chip *chip,
1042                                                u8 *buf, int oob_required,
1043                                                int page)
1044 {
1045         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1046                                              true);
1047 }
1048
1049 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1050 {
1051         struct mtd_info *mtd = nand_to_mtd(chip);
1052         struct atmel_nand *nand = to_atmel_nand(chip);
1053         struct atmel_nand_controller *nc;
1054         struct atmel_pmecc_user_req req;
1055
1056         nc = to_nand_controller(chip->controller);
1057
1058         if (!nc->pmecc) {
1059                 dev_err(nc->dev, "HW ECC not supported\n");
1060                 return -ENOTSUPP;
1061         }
1062
1063         if (nc->caps->legacy_of_bindings) {
1064                 u32 val;
1065
1066                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1067                                           &val))
1068                         chip->ecc.strength = val;
1069
1070                 if (!of_property_read_u32(nc->dev->of_node,
1071                                           "atmel,pmecc-sector-size",
1072                                           &val))
1073                         chip->ecc.size = val;
1074         }
1075
1076         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1077                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1078         else if (chip->ecc.strength)
1079                 req.ecc.strength = chip->ecc.strength;
1080         else if (chip->ecc_strength_ds)
1081                 req.ecc.strength = chip->ecc_strength_ds;
1082         else
1083                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1084
1085         if (chip->ecc.size)
1086                 req.ecc.sectorsize = chip->ecc.size;
1087         else if (chip->ecc_step_ds)
1088                 req.ecc.sectorsize = chip->ecc_step_ds;
1089         else
1090                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1091
1092         req.pagesize = mtd->writesize;
1093         req.oobsize = mtd->oobsize;
1094
1095         if (mtd->writesize <= 512) {
1096                 req.ecc.bytes = 4;
1097                 req.ecc.ooboffset = 0;
1098         } else {
1099                 req.ecc.bytes = mtd->oobsize - 2;
1100                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1101         }
1102
1103         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1104         if (IS_ERR(nand->pmecc))
1105                 return PTR_ERR(nand->pmecc);
1106
1107         chip->ecc.algo = NAND_ECC_BCH;
1108         chip->ecc.size = req.ecc.sectorsize;
1109         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1110         chip->ecc.strength = req.ecc.strength;
1111
1112         chip->options |= NAND_NO_SUBPAGE_WRITE;
1113
1114         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1115
1116         return 0;
1117 }
1118
1119 static int atmel_nand_ecc_init(struct atmel_nand *nand)
1120 {
1121         struct nand_chip *chip = &nand->base;
1122         struct atmel_nand_controller *nc;
1123         int ret;
1124
1125         nc = to_nand_controller(chip->controller);
1126
1127         switch (chip->ecc.mode) {
1128         case NAND_ECC_NONE:
1129         case NAND_ECC_SOFT:
1130                 /*
1131                  * Nothing to do, the core will initialize everything for us.
1132                  */
1133                 break;
1134
1135         case NAND_ECC_HW:
1136                 ret = atmel_nand_pmecc_init(chip);
1137                 if (ret)
1138                         return ret;
1139
1140                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1141                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1142                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1143                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1144                 break;
1145
1146         default:
1147                 /* Other modes are not supported. */
1148                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1149                         chip->ecc.mode);
1150                 return -ENOTSUPP;
1151         }
1152
1153         return 0;
1154 }
1155
1156 static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
1157 {
1158         struct nand_chip *chip = &nand->base;
1159         int ret;
1160
1161         ret = atmel_nand_ecc_init(nand);
1162         if (ret)
1163                 return ret;
1164
1165         if (chip->ecc.mode != NAND_ECC_HW)
1166                 return 0;
1167
1168         /* Adjust the ECC operations for the HSMC IP. */
1169         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1170         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1171         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1172         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1173         chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1174
1175         return 0;
1176 }
1177
1178 static void atmel_nand_init(struct atmel_nand_controller *nc,
1179                             struct atmel_nand *nand)
1180 {
1181         struct nand_chip *chip = &nand->base;
1182         struct mtd_info *mtd = nand_to_mtd(chip);
1183
1184         mtd->dev.parent = nc->dev;
1185         nand->base.controller = &nc->base;
1186
1187         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1188         chip->read_byte = atmel_nand_read_byte;
1189         chip->read_word = atmel_nand_read_word;
1190         chip->write_byte = atmel_nand_write_byte;
1191         chip->read_buf = atmel_nand_read_buf;
1192         chip->write_buf = atmel_nand_write_buf;
1193         chip->select_chip = atmel_nand_select_chip;
1194
1195         /* Some NANDs require a longer delay than the default one (20us). */
1196         chip->chip_delay = 40;
1197
1198         /*
1199          * Use a bounce buffer when the buffer passed by the MTD user is not
1200          * suitable for DMA.
1201          */
1202         if (nc->dmac)
1203                 chip->options |= NAND_USE_BOUNCE_BUFFER;
1204
1205         /* Default to HW ECC if pmecc is available. */
1206         if (nc->pmecc)
1207                 chip->ecc.mode = NAND_ECC_HW;
1208 }
1209
1210 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1211                                 struct atmel_nand *nand)
1212 {
1213         struct nand_chip *chip = &nand->base;
1214         struct atmel_smc_nand_controller *smc_nc;
1215         int i;
1216
1217         atmel_nand_init(nc, nand);
1218
1219         smc_nc = to_smc_nand_controller(chip->controller);
1220         if (!smc_nc->matrix)
1221                 return;
1222
1223         /* Attach the CS to the NAND Flash logic. */
1224         for (i = 0; i < nand->numcs; i++)
1225                 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1226                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1227 }
1228
1229 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1230                                  struct atmel_nand *nand)
1231 {
1232         struct nand_chip *chip = &nand->base;
1233
1234         atmel_nand_init(nc, nand);
1235
1236         /* Overload some methods for the HSMC controller. */
1237         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1238         chip->select_chip = atmel_hsmc_nand_select_chip;
1239 }
1240
1241 static int atmel_nand_detect(struct atmel_nand *nand)
1242 {
1243         struct nand_chip *chip = &nand->base;
1244         struct mtd_info *mtd = nand_to_mtd(chip);
1245         struct atmel_nand_controller *nc;
1246         int ret;
1247
1248         nc = to_nand_controller(chip->controller);
1249
1250         ret = nand_scan_ident(mtd, nand->numcs, NULL);
1251         if (ret)
1252                 dev_err(nc->dev, "nand_scan_ident() failed: %d\n", ret);
1253
1254         return ret;
1255 }
1256
1257 static int atmel_nand_unregister(struct atmel_nand *nand)
1258 {
1259         struct nand_chip *chip = &nand->base;
1260         struct mtd_info *mtd = nand_to_mtd(chip);
1261         int ret;
1262
1263         ret = mtd_device_unregister(mtd);
1264         if (ret)
1265                 return ret;
1266
1267         nand_cleanup(chip);
1268         list_del(&nand->node);
1269
1270         return 0;
1271 }
1272
1273 static int atmel_nand_register(struct atmel_nand *nand)
1274 {
1275         struct nand_chip *chip = &nand->base;
1276         struct mtd_info *mtd = nand_to_mtd(chip);
1277         struct atmel_nand_controller *nc;
1278         int ret;
1279
1280         nc = to_nand_controller(chip->controller);
1281
1282         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1283                 /*
1284                  * We keep the MTD name unchanged to avoid breaking platforms
1285                  * where the MTD cmdline parser is used and the bootloader
1286                  * has not been updated to use the new naming scheme.
1287                  */
1288                 mtd->name = "atmel_nand";
1289         } else if (!mtd->name) {
1290                 /*
1291                  * If the new bindings are used and the bootloader has not been
1292                  * updated to pass a new mtdparts parameter on the cmdline, you
1293                  * should define the following property in your nand node:
1294                  *
1295                  *      label = "atmel_nand";
1296                  *
1297                  * This way, mtd->name will be set by the core when
1298                  * nand_set_flash_node() is called.
1299                  */
1300                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1301                                            "%s:nand.%d", dev_name(nc->dev),
1302                                            nand->cs[0].id);
1303                 if (!mtd->name) {
1304                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1305                         return -ENOMEM;
1306                 }
1307         }
1308
1309         ret = nand_scan_tail(mtd);
1310         if (ret) {
1311                 dev_err(nc->dev, "nand_scan_tail() failed: %d\n", ret);
1312                 return ret;
1313         }
1314
1315         ret = mtd_device_register(mtd, NULL, 0);
1316         if (ret) {
1317                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1318                 nand_cleanup(chip);
1319                 return ret;
1320         }
1321
1322         list_add_tail(&nand->node, &nc->chips);
1323
1324         return 0;
1325 }
1326
1327 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1328                                             struct device_node *np,
1329                                             int reg_cells)
1330 {
1331         struct atmel_nand *nand;
1332         struct gpio_desc *gpio;
1333         int numcs, ret, i;
1334
1335         numcs = of_property_count_elems_of_size(np, "reg",
1336                                                 reg_cells * sizeof(u32));
1337         if (numcs < 1) {
1338                 dev_err(nc->dev, "Missing or invalid reg property\n");
1339                 return ERR_PTR(-EINVAL);
1340         }
1341
1342         nand = devm_kzalloc(nc->dev,
1343                             sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1344                             GFP_KERNEL);
1345         if (!nand) {
1346                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1347                 return ERR_PTR(-ENOMEM);
1348         }
1349
1350         nand->numcs = numcs;
1351
1352         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1353                                                       &np->fwnode, GPIOD_IN,
1354                                                       "nand-det");
1355         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1356                 dev_err(nc->dev,
1357                         "Failed to get detect gpio (err = %ld)\n",
1358                         PTR_ERR(gpio));
1359                 return ERR_CAST(gpio);
1360         }
1361
1362         if (!IS_ERR(gpio))
1363                 nand->cdgpio = gpio;
1364
1365         for (i = 0; i < numcs; i++) {
1366                 struct resource res;
1367                 u32 val;
1368
1369                 ret = of_address_to_resource(np, 0, &res);
1370                 if (ret) {
1371                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1372                                 ret);
1373                         return ERR_PTR(ret);
1374                 }
1375
1376                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1377                                                  &val);
1378                 if (ret) {
1379                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1380                                 ret);
1381                         return ERR_PTR(ret);
1382                 }
1383
1384                 nand->cs[i].id = val;
1385
1386                 nand->cs[i].io.dma = res.start;
1387                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1388                 if (IS_ERR(nand->cs[i].io.virt))
1389                         return ERR_CAST(nand->cs[i].io.virt);
1390
1391                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1392                         if (val > ATMEL_NFC_MAX_RB_ID)
1393                                 return ERR_PTR(-EINVAL);
1394
1395                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1396                         nand->cs[i].rb.id = val;
1397                 } else {
1398                         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1399                                                         "rb", i, &np->fwnode,
1400                                                         GPIOD_IN, "nand-rb");
1401                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1402                                 dev_err(nc->dev,
1403                                         "Failed to get R/B gpio (err = %ld)\n",
1404                                         PTR_ERR(gpio));
1405                                 return ERR_CAST(gpio);
1406                         }
1407
1408                         if (!IS_ERR(gpio)) {
1409                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1410                                 nand->cs[i].rb.gpio = gpio;
1411                         }
1412                 }
1413
1414                 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1415                                                               i, &np->fwnode,
1416                                                               GPIOD_OUT_HIGH,
1417                                                               "nand-cs");
1418                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1419                         dev_err(nc->dev,
1420                                 "Failed to get CS gpio (err = %ld)\n",
1421                                 PTR_ERR(gpio));
1422                         return ERR_CAST(gpio);
1423                 }
1424
1425                 if (!IS_ERR(gpio))
1426                         nand->cs[i].csgpio = gpio;
1427         }
1428
1429         nand_set_flash_node(&nand->base, np);
1430
1431         return nand;
1432 }
1433
1434 static int
1435 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1436                                struct atmel_nand *nand)
1437 {
1438         int ret;
1439
1440         /* No card inserted, skip this NAND. */
1441         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1442                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1443                 return 0;
1444         }
1445
1446         nc->caps->ops->nand_init(nc, nand);
1447
1448         ret = atmel_nand_detect(nand);
1449         if (ret)
1450                 return ret;
1451
1452         ret = nc->caps->ops->ecc_init(nand);
1453         if (ret)
1454                 return ret;
1455
1456         return atmel_nand_register(nand);
1457 }
1458
1459 static int
1460 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1461 {
1462         struct atmel_nand *nand, *tmp;
1463         int ret;
1464
1465         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1466                 ret = atmel_nand_unregister(nand);
1467                 if (ret)
1468                         return ret;
1469         }
1470
1471         return 0;
1472 }
1473
1474 static int
1475 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1476 {
1477         struct device *dev = nc->dev;
1478         struct platform_device *pdev = to_platform_device(dev);
1479         struct atmel_nand *nand;
1480         struct gpio_desc *gpio;
1481         struct resource *res;
1482
1483         /*
1484          * Legacy bindings only allow connecting a single NAND with a unique CS
1485          * line to the controller.
1486          */
1487         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1488                             GFP_KERNEL);
1489         if (!nand)
1490                 return -ENOMEM;
1491
1492         nand->numcs = 1;
1493
1494         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1495         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1496         if (IS_ERR(nand->cs[0].io.virt))
1497                 return PTR_ERR(nand->cs[0].io.virt);
1498
1499         nand->cs[0].io.dma = res->start;
1500
1501         /*
1502          * The old driver was hardcoding the CS id to 3 for all sama5
1503          * controllers. Since this id is only meaningful for the sama5
1504          * controller we can safely assign this id to 3 no matter the
1505          * controller.
1506          * If one wants to connect a NAND to a different CS line, he will
1507          * have to use the new bindings.
1508          */
1509         nand->cs[0].id = 3;
1510
1511         /* R/B GPIO. */
1512         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1513         if (IS_ERR(gpio)) {
1514                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1515                         PTR_ERR(gpio));
1516                 return PTR_ERR(gpio);
1517         }
1518
1519         if (gpio) {
1520                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1521                 nand->cs[0].rb.gpio = gpio;
1522         }
1523
1524         /* CS GPIO. */
1525         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1526         if (IS_ERR(gpio)) {
1527                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1528                         PTR_ERR(gpio));
1529                 return PTR_ERR(gpio);
1530         }
1531
1532         nand->cs[0].csgpio = gpio;
1533
1534         /* Card detect GPIO. */
1535         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1536         if (IS_ERR(gpio)) {
1537                 dev_err(dev,
1538                         "Failed to get detect gpio (err = %ld)\n",
1539                         PTR_ERR(gpio));
1540                 return PTR_ERR(gpio);
1541         }
1542
1543         nand->cdgpio = gpio;
1544
1545         nand_set_flash_node(&nand->base, nc->dev->of_node);
1546
1547         return atmel_nand_controller_add_nand(nc, nand);
1548 }
1549
1550 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1551 {
1552         struct device_node *np, *nand_np;
1553         struct device *dev = nc->dev;
1554         int ret, reg_cells;
1555         u32 val;
1556
1557         /* We do not retrieve the SMC syscon when parsing old DTs. */
1558         if (nc->caps->legacy_of_bindings)
1559                 return atmel_nand_controller_legacy_add_nands(nc);
1560
1561         np = dev->of_node;
1562
1563         ret = of_property_read_u32(np, "#address-cells", &val);
1564         if (ret) {
1565                 dev_err(dev, "missing #address-cells property\n");
1566                 return ret;
1567         }
1568
1569         reg_cells = val;
1570
1571         ret = of_property_read_u32(np, "#size-cells", &val);
1572         if (ret) {
1573                 dev_err(dev, "missing #address-cells property\n");
1574                 return ret;
1575         }
1576
1577         reg_cells += val;
1578
1579         for_each_child_of_node(np, nand_np) {
1580                 struct atmel_nand *nand;
1581
1582                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1583                 if (IS_ERR(nand)) {
1584                         ret = PTR_ERR(nand);
1585                         goto err;
1586                 }
1587
1588                 ret = atmel_nand_controller_add_nand(nc, nand);
1589                 if (ret)
1590                         goto err;
1591         }
1592
1593         return 0;
1594
1595 err:
1596         atmel_nand_controller_remove_nands(nc);
1597
1598         return ret;
1599 }
1600
1601 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1602 {
1603         if (nc->dmac)
1604                 dma_release_channel(nc->dmac);
1605
1606         clk_put(nc->mck);
1607 }
1608
1609 static const struct of_device_id atmel_matrix_of_ids[] = {
1610         {
1611                 .compatible = "atmel,at91sam9260-matrix",
1612                 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1613         },
1614         {
1615                 .compatible = "atmel,at91sam9261-matrix",
1616                 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1617         },
1618         {
1619                 .compatible = "atmel,at91sam9263-matrix",
1620                 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1621         },
1622         {
1623                 .compatible = "atmel,at91sam9rl-matrix",
1624                 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1625         },
1626         {
1627                 .compatible = "atmel,at91sam9g45-matrix",
1628                 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1629         },
1630         {
1631                 .compatible = "atmel,at91sam9n12-matrix",
1632                 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1633         },
1634         {
1635                 .compatible = "atmel,at91sam9x5-matrix",
1636                 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1637         },
1638         { /* sentinel */ },
1639 };
1640
1641 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1642                                 struct platform_device *pdev,
1643                                 const struct atmel_nand_controller_caps *caps)
1644 {
1645         struct device *dev = &pdev->dev;
1646         struct device_node *np = dev->of_node;
1647         int ret;
1648
1649         nand_hw_control_init(&nc->base);
1650         INIT_LIST_HEAD(&nc->chips);
1651         nc->dev = dev;
1652         nc->caps = caps;
1653
1654         platform_set_drvdata(pdev, nc);
1655
1656         nc->pmecc = devm_atmel_pmecc_get(dev);
1657         if (IS_ERR(nc->pmecc)) {
1658                 ret = PTR_ERR(nc->pmecc);
1659                 if (ret != -EPROBE_DEFER)
1660                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1661                                 ret);
1662                 return ret;
1663         }
1664
1665         if (nc->caps->has_dma) {
1666                 dma_cap_mask_t mask;
1667
1668                 dma_cap_zero(mask);
1669                 dma_cap_set(DMA_MEMCPY, mask);
1670
1671                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1672                 if (!nc->dmac)
1673                         dev_err(nc->dev, "Failed to request DMA channel\n");
1674         }
1675
1676         /* We do not retrieve the SMC syscon when parsing old DTs. */
1677         if (nc->caps->legacy_of_bindings)
1678                 return 0;
1679
1680         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1681         if (!np) {
1682                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1683                 return -EINVAL;
1684         }
1685
1686         nc->smc = syscon_node_to_regmap(np);
1687         of_node_put(np);
1688         if (IS_ERR(nc->smc)) {
1689                 ret = PTR_ERR(nc->smc);
1690                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1691                 return ret;
1692         }
1693
1694         return 0;
1695 }
1696
1697 static int
1698 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
1699 {
1700         struct device *dev = nc->base.dev;
1701         const struct of_device_id *match;
1702         struct device_node *np;
1703         int ret;
1704
1705         /* We do not retrieve the matrix syscon when parsing old DTs. */
1706         if (nc->base.caps->legacy_of_bindings)
1707                 return 0;
1708
1709         np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
1710         if (!np)
1711                 return 0;
1712
1713         match = of_match_node(atmel_matrix_of_ids, np);
1714         if (!match) {
1715                 of_node_put(np);
1716                 return 0;
1717         }
1718
1719         nc->matrix = syscon_node_to_regmap(np);
1720         of_node_put(np);
1721         if (IS_ERR(nc->matrix)) {
1722                 ret = PTR_ERR(nc->matrix);
1723                 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
1724                 return ret;
1725         }
1726
1727         nc->ebi_csa_offs = (unsigned int)match->data;
1728
1729         /*
1730          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
1731          * add 4 to ->ebi_csa_offs.
1732          */
1733         if (of_device_is_compatible(dev->parent->of_node,
1734                                     "atmel,at91sam9263-ebi1"))
1735                 nc->ebi_csa_offs += 4;
1736
1737         return 0;
1738 }
1739
1740 static int
1741 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
1742 {
1743         struct regmap_config regmap_conf = {
1744                 .reg_bits = 32,
1745                 .val_bits = 32,
1746                 .reg_stride = 4,
1747         };
1748
1749         struct device *dev = nc->base.dev;
1750         struct device_node *nand_np, *nfc_np;
1751         void __iomem *iomem;
1752         struct resource res;
1753         int ret;
1754
1755         nand_np = dev->of_node;
1756         nfc_np = of_find_compatible_node(dev->of_node, NULL,
1757                                          "atmel,sama5d3-nfc");
1758
1759         nc->clk = of_clk_get(nfc_np, 0);
1760         if (IS_ERR(nc->clk)) {
1761                 ret = PTR_ERR(nc->clk);
1762                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
1763                         ret);
1764                 goto out;
1765         }
1766
1767         ret = clk_prepare_enable(nc->clk);
1768         if (ret) {
1769                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
1770                         ret);
1771                 goto out;
1772         }
1773
1774         nc->irq = of_irq_get(nand_np, 0);
1775         if (nc->irq < 0) {
1776                 ret = nc->irq;
1777                 if (ret != -EPROBE_DEFER)
1778                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
1779                                 ret);
1780                 goto out;
1781         }
1782
1783         ret = of_address_to_resource(nfc_np, 0, &res);
1784         if (ret) {
1785                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
1786                         ret);
1787                 goto out;
1788         }
1789
1790         iomem = devm_ioremap_resource(dev, &res);
1791         if (IS_ERR(iomem)) {
1792                 ret = PTR_ERR(iomem);
1793                 goto out;
1794         }
1795
1796         regmap_conf.name = "nfc-io";
1797         regmap_conf.max_register = resource_size(&res) - 4;
1798         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
1799         if (IS_ERR(nc->io)) {
1800                 ret = PTR_ERR(nc->io);
1801                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
1802                         ret);
1803                 goto out;
1804         }
1805
1806         ret = of_address_to_resource(nfc_np, 1, &res);
1807         if (ret) {
1808                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
1809                         ret);
1810                 goto out;
1811         }
1812
1813         iomem = devm_ioremap_resource(dev, &res);
1814         if (IS_ERR(iomem)) {
1815                 ret = PTR_ERR(iomem);
1816                 goto out;
1817         }
1818
1819         regmap_conf.name = "smc";
1820         regmap_conf.max_register = resource_size(&res) - 4;
1821         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
1822         if (IS_ERR(nc->base.smc)) {
1823                 ret = PTR_ERR(nc->base.smc);
1824                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
1825                         ret);
1826                 goto out;
1827         }
1828
1829         ret = of_address_to_resource(nfc_np, 2, &res);
1830         if (ret) {
1831                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
1832                         ret);
1833                 goto out;
1834         }
1835
1836         nc->sram.virt = devm_ioremap_resource(dev, &res);
1837         if (IS_ERR(nc->sram.virt)) {
1838                 ret = PTR_ERR(nc->sram.virt);
1839                 goto out;
1840         }
1841
1842         nc->sram.dma = res.start;
1843
1844 out:
1845         of_node_put(nfc_np);
1846
1847         return ret;
1848 }
1849
1850 static int
1851 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
1852 {
1853         struct device *dev = nc->base.dev;
1854         struct device_node *np;
1855         int ret;
1856
1857         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1858         if (!np) {
1859                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1860                 return -EINVAL;
1861         }
1862
1863         nc->irq = of_irq_get(np, 0);
1864         of_node_put(np);
1865         if (nc->irq < 0) {
1866                 if (nc->irq != -EPROBE_DEFER)
1867                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
1868                                 nc->irq);
1869                 return nc->irq;
1870         }
1871
1872         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
1873         if (!np) {
1874                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
1875                 return -EINVAL;
1876         }
1877
1878         nc->io = syscon_node_to_regmap(np);
1879         of_node_put(np);
1880         if (IS_ERR(nc->io)) {
1881                 ret = PTR_ERR(nc->io);
1882                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
1883                 return ret;
1884         }
1885
1886         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
1887                                          "atmel,nfc-sram", 0);
1888         if (!nc->sram.pool) {
1889                 dev_err(nc->base.dev, "Missing SRAM\n");
1890                 return -ENOMEM;
1891         }
1892
1893         nc->sram.virt = gen_pool_dma_alloc(nc->sram.pool,
1894                                             ATMEL_NFC_SRAM_SIZE,
1895                                             &nc->sram.dma);
1896         if (!nc->sram.virt) {
1897                 dev_err(nc->base.dev,
1898                         "Could not allocate memory from the NFC SRAM pool\n");
1899                 return -ENOMEM;
1900         }
1901
1902         return 0;
1903 }
1904
1905 static int
1906 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
1907 {
1908         struct atmel_hsmc_nand_controller *hsmc_nc;
1909         int ret;
1910
1911         ret = atmel_nand_controller_remove_nands(nc);
1912         if (ret)
1913                 return ret;
1914
1915         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
1916         if (hsmc_nc->sram.pool)
1917                 gen_pool_free(hsmc_nc->sram.pool,
1918                               (unsigned long)hsmc_nc->sram.virt,
1919                               ATMEL_NFC_SRAM_SIZE);
1920
1921         if (hsmc_nc->clk) {
1922                 clk_disable_unprepare(hsmc_nc->clk);
1923                 clk_put(hsmc_nc->clk);
1924         }
1925
1926         atmel_nand_controller_cleanup(nc);
1927
1928         return 0;
1929 }
1930
1931 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
1932                                 const struct atmel_nand_controller_caps *caps)
1933 {
1934         struct device *dev = &pdev->dev;
1935         struct atmel_hsmc_nand_controller *nc;
1936         int ret;
1937
1938         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
1939         if (!nc)
1940                 return -ENOMEM;
1941
1942         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
1943         if (ret)
1944                 return ret;
1945
1946         if (caps->legacy_of_bindings)
1947                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
1948         else
1949                 ret = atmel_hsmc_nand_controller_init(nc);
1950
1951         if (ret)
1952                 return ret;
1953
1954         /* Make sure all irqs are masked before registering our IRQ handler. */
1955         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
1956         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
1957                                IRQF_SHARED, "nfc", nc);
1958         if (ret) {
1959                 dev_err(dev,
1960                         "Could not get register NFC interrupt handler (err = %d)\n",
1961                         ret);
1962                 goto err;
1963         }
1964
1965         /* Initial NFC configuration. */
1966         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
1967                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
1968
1969         ret = atmel_nand_controller_add_nands(&nc->base);
1970         if (ret)
1971                 goto err;
1972
1973         return 0;
1974
1975 err:
1976         atmel_hsmc_nand_controller_remove(&nc->base);
1977
1978         return ret;
1979 }
1980
1981 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
1982         .probe = atmel_hsmc_nand_controller_probe,
1983         .remove = atmel_hsmc_nand_controller_remove,
1984         .ecc_init = atmel_hsmc_nand_ecc_init,
1985         .nand_init = atmel_hsmc_nand_init,
1986 };
1987
1988 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
1989         .has_dma = true,
1990         .ale_offs = BIT(21),
1991         .cle_offs = BIT(22),
1992         .ops = &atmel_hsmc_nc_ops,
1993 };
1994
1995 /* Only used to parse old bindings. */
1996 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
1997         .has_dma = true,
1998         .ale_offs = BIT(21),
1999         .cle_offs = BIT(22),
2000         .ops = &atmel_hsmc_nc_ops,
2001         .legacy_of_bindings = true,
2002 };
2003
2004 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2005                                 const struct atmel_nand_controller_caps *caps)
2006 {
2007         struct device *dev = &pdev->dev;
2008         struct atmel_smc_nand_controller *nc;
2009         int ret;
2010
2011         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2012         if (!nc)
2013                 return -ENOMEM;
2014
2015         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2016         if (ret)
2017                 return ret;
2018
2019         ret = atmel_smc_nand_controller_init(nc);
2020         if (ret)
2021                 return ret;
2022
2023         return atmel_nand_controller_add_nands(&nc->base);
2024 }
2025
2026 static int
2027 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2028 {
2029         int ret;
2030
2031         ret = atmel_nand_controller_remove_nands(nc);
2032         if (ret)
2033                 return ret;
2034
2035         atmel_nand_controller_cleanup(nc);
2036
2037         return 0;
2038 }
2039
2040 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2041         .probe = atmel_smc_nand_controller_probe,
2042         .remove = atmel_smc_nand_controller_remove,
2043         .ecc_init = atmel_nand_ecc_init,
2044         .nand_init = atmel_smc_nand_init,
2045 };
2046
2047 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2048         .ale_offs = BIT(21),
2049         .cle_offs = BIT(22),
2050         .ops = &atmel_smc_nc_ops,
2051 };
2052
2053 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2054         .ale_offs = BIT(22),
2055         .cle_offs = BIT(21),
2056         .ops = &atmel_smc_nc_ops,
2057 };
2058
2059 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2060         .has_dma = true,
2061         .ale_offs = BIT(21),
2062         .cle_offs = BIT(22),
2063         .ops = &atmel_smc_nc_ops,
2064 };
2065
2066 /* Only used to parse old bindings. */
2067 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2068         .ale_offs = BIT(21),
2069         .cle_offs = BIT(22),
2070         .ops = &atmel_smc_nc_ops,
2071         .legacy_of_bindings = true,
2072 };
2073
2074 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2075         .ale_offs = BIT(22),
2076         .cle_offs = BIT(21),
2077         .ops = &atmel_smc_nc_ops,
2078         .legacy_of_bindings = true,
2079 };
2080
2081 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2082         .has_dma = true,
2083         .ale_offs = BIT(21),
2084         .cle_offs = BIT(22),
2085         .ops = &atmel_smc_nc_ops,
2086         .legacy_of_bindings = true,
2087 };
2088
2089 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2090         {
2091                 .compatible = "atmel,at91rm9200-nand-controller",
2092                 .data = &atmel_rm9200_nc_caps,
2093         },
2094         {
2095                 .compatible = "atmel,at91sam9260-nand-controller",
2096                 .data = &atmel_rm9200_nc_caps,
2097         },
2098         {
2099                 .compatible = "atmel,at91sam9261-nand-controller",
2100                 .data = &atmel_sam9261_nc_caps,
2101         },
2102         {
2103                 .compatible = "atmel,at91sam9g45-nand-controller",
2104                 .data = &atmel_sam9g45_nc_caps,
2105         },
2106         {
2107                 .compatible = "atmel,sama5d3-nand-controller",
2108                 .data = &atmel_sama5_nc_caps,
2109         },
2110         /* Support for old/deprecated bindings: */
2111         {
2112                 .compatible = "atmel,at91rm9200-nand",
2113                 .data = &atmel_rm9200_nand_caps,
2114         },
2115         {
2116                 .compatible = "atmel,sama5d4-nand",
2117                 .data = &atmel_rm9200_nand_caps,
2118         },
2119         {
2120                 .compatible = "atmel,sama5d2-nand",
2121                 .data = &atmel_rm9200_nand_caps,
2122         },
2123         { /* sentinel */ },
2124 };
2125 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2126
2127 static int atmel_nand_controller_probe(struct platform_device *pdev)
2128 {
2129         const struct atmel_nand_controller_caps *caps;
2130
2131         if (pdev->id_entry)
2132                 caps = (void *)pdev->id_entry->driver_data;
2133         else
2134                 caps = of_device_get_match_data(&pdev->dev);
2135
2136         if (!caps) {
2137                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2138                 return -EINVAL;
2139         }
2140
2141         if (caps->legacy_of_bindings) {
2142                 u32 ale_offs = 21;
2143
2144                 /*
2145                  * If we are parsing legacy DT props and the DT contains a
2146                  * valid NFC node, forward the request to the sama5 logic.
2147                  */
2148                 if (of_find_compatible_node(pdev->dev.of_node, NULL,
2149                                             "atmel,sama5d3-nfc"))
2150                         caps = &atmel_sama5_nand_caps;
2151
2152                 /*
2153                  * Even if the compatible says we are dealing with an
2154                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2155                  * this controller supports DMA, which means we are in fact
2156                  * dealing with an at91sam9g45+ controller.
2157                  */
2158                 if (!caps->has_dma &&
2159                     of_property_read_bool(pdev->dev.of_node,
2160                                           "atmel,nand-has-dma"))
2161                         caps = &atmel_sam9g45_nand_caps;
2162
2163                 /*
2164                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2165                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2166                  * actually dealing with an at91sam9261 controller.
2167                  */
2168                 of_property_read_u32(pdev->dev.of_node,
2169                                      "atmel,nand-addr-offset", &ale_offs);
2170                 if (ale_offs != 21)
2171                         caps = &atmel_sam9261_nand_caps;
2172         }
2173
2174         return caps->ops->probe(pdev, caps);
2175 }
2176
2177 static int atmel_nand_controller_remove(struct platform_device *pdev)
2178 {
2179         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2180
2181         return nc->caps->ops->remove(nc);
2182 }
2183
2184 static struct platform_driver atmel_nand_controller_driver = {
2185         .driver = {
2186                 .name = "atmel-nand-controller",
2187                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2188         },
2189         .probe = atmel_nand_controller_probe,
2190         .remove = atmel_nand_controller_remove,
2191 };
2192 module_platform_driver(atmel_nand_controller_driver);
2193
2194 MODULE_LICENSE("GPL");
2195 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2196 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2197 MODULE_ALIAS("platform:atmel-nand-controller");