mtd: nand: atmel: Add ->setup_data_interface() hooks
[karo-tx-linux.git] / drivers / mtd / nand / atmel / nand-controller.c
1 /*
2  * Copyright 2017 ATMEL
3  * Copyright 2017 Free Electrons
4  *
5  * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
6  *
7  * Derived from the atmel_nand.c driver which contained the following
8  * copyrights:
9  *
10  *   Copyright 2003 Rick Bronson
11  *
12  *   Derived from drivers/mtd/nand/autcpu12.c
13  *      Copyright 2001 Thomas Gleixner (gleixner@autronix.de)
14  *
15  *   Derived from drivers/mtd/spia.c
16  *      Copyright 2000 Steven J. Hill (sjhill@cotw.com)
17  *
18  *
19  *   Add Hardware ECC support for AT91SAM9260 / AT91SAM9263
20  *      Richard Genoud (richard.genoud@gmail.com), Adeneo Copyright 2007
21  *
22  *   Derived from Das U-Boot source code
23  *      (u-boot-1.1.5/board/atmel/at91sam9263ek/nand.c)
24  *      Copyright 2006 ATMEL Rousset, Lacressonniere Nicolas
25  *
26  *   Add Programmable Multibit ECC support for various AT91 SoC
27  *      Copyright 2012 ATMEL, Hong Xu
28  *
29  *   Add Nand Flash Controller support for SAMA5 SoC
30  *      Copyright 2013 ATMEL, Josh Wu (josh.wu@atmel.com)
31  *
32  * This program is free software; you can redistribute it and/or modify
33  * it under the terms of the GNU General Public License version 2 as
34  * published by the Free Software Foundation.
35  *
36  * A few words about the naming convention in this file. This convention
37  * applies to structure and function names.
38  *
39  * Prefixes:
40  *
41  * - atmel_nand_: all generic structures/functions
42  * - atmel_smc_nand_: all structures/functions specific to the SMC interface
43  *                    (at91sam9 and avr32 SoCs)
44  * - atmel_hsmc_nand_: all structures/functions specific to the HSMC interface
45  *                     (sama5 SoCs and later)
46  * - atmel_nfc_: all structures/functions used to manipulate the NFC sub-block
47  *               that is available in the HSMC block
48  * - <soc>_nand_: all SoC specific structures/functions
49  */
50
51 #include <linux/clk.h>
52 #include <linux/dma-mapping.h>
53 #include <linux/dmaengine.h>
54 #include <linux/genalloc.h>
55 #include <linux/gpio.h>
56 #include <linux/gpio/consumer.h>
57 #include <linux/interrupt.h>
58 #include <linux/mfd/syscon.h>
59 #include <linux/mfd/syscon/atmel-matrix.h>
60 #include <linux/mfd/syscon/atmel-smc.h>
61 #include <linux/module.h>
62 #include <linux/mtd/nand.h>
63 #include <linux/of_address.h>
64 #include <linux/of_irq.h>
65 #include <linux/of_platform.h>
66 #include <linux/iopoll.h>
67 #include <linux/platform_device.h>
68 #include <linux/platform_data/atmel.h>
69 #include <linux/regmap.h>
70
71 #include "pmecc.h"
72
73 #define ATMEL_HSMC_NFC_CFG                      0x0
74 #define ATMEL_HSMC_NFC_CFG_SPARESIZE(x)         (((x) / 4) << 24)
75 #define ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK       GENMASK(30, 24)
76 #define ATMEL_HSMC_NFC_CFG_DTO(cyc, mul)        (((cyc) << 16) | ((mul) << 20))
77 #define ATMEL_HSMC_NFC_CFG_DTO_MAX              GENMASK(22, 16)
78 #define ATMEL_HSMC_NFC_CFG_RBEDGE               BIT(13)
79 #define ATMEL_HSMC_NFC_CFG_FALLING_EDGE         BIT(12)
80 #define ATMEL_HSMC_NFC_CFG_RSPARE               BIT(9)
81 #define ATMEL_HSMC_NFC_CFG_WSPARE               BIT(8)
82 #define ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK        GENMASK(2, 0)
83 #define ATMEL_HSMC_NFC_CFG_PAGESIZE(x)          (fls((x) / 512) - 1)
84
85 #define ATMEL_HSMC_NFC_CTRL                     0x4
86 #define ATMEL_HSMC_NFC_CTRL_EN                  BIT(0)
87 #define ATMEL_HSMC_NFC_CTRL_DIS                 BIT(1)
88
89 #define ATMEL_HSMC_NFC_SR                       0x8
90 #define ATMEL_HSMC_NFC_IER                      0xc
91 #define ATMEL_HSMC_NFC_IDR                      0x10
92 #define ATMEL_HSMC_NFC_IMR                      0x14
93 #define ATMEL_HSMC_NFC_SR_ENABLED               BIT(1)
94 #define ATMEL_HSMC_NFC_SR_RB_RISE               BIT(4)
95 #define ATMEL_HSMC_NFC_SR_RB_FALL               BIT(5)
96 #define ATMEL_HSMC_NFC_SR_BUSY                  BIT(8)
97 #define ATMEL_HSMC_NFC_SR_WR                    BIT(11)
98 #define ATMEL_HSMC_NFC_SR_CSID                  GENMASK(14, 12)
99 #define ATMEL_HSMC_NFC_SR_XFRDONE               BIT(16)
100 #define ATMEL_HSMC_NFC_SR_CMDDONE               BIT(17)
101 #define ATMEL_HSMC_NFC_SR_DTOE                  BIT(20)
102 #define ATMEL_HSMC_NFC_SR_UNDEF                 BIT(21)
103 #define ATMEL_HSMC_NFC_SR_AWB                   BIT(22)
104 #define ATMEL_HSMC_NFC_SR_NFCASE                BIT(23)
105 #define ATMEL_HSMC_NFC_SR_ERRORS                (ATMEL_HSMC_NFC_SR_DTOE | \
106                                                  ATMEL_HSMC_NFC_SR_UNDEF | \
107                                                  ATMEL_HSMC_NFC_SR_AWB | \
108                                                  ATMEL_HSMC_NFC_SR_NFCASE)
109 #define ATMEL_HSMC_NFC_SR_RBEDGE(x)             BIT((x) + 24)
110
111 #define ATMEL_HSMC_NFC_ADDR                     0x18
112 #define ATMEL_HSMC_NFC_BANK                     0x1c
113
114 #define ATMEL_NFC_MAX_RB_ID                     7
115
116 #define ATMEL_NFC_SRAM_SIZE                     0x2400
117
118 #define ATMEL_NFC_CMD(pos, cmd)                 ((cmd) << (((pos) * 8) + 2))
119 #define ATMEL_NFC_VCMD2                         BIT(18)
120 #define ATMEL_NFC_ACYCLE(naddrs)                ((naddrs) << 19)
121 #define ATMEL_NFC_CSID(cs)                      ((cs) << 22)
122 #define ATMEL_NFC_DATAEN                        BIT(25)
123 #define ATMEL_NFC_NFCWR                         BIT(26)
124
125 #define ATMEL_NFC_MAX_ADDR_CYCLES               5
126
127 #define ATMEL_NAND_ALE_OFFSET                   BIT(21)
128 #define ATMEL_NAND_CLE_OFFSET                   BIT(22)
129
130 #define DEFAULT_TIMEOUT_MS                      1000
131 #define MIN_DMA_LEN                             128
132
133 enum atmel_nand_rb_type {
134         ATMEL_NAND_NO_RB,
135         ATMEL_NAND_NATIVE_RB,
136         ATMEL_NAND_GPIO_RB,
137 };
138
139 struct atmel_nand_rb {
140         enum atmel_nand_rb_type type;
141         union {
142                 struct gpio_desc *gpio;
143                 int id;
144         };
145 };
146
147 struct atmel_nand_cs {
148         int id;
149         struct atmel_nand_rb rb;
150         struct gpio_desc *csgpio;
151         struct {
152                 void __iomem *virt;
153                 dma_addr_t dma;
154         } io;
155
156         struct atmel_smc_cs_conf smcconf;
157 };
158
159 struct atmel_nand {
160         struct list_head node;
161         struct device *dev;
162         struct nand_chip base;
163         struct atmel_nand_cs *activecs;
164         struct atmel_pmecc_user *pmecc;
165         struct gpio_desc *cdgpio;
166         int numcs;
167         struct atmel_nand_cs cs[];
168 };
169
170 static inline struct atmel_nand *to_atmel_nand(struct nand_chip *chip)
171 {
172         return container_of(chip, struct atmel_nand, base);
173 }
174
175 enum atmel_nfc_data_xfer {
176         ATMEL_NFC_NO_DATA,
177         ATMEL_NFC_READ_DATA,
178         ATMEL_NFC_WRITE_DATA,
179 };
180
181 struct atmel_nfc_op {
182         u8 cs;
183         u8 ncmds;
184         u8 cmds[2];
185         u8 naddrs;
186         u8 addrs[5];
187         enum atmel_nfc_data_xfer data;
188         u32 wait;
189         u32 errors;
190 };
191
192 struct atmel_nand_controller;
193 struct atmel_nand_controller_caps;
194
195 struct atmel_nand_controller_ops {
196         int (*probe)(struct platform_device *pdev,
197                      const struct atmel_nand_controller_caps *caps);
198         int (*remove)(struct atmel_nand_controller *nc);
199         void (*nand_init)(struct atmel_nand_controller *nc,
200                           struct atmel_nand *nand);
201         int (*ecc_init)(struct atmel_nand *nand);
202         int (*setup_data_interface)(struct atmel_nand *nand, int csline,
203                                     const struct nand_data_interface *conf);
204 };
205
206 struct atmel_nand_controller_caps {
207         bool has_dma;
208         bool legacy_of_bindings;
209         u32 ale_offs;
210         u32 cle_offs;
211         const struct atmel_nand_controller_ops *ops;
212 };
213
214 struct atmel_nand_controller {
215         struct nand_hw_control base;
216         const struct atmel_nand_controller_caps *caps;
217         struct device *dev;
218         struct regmap *smc;
219         struct dma_chan *dmac;
220         struct atmel_pmecc *pmecc;
221         struct list_head chips;
222         struct clk *mck;
223 };
224
225 static inline struct atmel_nand_controller *
226 to_nand_controller(struct nand_hw_control *ctl)
227 {
228         return container_of(ctl, struct atmel_nand_controller, base);
229 }
230
231 struct atmel_smc_nand_controller {
232         struct atmel_nand_controller base;
233         struct regmap *matrix;
234         unsigned int ebi_csa_offs;
235 };
236
237 static inline struct atmel_smc_nand_controller *
238 to_smc_nand_controller(struct nand_hw_control *ctl)
239 {
240         return container_of(to_nand_controller(ctl),
241                             struct atmel_smc_nand_controller, base);
242 }
243
244 struct atmel_hsmc_nand_controller {
245         struct atmel_nand_controller base;
246         struct {
247                 struct gen_pool *pool;
248                 void __iomem *virt;
249                 dma_addr_t dma;
250         } sram;
251         struct regmap *io;
252         struct atmel_nfc_op op;
253         struct completion complete;
254         int irq;
255
256         /* Only used when instantiating from legacy DT bindings. */
257         struct clk *clk;
258 };
259
260 static inline struct atmel_hsmc_nand_controller *
261 to_hsmc_nand_controller(struct nand_hw_control *ctl)
262 {
263         return container_of(to_nand_controller(ctl),
264                             struct atmel_hsmc_nand_controller, base);
265 }
266
267 static bool atmel_nfc_op_done(struct atmel_nfc_op *op, u32 status)
268 {
269         op->errors |= status & ATMEL_HSMC_NFC_SR_ERRORS;
270         op->wait ^= status & op->wait;
271
272         return !op->wait || op->errors;
273 }
274
275 static irqreturn_t atmel_nfc_interrupt(int irq, void *data)
276 {
277         struct atmel_hsmc_nand_controller *nc = data;
278         u32 sr, rcvd;
279         bool done;
280
281         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &sr);
282
283         rcvd = sr & (nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
284         done = atmel_nfc_op_done(&nc->op, sr);
285
286         if (rcvd)
287                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, rcvd);
288
289         if (done)
290                 complete(&nc->complete);
291
292         return rcvd ? IRQ_HANDLED : IRQ_NONE;
293 }
294
295 static int atmel_nfc_wait(struct atmel_hsmc_nand_controller *nc, bool poll,
296                           unsigned int timeout_ms)
297 {
298         int ret;
299
300         if (!timeout_ms)
301                 timeout_ms = DEFAULT_TIMEOUT_MS;
302
303         if (poll) {
304                 u32 status;
305
306                 ret = regmap_read_poll_timeout(nc->base.smc,
307                                                ATMEL_HSMC_NFC_SR, status,
308                                                atmel_nfc_op_done(&nc->op,
309                                                                  status),
310                                                0, timeout_ms * 1000);
311         } else {
312                 init_completion(&nc->complete);
313                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IER,
314                              nc->op.wait | ATMEL_HSMC_NFC_SR_ERRORS);
315                 ret = wait_for_completion_timeout(&nc->complete,
316                                                 msecs_to_jiffies(timeout_ms));
317                 if (!ret)
318                         ret = -ETIMEDOUT;
319                 else
320                         ret = 0;
321
322                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
323         }
324
325         if (nc->op.errors & ATMEL_HSMC_NFC_SR_DTOE) {
326                 dev_err(nc->base.dev, "Waiting NAND R/B Timeout\n");
327                 ret = -ETIMEDOUT;
328         }
329
330         if (nc->op.errors & ATMEL_HSMC_NFC_SR_UNDEF) {
331                 dev_err(nc->base.dev, "Access to an undefined area\n");
332                 ret = -EIO;
333         }
334
335         if (nc->op.errors & ATMEL_HSMC_NFC_SR_AWB) {
336                 dev_err(nc->base.dev, "Access while busy\n");
337                 ret = -EIO;
338         }
339
340         if (nc->op.errors & ATMEL_HSMC_NFC_SR_NFCASE) {
341                 dev_err(nc->base.dev, "Wrong access size\n");
342                 ret = -EIO;
343         }
344
345         return ret;
346 }
347
348 static void atmel_nand_dma_transfer_finished(void *data)
349 {
350         struct completion *finished = data;
351
352         complete(finished);
353 }
354
355 static int atmel_nand_dma_transfer(struct atmel_nand_controller *nc,
356                                    void *buf, dma_addr_t dev_dma, size_t len,
357                                    enum dma_data_direction dir)
358 {
359         DECLARE_COMPLETION_ONSTACK(finished);
360         dma_addr_t src_dma, dst_dma, buf_dma;
361         struct dma_async_tx_descriptor *tx;
362         dma_cookie_t cookie;
363
364         buf_dma = dma_map_single(nc->dev, buf, len, dir);
365         if (dma_mapping_error(nc->dev, dev_dma)) {
366                 dev_err(nc->dev,
367                         "Failed to prepare a buffer for DMA access\n");
368                 goto err;
369         }
370
371         if (dir == DMA_FROM_DEVICE) {
372                 src_dma = dev_dma;
373                 dst_dma = buf_dma;
374         } else {
375                 src_dma = buf_dma;
376                 dst_dma = dev_dma;
377         }
378
379         tx = dmaengine_prep_dma_memcpy(nc->dmac, dst_dma, src_dma, len,
380                                        DMA_CTRL_ACK | DMA_PREP_INTERRUPT);
381         if (!tx) {
382                 dev_err(nc->dev, "Failed to prepare DMA memcpy\n");
383                 goto err_unmap;
384         }
385
386         tx->callback = atmel_nand_dma_transfer_finished;
387         tx->callback_param = &finished;
388
389         cookie = dmaengine_submit(tx);
390         if (dma_submit_error(cookie)) {
391                 dev_err(nc->dev, "Failed to do DMA tx_submit\n");
392                 goto err_unmap;
393         }
394
395         dma_async_issue_pending(nc->dmac);
396         wait_for_completion(&finished);
397
398         return 0;
399
400 err_unmap:
401         dma_unmap_single(nc->dev, buf_dma, len, dir);
402
403 err:
404         dev_dbg(nc->dev, "Fall back to CPU I/O\n");
405
406         return -EIO;
407 }
408
409 static u8 atmel_nand_read_byte(struct mtd_info *mtd)
410 {
411         struct nand_chip *chip = mtd_to_nand(mtd);
412         struct atmel_nand *nand = to_atmel_nand(chip);
413
414         return ioread8(nand->activecs->io.virt);
415 }
416
417 static u16 atmel_nand_read_word(struct mtd_info *mtd)
418 {
419         struct nand_chip *chip = mtd_to_nand(mtd);
420         struct atmel_nand *nand = to_atmel_nand(chip);
421
422         return ioread16(nand->activecs->io.virt);
423 }
424
425 static void atmel_nand_write_byte(struct mtd_info *mtd, u8 byte)
426 {
427         struct nand_chip *chip = mtd_to_nand(mtd);
428         struct atmel_nand *nand = to_atmel_nand(chip);
429
430         if (chip->options & NAND_BUSWIDTH_16)
431                 iowrite16(byte | (byte << 8), nand->activecs->io.virt);
432         else
433                 iowrite8(byte, nand->activecs->io.virt);
434 }
435
436 static void atmel_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
437 {
438         struct nand_chip *chip = mtd_to_nand(mtd);
439         struct atmel_nand *nand = to_atmel_nand(chip);
440         struct atmel_nand_controller *nc;
441
442         nc = to_nand_controller(chip->controller);
443
444         /*
445          * If the controller supports DMA, the buffer address is DMA-able and
446          * len is long enough to make DMA transfers profitable, let's trigger
447          * a DMA transfer. If it fails, fallback to PIO mode.
448          */
449         if (nc->dmac && virt_addr_valid(buf) &&
450             len >= MIN_DMA_LEN &&
451             !atmel_nand_dma_transfer(nc, buf, nand->activecs->io.dma, len,
452                                      DMA_FROM_DEVICE))
453                 return;
454
455         if (chip->options & NAND_BUSWIDTH_16)
456                 ioread16_rep(nand->activecs->io.virt, buf, len / 2);
457         else
458                 ioread8_rep(nand->activecs->io.virt, buf, len);
459 }
460
461 static void atmel_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
462 {
463         struct nand_chip *chip = mtd_to_nand(mtd);
464         struct atmel_nand *nand = to_atmel_nand(chip);
465         struct atmel_nand_controller *nc;
466
467         nc = to_nand_controller(chip->controller);
468
469         /*
470          * If the controller supports DMA, the buffer address is DMA-able and
471          * len is long enough to make DMA transfers profitable, let's trigger
472          * a DMA transfer. If it fails, fallback to PIO mode.
473          */
474         if (nc->dmac && virt_addr_valid(buf) &&
475             len >= MIN_DMA_LEN &&
476             !atmel_nand_dma_transfer(nc, (void *)buf, nand->activecs->io.dma,
477                                      len, DMA_TO_DEVICE))
478                 return;
479
480         if (chip->options & NAND_BUSWIDTH_16)
481                 iowrite16_rep(nand->activecs->io.virt, buf, len / 2);
482         else
483                 iowrite8_rep(nand->activecs->io.virt, buf, len);
484 }
485
486 static int atmel_nand_dev_ready(struct mtd_info *mtd)
487 {
488         struct nand_chip *chip = mtd_to_nand(mtd);
489         struct atmel_nand *nand = to_atmel_nand(chip);
490
491         return gpiod_get_value(nand->activecs->rb.gpio);
492 }
493
494 static void atmel_nand_select_chip(struct mtd_info *mtd, int cs)
495 {
496         struct nand_chip *chip = mtd_to_nand(mtd);
497         struct atmel_nand *nand = to_atmel_nand(chip);
498
499         if (cs < 0 || cs >= nand->numcs) {
500                 nand->activecs = NULL;
501                 chip->dev_ready = NULL;
502                 return;
503         }
504
505         nand->activecs = &nand->cs[cs];
506
507         if (nand->activecs->rb.type == ATMEL_NAND_GPIO_RB)
508                 chip->dev_ready = atmel_nand_dev_ready;
509 }
510
511 static int atmel_hsmc_nand_dev_ready(struct mtd_info *mtd)
512 {
513         struct nand_chip *chip = mtd_to_nand(mtd);
514         struct atmel_nand *nand = to_atmel_nand(chip);
515         struct atmel_hsmc_nand_controller *nc;
516         u32 status;
517
518         nc = to_hsmc_nand_controller(chip->controller);
519
520         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &status);
521
522         return status & ATMEL_HSMC_NFC_SR_RBEDGE(nand->activecs->rb.id);
523 }
524
525 static void atmel_hsmc_nand_select_chip(struct mtd_info *mtd, int cs)
526 {
527         struct nand_chip *chip = mtd_to_nand(mtd);
528         struct atmel_nand *nand = to_atmel_nand(chip);
529         struct atmel_hsmc_nand_controller *nc;
530
531         nc = to_hsmc_nand_controller(chip->controller);
532
533         atmel_nand_select_chip(mtd, cs);
534
535         if (!nand->activecs) {
536                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
537                              ATMEL_HSMC_NFC_CTRL_DIS);
538                 return;
539         }
540
541         if (nand->activecs->rb.type == ATMEL_NAND_NATIVE_RB)
542                 chip->dev_ready = atmel_hsmc_nand_dev_ready;
543
544         regmap_update_bits(nc->base.smc, ATMEL_HSMC_NFC_CFG,
545                            ATMEL_HSMC_NFC_CFG_PAGESIZE_MASK |
546                            ATMEL_HSMC_NFC_CFG_SPARESIZE_MASK |
547                            ATMEL_HSMC_NFC_CFG_RSPARE |
548                            ATMEL_HSMC_NFC_CFG_WSPARE,
549                            ATMEL_HSMC_NFC_CFG_PAGESIZE(mtd->writesize) |
550                            ATMEL_HSMC_NFC_CFG_SPARESIZE(mtd->oobsize) |
551                            ATMEL_HSMC_NFC_CFG_RSPARE);
552         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CTRL,
553                      ATMEL_HSMC_NFC_CTRL_EN);
554 }
555
556 static int atmel_nfc_exec_op(struct atmel_hsmc_nand_controller *nc, bool poll)
557 {
558         u8 *addrs = nc->op.addrs;
559         unsigned int op = 0;
560         u32 addr, val;
561         int i, ret;
562
563         nc->op.wait = ATMEL_HSMC_NFC_SR_CMDDONE;
564
565         for (i = 0; i < nc->op.ncmds; i++)
566                 op |= ATMEL_NFC_CMD(i, nc->op.cmds[i]);
567
568         if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
569                 regmap_write(nc->base.smc, ATMEL_HSMC_NFC_ADDR, *addrs++);
570
571         op |= ATMEL_NFC_CSID(nc->op.cs) |
572               ATMEL_NFC_ACYCLE(nc->op.naddrs);
573
574         if (nc->op.ncmds > 1)
575                 op |= ATMEL_NFC_VCMD2;
576
577         addr = addrs[0] | (addrs[1] << 8) | (addrs[2] << 16) |
578                (addrs[3] << 24);
579
580         if (nc->op.data != ATMEL_NFC_NO_DATA) {
581                 op |= ATMEL_NFC_DATAEN;
582                 nc->op.wait |= ATMEL_HSMC_NFC_SR_XFRDONE;
583
584                 if (nc->op.data == ATMEL_NFC_WRITE_DATA)
585                         op |= ATMEL_NFC_NFCWR;
586         }
587
588         /* Clear all flags. */
589         regmap_read(nc->base.smc, ATMEL_HSMC_NFC_SR, &val);
590
591         /* Send the command. */
592         regmap_write(nc->io, op, addr);
593
594         ret = atmel_nfc_wait(nc, poll, 0);
595         if (ret)
596                 dev_err(nc->base.dev,
597                         "Failed to send NAND command (err = %d)!",
598                         ret);
599
600         /* Reset the op state. */
601         memset(&nc->op, 0, sizeof(nc->op));
602
603         return ret;
604 }
605
606 static void atmel_hsmc_nand_cmd_ctrl(struct mtd_info *mtd, int dat,
607                                      unsigned int ctrl)
608 {
609         struct nand_chip *chip = mtd_to_nand(mtd);
610         struct atmel_nand *nand = to_atmel_nand(chip);
611         struct atmel_hsmc_nand_controller *nc;
612
613         nc = to_hsmc_nand_controller(chip->controller);
614
615         if (ctrl & NAND_ALE) {
616                 if (nc->op.naddrs == ATMEL_NFC_MAX_ADDR_CYCLES)
617                         return;
618
619                 nc->op.addrs[nc->op.naddrs++] = dat;
620         } else if (ctrl & NAND_CLE) {
621                 if (nc->op.ncmds > 1)
622                         return;
623
624                 nc->op.cmds[nc->op.ncmds++] = dat;
625         }
626
627         if (dat == NAND_CMD_NONE) {
628                 nc->op.cs = nand->activecs->id;
629                 atmel_nfc_exec_op(nc, true);
630         }
631 }
632
633 static void atmel_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
634                                 unsigned int ctrl)
635 {
636         struct nand_chip *chip = mtd_to_nand(mtd);
637         struct atmel_nand *nand = to_atmel_nand(chip);
638         struct atmel_nand_controller *nc;
639
640         nc = to_nand_controller(chip->controller);
641
642         if ((ctrl & NAND_CTRL_CHANGE) && nand->activecs->csgpio) {
643                 if (ctrl & NAND_NCE)
644                         gpiod_set_value(nand->activecs->csgpio, 0);
645                 else
646                         gpiod_set_value(nand->activecs->csgpio, 1);
647         }
648
649         if (ctrl & NAND_ALE)
650                 writeb(cmd, nand->activecs->io.virt + nc->caps->ale_offs);
651         else if (ctrl & NAND_CLE)
652                 writeb(cmd, nand->activecs->io.virt + nc->caps->cle_offs);
653 }
654
655 static void atmel_nfc_copy_to_sram(struct nand_chip *chip, const u8 *buf,
656                                    bool oob_required)
657 {
658         struct mtd_info *mtd = nand_to_mtd(chip);
659         struct atmel_hsmc_nand_controller *nc;
660         int ret = -EIO;
661
662         nc = to_hsmc_nand_controller(chip->controller);
663
664         if (nc->base.dmac)
665                 ret = atmel_nand_dma_transfer(&nc->base, (void *)buf,
666                                               nc->sram.dma, mtd->writesize,
667                                               DMA_TO_DEVICE);
668
669         /* Falling back to CPU copy. */
670         if (ret)
671                 memcpy_toio(nc->sram.virt, buf, mtd->writesize);
672
673         if (oob_required)
674                 memcpy_toio(nc->sram.virt + mtd->writesize, chip->oob_poi,
675                             mtd->oobsize);
676 }
677
678 static void atmel_nfc_copy_from_sram(struct nand_chip *chip, u8 *buf,
679                                      bool oob_required)
680 {
681         struct mtd_info *mtd = nand_to_mtd(chip);
682         struct atmel_hsmc_nand_controller *nc;
683         int ret = -EIO;
684
685         nc = to_hsmc_nand_controller(chip->controller);
686
687         if (nc->base.dmac)
688                 ret = atmel_nand_dma_transfer(&nc->base, buf, nc->sram.dma,
689                                               mtd->writesize, DMA_FROM_DEVICE);
690
691         /* Falling back to CPU copy. */
692         if (ret)
693                 memcpy_fromio(buf, nc->sram.virt, mtd->writesize);
694
695         if (oob_required)
696                 memcpy_fromio(chip->oob_poi, nc->sram.virt + mtd->writesize,
697                               mtd->oobsize);
698 }
699
700 static void atmel_nfc_set_op_addr(struct nand_chip *chip, int page, int column)
701 {
702         struct mtd_info *mtd = nand_to_mtd(chip);
703         struct atmel_hsmc_nand_controller *nc;
704
705         nc = to_hsmc_nand_controller(chip->controller);
706
707         if (column >= 0) {
708                 nc->op.addrs[nc->op.naddrs++] = column;
709
710                 /*
711                  * 2 address cycles for the column offset on large page NANDs.
712                  */
713                 if (mtd->writesize > 512)
714                         nc->op.addrs[nc->op.naddrs++] = column >> 8;
715         }
716
717         if (page >= 0) {
718                 nc->op.addrs[nc->op.naddrs++] = page;
719                 nc->op.addrs[nc->op.naddrs++] = page >> 8;
720
721                 if ((mtd->writesize > 512 && chip->chipsize > SZ_128M) ||
722                     (mtd->writesize <= 512 && chip->chipsize > SZ_32M))
723                         nc->op.addrs[nc->op.naddrs++] = page >> 16;
724         }
725 }
726
727 static int atmel_nand_pmecc_enable(struct nand_chip *chip, int op, bool raw)
728 {
729         struct atmel_nand *nand = to_atmel_nand(chip);
730         struct atmel_nand_controller *nc;
731         int ret;
732
733         nc = to_nand_controller(chip->controller);
734
735         if (raw)
736                 return 0;
737
738         ret = atmel_pmecc_enable(nand->pmecc, op);
739         if (ret)
740                 dev_err(nc->dev,
741                         "Failed to enable ECC engine (err = %d)\n", ret);
742
743         return ret;
744 }
745
746 static void atmel_nand_pmecc_disable(struct nand_chip *chip, bool raw)
747 {
748         struct atmel_nand *nand = to_atmel_nand(chip);
749
750         if (!raw)
751                 atmel_pmecc_disable(nand->pmecc);
752 }
753
754 static int atmel_nand_pmecc_generate_eccbytes(struct nand_chip *chip, bool raw)
755 {
756         struct atmel_nand *nand = to_atmel_nand(chip);
757         struct mtd_info *mtd = nand_to_mtd(chip);
758         struct atmel_nand_controller *nc;
759         struct mtd_oob_region oobregion;
760         void *eccbuf;
761         int ret, i;
762
763         nc = to_nand_controller(chip->controller);
764
765         if (raw)
766                 return 0;
767
768         ret = atmel_pmecc_wait_rdy(nand->pmecc);
769         if (ret) {
770                 dev_err(nc->dev,
771                         "Failed to transfer NAND page data (err = %d)\n",
772                         ret);
773                 return ret;
774         }
775
776         mtd_ooblayout_ecc(mtd, 0, &oobregion);
777         eccbuf = chip->oob_poi + oobregion.offset;
778
779         for (i = 0; i < chip->ecc.steps; i++) {
780                 atmel_pmecc_get_generated_eccbytes(nand->pmecc, i,
781                                                    eccbuf);
782                 eccbuf += chip->ecc.bytes;
783         }
784
785         return 0;
786 }
787
788 static int atmel_nand_pmecc_correct_data(struct nand_chip *chip, void *buf,
789                                          bool raw)
790 {
791         struct atmel_nand *nand = to_atmel_nand(chip);
792         struct mtd_info *mtd = nand_to_mtd(chip);
793         struct atmel_nand_controller *nc;
794         struct mtd_oob_region oobregion;
795         int ret, i, max_bitflips = 0;
796         void *databuf, *eccbuf;
797
798         nc = to_nand_controller(chip->controller);
799
800         if (raw)
801                 return 0;
802
803         ret = atmel_pmecc_wait_rdy(nand->pmecc);
804         if (ret) {
805                 dev_err(nc->dev,
806                         "Failed to read NAND page data (err = %d)\n",
807                         ret);
808                 return ret;
809         }
810
811         mtd_ooblayout_ecc(mtd, 0, &oobregion);
812         eccbuf = chip->oob_poi + oobregion.offset;
813         databuf = buf;
814
815         for (i = 0; i < chip->ecc.steps; i++) {
816                 ret = atmel_pmecc_correct_sector(nand->pmecc, i, databuf,
817                                                  eccbuf);
818                 if (ret < 0 && !atmel_pmecc_correct_erased_chunks(nand->pmecc))
819                         ret = nand_check_erased_ecc_chunk(databuf,
820                                                           chip->ecc.size,
821                                                           eccbuf,
822                                                           chip->ecc.bytes,
823                                                           NULL, 0,
824                                                           chip->ecc.strength);
825
826                 if (ret >= 0)
827                         max_bitflips = max(ret, max_bitflips);
828                 else
829                         mtd->ecc_stats.failed++;
830
831                 databuf += chip->ecc.size;
832                 eccbuf += chip->ecc.bytes;
833         }
834
835         return max_bitflips;
836 }
837
838 static int atmel_nand_pmecc_write_pg(struct nand_chip *chip, const u8 *buf,
839                                      bool oob_required, int page, bool raw)
840 {
841         struct mtd_info *mtd = nand_to_mtd(chip);
842         struct atmel_nand *nand = to_atmel_nand(chip);
843         int ret;
844
845         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
846         if (ret)
847                 return ret;
848
849         atmel_nand_write_buf(mtd, buf, mtd->writesize);
850
851         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
852         if (ret) {
853                 atmel_pmecc_disable(nand->pmecc);
854                 return ret;
855         }
856
857         atmel_nand_pmecc_disable(chip, raw);
858
859         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
860
861         return 0;
862 }
863
864 static int atmel_nand_pmecc_write_page(struct mtd_info *mtd,
865                                        struct nand_chip *chip, const u8 *buf,
866                                        int oob_required, int page)
867 {
868         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, false);
869 }
870
871 static int atmel_nand_pmecc_write_page_raw(struct mtd_info *mtd,
872                                            struct nand_chip *chip,
873                                            const u8 *buf, int oob_required,
874                                            int page)
875 {
876         return atmel_nand_pmecc_write_pg(chip, buf, oob_required, page, true);
877 }
878
879 static int atmel_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
880                                     bool oob_required, int page, bool raw)
881 {
882         struct mtd_info *mtd = nand_to_mtd(chip);
883         int ret;
884
885         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
886         if (ret)
887                 return ret;
888
889         atmel_nand_read_buf(mtd, buf, mtd->writesize);
890         atmel_nand_read_buf(mtd, chip->oob_poi, mtd->oobsize);
891
892         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
893
894         atmel_nand_pmecc_disable(chip, raw);
895
896         return ret;
897 }
898
899 static int atmel_nand_pmecc_read_page(struct mtd_info *mtd,
900                                       struct nand_chip *chip, u8 *buf,
901                                       int oob_required, int page)
902 {
903         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, false);
904 }
905
906 static int atmel_nand_pmecc_read_page_raw(struct mtd_info *mtd,
907                                           struct nand_chip *chip, u8 *buf,
908                                           int oob_required, int page)
909 {
910         return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page, true);
911 }
912
913 static int atmel_hsmc_nand_pmecc_write_pg(struct nand_chip *chip,
914                                           const u8 *buf, bool oob_required,
915                                           int page, bool raw)
916 {
917         struct mtd_info *mtd = nand_to_mtd(chip);
918         struct atmel_nand *nand = to_atmel_nand(chip);
919         struct atmel_hsmc_nand_controller *nc;
920         int ret;
921
922         nc = to_hsmc_nand_controller(chip->controller);
923
924         atmel_nfc_copy_to_sram(chip, buf, false);
925
926         nc->op.cmds[0] = NAND_CMD_SEQIN;
927         nc->op.ncmds = 1;
928         atmel_nfc_set_op_addr(chip, page, 0x0);
929         nc->op.cs = nand->activecs->id;
930         nc->op.data = ATMEL_NFC_WRITE_DATA;
931
932         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_WRITE, raw);
933         if (ret)
934                 return ret;
935
936         ret = atmel_nfc_exec_op(nc, false);
937         if (ret) {
938                 atmel_nand_pmecc_disable(chip, raw);
939                 dev_err(nc->base.dev,
940                         "Failed to transfer NAND page data (err = %d)\n",
941                         ret);
942                 return ret;
943         }
944
945         ret = atmel_nand_pmecc_generate_eccbytes(chip, raw);
946
947         atmel_nand_pmecc_disable(chip, raw);
948
949         if (ret)
950                 return ret;
951
952         atmel_nand_write_buf(mtd, chip->oob_poi, mtd->oobsize);
953
954         nc->op.cmds[0] = NAND_CMD_PAGEPROG;
955         nc->op.ncmds = 1;
956         nc->op.cs = nand->activecs->id;
957         ret = atmel_nfc_exec_op(nc, false);
958         if (ret)
959                 dev_err(nc->base.dev, "Failed to program NAND page (err = %d)\n",
960                         ret);
961
962         return ret;
963 }
964
965 static int atmel_hsmc_nand_pmecc_write_page(struct mtd_info *mtd,
966                                             struct nand_chip *chip,
967                                             const u8 *buf, int oob_required,
968                                             int page)
969 {
970         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
971                                               false);
972 }
973
974 static int atmel_hsmc_nand_pmecc_write_page_raw(struct mtd_info *mtd,
975                                                 struct nand_chip *chip,
976                                                 const u8 *buf,
977                                                 int oob_required, int page)
978 {
979         return atmel_hsmc_nand_pmecc_write_pg(chip, buf, oob_required, page,
980                                               true);
981 }
982
983 static int atmel_hsmc_nand_pmecc_read_pg(struct nand_chip *chip, u8 *buf,
984                                          bool oob_required, int page,
985                                          bool raw)
986 {
987         struct mtd_info *mtd = nand_to_mtd(chip);
988         struct atmel_nand *nand = to_atmel_nand(chip);
989         struct atmel_hsmc_nand_controller *nc;
990         int ret;
991
992         nc = to_hsmc_nand_controller(chip->controller);
993
994         /*
995          * Optimized read page accessors only work when the NAND R/B pin is
996          * connected to a native SoC R/B pin. If that's not the case, fallback
997          * to the non-optimized one.
998          */
999         if (nand->activecs->rb.type != ATMEL_NAND_NATIVE_RB) {
1000                 chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
1001
1002                 return atmel_nand_pmecc_read_pg(chip, buf, oob_required, page,
1003                                                 raw);
1004         }
1005
1006         nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READ0;
1007
1008         if (mtd->writesize > 512)
1009                 nc->op.cmds[nc->op.ncmds++] = NAND_CMD_READSTART;
1010
1011         atmel_nfc_set_op_addr(chip, page, 0x0);
1012         nc->op.cs = nand->activecs->id;
1013         nc->op.data = ATMEL_NFC_READ_DATA;
1014
1015         ret = atmel_nand_pmecc_enable(chip, NAND_ECC_READ, raw);
1016         if (ret)
1017                 return ret;
1018
1019         ret = atmel_nfc_exec_op(nc, false);
1020         if (ret) {
1021                 atmel_nand_pmecc_disable(chip, raw);
1022                 dev_err(nc->base.dev,
1023                         "Failed to load NAND page data (err = %d)\n",
1024                         ret);
1025                 return ret;
1026         }
1027
1028         atmel_nfc_copy_from_sram(chip, buf, true);
1029
1030         ret = atmel_nand_pmecc_correct_data(chip, buf, raw);
1031
1032         atmel_nand_pmecc_disable(chip, raw);
1033
1034         return ret;
1035 }
1036
1037 static int atmel_hsmc_nand_pmecc_read_page(struct mtd_info *mtd,
1038                                            struct nand_chip *chip, u8 *buf,
1039                                            int oob_required, int page)
1040 {
1041         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1042                                              false);
1043 }
1044
1045 static int atmel_hsmc_nand_pmecc_read_page_raw(struct mtd_info *mtd,
1046                                                struct nand_chip *chip,
1047                                                u8 *buf, int oob_required,
1048                                                int page)
1049 {
1050         return atmel_hsmc_nand_pmecc_read_pg(chip, buf, oob_required, page,
1051                                              true);
1052 }
1053
1054 static int atmel_nand_pmecc_init(struct nand_chip *chip)
1055 {
1056         struct mtd_info *mtd = nand_to_mtd(chip);
1057         struct atmel_nand *nand = to_atmel_nand(chip);
1058         struct atmel_nand_controller *nc;
1059         struct atmel_pmecc_user_req req;
1060
1061         nc = to_nand_controller(chip->controller);
1062
1063         if (!nc->pmecc) {
1064                 dev_err(nc->dev, "HW ECC not supported\n");
1065                 return -ENOTSUPP;
1066         }
1067
1068         if (nc->caps->legacy_of_bindings) {
1069                 u32 val;
1070
1071                 if (!of_property_read_u32(nc->dev->of_node, "atmel,pmecc-cap",
1072                                           &val))
1073                         chip->ecc.strength = val;
1074
1075                 if (!of_property_read_u32(nc->dev->of_node,
1076                                           "atmel,pmecc-sector-size",
1077                                           &val))
1078                         chip->ecc.size = val;
1079         }
1080
1081         if (chip->ecc.options & NAND_ECC_MAXIMIZE)
1082                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1083         else if (chip->ecc.strength)
1084                 req.ecc.strength = chip->ecc.strength;
1085         else if (chip->ecc_strength_ds)
1086                 req.ecc.strength = chip->ecc_strength_ds;
1087         else
1088                 req.ecc.strength = ATMEL_PMECC_MAXIMIZE_ECC_STRENGTH;
1089
1090         if (chip->ecc.size)
1091                 req.ecc.sectorsize = chip->ecc.size;
1092         else if (chip->ecc_step_ds)
1093                 req.ecc.sectorsize = chip->ecc_step_ds;
1094         else
1095                 req.ecc.sectorsize = ATMEL_PMECC_SECTOR_SIZE_AUTO;
1096
1097         req.pagesize = mtd->writesize;
1098         req.oobsize = mtd->oobsize;
1099
1100         if (mtd->writesize <= 512) {
1101                 req.ecc.bytes = 4;
1102                 req.ecc.ooboffset = 0;
1103         } else {
1104                 req.ecc.bytes = mtd->oobsize - 2;
1105                 req.ecc.ooboffset = ATMEL_PMECC_OOBOFFSET_AUTO;
1106         }
1107
1108         nand->pmecc = atmel_pmecc_create_user(nc->pmecc, &req);
1109         if (IS_ERR(nand->pmecc))
1110                 return PTR_ERR(nand->pmecc);
1111
1112         chip->ecc.algo = NAND_ECC_BCH;
1113         chip->ecc.size = req.ecc.sectorsize;
1114         chip->ecc.bytes = req.ecc.bytes / req.ecc.nsectors;
1115         chip->ecc.strength = req.ecc.strength;
1116
1117         chip->options |= NAND_NO_SUBPAGE_WRITE;
1118
1119         mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
1120
1121         return 0;
1122 }
1123
1124 static int atmel_nand_ecc_init(struct atmel_nand *nand)
1125 {
1126         struct nand_chip *chip = &nand->base;
1127         struct atmel_nand_controller *nc;
1128         int ret;
1129
1130         nc = to_nand_controller(chip->controller);
1131
1132         switch (chip->ecc.mode) {
1133         case NAND_ECC_NONE:
1134         case NAND_ECC_SOFT:
1135                 /*
1136                  * Nothing to do, the core will initialize everything for us.
1137                  */
1138                 break;
1139
1140         case NAND_ECC_HW:
1141                 ret = atmel_nand_pmecc_init(chip);
1142                 if (ret)
1143                         return ret;
1144
1145                 chip->ecc.read_page = atmel_nand_pmecc_read_page;
1146                 chip->ecc.write_page = atmel_nand_pmecc_write_page;
1147                 chip->ecc.read_page_raw = atmel_nand_pmecc_read_page_raw;
1148                 chip->ecc.write_page_raw = atmel_nand_pmecc_write_page_raw;
1149                 break;
1150
1151         default:
1152                 /* Other modes are not supported. */
1153                 dev_err(nc->dev, "Unsupported ECC mode: %d\n",
1154                         chip->ecc.mode);
1155                 return -ENOTSUPP;
1156         }
1157
1158         return 0;
1159 }
1160
1161 static int atmel_hsmc_nand_ecc_init(struct atmel_nand *nand)
1162 {
1163         struct nand_chip *chip = &nand->base;
1164         int ret;
1165
1166         ret = atmel_nand_ecc_init(nand);
1167         if (ret)
1168                 return ret;
1169
1170         if (chip->ecc.mode != NAND_ECC_HW)
1171                 return 0;
1172
1173         /* Adjust the ECC operations for the HSMC IP. */
1174         chip->ecc.read_page = atmel_hsmc_nand_pmecc_read_page;
1175         chip->ecc.write_page = atmel_hsmc_nand_pmecc_write_page;
1176         chip->ecc.read_page_raw = atmel_hsmc_nand_pmecc_read_page_raw;
1177         chip->ecc.write_page_raw = atmel_hsmc_nand_pmecc_write_page_raw;
1178         chip->ecc.options |= NAND_ECC_CUSTOM_PAGE_ACCESS;
1179
1180         return 0;
1181 }
1182
1183 static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
1184                                         const struct nand_data_interface *conf,
1185                                         struct atmel_smc_cs_conf *smcconf)
1186 {
1187         u32 ncycles, totalcycles, timeps, mckperiodps;
1188         struct atmel_nand_controller *nc;
1189         int ret;
1190
1191         nc = to_nand_controller(nand->base.controller);
1192
1193         /* DDR interface not supported. */
1194         if (conf->type != NAND_SDR_IFACE)
1195                 return -ENOTSUPP;
1196
1197         /*
1198          * tRC < 30ns implies EDO mode. This controller does not support this
1199          * mode.
1200          */
1201         if (conf->timings.sdr.tRC_min < 30)
1202                 return -ENOTSUPP;
1203
1204         atmel_smc_cs_conf_init(smcconf);
1205
1206         mckperiodps = NSEC_PER_SEC / clk_get_rate(nc->mck);
1207         mckperiodps *= 1000;
1208
1209         /*
1210          * Set write pulse timing. This one is easy to extract:
1211          *
1212          * NWE_PULSE = tWP
1213          */
1214         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWP_min, mckperiodps);
1215         totalcycles = ncycles;
1216         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NWE_SHIFT,
1217                                           ncycles);
1218         if (ret)
1219                 return ret;
1220
1221         /*
1222          * The write setup timing depends on the operation done on the NAND.
1223          * All operations goes through the same data bus, but the operation
1224          * type depends on the address we are writing to (ALE/CLE address
1225          * lines).
1226          * Since we have no way to differentiate the different operations at
1227          * the SMC level, we must consider the worst case (the biggest setup
1228          * time among all operation types):
1229          *
1230          * NWE_SETUP = max(tCLS, tCS, tALS, tDS) - NWE_PULSE
1231          */
1232         timeps = max3(conf->timings.sdr.tCLS_min, conf->timings.sdr.tCS_min,
1233                       conf->timings.sdr.tALS_min);
1234         timeps = max(timeps, conf->timings.sdr.tDS_min);
1235         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1236         ncycles = ncycles > totalcycles ? ncycles - totalcycles : 0;
1237         totalcycles += ncycles;
1238         ret = atmel_smc_cs_conf_set_setup(smcconf, ATMEL_SMC_NWE_SHIFT,
1239                                           ncycles);
1240         if (ret)
1241                 return ret;
1242
1243         /*
1244          * As for the write setup timing, the write hold timing depends on the
1245          * operation done on the NAND:
1246          *
1247          * NWE_HOLD = max(tCLH, tCH, tALH, tDH, tWH)
1248          */
1249         timeps = max3(conf->timings.sdr.tCLH_min, conf->timings.sdr.tCH_min,
1250                       conf->timings.sdr.tALH_min);
1251         timeps = max3(timeps, conf->timings.sdr.tDH_min,
1252                       conf->timings.sdr.tWH_min);
1253         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1254         totalcycles += ncycles;
1255
1256         /*
1257          * The write cycle timing is directly matching tWC, but is also
1258          * dependent on the other timings on the setup and hold timings we
1259          * calculated earlier, which gives:
1260          *
1261          * NWE_CYCLE = max(tWC, NWE_SETUP + NWE_PULSE + NWE_HOLD)
1262          */
1263         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWC_min, mckperiodps);
1264         ncycles = max(totalcycles, ncycles);
1265         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NWE_SHIFT,
1266                                           ncycles);
1267         if (ret)
1268                 return ret;
1269
1270         /*
1271          * We don't want the CS line to be toggled between each byte/word
1272          * transfer to the NAND. The only way to guarantee that is to have the
1273          * NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1274          *
1275          * NCS_WR_PULSE = NWE_CYCLE
1276          */
1277         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_WR_SHIFT,
1278                                           ncycles);
1279         if (ret)
1280                 return ret;
1281
1282         /*
1283          * As for the write setup timing, the read hold timing depends on the
1284          * operation done on the NAND:
1285          *
1286          * NRD_HOLD = max(tREH, tRHOH)
1287          */
1288         timeps = max(conf->timings.sdr.tREH_min, conf->timings.sdr.tRHOH_min);
1289         ncycles = DIV_ROUND_UP(timeps, mckperiodps);
1290         totalcycles = ncycles;
1291
1292         /*
1293          * TDF = tRHZ - NRD_HOLD
1294          */
1295         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRHZ_max, mckperiodps);
1296         ncycles -= totalcycles;
1297
1298         /*
1299          * In ONFI 4.0 specs, tRHZ has been increased to support EDO NANDs and
1300          * we might end up with a config that does not fit in the TDF field.
1301          * Just take the max value in this case and hope that the NAND is more
1302          * tolerant than advertised.
1303          */
1304         if (ncycles > ATMEL_SMC_MODE_TDF_MAX)
1305                 ncycles = ATMEL_SMC_MODE_TDF_MAX;
1306         else if (ncycles < ATMEL_SMC_MODE_TDF_MIN)
1307                 ncycles = ATMEL_SMC_MODE_TDF_MIN;
1308
1309         smcconf->mode |= ATMEL_SMC_MODE_TDF(ncycles) |
1310                          ATMEL_SMC_MODE_TDFMODE_OPTIMIZED;
1311
1312         /*
1313          * Read pulse timing directly matches tRP:
1314          *
1315          * NRD_PULSE = tRP
1316          */
1317         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRP_min, mckperiodps);
1318         totalcycles += ncycles;
1319         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NRD_SHIFT,
1320                                           ncycles);
1321         if (ret)
1322                 return ret;
1323
1324         /*
1325          * The write cycle timing is directly matching tWC, but is also
1326          * dependent on the setup and hold timings we calculated earlier,
1327          * which gives:
1328          *
1329          * NRD_CYCLE = max(tRC, NRD_PULSE + NRD_HOLD)
1330          *
1331          * NRD_SETUP is always 0.
1332          */
1333         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRC_min, mckperiodps);
1334         ncycles = max(totalcycles, ncycles);
1335         ret = atmel_smc_cs_conf_set_cycle(smcconf, ATMEL_SMC_NRD_SHIFT,
1336                                           ncycles);
1337         if (ret)
1338                 return ret;
1339
1340         /*
1341          * We don't want the CS line to be toggled between each byte/word
1342          * transfer from the NAND. The only way to guarantee that is to have
1343          * the NCS_{WR,RD}_{SETUP,HOLD} timings set to 0, which in turn means:
1344          *
1345          * NCS_RD_PULSE = NRD_CYCLE
1346          */
1347         ret = atmel_smc_cs_conf_set_pulse(smcconf, ATMEL_SMC_NCS_RD_SHIFT,
1348                                           ncycles);
1349         if (ret)
1350                 return ret;
1351
1352         /* Txxx timings are directly matching tXXX ones. */
1353         ncycles = DIV_ROUND_UP(conf->timings.sdr.tCLR_min, mckperiodps);
1354         ret = atmel_smc_cs_conf_set_timing(smcconf,
1355                                            ATMEL_HSMC_TIMINGS_TCLR_SHIFT,
1356                                            ncycles);
1357         if (ret)
1358                 return ret;
1359
1360         ncycles = DIV_ROUND_UP(conf->timings.sdr.tADL_min, mckperiodps);
1361         ret = atmel_smc_cs_conf_set_timing(smcconf,
1362                                            ATMEL_HSMC_TIMINGS_TADL_SHIFT,
1363                                            ncycles);
1364         if (ret)
1365                 return ret;
1366
1367         ncycles = DIV_ROUND_UP(conf->timings.sdr.tAR_min, mckperiodps);
1368         ret = atmel_smc_cs_conf_set_timing(smcconf,
1369                                            ATMEL_HSMC_TIMINGS_TAR_SHIFT,
1370                                            ncycles);
1371         if (ret)
1372                 return ret;
1373
1374         ncycles = DIV_ROUND_UP(conf->timings.sdr.tRR_min, mckperiodps);
1375         ret = atmel_smc_cs_conf_set_timing(smcconf,
1376                                            ATMEL_HSMC_TIMINGS_TRR_SHIFT,
1377                                            ncycles);
1378         if (ret)
1379                 return ret;
1380
1381         ncycles = DIV_ROUND_UP(conf->timings.sdr.tWB_max, mckperiodps);
1382         ret = atmel_smc_cs_conf_set_timing(smcconf,
1383                                            ATMEL_HSMC_TIMINGS_TWB_SHIFT,
1384                                            ncycles);
1385         if (ret)
1386                 return ret;
1387
1388         /* Attach the CS line to the NFC logic. */
1389         smcconf->timings |= ATMEL_HSMC_TIMINGS_NFSEL;
1390
1391         /* Set the appropriate data bus width. */
1392         if (nand->base.options & NAND_BUSWIDTH_16)
1393                 smcconf->mode |= ATMEL_SMC_MODE_DBW_16;
1394
1395         /* Operate in NRD/NWE READ/WRITEMODE. */
1396         smcconf->mode |= ATMEL_SMC_MODE_READMODE_NRD |
1397                          ATMEL_SMC_MODE_WRITEMODE_NWE;
1398
1399         return 0;
1400 }
1401
1402 static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
1403                                         int csline,
1404                                         const struct nand_data_interface *conf)
1405 {
1406         struct atmel_nand_controller *nc;
1407         struct atmel_smc_cs_conf smcconf;
1408         struct atmel_nand_cs *cs;
1409         int ret;
1410
1411         nc = to_nand_controller(nand->base.controller);
1412
1413         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1414         if (ret)
1415                 return ret;
1416
1417         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1418                 return 0;
1419
1420         cs = &nand->cs[csline];
1421         cs->smcconf = smcconf;
1422         atmel_smc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1423
1424         return 0;
1425 }
1426
1427 static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
1428                                         int csline,
1429                                         const struct nand_data_interface *conf)
1430 {
1431         struct atmel_nand_controller *nc;
1432         struct atmel_smc_cs_conf smcconf;
1433         struct atmel_nand_cs *cs;
1434         int ret;
1435
1436         nc = to_nand_controller(nand->base.controller);
1437
1438         ret = atmel_smc_nand_prepare_smcconf(nand, conf, &smcconf);
1439         if (ret)
1440                 return ret;
1441
1442         if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1443                 return 0;
1444
1445         cs = &nand->cs[csline];
1446         cs->smcconf = smcconf;
1447
1448         if (cs->rb.type == ATMEL_NAND_NATIVE_RB)
1449                 cs->smcconf.timings |= ATMEL_HSMC_TIMINGS_RBNSEL(cs->rb.id);
1450
1451         atmel_hsmc_cs_conf_apply(nc->smc, cs->id, &cs->smcconf);
1452
1453         return 0;
1454 }
1455
1456 static int atmel_nand_setup_data_interface(struct mtd_info *mtd, int csline,
1457                                         const struct nand_data_interface *conf)
1458 {
1459         struct nand_chip *chip = mtd_to_nand(mtd);
1460         struct atmel_nand *nand = to_atmel_nand(chip);
1461         struct atmel_nand_controller *nc;
1462
1463         nc = to_nand_controller(nand->base.controller);
1464
1465         if (csline >= nand->numcs ||
1466             (csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
1467                 return -EINVAL;
1468
1469         return nc->caps->ops->setup_data_interface(nand, csline, conf);
1470 }
1471
1472 static void atmel_nand_init(struct atmel_nand_controller *nc,
1473                             struct atmel_nand *nand)
1474 {
1475         struct nand_chip *chip = &nand->base;
1476         struct mtd_info *mtd = nand_to_mtd(chip);
1477
1478         mtd->dev.parent = nc->dev;
1479         nand->base.controller = &nc->base;
1480
1481         chip->cmd_ctrl = atmel_nand_cmd_ctrl;
1482         chip->read_byte = atmel_nand_read_byte;
1483         chip->read_word = atmel_nand_read_word;
1484         chip->write_byte = atmel_nand_write_byte;
1485         chip->read_buf = atmel_nand_read_buf;
1486         chip->write_buf = atmel_nand_write_buf;
1487         chip->select_chip = atmel_nand_select_chip;
1488
1489         if (nc->mck && nc->caps->ops->setup_data_interface)
1490                 chip->setup_data_interface = atmel_nand_setup_data_interface;
1491
1492         /* Some NANDs require a longer delay than the default one (20us). */
1493         chip->chip_delay = 40;
1494
1495         /*
1496          * Use a bounce buffer when the buffer passed by the MTD user is not
1497          * suitable for DMA.
1498          */
1499         if (nc->dmac)
1500                 chip->options |= NAND_USE_BOUNCE_BUFFER;
1501
1502         /* Default to HW ECC if pmecc is available. */
1503         if (nc->pmecc)
1504                 chip->ecc.mode = NAND_ECC_HW;
1505 }
1506
1507 static void atmel_smc_nand_init(struct atmel_nand_controller *nc,
1508                                 struct atmel_nand *nand)
1509 {
1510         struct nand_chip *chip = &nand->base;
1511         struct atmel_smc_nand_controller *smc_nc;
1512         int i;
1513
1514         atmel_nand_init(nc, nand);
1515
1516         smc_nc = to_smc_nand_controller(chip->controller);
1517         if (!smc_nc->matrix)
1518                 return;
1519
1520         /* Attach the CS to the NAND Flash logic. */
1521         for (i = 0; i < nand->numcs; i++)
1522                 regmap_update_bits(smc_nc->matrix, smc_nc->ebi_csa_offs,
1523                                    BIT(nand->cs[i].id), BIT(nand->cs[i].id));
1524 }
1525
1526 static void atmel_hsmc_nand_init(struct atmel_nand_controller *nc,
1527                                  struct atmel_nand *nand)
1528 {
1529         struct nand_chip *chip = &nand->base;
1530
1531         atmel_nand_init(nc, nand);
1532
1533         /* Overload some methods for the HSMC controller. */
1534         chip->cmd_ctrl = atmel_hsmc_nand_cmd_ctrl;
1535         chip->select_chip = atmel_hsmc_nand_select_chip;
1536 }
1537
1538 static int atmel_nand_detect(struct atmel_nand *nand)
1539 {
1540         struct nand_chip *chip = &nand->base;
1541         struct mtd_info *mtd = nand_to_mtd(chip);
1542         struct atmel_nand_controller *nc;
1543         int ret;
1544
1545         nc = to_nand_controller(chip->controller);
1546
1547         ret = nand_scan_ident(mtd, nand->numcs, NULL);
1548         if (ret)
1549                 dev_err(nc->dev, "nand_scan_ident() failed: %d\n", ret);
1550
1551         return ret;
1552 }
1553
1554 static int atmel_nand_unregister(struct atmel_nand *nand)
1555 {
1556         struct nand_chip *chip = &nand->base;
1557         struct mtd_info *mtd = nand_to_mtd(chip);
1558         int ret;
1559
1560         ret = mtd_device_unregister(mtd);
1561         if (ret)
1562                 return ret;
1563
1564         nand_cleanup(chip);
1565         list_del(&nand->node);
1566
1567         return 0;
1568 }
1569
1570 static int atmel_nand_register(struct atmel_nand *nand)
1571 {
1572         struct nand_chip *chip = &nand->base;
1573         struct mtd_info *mtd = nand_to_mtd(chip);
1574         struct atmel_nand_controller *nc;
1575         int ret;
1576
1577         nc = to_nand_controller(chip->controller);
1578
1579         if (nc->caps->legacy_of_bindings || !nc->dev->of_node) {
1580                 /*
1581                  * We keep the MTD name unchanged to avoid breaking platforms
1582                  * where the MTD cmdline parser is used and the bootloader
1583                  * has not been updated to use the new naming scheme.
1584                  */
1585                 mtd->name = "atmel_nand";
1586         } else if (!mtd->name) {
1587                 /*
1588                  * If the new bindings are used and the bootloader has not been
1589                  * updated to pass a new mtdparts parameter on the cmdline, you
1590                  * should define the following property in your nand node:
1591                  *
1592                  *      label = "atmel_nand";
1593                  *
1594                  * This way, mtd->name will be set by the core when
1595                  * nand_set_flash_node() is called.
1596                  */
1597                 mtd->name = devm_kasprintf(nc->dev, GFP_KERNEL,
1598                                            "%s:nand.%d", dev_name(nc->dev),
1599                                            nand->cs[0].id);
1600                 if (!mtd->name) {
1601                         dev_err(nc->dev, "Failed to allocate mtd->name\n");
1602                         return -ENOMEM;
1603                 }
1604         }
1605
1606         ret = nand_scan_tail(mtd);
1607         if (ret) {
1608                 dev_err(nc->dev, "nand_scan_tail() failed: %d\n", ret);
1609                 return ret;
1610         }
1611
1612         ret = mtd_device_register(mtd, NULL, 0);
1613         if (ret) {
1614                 dev_err(nc->dev, "Failed to register mtd device: %d\n", ret);
1615                 nand_cleanup(chip);
1616                 return ret;
1617         }
1618
1619         list_add_tail(&nand->node, &nc->chips);
1620
1621         return 0;
1622 }
1623
1624 static struct atmel_nand *atmel_nand_create(struct atmel_nand_controller *nc,
1625                                             struct device_node *np,
1626                                             int reg_cells)
1627 {
1628         struct atmel_nand *nand;
1629         struct gpio_desc *gpio;
1630         int numcs, ret, i;
1631
1632         numcs = of_property_count_elems_of_size(np, "reg",
1633                                                 reg_cells * sizeof(u32));
1634         if (numcs < 1) {
1635                 dev_err(nc->dev, "Missing or invalid reg property\n");
1636                 return ERR_PTR(-EINVAL);
1637         }
1638
1639         nand = devm_kzalloc(nc->dev,
1640                             sizeof(*nand) + (numcs * sizeof(*nand->cs)),
1641                             GFP_KERNEL);
1642         if (!nand) {
1643                 dev_err(nc->dev, "Failed to allocate NAND object\n");
1644                 return ERR_PTR(-ENOMEM);
1645         }
1646
1647         nand->numcs = numcs;
1648
1649         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "det", 0,
1650                                                       &np->fwnode, GPIOD_IN,
1651                                                       "nand-det");
1652         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1653                 dev_err(nc->dev,
1654                         "Failed to get detect gpio (err = %ld)\n",
1655                         PTR_ERR(gpio));
1656                 return ERR_CAST(gpio);
1657         }
1658
1659         if (!IS_ERR(gpio))
1660                 nand->cdgpio = gpio;
1661
1662         for (i = 0; i < numcs; i++) {
1663                 struct resource res;
1664                 u32 val;
1665
1666                 ret = of_address_to_resource(np, 0, &res);
1667                 if (ret) {
1668                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1669                                 ret);
1670                         return ERR_PTR(ret);
1671                 }
1672
1673                 ret = of_property_read_u32_index(np, "reg", i * reg_cells,
1674                                                  &val);
1675                 if (ret) {
1676                         dev_err(nc->dev, "Invalid reg property (err = %d)\n",
1677                                 ret);
1678                         return ERR_PTR(ret);
1679                 }
1680
1681                 nand->cs[i].id = val;
1682
1683                 nand->cs[i].io.dma = res.start;
1684                 nand->cs[i].io.virt = devm_ioremap_resource(nc->dev, &res);
1685                 if (IS_ERR(nand->cs[i].io.virt))
1686                         return ERR_CAST(nand->cs[i].io.virt);
1687
1688                 if (!of_property_read_u32(np, "atmel,rb", &val)) {
1689                         if (val > ATMEL_NFC_MAX_RB_ID)
1690                                 return ERR_PTR(-EINVAL);
1691
1692                         nand->cs[i].rb.type = ATMEL_NAND_NATIVE_RB;
1693                         nand->cs[i].rb.id = val;
1694                 } else {
1695                         gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev,
1696                                                         "rb", i, &np->fwnode,
1697                                                         GPIOD_IN, "nand-rb");
1698                         if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1699                                 dev_err(nc->dev,
1700                                         "Failed to get R/B gpio (err = %ld)\n",
1701                                         PTR_ERR(gpio));
1702                                 return ERR_CAST(gpio);
1703                         }
1704
1705                         if (!IS_ERR(gpio)) {
1706                                 nand->cs[i].rb.type = ATMEL_NAND_GPIO_RB;
1707                                 nand->cs[i].rb.gpio = gpio;
1708                         }
1709                 }
1710
1711                 gpio = devm_fwnode_get_index_gpiod_from_child(nc->dev, "cs",
1712                                                               i, &np->fwnode,
1713                                                               GPIOD_OUT_HIGH,
1714                                                               "nand-cs");
1715                 if (IS_ERR(gpio) && PTR_ERR(gpio) != -ENOENT) {
1716                         dev_err(nc->dev,
1717                                 "Failed to get CS gpio (err = %ld)\n",
1718                                 PTR_ERR(gpio));
1719                         return ERR_CAST(gpio);
1720                 }
1721
1722                 if (!IS_ERR(gpio))
1723                         nand->cs[i].csgpio = gpio;
1724         }
1725
1726         nand_set_flash_node(&nand->base, np);
1727
1728         return nand;
1729 }
1730
1731 static int
1732 atmel_nand_controller_add_nand(struct atmel_nand_controller *nc,
1733                                struct atmel_nand *nand)
1734 {
1735         int ret;
1736
1737         /* No card inserted, skip this NAND. */
1738         if (nand->cdgpio && gpiod_get_value(nand->cdgpio)) {
1739                 dev_info(nc->dev, "No SmartMedia card inserted.\n");
1740                 return 0;
1741         }
1742
1743         nc->caps->ops->nand_init(nc, nand);
1744
1745         ret = atmel_nand_detect(nand);
1746         if (ret)
1747                 return ret;
1748
1749         ret = nc->caps->ops->ecc_init(nand);
1750         if (ret)
1751                 return ret;
1752
1753         return atmel_nand_register(nand);
1754 }
1755
1756 static int
1757 atmel_nand_controller_remove_nands(struct atmel_nand_controller *nc)
1758 {
1759         struct atmel_nand *nand, *tmp;
1760         int ret;
1761
1762         list_for_each_entry_safe(nand, tmp, &nc->chips, node) {
1763                 ret = atmel_nand_unregister(nand);
1764                 if (ret)
1765                         return ret;
1766         }
1767
1768         return 0;
1769 }
1770
1771 static int
1772 atmel_nand_controller_legacy_add_nands(struct atmel_nand_controller *nc)
1773 {
1774         struct device *dev = nc->dev;
1775         struct platform_device *pdev = to_platform_device(dev);
1776         struct atmel_nand *nand;
1777         struct gpio_desc *gpio;
1778         struct resource *res;
1779
1780         /*
1781          * Legacy bindings only allow connecting a single NAND with a unique CS
1782          * line to the controller.
1783          */
1784         nand = devm_kzalloc(nc->dev, sizeof(*nand) + sizeof(*nand->cs),
1785                             GFP_KERNEL);
1786         if (!nand)
1787                 return -ENOMEM;
1788
1789         nand->numcs = 1;
1790
1791         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1792         nand->cs[0].io.virt = devm_ioremap_resource(dev, res);
1793         if (IS_ERR(nand->cs[0].io.virt))
1794                 return PTR_ERR(nand->cs[0].io.virt);
1795
1796         nand->cs[0].io.dma = res->start;
1797
1798         /*
1799          * The old driver was hardcoding the CS id to 3 for all sama5
1800          * controllers. Since this id is only meaningful for the sama5
1801          * controller we can safely assign this id to 3 no matter the
1802          * controller.
1803          * If one wants to connect a NAND to a different CS line, he will
1804          * have to use the new bindings.
1805          */
1806         nand->cs[0].id = 3;
1807
1808         /* R/B GPIO. */
1809         gpio = devm_gpiod_get_index_optional(dev, NULL, 0,  GPIOD_IN);
1810         if (IS_ERR(gpio)) {
1811                 dev_err(dev, "Failed to get R/B gpio (err = %ld)\n",
1812                         PTR_ERR(gpio));
1813                 return PTR_ERR(gpio);
1814         }
1815
1816         if (gpio) {
1817                 nand->cs[0].rb.type = ATMEL_NAND_GPIO_RB;
1818                 nand->cs[0].rb.gpio = gpio;
1819         }
1820
1821         /* CS GPIO. */
1822         gpio = devm_gpiod_get_index_optional(dev, NULL, 1, GPIOD_OUT_HIGH);
1823         if (IS_ERR(gpio)) {
1824                 dev_err(dev, "Failed to get CS gpio (err = %ld)\n",
1825                         PTR_ERR(gpio));
1826                 return PTR_ERR(gpio);
1827         }
1828
1829         nand->cs[0].csgpio = gpio;
1830
1831         /* Card detect GPIO. */
1832         gpio = devm_gpiod_get_index_optional(nc->dev, NULL, 2, GPIOD_IN);
1833         if (IS_ERR(gpio)) {
1834                 dev_err(dev,
1835                         "Failed to get detect gpio (err = %ld)\n",
1836                         PTR_ERR(gpio));
1837                 return PTR_ERR(gpio);
1838         }
1839
1840         nand->cdgpio = gpio;
1841
1842         nand_set_flash_node(&nand->base, nc->dev->of_node);
1843
1844         return atmel_nand_controller_add_nand(nc, nand);
1845 }
1846
1847 static int atmel_nand_controller_add_nands(struct atmel_nand_controller *nc)
1848 {
1849         struct device_node *np, *nand_np;
1850         struct device *dev = nc->dev;
1851         int ret, reg_cells;
1852         u32 val;
1853
1854         /* We do not retrieve the SMC syscon when parsing old DTs. */
1855         if (nc->caps->legacy_of_bindings)
1856                 return atmel_nand_controller_legacy_add_nands(nc);
1857
1858         np = dev->of_node;
1859
1860         ret = of_property_read_u32(np, "#address-cells", &val);
1861         if (ret) {
1862                 dev_err(dev, "missing #address-cells property\n");
1863                 return ret;
1864         }
1865
1866         reg_cells = val;
1867
1868         ret = of_property_read_u32(np, "#size-cells", &val);
1869         if (ret) {
1870                 dev_err(dev, "missing #address-cells property\n");
1871                 return ret;
1872         }
1873
1874         reg_cells += val;
1875
1876         for_each_child_of_node(np, nand_np) {
1877                 struct atmel_nand *nand;
1878
1879                 nand = atmel_nand_create(nc, nand_np, reg_cells);
1880                 if (IS_ERR(nand)) {
1881                         ret = PTR_ERR(nand);
1882                         goto err;
1883                 }
1884
1885                 ret = atmel_nand_controller_add_nand(nc, nand);
1886                 if (ret)
1887                         goto err;
1888         }
1889
1890         return 0;
1891
1892 err:
1893         atmel_nand_controller_remove_nands(nc);
1894
1895         return ret;
1896 }
1897
1898 static void atmel_nand_controller_cleanup(struct atmel_nand_controller *nc)
1899 {
1900         if (nc->dmac)
1901                 dma_release_channel(nc->dmac);
1902
1903         clk_put(nc->mck);
1904 }
1905
1906 static const struct of_device_id atmel_matrix_of_ids[] = {
1907         {
1908                 .compatible = "atmel,at91sam9260-matrix",
1909                 .data = (void *)AT91SAM9260_MATRIX_EBICSA,
1910         },
1911         {
1912                 .compatible = "atmel,at91sam9261-matrix",
1913                 .data = (void *)AT91SAM9261_MATRIX_EBICSA,
1914         },
1915         {
1916                 .compatible = "atmel,at91sam9263-matrix",
1917                 .data = (void *)AT91SAM9263_MATRIX_EBI0CSA,
1918         },
1919         {
1920                 .compatible = "atmel,at91sam9rl-matrix",
1921                 .data = (void *)AT91SAM9RL_MATRIX_EBICSA,
1922         },
1923         {
1924                 .compatible = "atmel,at91sam9g45-matrix",
1925                 .data = (void *)AT91SAM9G45_MATRIX_EBICSA,
1926         },
1927         {
1928                 .compatible = "atmel,at91sam9n12-matrix",
1929                 .data = (void *)AT91SAM9N12_MATRIX_EBICSA,
1930         },
1931         {
1932                 .compatible = "atmel,at91sam9x5-matrix",
1933                 .data = (void *)AT91SAM9X5_MATRIX_EBICSA,
1934         },
1935         { /* sentinel */ },
1936 };
1937
1938 static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
1939                                 struct platform_device *pdev,
1940                                 const struct atmel_nand_controller_caps *caps)
1941 {
1942         struct device *dev = &pdev->dev;
1943         struct device_node *np = dev->of_node;
1944         int ret;
1945
1946         nand_hw_control_init(&nc->base);
1947         INIT_LIST_HEAD(&nc->chips);
1948         nc->dev = dev;
1949         nc->caps = caps;
1950
1951         platform_set_drvdata(pdev, nc);
1952
1953         nc->pmecc = devm_atmel_pmecc_get(dev);
1954         if (IS_ERR(nc->pmecc)) {
1955                 ret = PTR_ERR(nc->pmecc);
1956                 if (ret != -EPROBE_DEFER)
1957                         dev_err(dev, "Could not get PMECC object (err = %d)\n",
1958                                 ret);
1959                 return ret;
1960         }
1961
1962         if (nc->caps->has_dma) {
1963                 dma_cap_mask_t mask;
1964
1965                 dma_cap_zero(mask);
1966                 dma_cap_set(DMA_MEMCPY, mask);
1967
1968                 nc->dmac = dma_request_channel(mask, NULL, NULL);
1969                 if (!nc->dmac)
1970                         dev_err(nc->dev, "Failed to request DMA channel\n");
1971         }
1972
1973         /* We do not retrieve the SMC syscon when parsing old DTs. */
1974         if (nc->caps->legacy_of_bindings)
1975                 return 0;
1976
1977         nc->mck = of_clk_get(dev->parent->of_node, 0);
1978         if (IS_ERR(nc->mck)) {
1979                 dev_err(dev, "Failed to retrieve MCK clk\n");
1980                 return PTR_ERR(nc->mck);
1981         }
1982
1983         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
1984         if (!np) {
1985                 dev_err(dev, "Missing or invalid atmel,smc property\n");
1986                 return -EINVAL;
1987         }
1988
1989         nc->smc = syscon_node_to_regmap(np);
1990         of_node_put(np);
1991         if (IS_ERR(nc->smc)) {
1992                 ret = PTR_ERR(nc->smc);
1993                 dev_err(dev, "Could not get SMC regmap (err = %d)\n", ret);
1994                 return ret;
1995         }
1996
1997         return 0;
1998 }
1999
2000 static int
2001 atmel_smc_nand_controller_init(struct atmel_smc_nand_controller *nc)
2002 {
2003         struct device *dev = nc->base.dev;
2004         const struct of_device_id *match;
2005         struct device_node *np;
2006         int ret;
2007
2008         /* We do not retrieve the matrix syscon when parsing old DTs. */
2009         if (nc->base.caps->legacy_of_bindings)
2010                 return 0;
2011
2012         np = of_parse_phandle(dev->parent->of_node, "atmel,matrix", 0);
2013         if (!np)
2014                 return 0;
2015
2016         match = of_match_node(atmel_matrix_of_ids, np);
2017         if (!match) {
2018                 of_node_put(np);
2019                 return 0;
2020         }
2021
2022         nc->matrix = syscon_node_to_regmap(np);
2023         of_node_put(np);
2024         if (IS_ERR(nc->matrix)) {
2025                 ret = PTR_ERR(nc->matrix);
2026                 dev_err(dev, "Could not get Matrix regmap (err = %d)\n", ret);
2027                 return ret;
2028         }
2029
2030         nc->ebi_csa_offs = (unsigned int)match->data;
2031
2032         /*
2033          * The at91sam9263 has 2 EBIs, if the NAND controller is under EBI1
2034          * add 4 to ->ebi_csa_offs.
2035          */
2036         if (of_device_is_compatible(dev->parent->of_node,
2037                                     "atmel,at91sam9263-ebi1"))
2038                 nc->ebi_csa_offs += 4;
2039
2040         return 0;
2041 }
2042
2043 static int
2044 atmel_hsmc_nand_controller_legacy_init(struct atmel_hsmc_nand_controller *nc)
2045 {
2046         struct regmap_config regmap_conf = {
2047                 .reg_bits = 32,
2048                 .val_bits = 32,
2049                 .reg_stride = 4,
2050         };
2051
2052         struct device *dev = nc->base.dev;
2053         struct device_node *nand_np, *nfc_np;
2054         void __iomem *iomem;
2055         struct resource res;
2056         int ret;
2057
2058         nand_np = dev->of_node;
2059         nfc_np = of_find_compatible_node(dev->of_node, NULL,
2060                                          "atmel,sama5d3-nfc");
2061
2062         nc->clk = of_clk_get(nfc_np, 0);
2063         if (IS_ERR(nc->clk)) {
2064                 ret = PTR_ERR(nc->clk);
2065                 dev_err(dev, "Failed to retrieve HSMC clock (err = %d)\n",
2066                         ret);
2067                 goto out;
2068         }
2069
2070         ret = clk_prepare_enable(nc->clk);
2071         if (ret) {
2072                 dev_err(dev, "Failed to enable the HSMC clock (err = %d)\n",
2073                         ret);
2074                 goto out;
2075         }
2076
2077         nc->irq = of_irq_get(nand_np, 0);
2078         if (nc->irq < 0) {
2079                 ret = nc->irq;
2080                 if (ret != -EPROBE_DEFER)
2081                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2082                                 ret);
2083                 goto out;
2084         }
2085
2086         ret = of_address_to_resource(nfc_np, 0, &res);
2087         if (ret) {
2088                 dev_err(dev, "Invalid or missing NFC IO resource (err = %d)\n",
2089                         ret);
2090                 goto out;
2091         }
2092
2093         iomem = devm_ioremap_resource(dev, &res);
2094         if (IS_ERR(iomem)) {
2095                 ret = PTR_ERR(iomem);
2096                 goto out;
2097         }
2098
2099         regmap_conf.name = "nfc-io";
2100         regmap_conf.max_register = resource_size(&res) - 4;
2101         nc->io = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2102         if (IS_ERR(nc->io)) {
2103                 ret = PTR_ERR(nc->io);
2104                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2105                         ret);
2106                 goto out;
2107         }
2108
2109         ret = of_address_to_resource(nfc_np, 1, &res);
2110         if (ret) {
2111                 dev_err(dev, "Invalid or missing HSMC resource (err = %d)\n",
2112                         ret);
2113                 goto out;
2114         }
2115
2116         iomem = devm_ioremap_resource(dev, &res);
2117         if (IS_ERR(iomem)) {
2118                 ret = PTR_ERR(iomem);
2119                 goto out;
2120         }
2121
2122         regmap_conf.name = "smc";
2123         regmap_conf.max_register = resource_size(&res) - 4;
2124         nc->base.smc = devm_regmap_init_mmio(dev, iomem, &regmap_conf);
2125         if (IS_ERR(nc->base.smc)) {
2126                 ret = PTR_ERR(nc->base.smc);
2127                 dev_err(dev, "Could not create NFC IO regmap (err = %d)\n",
2128                         ret);
2129                 goto out;
2130         }
2131
2132         ret = of_address_to_resource(nfc_np, 2, &res);
2133         if (ret) {
2134                 dev_err(dev, "Invalid or missing SRAM resource (err = %d)\n",
2135                         ret);
2136                 goto out;
2137         }
2138
2139         nc->sram.virt = devm_ioremap_resource(dev, &res);
2140         if (IS_ERR(nc->sram.virt)) {
2141                 ret = PTR_ERR(nc->sram.virt);
2142                 goto out;
2143         }
2144
2145         nc->sram.dma = res.start;
2146
2147 out:
2148         of_node_put(nfc_np);
2149
2150         return ret;
2151 }
2152
2153 static int
2154 atmel_hsmc_nand_controller_init(struct atmel_hsmc_nand_controller *nc)
2155 {
2156         struct device *dev = nc->base.dev;
2157         struct device_node *np;
2158         int ret;
2159
2160         np = of_parse_phandle(dev->parent->of_node, "atmel,smc", 0);
2161         if (!np) {
2162                 dev_err(dev, "Missing or invalid atmel,smc property\n");
2163                 return -EINVAL;
2164         }
2165
2166         nc->irq = of_irq_get(np, 0);
2167         of_node_put(np);
2168         if (nc->irq < 0) {
2169                 if (nc->irq != -EPROBE_DEFER)
2170                         dev_err(dev, "Failed to get IRQ number (err = %d)\n",
2171                                 nc->irq);
2172                 return nc->irq;
2173         }
2174
2175         np = of_parse_phandle(dev->of_node, "atmel,nfc-io", 0);
2176         if (!np) {
2177                 dev_err(dev, "Missing or invalid atmel,nfc-io property\n");
2178                 return -EINVAL;
2179         }
2180
2181         nc->io = syscon_node_to_regmap(np);
2182         of_node_put(np);
2183         if (IS_ERR(nc->io)) {
2184                 ret = PTR_ERR(nc->io);
2185                 dev_err(dev, "Could not get NFC IO regmap (err = %d)\n", ret);
2186                 return ret;
2187         }
2188
2189         nc->sram.pool = of_gen_pool_get(nc->base.dev->of_node,
2190                                          "atmel,nfc-sram", 0);
2191         if (!nc->sram.pool) {
2192                 dev_err(nc->base.dev, "Missing SRAM\n");
2193                 return -ENOMEM;
2194         }
2195
2196         nc->sram.virt = gen_pool_dma_alloc(nc->sram.pool,
2197                                             ATMEL_NFC_SRAM_SIZE,
2198                                             &nc->sram.dma);
2199         if (!nc->sram.virt) {
2200                 dev_err(nc->base.dev,
2201                         "Could not allocate memory from the NFC SRAM pool\n");
2202                 return -ENOMEM;
2203         }
2204
2205         return 0;
2206 }
2207
2208 static int
2209 atmel_hsmc_nand_controller_remove(struct atmel_nand_controller *nc)
2210 {
2211         struct atmel_hsmc_nand_controller *hsmc_nc;
2212         int ret;
2213
2214         ret = atmel_nand_controller_remove_nands(nc);
2215         if (ret)
2216                 return ret;
2217
2218         hsmc_nc = container_of(nc, struct atmel_hsmc_nand_controller, base);
2219         if (hsmc_nc->sram.pool)
2220                 gen_pool_free(hsmc_nc->sram.pool,
2221                               (unsigned long)hsmc_nc->sram.virt,
2222                               ATMEL_NFC_SRAM_SIZE);
2223
2224         if (hsmc_nc->clk) {
2225                 clk_disable_unprepare(hsmc_nc->clk);
2226                 clk_put(hsmc_nc->clk);
2227         }
2228
2229         atmel_nand_controller_cleanup(nc);
2230
2231         return 0;
2232 }
2233
2234 static int atmel_hsmc_nand_controller_probe(struct platform_device *pdev,
2235                                 const struct atmel_nand_controller_caps *caps)
2236 {
2237         struct device *dev = &pdev->dev;
2238         struct atmel_hsmc_nand_controller *nc;
2239         int ret;
2240
2241         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2242         if (!nc)
2243                 return -ENOMEM;
2244
2245         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2246         if (ret)
2247                 return ret;
2248
2249         if (caps->legacy_of_bindings)
2250                 ret = atmel_hsmc_nand_controller_legacy_init(nc);
2251         else
2252                 ret = atmel_hsmc_nand_controller_init(nc);
2253
2254         if (ret)
2255                 return ret;
2256
2257         /* Make sure all irqs are masked before registering our IRQ handler. */
2258         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_IDR, 0xffffffff);
2259         ret = devm_request_irq(dev, nc->irq, atmel_nfc_interrupt,
2260                                IRQF_SHARED, "nfc", nc);
2261         if (ret) {
2262                 dev_err(dev,
2263                         "Could not get register NFC interrupt handler (err = %d)\n",
2264                         ret);
2265                 goto err;
2266         }
2267
2268         /* Initial NFC configuration. */
2269         regmap_write(nc->base.smc, ATMEL_HSMC_NFC_CFG,
2270                      ATMEL_HSMC_NFC_CFG_DTO_MAX);
2271
2272         ret = atmel_nand_controller_add_nands(&nc->base);
2273         if (ret)
2274                 goto err;
2275
2276         return 0;
2277
2278 err:
2279         atmel_hsmc_nand_controller_remove(&nc->base);
2280
2281         return ret;
2282 }
2283
2284 static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
2285         .probe = atmel_hsmc_nand_controller_probe,
2286         .remove = atmel_hsmc_nand_controller_remove,
2287         .ecc_init = atmel_hsmc_nand_ecc_init,
2288         .nand_init = atmel_hsmc_nand_init,
2289         .setup_data_interface = atmel_hsmc_nand_setup_data_interface,
2290 };
2291
2292 static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
2293         .has_dma = true,
2294         .ale_offs = BIT(21),
2295         .cle_offs = BIT(22),
2296         .ops = &atmel_hsmc_nc_ops,
2297 };
2298
2299 /* Only used to parse old bindings. */
2300 static const struct atmel_nand_controller_caps atmel_sama5_nand_caps = {
2301         .has_dma = true,
2302         .ale_offs = BIT(21),
2303         .cle_offs = BIT(22),
2304         .ops = &atmel_hsmc_nc_ops,
2305         .legacy_of_bindings = true,
2306 };
2307
2308 static int atmel_smc_nand_controller_probe(struct platform_device *pdev,
2309                                 const struct atmel_nand_controller_caps *caps)
2310 {
2311         struct device *dev = &pdev->dev;
2312         struct atmel_smc_nand_controller *nc;
2313         int ret;
2314
2315         nc = devm_kzalloc(dev, sizeof(*nc), GFP_KERNEL);
2316         if (!nc)
2317                 return -ENOMEM;
2318
2319         ret = atmel_nand_controller_init(&nc->base, pdev, caps);
2320         if (ret)
2321                 return ret;
2322
2323         ret = atmel_smc_nand_controller_init(nc);
2324         if (ret)
2325                 return ret;
2326
2327         return atmel_nand_controller_add_nands(&nc->base);
2328 }
2329
2330 static int
2331 atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
2332 {
2333         int ret;
2334
2335         ret = atmel_nand_controller_remove_nands(nc);
2336         if (ret)
2337                 return ret;
2338
2339         atmel_nand_controller_cleanup(nc);
2340
2341         return 0;
2342 }
2343
2344 /*
2345  * The SMC reg layout of at91rm9200 is completely different which prevents us
2346  * from re-using atmel_smc_nand_setup_data_interface() for the
2347  * ->setup_data_interface() hook.
2348  * At this point, there's no support for the at91rm9200 SMC IP, so we leave
2349  * ->setup_data_interface() unassigned.
2350  */
2351 static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
2352         .probe = atmel_smc_nand_controller_probe,
2353         .remove = atmel_smc_nand_controller_remove,
2354         .ecc_init = atmel_nand_ecc_init,
2355         .nand_init = atmel_smc_nand_init,
2356 };
2357
2358 static const struct atmel_nand_controller_caps atmel_rm9200_nc_caps = {
2359         .ale_offs = BIT(21),
2360         .cle_offs = BIT(22),
2361         .ops = &at91rm9200_nc_ops,
2362 };
2363
2364 static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
2365         .probe = atmel_smc_nand_controller_probe,
2366         .remove = atmel_smc_nand_controller_remove,
2367         .ecc_init = atmel_nand_ecc_init,
2368         .nand_init = atmel_smc_nand_init,
2369         .setup_data_interface = atmel_smc_nand_setup_data_interface,
2370 };
2371
2372 static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
2373         .ale_offs = BIT(21),
2374         .cle_offs = BIT(22),
2375         .ops = &atmel_smc_nc_ops,
2376 };
2377
2378 static const struct atmel_nand_controller_caps atmel_sam9261_nc_caps = {
2379         .ale_offs = BIT(22),
2380         .cle_offs = BIT(21),
2381         .ops = &atmel_smc_nc_ops,
2382 };
2383
2384 static const struct atmel_nand_controller_caps atmel_sam9g45_nc_caps = {
2385         .has_dma = true,
2386         .ale_offs = BIT(21),
2387         .cle_offs = BIT(22),
2388         .ops = &atmel_smc_nc_ops,
2389 };
2390
2391 /* Only used to parse old bindings. */
2392 static const struct atmel_nand_controller_caps atmel_rm9200_nand_caps = {
2393         .ale_offs = BIT(21),
2394         .cle_offs = BIT(22),
2395         .ops = &atmel_smc_nc_ops,
2396         .legacy_of_bindings = true,
2397 };
2398
2399 static const struct atmel_nand_controller_caps atmel_sam9261_nand_caps = {
2400         .ale_offs = BIT(22),
2401         .cle_offs = BIT(21),
2402         .ops = &atmel_smc_nc_ops,
2403         .legacy_of_bindings = true,
2404 };
2405
2406 static const struct atmel_nand_controller_caps atmel_sam9g45_nand_caps = {
2407         .has_dma = true,
2408         .ale_offs = BIT(21),
2409         .cle_offs = BIT(22),
2410         .ops = &atmel_smc_nc_ops,
2411         .legacy_of_bindings = true,
2412 };
2413
2414 static const struct of_device_id atmel_nand_controller_of_ids[] = {
2415         {
2416                 .compatible = "atmel,at91rm9200-nand-controller",
2417                 .data = &atmel_rm9200_nc_caps,
2418         },
2419         {
2420                 .compatible = "atmel,at91sam9260-nand-controller",
2421                 .data = &atmel_sam9260_nc_caps,
2422         },
2423         {
2424                 .compatible = "atmel,at91sam9261-nand-controller",
2425                 .data = &atmel_sam9261_nc_caps,
2426         },
2427         {
2428                 .compatible = "atmel,at91sam9g45-nand-controller",
2429                 .data = &atmel_sam9g45_nc_caps,
2430         },
2431         {
2432                 .compatible = "atmel,sama5d3-nand-controller",
2433                 .data = &atmel_sama5_nc_caps,
2434         },
2435         /* Support for old/deprecated bindings: */
2436         {
2437                 .compatible = "atmel,at91rm9200-nand",
2438                 .data = &atmel_rm9200_nand_caps,
2439         },
2440         {
2441                 .compatible = "atmel,sama5d4-nand",
2442                 .data = &atmel_rm9200_nand_caps,
2443         },
2444         {
2445                 .compatible = "atmel,sama5d2-nand",
2446                 .data = &atmel_rm9200_nand_caps,
2447         },
2448         { /* sentinel */ },
2449 };
2450 MODULE_DEVICE_TABLE(of, atmel_nand_controller_of_ids);
2451
2452 static int atmel_nand_controller_probe(struct platform_device *pdev)
2453 {
2454         const struct atmel_nand_controller_caps *caps;
2455
2456         if (pdev->id_entry)
2457                 caps = (void *)pdev->id_entry->driver_data;
2458         else
2459                 caps = of_device_get_match_data(&pdev->dev);
2460
2461         if (!caps) {
2462                 dev_err(&pdev->dev, "Could not retrieve NFC caps\n");
2463                 return -EINVAL;
2464         }
2465
2466         if (caps->legacy_of_bindings) {
2467                 u32 ale_offs = 21;
2468
2469                 /*
2470                  * If we are parsing legacy DT props and the DT contains a
2471                  * valid NFC node, forward the request to the sama5 logic.
2472                  */
2473                 if (of_find_compatible_node(pdev->dev.of_node, NULL,
2474                                             "atmel,sama5d3-nfc"))
2475                         caps = &atmel_sama5_nand_caps;
2476
2477                 /*
2478                  * Even if the compatible says we are dealing with an
2479                  * at91rm9200 controller, the atmel,nand-has-dma specify that
2480                  * this controller supports DMA, which means we are in fact
2481                  * dealing with an at91sam9g45+ controller.
2482                  */
2483                 if (!caps->has_dma &&
2484                     of_property_read_bool(pdev->dev.of_node,
2485                                           "atmel,nand-has-dma"))
2486                         caps = &atmel_sam9g45_nand_caps;
2487
2488                 /*
2489                  * All SoCs except the at91sam9261 are assigning ALE to A21 and
2490                  * CLE to A22. If atmel,nand-addr-offset != 21 this means we're
2491                  * actually dealing with an at91sam9261 controller.
2492                  */
2493                 of_property_read_u32(pdev->dev.of_node,
2494                                      "atmel,nand-addr-offset", &ale_offs);
2495                 if (ale_offs != 21)
2496                         caps = &atmel_sam9261_nand_caps;
2497         }
2498
2499         return caps->ops->probe(pdev, caps);
2500 }
2501
2502 static int atmel_nand_controller_remove(struct platform_device *pdev)
2503 {
2504         struct atmel_nand_controller *nc = platform_get_drvdata(pdev);
2505
2506         return nc->caps->ops->remove(nc);
2507 }
2508
2509 static struct platform_driver atmel_nand_controller_driver = {
2510         .driver = {
2511                 .name = "atmel-nand-controller",
2512                 .of_match_table = of_match_ptr(atmel_nand_controller_of_ids),
2513         },
2514         .probe = atmel_nand_controller_probe,
2515         .remove = atmel_nand_controller_remove,
2516 };
2517 module_platform_driver(atmel_nand_controller_driver);
2518
2519 MODULE_LICENSE("GPL");
2520 MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
2521 MODULE_DESCRIPTION("NAND Flash Controller driver for Atmel SoCs");
2522 MODULE_ALIAS("platform:atmel-nand-controller");