drivers/mtd/nand/denali.h

   1 /*
   2  * NAND Flash Controller Device Driver
   3  * Copyright (c) 2009 - 2010, Intel Corporation and its suppliers.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17  *
  18  */
  19
  20 #ifndef __DENALI_H__
  21 #define __DENALI_H__
  22
  23 #include <linux/bitops.h>
  24 #include <linux/mtd/nand.h>
  25
  26 #define DEVICE_RESET                            0x0
  27 #define     DEVICE_RESET__BANK0                         0x0001
  28 #define     DEVICE_RESET__BANK1                         0x0002
  29 #define     DEVICE_RESET__BANK2                         0x0004
  30 #define     DEVICE_RESET__BANK3                         0x0008
  31
  32 #define TRANSFER_SPARE_REG                      0x10
  33 #define     TRANSFER_SPARE_REG__FLAG                    0x0001
  34
  35 #define LOAD_WAIT_CNT                           0x20
  36 #define     LOAD_WAIT_CNT__VALUE                        0xffff
  37
  38 #define PROGRAM_WAIT_CNT                        0x30
  39 #define     PROGRAM_WAIT_CNT__VALUE                     0xffff
  40
  41 #define ERASE_WAIT_CNT                          0x40
  42 #define     ERASE_WAIT_CNT__VALUE                       0xffff
  43
  44 #define INT_MON_CYCCNT                          0x50
  45 #define     INT_MON_CYCCNT__VALUE                       0xffff
  46
  47 #define RB_PIN_ENABLED                          0x60
  48 #define     RB_PIN_ENABLED__BANK0                       0x0001
  49 #define     RB_PIN_ENABLED__BANK1                       0x0002
  50 #define     RB_PIN_ENABLED__BANK2                       0x0004
  51 #define     RB_PIN_ENABLED__BANK3                       0x0008
  52
  53 #define MULTIPLANE_OPERATION                    0x70
  54 #define     MULTIPLANE_OPERATION__FLAG                  0x0001
  55
  56 #define MULTIPLANE_READ_ENABLE                  0x80
  57 #define     MULTIPLANE_READ_ENABLE__FLAG                0x0001
  58
  59 #define COPYBACK_DISABLE                        0x90
  60 #define     COPYBACK_DISABLE__FLAG                      0x0001
  61
  62 #define CACHE_WRITE_ENABLE                      0xa0
  63 #define     CACHE_WRITE_ENABLE__FLAG                    0x0001
  64
  65 #define CACHE_READ_ENABLE                       0xb0
  66 #define     CACHE_READ_ENABLE__FLAG                     0x0001
  67
  68 #define PREFETCH_MODE                           0xc0
  69 #define     PREFETCH_MODE__PREFETCH_EN                  0x0001
  70 #define     PREFETCH_MODE__PREFETCH_BURST_LENGTH        0xfff0
  71
  72 #define CHIP_ENABLE_DONT_CARE                   0xd0
  73 #define     CHIP_EN_DONT_CARE__FLAG                     0x01
  74
  75 #define ECC_ENABLE                              0xe0
  76 #define     ECC_ENABLE__FLAG                            0x0001
  77
  78 #define GLOBAL_INT_ENABLE                       0xf0
  79 #define     GLOBAL_INT_EN_FLAG                          0x01
  80
  81 #define WE_2_RE                                 0x100
  82 #define     WE_2_RE__VALUE                              0x003f
  83
  84 #define ADDR_2_DATA                             0x110
  85 #define     ADDR_2_DATA__VALUE                          0x003f
  86
  87 #define RE_2_WE                                 0x120
  88 #define     RE_2_WE__VALUE                              0x003f
  89
  90 #define ACC_CLKS                                0x130
  91 #define     ACC_CLKS__VALUE                             0x000f
  92
  93 #define NUMBER_OF_PLANES                        0x140
  94 #define     NUMBER_OF_PLANES__VALUE                     0x0007
  95
  96 #define PAGES_PER_BLOCK                         0x150
  97 #define     PAGES_PER_BLOCK__VALUE                      0xffff
  98
  99 #define DEVICE_WIDTH                            0x160
 100 #define     DEVICE_WIDTH__VALUE                         0x0003
 101
 102 #define DEVICE_MAIN_AREA_SIZE                   0x170
 103 #define     DEVICE_MAIN_AREA_SIZE__VALUE                0xffff
 104
 105 #define DEVICE_SPARE_AREA_SIZE                  0x180
 106 #define     DEVICE_SPARE_AREA_SIZE__VALUE               0xffff
 107
 108 #define TWO_ROW_ADDR_CYCLES                     0x190
 109 #define     TWO_ROW_ADDR_CYCLES__FLAG                   0x0001
 110
 111 #define MULTIPLANE_ADDR_RESTRICT                0x1a0
 112 #define     MULTIPLANE_ADDR_RESTRICT__FLAG              0x0001
 113
 114 #define ECC_CORRECTION                          0x1b0
 115 #define     ECC_CORRECTION__VALUE                       0x001f
 116
 117 #define READ_MODE                               0x1c0
 118 #define     READ_MODE__VALUE                            0x000f
 119
 120 #define WRITE_MODE                              0x1d0
 121 #define     WRITE_MODE__VALUE                           0x000f
 122
 123 #define COPYBACK_MODE                           0x1e0
 124 #define     COPYBACK_MODE__VALUE                        0x000f
 125
 126 #define RDWR_EN_LO_CNT                          0x1f0
 127 #define     RDWR_EN_LO_CNT__VALUE                       0x001f
 128
 129 #define RDWR_EN_HI_CNT                          0x200
 130 #define     RDWR_EN_HI_CNT__VALUE                       0x001f
 131
 132 #define MAX_RD_DELAY                            0x210
 133 #define     MAX_RD_DELAY__VALUE                         0x000f
 134
 135 #define CS_SETUP_CNT                            0x220
 136 #define     CS_SETUP_CNT__VALUE                         0x001f
 137
 138 #define SPARE_AREA_SKIP_BYTES                   0x230
 139 #define     SPARE_AREA_SKIP_BYTES__VALUE                0x003f
 140
 141 #define SPARE_AREA_MARKER                       0x240
 142 #define     SPARE_AREA_MARKER__VALUE                    0xffff
 143
 144 #define DEVICES_CONNECTED                       0x250
 145 #define     DEVICES_CONNECTED__VALUE                    0x0007
 146
 147 #define DIE_MASK                                0x260
 148 #define     DIE_MASK__VALUE                             0x00ff
 149
 150 #define FIRST_BLOCK_OF_NEXT_PLANE               0x270
 151 #define     FIRST_BLOCK_OF_NEXT_PLANE__VALUE            0xffff
 152
 153 #define WRITE_PROTECT                           0x280
 154 #define     WRITE_PROTECT__FLAG                         0x0001
 155
 156 #define RE_2_RE                                 0x290
 157 #define     RE_2_RE__VALUE                              0x003f
 158
 159 #define MANUFACTURER_ID                         0x300
 160 #define     MANUFACTURER_ID__VALUE                      0x00ff
 161
 162 #define DEVICE_ID                               0x310
 163 #define     DEVICE_ID__VALUE                            0x00ff
 164
 165 #define DEVICE_PARAM_0                          0x320
 166 #define     DEVICE_PARAM_0__VALUE                       0x00ff
 167
 168 #define DEVICE_PARAM_1                          0x330
 169 #define     DEVICE_PARAM_1__VALUE                       0x00ff
 170
 171 #define DEVICE_PARAM_2                          0x340
 172 #define     DEVICE_PARAM_2__VALUE                       0x00ff
 173
 174 #define LOGICAL_PAGE_DATA_SIZE                  0x350
 175 #define     LOGICAL_PAGE_DATA_SIZE__VALUE               0xffff
 176
 177 #define LOGICAL_PAGE_SPARE_SIZE                 0x360
 178 #define     LOGICAL_PAGE_SPARE_SIZE__VALUE              0xffff
 179
 180 #define REVISION                                0x370
 181 #define     REVISION__VALUE                             0xffff
 182
 183 #define ONFI_DEVICE_FEATURES                    0x380
 184 #define     ONFI_DEVICE_FEATURES__VALUE                 0x003f
 185
 186 #define ONFI_OPTIONAL_COMMANDS                  0x390
 187 #define     ONFI_OPTIONAL_COMMANDS__VALUE               0x003f
 188
 189 #define ONFI_TIMING_MODE                        0x3a0
 190 #define     ONFI_TIMING_MODE__VALUE                     0x003f
 191
 192 #define ONFI_PGM_CACHE_TIMING_MODE              0x3b0
 193 #define     ONFI_PGM_CACHE_TIMING_MODE__VALUE           0x003f
 194
 195 #define ONFI_DEVICE_NO_OF_LUNS                  0x3c0
 196 #define     ONFI_DEVICE_NO_OF_LUNS__NO_OF_LUNS          0x00ff
 197 #define     ONFI_DEVICE_NO_OF_LUNS__ONFI_DEVICE         0x0100
 198
 199 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L      0x3d0
 200 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_L__VALUE   0xffff
 201
 202 #define ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U      0x3e0
 203 #define     ONFI_DEVICE_NO_OF_BLOCKS_PER_LUN_U__VALUE   0xffff
 204
 205 #define FEATURES                                        0x3f0
 206 #define     FEATURES__N_BANKS                           0x0003
 207 #define     FEATURES__ECC_MAX_ERR                       0x003c
 208 #define     FEATURES__DMA                               0x0040
 209 #define     FEATURES__CMD_DMA                           0x0080
 210 #define     FEATURES__PARTITION                         0x0100
 211 #define     FEATURES__XDMA_SIDEBAND                     0x0200
 212 #define     FEATURES__GPREG                             0x0400
 213 #define     FEATURES__INDEX_ADDR                        0x0800
 214
 215 #define TRANSFER_MODE                           0x400
 216 #define     TRANSFER_MODE__VALUE                        0x0003
 217
 218 #define INTR_STATUS(__bank)     (0x410 + ((__bank) * 0x50))
 219 #define INTR_EN(__bank)         (0x420 + ((__bank) * 0x50))
 220 /* bit[1:0] is used differently depending on IP version */
 221 #define     INTR__ECC_UNCOR_ERR                         0x0001  /* new IP */
 222 #define     INTR__ECC_TRANSACTION_DONE                  0x0001  /* old IP */
 223 #define     INTR__ECC_ERR                               0x0002  /* old IP */
 224 #define     INTR__DMA_CMD_COMP                          0x0004
 225 #define     INTR__TIME_OUT                              0x0008
 226 #define     INTR__PROGRAM_FAIL                          0x0010
 227 #define     INTR__ERASE_FAIL                            0x0020
 228 #define     INTR__LOAD_COMP                             0x0040
 229 #define     INTR__PROGRAM_COMP                          0x0080
 230 #define     INTR__ERASE_COMP                            0x0100
 231 #define     INTR__PIPE_CPYBCK_CMD_COMP                  0x0200
 232 #define     INTR__LOCKED_BLK                            0x0400
 233 #define     INTR__UNSUP_CMD                             0x0800
 234 #define     INTR__INT_ACT                               0x1000
 235 #define     INTR__RST_COMP                              0x2000
 236 #define     INTR__PIPE_CMD_ERR                          0x4000
 237 #define     INTR__PAGE_XFER_INC                         0x8000
 238
 239 #define PAGE_CNT(__bank)        (0x430 + ((__bank) * 0x50))
 240 #define ERR_PAGE_ADDR(__bank)   (0x440 + ((__bank) * 0x50))
 241 #define ERR_BLOCK_ADDR(__bank)  (0x450 + ((__bank) * 0x50))
 242
 243 #define ECC_THRESHOLD                           0x600
 244 #define     ECC_THRESHOLD__VALUE                        0x03ff
 245
 246 #define ECC_ERROR_BLOCK_ADDRESS                 0x610
 247 #define     ECC_ERROR_BLOCK_ADDRESS__VALUE              0xffff
 248
 249 #define ECC_ERROR_PAGE_ADDRESS                  0x620
 250 #define     ECC_ERROR_PAGE_ADDRESS__VALUE               0x0fff
 251 #define     ECC_ERROR_PAGE_ADDRESS__BANK                0xf000
 252
 253 #define ECC_ERROR_ADDRESS                       0x630
 254 #define     ECC_ERROR_ADDRESS__OFFSET                   0x0fff
 255 #define     ECC_ERROR_ADDRESS__SECTOR_NR                0xf000
 256
 257 #define ERR_CORRECTION_INFO                     0x640
 258 #define     ERR_CORRECTION_INFO__BYTEMASK               0x00ff
 259 #define     ERR_CORRECTION_INFO__DEVICE_NR              0x0f00
 260 #define     ERR_CORRECTION_INFO__ERROR_TYPE             0x4000
 261 #define     ERR_CORRECTION_INFO__LAST_ERR_INFO          0x8000
 262
 263 #define ECC_COR_INFO(bank)                      (0x650 + (bank) / 2 * 0x10)
 264 #define     ECC_COR_INFO__SHIFT(bank)                   ((bank) % 2 * 8)
 265 #define     ECC_COR_INFO__MAX_ERRORS                    0x007f
 266 #define     ECC_COR_INFO__UNCOR_ERR                     0x0080
 267
 268 #define DMA_ENABLE                              0x700
 269 #define     DMA_ENABLE__FLAG                            0x0001
 270
 271 #define IGNORE_ECC_DONE                         0x710
 272 #define     IGNORE_ECC_DONE__FLAG                       0x0001
 273
 274 #define DMA_INTR                                0x720
 275 #define DMA_INTR_EN                             0x730
 276 #define     DMA_INTR__TARGET_ERROR                      0x0001
 277 #define     DMA_INTR__DESC_COMP_CHANNEL0                0x0002
 278 #define     DMA_INTR__DESC_COMP_CHANNEL1                0x0004
 279 #define     DMA_INTR__DESC_COMP_CHANNEL2                0x0008
 280 #define     DMA_INTR__DESC_COMP_CHANNEL3                0x0010
 281 #define     DMA_INTR__MEMCOPY_DESC_COMP                 0x0020
 282
 283 #define TARGET_ERR_ADDR_LO                      0x740
 284 #define     TARGET_ERR_ADDR_LO__VALUE                   0xffff
 285
 286 #define TARGET_ERR_ADDR_HI                      0x750
 287 #define     TARGET_ERR_ADDR_HI__VALUE                   0xffff
 288
 289 #define CHNL_ACTIVE                             0x760
 290 #define     CHNL_ACTIVE__CHANNEL0                       0x0001
 291 #define     CHNL_ACTIVE__CHANNEL1                       0x0002
 292 #define     CHNL_ACTIVE__CHANNEL2                       0x0004
 293 #define     CHNL_ACTIVE__CHANNEL3                       0x0008
 294
 295 #define FAIL 1                  /*failed flag*/
 296 #define PASS 0                  /*success flag*/
 297
 298 #define CLK_X  5
 299 #define CLK_MULTI 4
 300
 301 #define ONFI_BLOOM_TIME         1
 302 #define MODE5_WORKAROUND        0
 303
 304
 305 #define MODE_00    0x00000000
 306 #define MODE_01    0x04000000
 307 #define MODE_10    0x08000000
 308 #define MODE_11    0x0C000000
 309
 310 #define ECC_SECTOR_SIZE     512
 311
 312 struct nand_buf {
 313         int head;
 314         int tail;
 315         uint8_t *buf;
 316         dma_addr_t dma_buf;
 317 };
 318
 319 #define INTEL_CE4100    1
 320 #define INTEL_MRST      2
 321 #define DT              3
 322
 323 struct denali_nand_info {
 324         struct nand_chip nand;
 325         int flash_bank; /* currently selected chip */
 326         int status;
 327         int platform;
 328         struct nand_buf buf;
 329         struct device *dev;
 330         int total_used_banks;
 331         int page;
 332         void __iomem *flash_reg;        /* Register Interface */
 333         void __iomem *flash_mem;        /* Host Data/Command Interface */
 334
 335         /* elements used by ISR */
 336         struct completion complete;
 337         spinlock_t irq_lock;
 338         uint32_t irq_status;
 339         int irq;
 340
 341         int devnum;     /* represent how many nands connected */
 342         int bbtskipbytes;
 343         int max_banks;
 344         unsigned int revision;
 345         unsigned int caps;
 346 };
 347
 348 #define DENALI_CAP_HW_ECC_FIXUP                 BIT(0)
 349 #define DENALI_CAP_DMA_64BIT                    BIT(1)
 350
 351 extern int denali_init(struct denali_nand_info *denali);
 352 extern void denali_remove(struct denali_nand_info *denali);
 353
 354 #endif /* __DENALI_H__ */