drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 /* fsmc controller registers for NOR flash */
  42 #define CTRL                    0x0
  43         /* ctrl register definitions */
  44         #define BANK_ENABLE             (1 << 0)
  45         #define MUXED                   (1 << 1)
  46         #define NOR_DEV                 (2 << 2)
  47         #define WIDTH_8                 (0 << 4)
  48         #define WIDTH_16                (1 << 4)
  49         #define RSTPWRDWN               (1 << 6)
  50         #define WPROT                   (1 << 7)
  51         #define WRT_ENABLE              (1 << 12)
  52         #define WAIT_ENB                (1 << 13)
  53
  54 #define CTRL_TIM                0x4
  55         /* ctrl_tim register definitions */
  56
  57 #define FSMC_NOR_BANK_SZ        0x8
  58 #define FSMC_NOR_REG_SIZE       0x40
  59
  60 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  61                                                 FSMC_NOR_BANK_SZ * (bank) + \
  62                                                 reg)
  63
  64 /* fsmc controller registers for NAND flash */
  65 #define PC                      0x00
  66         /* pc register definitions */
  67         #define FSMC_RESET              (1 << 0)
  68         #define FSMC_WAITON             (1 << 1)
  69         #define FSMC_ENABLE             (1 << 2)
  70         #define FSMC_DEVTYPE_NAND       (1 << 3)
  71         #define FSMC_DEVWID_8           (0 << 4)
  72         #define FSMC_DEVWID_16          (1 << 4)
  73         #define FSMC_ECCEN              (1 << 6)
  74         #define FSMC_ECCPLEN_512        (0 << 7)
  75         #define FSMC_ECCPLEN_256        (1 << 7)
  76         #define FSMC_TCLR_1             (1)
  77         #define FSMC_TCLR_SHIFT         (9)
  78         #define FSMC_TCLR_MASK          (0xF)
  79         #define FSMC_TAR_1              (1)
  80         #define FSMC_TAR_SHIFT          (13)
  81         #define FSMC_TAR_MASK           (0xF)
  82 #define STS                     0x04
  83         /* sts register definitions */
  84         #define FSMC_CODE_RDY           (1 << 15)
  85 #define COMM                    0x08
  86         /* comm register definitions */
  87         #define FSMC_TSET_0             0
  88         #define FSMC_TSET_SHIFT         0
  89         #define FSMC_TSET_MASK          0xFF
  90         #define FSMC_TWAIT_6            6
  91         #define FSMC_TWAIT_SHIFT        8
  92         #define FSMC_TWAIT_MASK         0xFF
  93         #define FSMC_THOLD_4            4
  94         #define FSMC_THOLD_SHIFT        16
  95         #define FSMC_THOLD_MASK         0xFF
  96         #define FSMC_THIZ_1             1
  97         #define FSMC_THIZ_SHIFT         24
  98         #define FSMC_THIZ_MASK          0xFF
  99 #define ATTRIB                  0x0C
 100 #define IOATA                   0x10
 101 #define ECC1                    0x14
 102 #define ECC2                    0x18
 103 #define ECC3                    0x1C
 104 #define FSMC_NAND_BANK_SZ       0x20
 105
 106 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 107                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 108                                                 reg)
 109
 110 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 111
 112 struct fsmc_nand_timings {
 113         uint8_t tclr;
 114         uint8_t tar;
 115         uint8_t thiz;
 116         uint8_t thold;
 117         uint8_t twait;
 118         uint8_t tset;
 119 };
 120
 121 enum access_mode {
 122         USE_DMA_ACCESS = 1,
 123         USE_WORD_ACCESS,
 124 };
 125
 126 /**
 127  * struct fsmc_nand_data - structure for FSMC NAND device state
 128  *
 129  * @pid:                Part ID on the AMBA PrimeCell format
 130  * @mtd:                MTD info for a NAND flash.
 131  * @nand:               Chip related info for a NAND flash.
 132  * @partitions:         Partition info for a NAND Flash.
 133  * @nr_partitions:      Total number of partition of a NAND flash.
 134  *
 135  * @bank:               Bank number for probed device.
 136  * @clk:                Clock structure for FSMC.
 137  *
 138  * @read_dma_chan:      DMA channel for read access
 139  * @write_dma_chan:     DMA channel for write access to NAND
 140  * @dma_access_complete: Completion structure
 141  *
 142  * @data_pa:            NAND Physical port for Data.
 143  * @data_va:            NAND port for Data.
 144  * @cmd_va:             NAND port for Command.
 145  * @addr_va:            NAND port for Address.
 146  * @regs_va:            FSMC regs base address.
 147  */
 148 struct fsmc_nand_data {
 149         u32                     pid;
 150         struct nand_chip        nand;
 151
 152         unsigned int            bank;
 153         struct device           *dev;
 154         enum access_mode        mode;
 155         struct clk              *clk;
 156
 157         /* DMA related objects */
 158         struct dma_chan         *read_dma_chan;
 159         struct dma_chan         *write_dma_chan;
 160         struct completion       dma_access_complete;
 161
 162         struct fsmc_nand_timings *dev_timings;
 163
 164         dma_addr_t              data_pa;
 165         void __iomem            *data_va;
 166         void __iomem            *cmd_va;
 167         void __iomem            *addr_va;
 168         void __iomem            *regs_va;
 169 };
 170
 171 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 172                                    struct mtd_oob_region *oobregion)
 173 {
 174         struct nand_chip *chip = mtd_to_nand(mtd);
 175
 176         if (section >= chip->ecc.steps)
 177                 return -ERANGE;
 178
 179         oobregion->offset = (section * 16) + 2;
 180         oobregion->length = 3;
 181
 182         return 0;
 183 }
 184
 185 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 186                                     struct mtd_oob_region *oobregion)
 187 {
 188         struct nand_chip *chip = mtd_to_nand(mtd);
 189
 190         if (section >= chip->ecc.steps)
 191                 return -ERANGE;
 192
 193         oobregion->offset = (section * 16) + 8;
 194
 195         if (section < chip->ecc.steps - 1)
 196                 oobregion->length = 8;
 197         else
 198                 oobregion->length = mtd->oobsize - oobregion->offset;
 199
 200         return 0;
 201 }
 202
 203 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 204         .ecc = fsmc_ecc1_ooblayout_ecc,
 205         .free = fsmc_ecc1_ooblayout_free,
 206 };
 207
 208 /*
 209  * ECC placement definitions in oobfree type format.
 210  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 211  * consecutively and immediately after the 512 byte data block for hardware to
 212  * generate the error bit offsets in 512 byte data.
 213  */
 214 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 215                                    struct mtd_oob_region *oobregion)
 216 {
 217         struct nand_chip *chip = mtd_to_nand(mtd);
 218
 219         if (section >= chip->ecc.steps)
 220                 return -ERANGE;
 221
 222         oobregion->length = chip->ecc.bytes;
 223
 224         if (!section && mtd->writesize <= 512)
 225                 oobregion->offset = 0;
 226         else
 227                 oobregion->offset = (section * 16) + 2;
 228
 229         return 0;
 230 }
 231
 232 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 233                                     struct mtd_oob_region *oobregion)
 234 {
 235         struct nand_chip *chip = mtd_to_nand(mtd);
 236
 237         if (section >= chip->ecc.steps)
 238                 return -ERANGE;
 239
 240         oobregion->offset = (section * 16) + 15;
 241
 242         if (section < chip->ecc.steps - 1)
 243                 oobregion->length = 3;
 244         else
 245                 oobregion->length = mtd->oobsize - oobregion->offset;
 246
 247         return 0;
 248 }
 249
 250 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 251         .ecc = fsmc_ecc4_ooblayout_ecc,
 252         .free = fsmc_ecc4_ooblayout_free,
 253 };
 254
 255 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 256 {
 257         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 258 }
 259
 260 /*
 261  * fsmc_cmd_ctrl - For facilitaing Hardware access
 262  * This routine allows hardware specific access to control-lines(ALE,CLE)
 263  */
 264 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 265 {
 266         struct nand_chip *this = mtd_to_nand(mtd);
 267         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 268         void __iomem *regs = host->regs_va;
 269         unsigned int bank = host->bank;
 270
 271         if (ctrl & NAND_CTRL_CHANGE) {
 272                 u32 pc;
 273
 274                 if (ctrl & NAND_CLE) {
 275                         this->IO_ADDR_R = host->cmd_va;
 276                         this->IO_ADDR_W = host->cmd_va;
 277                 } else if (ctrl & NAND_ALE) {
 278                         this->IO_ADDR_R = host->addr_va;
 279                         this->IO_ADDR_W = host->addr_va;
 280                 } else {
 281                         this->IO_ADDR_R = host->data_va;
 282                         this->IO_ADDR_W = host->data_va;
 283                 }
 284
 285                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 286                 if (ctrl & NAND_NCE)
 287                         pc |= FSMC_ENABLE;
 288                 else
 289                         pc &= ~FSMC_ENABLE;
 290                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 291         }
 292
 293         mb();
 294
 295         if (cmd != NAND_CMD_NONE)
 296                 writeb_relaxed(cmd, this->IO_ADDR_W);
 297 }
 298
 299 /*
 300  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 301  *
 302  * This routine initializes timing parameters related to NAND memory access in
 303  * FSMC registers
 304  */
 305 static void fsmc_nand_setup(struct fsmc_nand_data *host,
 306                             struct fsmc_nand_timings *tims)
 307 {
 308         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 309         uint32_t tclr, tar, thiz, thold, twait, tset;
 310         unsigned int bank = host->bank;
 311         void __iomem *regs = host->regs_va;
 312
 313         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 314         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 315         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 316         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 317         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 318         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 319
 320         if (host->nand.options & NAND_BUSWIDTH_16)
 321                 writel_relaxed(value | FSMC_DEVWID_16,
 322                                 FSMC_NAND_REG(regs, bank, PC));
 323         else
 324                 writel_relaxed(value | FSMC_DEVWID_8,
 325                                 FSMC_NAND_REG(regs, bank, PC));
 326
 327         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 328                         FSMC_NAND_REG(regs, bank, PC));
 329         writel_relaxed(thiz | thold | twait | tset,
 330                         FSMC_NAND_REG(regs, bank, COMM));
 331         writel_relaxed(thiz | thold | twait | tset,
 332                         FSMC_NAND_REG(regs, bank, ATTRIB));
 333 }
 334
 335 static int fsmc_calc_timings(struct fsmc_nand_data *host,
 336                              const struct nand_sdr_timings *sdrt,
 337                              struct fsmc_nand_timings *tims)
 338 {
 339         unsigned long hclk = clk_get_rate(host->clk);
 340         unsigned long hclkn = NSEC_PER_SEC / hclk;
 341         uint32_t thiz, thold, twait, tset;
 342
 343         if (sdrt->tRC_min < 30000)
 344                 return -EOPNOTSUPP;
 345
 346         tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
 347         if (tims->tar > FSMC_TAR_MASK)
 348                 tims->tar = FSMC_TAR_MASK;
 349         tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
 350         if (tims->tclr > FSMC_TCLR_MASK)
 351                 tims->tclr = FSMC_TCLR_MASK;
 352
 353         thiz = sdrt->tCS_min - sdrt->tWP_min;
 354         tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
 355
 356         thold = sdrt->tDH_min;
 357         if (thold < sdrt->tCH_min)
 358                 thold = sdrt->tCH_min;
 359         if (thold < sdrt->tCLH_min)
 360                 thold = sdrt->tCLH_min;
 361         if (thold < sdrt->tWH_min)
 362                 thold = sdrt->tWH_min;
 363         if (thold < sdrt->tALH_min)
 364                 thold = sdrt->tALH_min;
 365         if (thold < sdrt->tREH_min)
 366                 thold = sdrt->tREH_min;
 367         tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
 368         if (tims->thold == 0)
 369                 tims->thold = 1;
 370         else if (tims->thold > FSMC_THOLD_MASK)
 371                 tims->thold = FSMC_THOLD_MASK;
 372
 373         twait = max(sdrt->tRP_min, sdrt->tWP_min);
 374         tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
 375         if (tims->twait == 0)
 376                 tims->twait = 1;
 377         else if (tims->twait > FSMC_TWAIT_MASK)
 378                 tims->twait = FSMC_TWAIT_MASK;
 379
 380         tset = max(sdrt->tCS_min - sdrt->tWP_min,
 381                    sdrt->tCEA_max - sdrt->tREA_max);
 382         tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
 383         if (tims->tset == 0)
 384                 tims->tset = 1;
 385         else if (tims->tset > FSMC_TSET_MASK)
 386                 tims->tset = FSMC_TSET_MASK;
 387
 388         return 0;
 389 }
 390
 391 static int fsmc_setup_data_interface(struct mtd_info *mtd,
 392                                      const struct nand_data_interface *conf,
 393                                      bool check_only)
 394 {
 395         struct nand_chip *nand = mtd_to_nand(mtd);
 396         struct fsmc_nand_data *host = nand_get_controller_data(nand);
 397         struct fsmc_nand_timings tims;
 398         const struct nand_sdr_timings *sdrt;
 399         int ret;
 400
 401         sdrt = nand_get_sdr_timings(conf);
 402         if (IS_ERR(sdrt))
 403                 return PTR_ERR(sdrt);
 404
 405         ret = fsmc_calc_timings(host, sdrt, &tims);
 406         if (ret)
 407                 return ret;
 408
 409         if (check_only)
 410                 return 0;
 411
 412         fsmc_nand_setup(host, &tims);
 413
 414         return 0;
 415 }
 416
 417 /*
 418  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 419  */
 420 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 421 {
 422         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 423         void __iomem *regs = host->regs_va;
 424         uint32_t bank = host->bank;
 425
 426         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 427                         FSMC_NAND_REG(regs, bank, PC));
 428         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 429                         FSMC_NAND_REG(regs, bank, PC));
 430         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 431                         FSMC_NAND_REG(regs, bank, PC));
 432 }
 433
 434 /*
 435  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 436  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 437  * max of 8-bits)
 438  */
 439 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 440                                 uint8_t *ecc)
 441 {
 442         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 443         void __iomem *regs = host->regs_va;
 444         uint32_t bank = host->bank;
 445         uint32_t ecc_tmp;
 446         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 447
 448         do {
 449                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 450                         break;
 451                 else
 452                         cond_resched();
 453         } while (!time_after_eq(jiffies, deadline));
 454
 455         if (time_after_eq(jiffies, deadline)) {
 456                 dev_err(host->dev, "calculate ecc timed out\n");
 457                 return -ETIMEDOUT;
 458         }
 459
 460         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 461         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 462         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 463         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 464         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 465
 466         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 467         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 468         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 469         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 470         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 471
 472         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 473         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 474         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 475         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 476         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 477
 478         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 479         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 480
 481         return 0;
 482 }
 483
 484 /*
 485  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 486  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 487  * max of 1-bit)
 488  */
 489 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 490                                 uint8_t *ecc)
 491 {
 492         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 493         void __iomem *regs = host->regs_va;
 494         uint32_t bank = host->bank;
 495         uint32_t ecc_tmp;
 496
 497         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 498         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 499         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 500         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 501
 502         return 0;
 503 }
 504
 505 /* Count the number of 0's in buff upto a max of max_bits */
 506 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 507 {
 508         int k, written_bits = 0;
 509
 510         for (k = 0; k < size; k++) {
 511                 written_bits += hweight8(~buff[k]);
 512                 if (written_bits > max_bits)
 513                         break;
 514         }
 515
 516         return written_bits;
 517 }
 518
 519 static void dma_complete(void *param)
 520 {
 521         struct fsmc_nand_data *host = param;
 522
 523         complete(&host->dma_access_complete);
 524 }
 525
 526 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 527                 enum dma_data_direction direction)
 528 {
 529         struct dma_chan *chan;
 530         struct dma_device *dma_dev;
 531         struct dma_async_tx_descriptor *tx;
 532         dma_addr_t dma_dst, dma_src, dma_addr;
 533         dma_cookie_t cookie;
 534         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 535         int ret;
 536         unsigned long time_left;
 537
 538         if (direction == DMA_TO_DEVICE)
 539                 chan = host->write_dma_chan;
 540         else if (direction == DMA_FROM_DEVICE)
 541                 chan = host->read_dma_chan;
 542         else
 543                 return -EINVAL;
 544
 545         dma_dev = chan->device;
 546         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 547
 548         if (direction == DMA_TO_DEVICE) {
 549                 dma_src = dma_addr;
 550                 dma_dst = host->data_pa;
 551         } else {
 552                 dma_src = host->data_pa;
 553                 dma_dst = dma_addr;
 554         }
 555
 556         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 557                         len, flags);
 558         if (!tx) {
 559                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 560                 ret = -EIO;
 561                 goto unmap_dma;
 562         }
 563
 564         tx->callback = dma_complete;
 565         tx->callback_param = host;
 566         cookie = tx->tx_submit(tx);
 567
 568         ret = dma_submit_error(cookie);
 569         if (ret) {
 570                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 571                 goto unmap_dma;
 572         }
 573
 574         dma_async_issue_pending(chan);
 575
 576         time_left =
 577         wait_for_completion_timeout(&host->dma_access_complete,
 578                                 msecs_to_jiffies(3000));
 579         if (time_left == 0) {
 580                 dmaengine_terminate_all(chan);
 581                 dev_err(host->dev, "wait_for_completion_timeout\n");
 582                 ret = -ETIMEDOUT;
 583                 goto unmap_dma;
 584         }
 585
 586         ret = 0;
 587
 588 unmap_dma:
 589         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 590
 591         return ret;
 592 }
 593
 594 /*
 595  * fsmc_write_buf - write buffer to chip
 596  * @mtd:        MTD device structure
 597  * @buf:        data buffer
 598  * @len:        number of bytes to write
 599  */
 600 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 601 {
 602         int i;
 603         struct nand_chip *chip = mtd_to_nand(mtd);
 604
 605         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 606                         IS_ALIGNED(len, sizeof(uint32_t))) {
 607                 uint32_t *p = (uint32_t *)buf;
 608                 len = len >> 2;
 609                 for (i = 0; i < len; i++)
 610                         writel_relaxed(p[i], chip->IO_ADDR_W);
 611         } else {
 612                 for (i = 0; i < len; i++)
 613                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 614         }
 615 }
 616
 617 /*
 618  * fsmc_read_buf - read chip data into buffer
 619  * @mtd:        MTD device structure
 620  * @buf:        buffer to store date
 621  * @len:        number of bytes to read
 622  */
 623 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 624 {
 625         int i;
 626         struct nand_chip *chip = mtd_to_nand(mtd);
 627
 628         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 629                         IS_ALIGNED(len, sizeof(uint32_t))) {
 630                 uint32_t *p = (uint32_t *)buf;
 631                 len = len >> 2;
 632                 for (i = 0; i < len; i++)
 633                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 634         } else {
 635                 for (i = 0; i < len; i++)
 636                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 637         }
 638 }
 639
 640 /*
 641  * fsmc_read_buf_dma - read chip data into buffer
 642  * @mtd:        MTD device structure
 643  * @buf:        buffer to store date
 644  * @len:        number of bytes to read
 645  */
 646 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 647 {
 648         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 649
 650         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 651 }
 652
 653 /*
 654  * fsmc_write_buf_dma - write buffer to chip
 655  * @mtd:        MTD device structure
 656  * @buf:        data buffer
 657  * @len:        number of bytes to write
 658  */
 659 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 660                 int len)
 661 {
 662         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 663
 664         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 665 }
 666
 667 /*
 668  * fsmc_read_page_hwecc
 669  * @mtd:        mtd info structure
 670  * @chip:       nand chip info structure
 671  * @buf:        buffer to store read data
 672  * @oob_required:       caller expects OOB data read to chip->oob_poi
 673  * @page:       page number to read
 674  *
 675  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 676  * performed in a strict sequence as follows:
 677  * data(512 byte) -> ecc(13 byte)
 678  * After this read, fsmc hardware generates and reports error data bits(up to a
 679  * max of 8 bits)
 680  */
 681 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 682                                  uint8_t *buf, int oob_required, int page)
 683 {
 684         int i, j, s, stat, eccsize = chip->ecc.size;
 685         int eccbytes = chip->ecc.bytes;
 686         int eccsteps = chip->ecc.steps;
 687         uint8_t *p = buf;
 688         uint8_t *ecc_calc = chip->buffers->ecccalc;
 689         uint8_t *ecc_code = chip->buffers->ecccode;
 690         int off, len, group = 0;
 691         /*
 692          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 693          * end up reading 14 bytes (7 words) from oob. The local array is
 694          * to maintain word alignment
 695          */
 696         uint16_t ecc_oob[7];
 697         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 698         unsigned int max_bitflips = 0;
 699
 700         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 701                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 702                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 703                 chip->read_buf(mtd, p, eccsize);
 704
 705                 for (j = 0; j < eccbytes;) {
 706                         struct mtd_oob_region oobregion;
 707                         int ret;
 708
 709                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 710                         if (ret)
 711                                 return ret;
 712
 713                         off = oobregion.offset;
 714                         len = oobregion.length;
 715
 716                         /*
 717                          * length is intentionally kept a higher multiple of 2
 718                          * to read at least 13 bytes even in case of 16 bit NAND
 719                          * devices
 720                          */
 721                         if (chip->options & NAND_BUSWIDTH_16)
 722                                 len = roundup(len, 2);
 723
 724                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 725                         chip->read_buf(mtd, oob + j, len);
 726                         j += len;
 727                 }
 728
 729                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 730                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 731
 732                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 733                 if (stat < 0) {
 734                         mtd->ecc_stats.failed++;
 735                 } else {
 736                         mtd->ecc_stats.corrected += stat;
 737                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 738                 }
 739         }
 740
 741         return max_bitflips;
 742 }
 743
 744 /*
 745  * fsmc_bch8_correct_data
 746  * @mtd:        mtd info structure
 747  * @dat:        buffer of read data
 748  * @read_ecc:   ecc read from device spare area
 749  * @calc_ecc:   ecc calculated from read data
 750  *
 751  * calc_ecc is a 104 bit information containing maximum of 8 error
 752  * offset informations of 13 bits each in 512 bytes of read data.
 753  */
 754 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 755                              uint8_t *read_ecc, uint8_t *calc_ecc)
 756 {
 757         struct nand_chip *chip = mtd_to_nand(mtd);
 758         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 759         void __iomem *regs = host->regs_va;
 760         unsigned int bank = host->bank;
 761         uint32_t err_idx[8];
 762         uint32_t num_err, i;
 763         uint32_t ecc1, ecc2, ecc3, ecc4;
 764
 765         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 766
 767         /* no bit flipping */
 768         if (likely(num_err == 0))
 769                 return 0;
 770
 771         /* too many errors */
 772         if (unlikely(num_err > 8)) {
 773                 /*
 774                  * This is a temporary erase check. A newly erased page read
 775                  * would result in an ecc error because the oob data is also
 776                  * erased to FF and the calculated ecc for an FF data is not
 777                  * FF..FF.
 778                  * This is a workaround to skip performing correction in case
 779                  * data is FF..FF
 780                  *
 781                  * Logic:
 782                  * For every page, each bit written as 0 is counted until these
 783                  * number of bits are greater than 8 (the maximum correction
 784                  * capability of FSMC for each 512 + 13 bytes)
 785                  */
 786
 787                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 788                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 789
 790                 if ((bits_ecc + bits_data) <= 8) {
 791                         if (bits_data)
 792                                 memset(dat, 0xff, chip->ecc.size);
 793                         return bits_data;
 794                 }
 795
 796                 return -EBADMSG;
 797         }
 798
 799         /*
 800          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 801          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 802          *
 803          * calc_ecc is a 104 bit information containing maximum of 8 error
 804          * offset informations of 13 bits each. calc_ecc is copied into a
 805          * uint64_t array and error offset indexes are populated in err_idx
 806          * array
 807          */
 808         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 809         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 810         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 811         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 812
 813         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 814         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 815         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 816         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 817         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 818         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 819         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 820         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 821
 822         i = 0;
 823         while (num_err--) {
 824                 change_bit(0, (unsigned long *)&err_idx[i]);
 825                 change_bit(1, (unsigned long *)&err_idx[i]);
 826
 827                 if (err_idx[i] < chip->ecc.size * 8) {
 828                         change_bit(err_idx[i], (unsigned long *)dat);
 829                         i++;
 830                 }
 831         }
 832         return i;
 833 }
 834
 835 static bool filter(struct dma_chan *chan, void *slave)
 836 {
 837         chan->private = slave;
 838         return true;
 839 }
 840
 841 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 842                                      struct fsmc_nand_data *host,
 843                                      struct nand_chip *nand)
 844 {
 845         struct device_node *np = pdev->dev.of_node;
 846         u32 val;
 847         int ret;
 848
 849         nand->options = 0;
 850
 851         if (!of_property_read_u32(np, "bank-width", &val)) {
 852                 if (val == 2) {
 853                         nand->options |= NAND_BUSWIDTH_16;
 854                 } else if (val != 1) {
 855                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 856                         return -EINVAL;
 857                 }
 858         }
 859
 860         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 861                 nand->options |= NAND_SKIP_BBTSCAN;
 862
 863         host->dev_timings = devm_kzalloc(&pdev->dev,
 864                                 sizeof(*host->dev_timings), GFP_KERNEL);
 865         if (!host->dev_timings)
 866                 return -ENOMEM;
 867         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 868                                                 sizeof(*host->dev_timings));
 869         if (ret)
 870                 host->dev_timings = NULL;
 871
 872         /* Set default NAND bank to 0 */
 873         host->bank = 0;
 874         if (!of_property_read_u32(np, "bank", &val)) {
 875                 if (val > 3) {
 876                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 877                         return -EINVAL;
 878                 }
 879                 host->bank = val;
 880         }
 881         return 0;
 882 }
 883
 884 /*
 885  * fsmc_nand_probe - Probe function
 886  * @pdev:       platform device structure
 887  */
 888 static int __init fsmc_nand_probe(struct platform_device *pdev)
 889 {
 890         struct fsmc_nand_data *host;
 891         struct mtd_info *mtd;
 892         struct nand_chip *nand;
 893         struct resource *res;
 894         dma_cap_mask_t mask;
 895         int ret = 0;
 896         u32 pid;
 897         int i;
 898
 899         /* Allocate memory for the device structure (and zero it) */
 900         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 901         if (!host)
 902                 return -ENOMEM;
 903
 904         nand = &host->nand;
 905
 906         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
 907         if (ret)
 908                 return ret;
 909
 910         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 911         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 912         if (IS_ERR(host->data_va))
 913                 return PTR_ERR(host->data_va);
 914
 915         host->data_pa = (dma_addr_t)res->start;
 916
 917         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 918         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 919         if (IS_ERR(host->addr_va))
 920                 return PTR_ERR(host->addr_va);
 921
 922         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 923         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 924         if (IS_ERR(host->cmd_va))
 925                 return PTR_ERR(host->cmd_va);
 926
 927         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 928         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 929         if (IS_ERR(host->regs_va))
 930                 return PTR_ERR(host->regs_va);
 931
 932         host->clk = devm_clk_get(&pdev->dev, NULL);
 933         if (IS_ERR(host->clk)) {
 934                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 935                 return PTR_ERR(host->clk);
 936         }
 937
 938         ret = clk_prepare_enable(host->clk);
 939         if (ret)
 940                 return ret;
 941
 942         /*
 943          * This device ID is actually a common AMBA ID as used on the
 944          * AMBA PrimeCell bus. However it is not a PrimeCell.
 945          */
 946         for (pid = 0, i = 0; i < 4; i++)
 947                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 948         host->pid = pid;
 949         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 950                  "revision %02x, config %02x\n",
 951                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 952                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 953
 954         host->dev = &pdev->dev;
 955
 956         if (host->mode == USE_DMA_ACCESS)
 957                 init_completion(&host->dma_access_complete);
 958
 959         /* Link all private pointers */
 960         mtd = nand_to_mtd(&host->nand);
 961         nand_set_controller_data(nand, host);
 962         nand_set_flash_node(nand, pdev->dev.of_node);
 963
 964         mtd->dev.parent = &pdev->dev;
 965         nand->IO_ADDR_R = host->data_va;
 966         nand->IO_ADDR_W = host->data_va;
 967         nand->cmd_ctrl = fsmc_cmd_ctrl;
 968         nand->chip_delay = 30;
 969
 970         /*
 971          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 972          * can overwrite this value if the DT provides a different value.
 973          */
 974         nand->ecc.mode = NAND_ECC_HW;
 975         nand->ecc.hwctl = fsmc_enable_hwecc;
 976         nand->ecc.size = 512;
 977         nand->badblockbits = 7;
 978
 979         switch (host->mode) {
 980         case USE_DMA_ACCESS:
 981                 dma_cap_zero(mask);
 982                 dma_cap_set(DMA_MEMCPY, mask);
 983                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
 984                 if (!host->read_dma_chan) {
 985                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
 986                         goto err_req_read_chnl;
 987                 }
 988                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
 989                 if (!host->write_dma_chan) {
 990                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
 991                         goto err_req_write_chnl;
 992                 }
 993                 nand->read_buf = fsmc_read_buf_dma;
 994                 nand->write_buf = fsmc_write_buf_dma;
 995                 break;
 996
 997         default:
 998         case USE_WORD_ACCESS:
 999                 nand->read_buf = fsmc_read_buf;
1000                 nand->write_buf = fsmc_write_buf;
1001                 break;
1002         }
1003
1004         if (host->dev_timings)
1005                 fsmc_nand_setup(host, host->dev_timings);
1006         else
1007                 nand->setup_data_interface = fsmc_setup_data_interface;
1008
1009         if (AMBA_REV_BITS(host->pid) >= 8) {
1010                 nand->ecc.read_page = fsmc_read_page_hwecc;
1011                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1012                 nand->ecc.correct = fsmc_bch8_correct_data;
1013                 nand->ecc.bytes = 13;
1014                 nand->ecc.strength = 8;
1015         }
1016
1017         /*
1018          * Scan to find existence of the device
1019          */
1020         ret = nand_scan_ident(mtd, 1, NULL);
1021         if (ret) {
1022                 dev_err(&pdev->dev, "No NAND Device found!\n");
1023                 goto err_scan_ident;
1024         }
1025
1026         if (AMBA_REV_BITS(host->pid) >= 8) {
1027                 switch (mtd->oobsize) {
1028                 case 16:
1029                 case 64:
1030                 case 128:
1031                 case 224:
1032                 case 256:
1033                         break;
1034                 default:
1035                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1036                                  mtd->oobsize);
1037                         ret = -EINVAL;
1038                         goto err_probe;
1039                 }
1040
1041                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1042         } else {
1043                 switch (nand->ecc.mode) {
1044                 case NAND_ECC_HW:
1045                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1046                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1047                         nand->ecc.correct = nand_correct_data;
1048                         nand->ecc.bytes = 3;
1049                         nand->ecc.strength = 1;
1050                         break;
1051
1052                 case NAND_ECC_SOFT:
1053                         if (nand->ecc.algo == NAND_ECC_BCH) {
1054                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1055                                 break;
1056                         }
1057
1058                 case NAND_ECC_ON_DIE:
1059                         break;
1060
1061                 default:
1062                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1063                         goto err_probe;
1064                 }
1065
1066                 /*
1067                  * Don't set layout for BCH4 SW ECC. This will be
1068                  * generated later in nand_bch_init() later.
1069                  */
1070                 if (nand->ecc.mode == NAND_ECC_HW) {
1071                         switch (mtd->oobsize) {
1072                         case 16:
1073                         case 64:
1074                         case 128:
1075                                 mtd_set_ooblayout(mtd,
1076                                                   &fsmc_ecc1_ooblayout_ops);
1077                                 break;
1078                         default:
1079                                 dev_warn(&pdev->dev,
1080                                          "No oob scheme defined for oobsize %d\n",
1081                                          mtd->oobsize);
1082                                 ret = -EINVAL;
1083                                 goto err_probe;
1084                         }
1085                 }
1086         }
1087
1088         /* Second stage of scan to fill MTD data-structures */
1089         ret = nand_scan_tail(mtd);
1090         if (ret)
1091                 goto err_probe;
1092
1093         mtd->name = "nand";
1094         ret = mtd_device_register(mtd, NULL, 0);
1095         if (ret)
1096                 goto err_probe;
1097
1098         platform_set_drvdata(pdev, host);
1099         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1100         return 0;
1101
1102 err_probe:
1103 err_scan_ident:
1104         if (host->mode == USE_DMA_ACCESS)
1105                 dma_release_channel(host->write_dma_chan);
1106 err_req_write_chnl:
1107         if (host->mode == USE_DMA_ACCESS)
1108                 dma_release_channel(host->read_dma_chan);
1109 err_req_read_chnl:
1110         clk_disable_unprepare(host->clk);
1111         return ret;
1112 }
1113
1114 /*
1115  * Clean up routine
1116  */
1117 static int fsmc_nand_remove(struct platform_device *pdev)
1118 {
1119         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1120
1121         if (host) {
1122                 nand_release(nand_to_mtd(&host->nand));
1123
1124                 if (host->mode == USE_DMA_ACCESS) {
1125                         dma_release_channel(host->write_dma_chan);
1126                         dma_release_channel(host->read_dma_chan);
1127                 }
1128                 clk_disable_unprepare(host->clk);
1129         }
1130
1131         return 0;
1132 }
1133
1134 #ifdef CONFIG_PM_SLEEP
1135 static int fsmc_nand_suspend(struct device *dev)
1136 {
1137         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1138         if (host)
1139                 clk_disable_unprepare(host->clk);
1140         return 0;
1141 }
1142
1143 static int fsmc_nand_resume(struct device *dev)
1144 {
1145         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1146         if (host) {
1147                 clk_prepare_enable(host->clk);
1148                 if (host->dev_timings)
1149                         fsmc_nand_setup(host, host->dev_timings);
1150         }
1151         return 0;
1152 }
1153 #endif
1154
1155 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1156
1157 static const struct of_device_id fsmc_nand_id_table[] = {
1158         { .compatible = "st,spear600-fsmc-nand" },
1159         { .compatible = "stericsson,fsmc-nand" },
1160         {}
1161 };
1162 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1163
1164 static struct platform_driver fsmc_nand_driver = {
1165         .remove = fsmc_nand_remove,
1166         .driver = {
1167                 .name = "fsmc-nand",
1168                 .of_match_table = fsmc_nand_id_table,
1169                 .pm = &fsmc_nand_pm_ops,
1170         },
1171 };
1172
1173 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1174
1175 MODULE_LICENSE("GPL");
1176 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1177 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");