drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 /* fsmc controller registers for NOR flash */
  42 #define CTRL                    0x0
  43         /* ctrl register definitions */
  44         #define BANK_ENABLE             (1 << 0)
  45         #define MUXED                   (1 << 1)
  46         #define NOR_DEV                 (2 << 2)
  47         #define WIDTH_8                 (0 << 4)
  48         #define WIDTH_16                (1 << 4)
  49         #define RSTPWRDWN               (1 << 6)
  50         #define WPROT                   (1 << 7)
  51         #define WRT_ENABLE              (1 << 12)
  52         #define WAIT_ENB                (1 << 13)
  53
  54 #define CTRL_TIM                0x4
  55         /* ctrl_tim register definitions */
  56
  57 #define FSMC_NOR_BANK_SZ        0x8
  58 #define FSMC_NOR_REG_SIZE       0x40
  59
  60 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  61                                                 FSMC_NOR_BANK_SZ * (bank) + \
  62                                                 reg)
  63
  64 /* fsmc controller registers for NAND flash */
  65 #define PC                      0x00
  66         /* pc register definitions */
  67         #define FSMC_RESET              (1 << 0)
  68         #define FSMC_WAITON             (1 << 1)
  69         #define FSMC_ENABLE             (1 << 2)
  70         #define FSMC_DEVTYPE_NAND       (1 << 3)
  71         #define FSMC_DEVWID_8           (0 << 4)
  72         #define FSMC_DEVWID_16          (1 << 4)
  73         #define FSMC_ECCEN              (1 << 6)
  74         #define FSMC_ECCPLEN_512        (0 << 7)
  75         #define FSMC_ECCPLEN_256        (1 << 7)
  76         #define FSMC_TCLR_1             (1)
  77         #define FSMC_TCLR_SHIFT         (9)
  78         #define FSMC_TCLR_MASK          (0xF)
  79         #define FSMC_TAR_1              (1)
  80         #define FSMC_TAR_SHIFT          (13)
  81         #define FSMC_TAR_MASK           (0xF)
  82 #define STS                     0x04
  83         /* sts register definitions */
  84         #define FSMC_CODE_RDY           (1 << 15)
  85 #define COMM                    0x08
  86         /* comm register definitions */
  87         #define FSMC_TSET_0             0
  88         #define FSMC_TSET_SHIFT         0
  89         #define FSMC_TSET_MASK          0xFF
  90         #define FSMC_TWAIT_6            6
  91         #define FSMC_TWAIT_SHIFT        8
  92         #define FSMC_TWAIT_MASK         0xFF
  93         #define FSMC_THOLD_4            4
  94         #define FSMC_THOLD_SHIFT        16
  95         #define FSMC_THOLD_MASK         0xFF
  96         #define FSMC_THIZ_1             1
  97         #define FSMC_THIZ_SHIFT         24
  98         #define FSMC_THIZ_MASK          0xFF
  99 #define ATTRIB                  0x0C
 100 #define IOATA                   0x10
 101 #define ECC1                    0x14
 102 #define ECC2                    0x18
 103 #define ECC3                    0x1C
 104 #define FSMC_NAND_BANK_SZ       0x20
 105
 106 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 107                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 108                                                 reg)
 109
 110 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 111
 112 struct fsmc_nand_timings {
 113         uint8_t tclr;
 114         uint8_t tar;
 115         uint8_t thiz;
 116         uint8_t thold;
 117         uint8_t twait;
 118         uint8_t tset;
 119 };
 120
 121 enum access_mode {
 122         USE_DMA_ACCESS = 1,
 123         USE_WORD_ACCESS,
 124 };
 125
 126 /**
 127  * struct fsmc_nand_data - structure for FSMC NAND device state
 128  *
 129  * @pid:                Part ID on the AMBA PrimeCell format
 130  * @mtd:                MTD info for a NAND flash.
 131  * @nand:               Chip related info for a NAND flash.
 132  * @partitions:         Partition info for a NAND Flash.
 133  * @nr_partitions:      Total number of partition of a NAND flash.
 134  *
 135  * @bank:               Bank number for probed device.
 136  * @clk:                Clock structure for FSMC.
 137  *
 138  * @read_dma_chan:      DMA channel for read access
 139  * @write_dma_chan:     DMA channel for write access to NAND
 140  * @dma_access_complete: Completion structure
 141  *
 142  * @data_pa:            NAND Physical port for Data.
 143  * @data_va:            NAND port for Data.
 144  * @cmd_va:             NAND port for Command.
 145  * @addr_va:            NAND port for Address.
 146  * @regs_va:            FSMC regs base address.
 147  */
 148 struct fsmc_nand_data {
 149         u32                     pid;
 150         struct nand_chip        nand;
 151
 152         unsigned int            bank;
 153         struct device           *dev;
 154         enum access_mode        mode;
 155         struct clk              *clk;
 156
 157         /* DMA related objects */
 158         struct dma_chan         *read_dma_chan;
 159         struct dma_chan         *write_dma_chan;
 160         struct completion       dma_access_complete;
 161
 162         struct fsmc_nand_timings *dev_timings;
 163
 164         dma_addr_t              data_pa;
 165         void __iomem            *data_va;
 166         void __iomem            *cmd_va;
 167         void __iomem            *addr_va;
 168         void __iomem            *regs_va;
 169 };
 170
 171 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 172                                    struct mtd_oob_region *oobregion)
 173 {
 174         struct nand_chip *chip = mtd_to_nand(mtd);
 175
 176         if (section >= chip->ecc.steps)
 177                 return -ERANGE;
 178
 179         oobregion->offset = (section * 16) + 2;
 180         oobregion->length = 3;
 181
 182         return 0;
 183 }
 184
 185 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 186                                     struct mtd_oob_region *oobregion)
 187 {
 188         struct nand_chip *chip = mtd_to_nand(mtd);
 189
 190         if (section >= chip->ecc.steps)
 191                 return -ERANGE;
 192
 193         oobregion->offset = (section * 16) + 8;
 194
 195         if (section < chip->ecc.steps - 1)
 196                 oobregion->length = 8;
 197         else
 198                 oobregion->length = mtd->oobsize - oobregion->offset;
 199
 200         return 0;
 201 }
 202
 203 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 204         .ecc = fsmc_ecc1_ooblayout_ecc,
 205         .free = fsmc_ecc1_ooblayout_free,
 206 };
 207
 208 /*
 209  * ECC placement definitions in oobfree type format.
 210  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 211  * consecutively and immediately after the 512 byte data block for hardware to
 212  * generate the error bit offsets in 512 byte data.
 213  */
 214 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 215                                    struct mtd_oob_region *oobregion)
 216 {
 217         struct nand_chip *chip = mtd_to_nand(mtd);
 218
 219         if (section >= chip->ecc.steps)
 220                 return -ERANGE;
 221
 222         oobregion->length = chip->ecc.bytes;
 223
 224         if (!section && mtd->writesize <= 512)
 225                 oobregion->offset = 0;
 226         else
 227                 oobregion->offset = (section * 16) + 2;
 228
 229         return 0;
 230 }
 231
 232 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 233                                     struct mtd_oob_region *oobregion)
 234 {
 235         struct nand_chip *chip = mtd_to_nand(mtd);
 236
 237         if (section >= chip->ecc.steps)
 238                 return -ERANGE;
 239
 240         oobregion->offset = (section * 16) + 15;
 241
 242         if (section < chip->ecc.steps - 1)
 243                 oobregion->length = 3;
 244         else
 245                 oobregion->length = mtd->oobsize - oobregion->offset;
 246
 247         return 0;
 248 }
 249
 250 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 251         .ecc = fsmc_ecc4_ooblayout_ecc,
 252         .free = fsmc_ecc4_ooblayout_free,
 253 };
 254
 255 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 256 {
 257         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 258 }
 259
 260 /*
 261  * fsmc_cmd_ctrl - For facilitaing Hardware access
 262  * This routine allows hardware specific access to control-lines(ALE,CLE)
 263  */
 264 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 265 {
 266         struct nand_chip *this = mtd_to_nand(mtd);
 267         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 268         void __iomem *regs = host->regs_va;
 269         unsigned int bank = host->bank;
 270
 271         if (ctrl & NAND_CTRL_CHANGE) {
 272                 u32 pc;
 273
 274                 if (ctrl & NAND_CLE) {
 275                         this->IO_ADDR_R = host->cmd_va;
 276                         this->IO_ADDR_W = host->cmd_va;
 277                 } else if (ctrl & NAND_ALE) {
 278                         this->IO_ADDR_R = host->addr_va;
 279                         this->IO_ADDR_W = host->addr_va;
 280                 } else {
 281                         this->IO_ADDR_R = host->data_va;
 282                         this->IO_ADDR_W = host->data_va;
 283                 }
 284
 285                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 286                 if (ctrl & NAND_NCE)
 287                         pc |= FSMC_ENABLE;
 288                 else
 289                         pc &= ~FSMC_ENABLE;
 290                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 291         }
 292
 293         mb();
 294
 295         if (cmd != NAND_CMD_NONE)
 296                 writeb_relaxed(cmd, this->IO_ADDR_W);
 297 }
 298
 299 /*
 300  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 301  *
 302  * This routine initializes timing parameters related to NAND memory access in
 303  * FSMC registers
 304  */
 305 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
 306                            uint32_t busw, struct fsmc_nand_timings *timings)
 307 {
 308         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 309         uint32_t tclr, tar, thiz, thold, twait, tset;
 310         struct fsmc_nand_timings *tims;
 311         struct fsmc_nand_timings default_timings = {
 312                 .tclr   = FSMC_TCLR_1,
 313                 .tar    = FSMC_TAR_1,
 314                 .thiz   = FSMC_THIZ_1,
 315                 .thold  = FSMC_THOLD_4,
 316                 .twait  = FSMC_TWAIT_6,
 317                 .tset   = FSMC_TSET_0,
 318         };
 319
 320         if (timings)
 321                 tims = timings;
 322         else
 323                 tims = &default_timings;
 324
 325         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 326         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 327         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 328         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 329         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 330         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 331
 332         if (busw)
 333                 writel_relaxed(value | FSMC_DEVWID_16,
 334                                 FSMC_NAND_REG(regs, bank, PC));
 335         else
 336                 writel_relaxed(value | FSMC_DEVWID_8,
 337                                 FSMC_NAND_REG(regs, bank, PC));
 338
 339         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 340                         FSMC_NAND_REG(regs, bank, PC));
 341         writel_relaxed(thiz | thold | twait | tset,
 342                         FSMC_NAND_REG(regs, bank, COMM));
 343         writel_relaxed(thiz | thold | twait | tset,
 344                         FSMC_NAND_REG(regs, bank, ATTRIB));
 345 }
 346
 347 /*
 348  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 349  */
 350 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 351 {
 352         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 353         void __iomem *regs = host->regs_va;
 354         uint32_t bank = host->bank;
 355
 356         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 357                         FSMC_NAND_REG(regs, bank, PC));
 358         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 359                         FSMC_NAND_REG(regs, bank, PC));
 360         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 361                         FSMC_NAND_REG(regs, bank, PC));
 362 }
 363
 364 /*
 365  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 366  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 367  * max of 8-bits)
 368  */
 369 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 370                                 uint8_t *ecc)
 371 {
 372         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 373         void __iomem *regs = host->regs_va;
 374         uint32_t bank = host->bank;
 375         uint32_t ecc_tmp;
 376         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 377
 378         do {
 379                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 380                         break;
 381                 else
 382                         cond_resched();
 383         } while (!time_after_eq(jiffies, deadline));
 384
 385         if (time_after_eq(jiffies, deadline)) {
 386                 dev_err(host->dev, "calculate ecc timed out\n");
 387                 return -ETIMEDOUT;
 388         }
 389
 390         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 391         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 392         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 393         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 394         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 395
 396         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 397         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 398         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 399         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 400         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 401
 402         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 403         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 404         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 405         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 406         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 407
 408         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 409         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 410
 411         return 0;
 412 }
 413
 414 /*
 415  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 416  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 417  * max of 1-bit)
 418  */
 419 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 420                                 uint8_t *ecc)
 421 {
 422         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 423         void __iomem *regs = host->regs_va;
 424         uint32_t bank = host->bank;
 425         uint32_t ecc_tmp;
 426
 427         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 428         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 429         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 430         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 431
 432         return 0;
 433 }
 434
 435 /* Count the number of 0's in buff upto a max of max_bits */
 436 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 437 {
 438         int k, written_bits = 0;
 439
 440         for (k = 0; k < size; k++) {
 441                 written_bits += hweight8(~buff[k]);
 442                 if (written_bits > max_bits)
 443                         break;
 444         }
 445
 446         return written_bits;
 447 }
 448
 449 static void dma_complete(void *param)
 450 {
 451         struct fsmc_nand_data *host = param;
 452
 453         complete(&host->dma_access_complete);
 454 }
 455
 456 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 457                 enum dma_data_direction direction)
 458 {
 459         struct dma_chan *chan;
 460         struct dma_device *dma_dev;
 461         struct dma_async_tx_descriptor *tx;
 462         dma_addr_t dma_dst, dma_src, dma_addr;
 463         dma_cookie_t cookie;
 464         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 465         int ret;
 466         unsigned long time_left;
 467
 468         if (direction == DMA_TO_DEVICE)
 469                 chan = host->write_dma_chan;
 470         else if (direction == DMA_FROM_DEVICE)
 471                 chan = host->read_dma_chan;
 472         else
 473                 return -EINVAL;
 474
 475         dma_dev = chan->device;
 476         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 477
 478         if (direction == DMA_TO_DEVICE) {
 479                 dma_src = dma_addr;
 480                 dma_dst = host->data_pa;
 481         } else {
 482                 dma_src = host->data_pa;
 483                 dma_dst = dma_addr;
 484         }
 485
 486         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 487                         len, flags);
 488         if (!tx) {
 489                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 490                 ret = -EIO;
 491                 goto unmap_dma;
 492         }
 493
 494         tx->callback = dma_complete;
 495         tx->callback_param = host;
 496         cookie = tx->tx_submit(tx);
 497
 498         ret = dma_submit_error(cookie);
 499         if (ret) {
 500                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 501                 goto unmap_dma;
 502         }
 503
 504         dma_async_issue_pending(chan);
 505
 506         time_left =
 507         wait_for_completion_timeout(&host->dma_access_complete,
 508                                 msecs_to_jiffies(3000));
 509         if (time_left == 0) {
 510                 dmaengine_terminate_all(chan);
 511                 dev_err(host->dev, "wait_for_completion_timeout\n");
 512                 ret = -ETIMEDOUT;
 513                 goto unmap_dma;
 514         }
 515
 516         ret = 0;
 517
 518 unmap_dma:
 519         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 520
 521         return ret;
 522 }
 523
 524 /*
 525  * fsmc_write_buf - write buffer to chip
 526  * @mtd:        MTD device structure
 527  * @buf:        data buffer
 528  * @len:        number of bytes to write
 529  */
 530 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 531 {
 532         int i;
 533         struct nand_chip *chip = mtd_to_nand(mtd);
 534
 535         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 536                         IS_ALIGNED(len, sizeof(uint32_t))) {
 537                 uint32_t *p = (uint32_t *)buf;
 538                 len = len >> 2;
 539                 for (i = 0; i < len; i++)
 540                         writel_relaxed(p[i], chip->IO_ADDR_W);
 541         } else {
 542                 for (i = 0; i < len; i++)
 543                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 544         }
 545 }
 546
 547 /*
 548  * fsmc_read_buf - read chip data into buffer
 549  * @mtd:        MTD device structure
 550  * @buf:        buffer to store date
 551  * @len:        number of bytes to read
 552  */
 553 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 554 {
 555         int i;
 556         struct nand_chip *chip = mtd_to_nand(mtd);
 557
 558         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 559                         IS_ALIGNED(len, sizeof(uint32_t))) {
 560                 uint32_t *p = (uint32_t *)buf;
 561                 len = len >> 2;
 562                 for (i = 0; i < len; i++)
 563                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 564         } else {
 565                 for (i = 0; i < len; i++)
 566                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 567         }
 568 }
 569
 570 /*
 571  * fsmc_read_buf_dma - read chip data into buffer
 572  * @mtd:        MTD device structure
 573  * @buf:        buffer to store date
 574  * @len:        number of bytes to read
 575  */
 576 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 577 {
 578         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 579
 580         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 581 }
 582
 583 /*
 584  * fsmc_write_buf_dma - write buffer to chip
 585  * @mtd:        MTD device structure
 586  * @buf:        data buffer
 587  * @len:        number of bytes to write
 588  */
 589 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 590                 int len)
 591 {
 592         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 593
 594         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 595 }
 596
 597 /*
 598  * fsmc_read_page_hwecc
 599  * @mtd:        mtd info structure
 600  * @chip:       nand chip info structure
 601  * @buf:        buffer to store read data
 602  * @oob_required:       caller expects OOB data read to chip->oob_poi
 603  * @page:       page number to read
 604  *
 605  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 606  * performed in a strict sequence as follows:
 607  * data(512 byte) -> ecc(13 byte)
 608  * After this read, fsmc hardware generates and reports error data bits(up to a
 609  * max of 8 bits)
 610  */
 611 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 612                                  uint8_t *buf, int oob_required, int page)
 613 {
 614         int i, j, s, stat, eccsize = chip->ecc.size;
 615         int eccbytes = chip->ecc.bytes;
 616         int eccsteps = chip->ecc.steps;
 617         uint8_t *p = buf;
 618         uint8_t *ecc_calc = chip->buffers->ecccalc;
 619         uint8_t *ecc_code = chip->buffers->ecccode;
 620         int off, len, group = 0;
 621         /*
 622          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 623          * end up reading 14 bytes (7 words) from oob. The local array is
 624          * to maintain word alignment
 625          */
 626         uint16_t ecc_oob[7];
 627         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 628         unsigned int max_bitflips = 0;
 629
 630         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 631                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 632                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 633                 chip->read_buf(mtd, p, eccsize);
 634
 635                 for (j = 0; j < eccbytes;) {
 636                         struct mtd_oob_region oobregion;
 637                         int ret;
 638
 639                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 640                         if (ret)
 641                                 return ret;
 642
 643                         off = oobregion.offset;
 644                         len = oobregion.length;
 645
 646                         /*
 647                          * length is intentionally kept a higher multiple of 2
 648                          * to read at least 13 bytes even in case of 16 bit NAND
 649                          * devices
 650                          */
 651                         if (chip->options & NAND_BUSWIDTH_16)
 652                                 len = roundup(len, 2);
 653
 654                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 655                         chip->read_buf(mtd, oob + j, len);
 656                         j += len;
 657                 }
 658
 659                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 660                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 661
 662                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 663                 if (stat < 0) {
 664                         mtd->ecc_stats.failed++;
 665                 } else {
 666                         mtd->ecc_stats.corrected += stat;
 667                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 668                 }
 669         }
 670
 671         return max_bitflips;
 672 }
 673
 674 /*
 675  * fsmc_bch8_correct_data
 676  * @mtd:        mtd info structure
 677  * @dat:        buffer of read data
 678  * @read_ecc:   ecc read from device spare area
 679  * @calc_ecc:   ecc calculated from read data
 680  *
 681  * calc_ecc is a 104 bit information containing maximum of 8 error
 682  * offset informations of 13 bits each in 512 bytes of read data.
 683  */
 684 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 685                              uint8_t *read_ecc, uint8_t *calc_ecc)
 686 {
 687         struct nand_chip *chip = mtd_to_nand(mtd);
 688         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 689         void __iomem *regs = host->regs_va;
 690         unsigned int bank = host->bank;
 691         uint32_t err_idx[8];
 692         uint32_t num_err, i;
 693         uint32_t ecc1, ecc2, ecc3, ecc4;
 694
 695         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 696
 697         /* no bit flipping */
 698         if (likely(num_err == 0))
 699                 return 0;
 700
 701         /* too many errors */
 702         if (unlikely(num_err > 8)) {
 703                 /*
 704                  * This is a temporary erase check. A newly erased page read
 705                  * would result in an ecc error because the oob data is also
 706                  * erased to FF and the calculated ecc for an FF data is not
 707                  * FF..FF.
 708                  * This is a workaround to skip performing correction in case
 709                  * data is FF..FF
 710                  *
 711                  * Logic:
 712                  * For every page, each bit written as 0 is counted until these
 713                  * number of bits are greater than 8 (the maximum correction
 714                  * capability of FSMC for each 512 + 13 bytes)
 715                  */
 716
 717                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 718                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 719
 720                 if ((bits_ecc + bits_data) <= 8) {
 721                         if (bits_data)
 722                                 memset(dat, 0xff, chip->ecc.size);
 723                         return bits_data;
 724                 }
 725
 726                 return -EBADMSG;
 727         }
 728
 729         /*
 730          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 731          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 732          *
 733          * calc_ecc is a 104 bit information containing maximum of 8 error
 734          * offset informations of 13 bits each. calc_ecc is copied into a
 735          * uint64_t array and error offset indexes are populated in err_idx
 736          * array
 737          */
 738         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 739         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 740         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 741         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 742
 743         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 744         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 745         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 746         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 747         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 748         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 749         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 750         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 751
 752         i = 0;
 753         while (num_err--) {
 754                 change_bit(0, (unsigned long *)&err_idx[i]);
 755                 change_bit(1, (unsigned long *)&err_idx[i]);
 756
 757                 if (err_idx[i] < chip->ecc.size * 8) {
 758                         change_bit(err_idx[i], (unsigned long *)dat);
 759                         i++;
 760                 }
 761         }
 762         return i;
 763 }
 764
 765 static bool filter(struct dma_chan *chan, void *slave)
 766 {
 767         chan->private = slave;
 768         return true;
 769 }
 770
 771 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 772                                      struct fsmc_nand_data *host,
 773                                      struct nand_chip *nand)
 774 {
 775         struct device_node *np = pdev->dev.of_node;
 776         u32 val;
 777         int ret;
 778
 779         nand->options = 0;
 780
 781         if (!of_property_read_u32(np, "bank-width", &val)) {
 782                 if (val == 2) {
 783                         nand->options |= NAND_BUSWIDTH_16;
 784                 } else if (val != 1) {
 785                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 786                         return -EINVAL;
 787                 }
 788         }
 789
 790         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 791                 nand->options |= NAND_SKIP_BBTSCAN;
 792
 793         host->dev_timings = devm_kzalloc(&pdev->dev,
 794                                 sizeof(*host->dev_timings), GFP_KERNEL);
 795         if (!host->dev_timings)
 796                 return -ENOMEM;
 797         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 798                                                 sizeof(*host->dev_timings));
 799         if (ret) {
 800                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 801                 host->dev_timings = NULL;
 802         }
 803
 804         /* Set default NAND bank to 0 */
 805         host->bank = 0;
 806         if (!of_property_read_u32(np, "bank", &val)) {
 807                 if (val > 3) {
 808                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 809                         return -EINVAL;
 810                 }
 811                 host->bank = val;
 812         }
 813         return 0;
 814 }
 815
 816 /*
 817  * fsmc_nand_probe - Probe function
 818  * @pdev:       platform device structure
 819  */
 820 static int __init fsmc_nand_probe(struct platform_device *pdev)
 821 {
 822         struct fsmc_nand_data *host;
 823         struct mtd_info *mtd;
 824         struct nand_chip *nand;
 825         struct resource *res;
 826         dma_cap_mask_t mask;
 827         int ret = 0;
 828         u32 pid;
 829         int i;
 830
 831         /* Allocate memory for the device structure (and zero it) */
 832         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 833         if (!host)
 834                 return -ENOMEM;
 835
 836         nand = &host->nand;
 837
 838         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
 839         if (ret)
 840                 return ret;
 841
 842         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 843         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 844         if (IS_ERR(host->data_va))
 845                 return PTR_ERR(host->data_va);
 846
 847         host->data_pa = (dma_addr_t)res->start;
 848
 849         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 850         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 851         if (IS_ERR(host->addr_va))
 852                 return PTR_ERR(host->addr_va);
 853
 854         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 855         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 856         if (IS_ERR(host->cmd_va))
 857                 return PTR_ERR(host->cmd_va);
 858
 859         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 860         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 861         if (IS_ERR(host->regs_va))
 862                 return PTR_ERR(host->regs_va);
 863
 864         host->clk = devm_clk_get(&pdev->dev, NULL);
 865         if (IS_ERR(host->clk)) {
 866                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 867                 return PTR_ERR(host->clk);
 868         }
 869
 870         ret = clk_prepare_enable(host->clk);
 871         if (ret)
 872                 return ret;
 873
 874         /*
 875          * This device ID is actually a common AMBA ID as used on the
 876          * AMBA PrimeCell bus. However it is not a PrimeCell.
 877          */
 878         for (pid = 0, i = 0; i < 4; i++)
 879                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 880         host->pid = pid;
 881         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 882                  "revision %02x, config %02x\n",
 883                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 884                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 885
 886         host->dev = &pdev->dev;
 887
 888         if (host->mode == USE_DMA_ACCESS)
 889                 init_completion(&host->dma_access_complete);
 890
 891         /* Link all private pointers */
 892         mtd = nand_to_mtd(&host->nand);
 893         nand_set_controller_data(nand, host);
 894         nand_set_flash_node(nand, pdev->dev.of_node);
 895
 896         mtd->dev.parent = &pdev->dev;
 897         nand->IO_ADDR_R = host->data_va;
 898         nand->IO_ADDR_W = host->data_va;
 899         nand->cmd_ctrl = fsmc_cmd_ctrl;
 900         nand->chip_delay = 30;
 901
 902         /*
 903          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 904          * can overwrite this value if the DT provides a different value.
 905          */
 906         nand->ecc.mode = NAND_ECC_HW;
 907         nand->ecc.hwctl = fsmc_enable_hwecc;
 908         nand->ecc.size = 512;
 909         nand->badblockbits = 7;
 910
 911         switch (host->mode) {
 912         case USE_DMA_ACCESS:
 913                 dma_cap_zero(mask);
 914                 dma_cap_set(DMA_MEMCPY, mask);
 915                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
 916                 if (!host->read_dma_chan) {
 917                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
 918                         goto err_req_read_chnl;
 919                 }
 920                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
 921                 if (!host->write_dma_chan) {
 922                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
 923                         goto err_req_write_chnl;
 924                 }
 925                 nand->read_buf = fsmc_read_buf_dma;
 926                 nand->write_buf = fsmc_write_buf_dma;
 927                 break;
 928
 929         default:
 930         case USE_WORD_ACCESS:
 931                 nand->read_buf = fsmc_read_buf;
 932                 nand->write_buf = fsmc_write_buf;
 933                 break;
 934         }
 935
 936         fsmc_nand_setup(host->regs_va, host->bank,
 937                         nand->options & NAND_BUSWIDTH_16,
 938                         host->dev_timings);
 939
 940         if (AMBA_REV_BITS(host->pid) >= 8) {
 941                 nand->ecc.read_page = fsmc_read_page_hwecc;
 942                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 943                 nand->ecc.correct = fsmc_bch8_correct_data;
 944                 nand->ecc.bytes = 13;
 945                 nand->ecc.strength = 8;
 946         }
 947
 948         /*
 949          * Scan to find existence of the device
 950          */
 951         ret = nand_scan_ident(mtd, 1, NULL);
 952         if (ret) {
 953                 dev_err(&pdev->dev, "No NAND Device found!\n");
 954                 goto err_scan_ident;
 955         }
 956
 957         if (AMBA_REV_BITS(host->pid) >= 8) {
 958                 switch (mtd->oobsize) {
 959                 case 16:
 960                 case 64:
 961                 case 128:
 962                 case 224:
 963                 case 256:
 964                         break;
 965                 default:
 966                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
 967                                  mtd->oobsize);
 968                         ret = -EINVAL;
 969                         goto err_probe;
 970                 }
 971
 972                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
 973         } else {
 974                 switch (nand->ecc.mode) {
 975                 case NAND_ECC_HW:
 976                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
 977                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
 978                         nand->ecc.correct = nand_correct_data;
 979                         nand->ecc.bytes = 3;
 980                         nand->ecc.strength = 1;
 981                         break;
 982
 983                 case NAND_ECC_SOFT:
 984                         if (nand->ecc.algo == NAND_ECC_BCH) {
 985                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 986                                 break;
 987                         }
 988
 989                 default:
 990                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
 991                         goto err_probe;
 992                 }
 993
 994                 /*
 995                  * Don't set layout for BCH4 SW ECC. This will be
 996                  * generated later in nand_bch_init() later.
 997                  */
 998                 if (nand->ecc.mode == NAND_ECC_HW) {
 999                         switch (mtd->oobsize) {
1000                         case 16:
1001                         case 64:
1002                         case 128:
1003                                 mtd_set_ooblayout(mtd,
1004                                                   &fsmc_ecc1_ooblayout_ops);
1005                                 break;
1006                         default:
1007                                 dev_warn(&pdev->dev,
1008                                          "No oob scheme defined for oobsize %d\n",
1009                                          mtd->oobsize);
1010                                 ret = -EINVAL;
1011                                 goto err_probe;
1012                         }
1013                 }
1014         }
1015
1016         /* Second stage of scan to fill MTD data-structures */
1017         ret = nand_scan_tail(mtd);
1018         if (ret)
1019                 goto err_probe;
1020
1021         mtd->name = "nand";
1022         ret = mtd_device_register(mtd, NULL, 0);
1023         if (ret)
1024                 goto err_probe;
1025
1026         platform_set_drvdata(pdev, host);
1027         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1028         return 0;
1029
1030 err_probe:
1031 err_scan_ident:
1032         if (host->mode == USE_DMA_ACCESS)
1033                 dma_release_channel(host->write_dma_chan);
1034 err_req_write_chnl:
1035         if (host->mode == USE_DMA_ACCESS)
1036                 dma_release_channel(host->read_dma_chan);
1037 err_req_read_chnl:
1038         clk_disable_unprepare(host->clk);
1039         return ret;
1040 }
1041
1042 /*
1043  * Clean up routine
1044  */
1045 static int fsmc_nand_remove(struct platform_device *pdev)
1046 {
1047         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1048
1049         if (host) {
1050                 nand_release(nand_to_mtd(&host->nand));
1051
1052                 if (host->mode == USE_DMA_ACCESS) {
1053                         dma_release_channel(host->write_dma_chan);
1054                         dma_release_channel(host->read_dma_chan);
1055                 }
1056                 clk_disable_unprepare(host->clk);
1057         }
1058
1059         return 0;
1060 }
1061
1062 #ifdef CONFIG_PM_SLEEP
1063 static int fsmc_nand_suspend(struct device *dev)
1064 {
1065         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1066         if (host)
1067                 clk_disable_unprepare(host->clk);
1068         return 0;
1069 }
1070
1071 static int fsmc_nand_resume(struct device *dev)
1072 {
1073         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1074         if (host) {
1075                 clk_prepare_enable(host->clk);
1076                 fsmc_nand_setup(host->regs_va, host->bank,
1077                                 host->nand.options & NAND_BUSWIDTH_16,
1078                                 host->dev_timings);
1079         }
1080         return 0;
1081 }
1082 #endif
1083
1084 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1085
1086 static const struct of_device_id fsmc_nand_id_table[] = {
1087         { .compatible = "st,spear600-fsmc-nand" },
1088         { .compatible = "stericsson,fsmc-nand" },
1089         {}
1090 };
1091 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1092
1093 static struct platform_driver fsmc_nand_driver = {
1094         .remove = fsmc_nand_remove,
1095         .driver = {
1096                 .name = "fsmc-nand",
1097                 .of_match_table = fsmc_nand_id_table,
1098                 .pm = &fsmc_nand_pm_ops,
1099         },
1100 };
1101
1102 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1103
1104 MODULE_LICENSE("GPL");
1105 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1106 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");