drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 #define FSMC_NAND_BW8           1
  42 #define FSMC_NAND_BW16          2
  43
  44 #define FSMC_MAX_NOR_BANKS      4
  45 #define FSMC_MAX_NAND_BANKS     4
  46
  47 #define FSMC_FLASH_WIDTH8       1
  48 #define FSMC_FLASH_WIDTH16      2
  49
  50 /* fsmc controller registers for NOR flash */
  51 #define CTRL                    0x0
  52         /* ctrl register definitions */
  53         #define BANK_ENABLE             (1 << 0)
  54         #define MUXED                   (1 << 1)
  55         #define NOR_DEV                 (2 << 2)
  56         #define WIDTH_8                 (0 << 4)
  57         #define WIDTH_16                (1 << 4)
  58         #define RSTPWRDWN               (1 << 6)
  59         #define WPROT                   (1 << 7)
  60         #define WRT_ENABLE              (1 << 12)
  61         #define WAIT_ENB                (1 << 13)
  62
  63 #define CTRL_TIM                0x4
  64         /* ctrl_tim register definitions */
  65
  66 #define FSMC_NOR_BANK_SZ        0x8
  67 #define FSMC_NOR_REG_SIZE       0x40
  68
  69 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  70                                                 FSMC_NOR_BANK_SZ * (bank) + \
  71                                                 reg)
  72
  73 /* fsmc controller registers for NAND flash */
  74 #define PC                      0x00
  75         /* pc register definitions */
  76         #define FSMC_RESET              (1 << 0)
  77         #define FSMC_WAITON             (1 << 1)
  78         #define FSMC_ENABLE             (1 << 2)
  79         #define FSMC_DEVTYPE_NAND       (1 << 3)
  80         #define FSMC_DEVWID_8           (0 << 4)
  81         #define FSMC_DEVWID_16          (1 << 4)
  82         #define FSMC_ECCEN              (1 << 6)
  83         #define FSMC_ECCPLEN_512        (0 << 7)
  84         #define FSMC_ECCPLEN_256        (1 << 7)
  85         #define FSMC_TCLR_1             (1)
  86         #define FSMC_TCLR_SHIFT         (9)
  87         #define FSMC_TCLR_MASK          (0xF)
  88         #define FSMC_TAR_1              (1)
  89         #define FSMC_TAR_SHIFT          (13)
  90         #define FSMC_TAR_MASK           (0xF)
  91 #define STS                     0x04
  92         /* sts register definitions */
  93         #define FSMC_CODE_RDY           (1 << 15)
  94 #define COMM                    0x08
  95         /* comm register definitions */
  96         #define FSMC_TSET_0             0
  97         #define FSMC_TSET_SHIFT         0
  98         #define FSMC_TSET_MASK          0xFF
  99         #define FSMC_TWAIT_6            6
 100         #define FSMC_TWAIT_SHIFT        8
 101         #define FSMC_TWAIT_MASK         0xFF
 102         #define FSMC_THOLD_4            4
 103         #define FSMC_THOLD_SHIFT        16
 104         #define FSMC_THOLD_MASK         0xFF
 105         #define FSMC_THIZ_1             1
 106         #define FSMC_THIZ_SHIFT         24
 107         #define FSMC_THIZ_MASK          0xFF
 108 #define ATTRIB                  0x0C
 109 #define IOATA                   0x10
 110 #define ECC1                    0x14
 111 #define ECC2                    0x18
 112 #define ECC3                    0x1C
 113 #define FSMC_NAND_BANK_SZ       0x20
 114
 115 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 116                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 117                                                 reg)
 118
 119 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 120
 121 struct fsmc_nand_timings {
 122         uint8_t tclr;
 123         uint8_t tar;
 124         uint8_t thiz;
 125         uint8_t thold;
 126         uint8_t twait;
 127         uint8_t tset;
 128 };
 129
 130 enum access_mode {
 131         USE_DMA_ACCESS = 1,
 132         USE_WORD_ACCESS,
 133 };
 134
 135 /**
 136  * fsmc_nand_platform_data - platform specific NAND controller config
 137  * @nand_timings: timing setup for the physical NAND interface
 138  * @partitions: partition table for the platform, use a default fallback
 139  * if this is NULL
 140  * @nr_partitions: the number of partitions in the previous entry
 141  * @options: different options for the driver
 142  * @width: bus width
 143  * @bank: default bank
 144  * @select_bank: callback to select a certain bank, this is
 145  * platform-specific. If the controller only supports one bank
 146  * this may be set to NULL
 147  */
 148 struct fsmc_nand_platform_data {
 149         struct fsmc_nand_timings *nand_timings;
 150         struct mtd_partition    *partitions;
 151         unsigned int            nr_partitions;
 152         unsigned int            options;
 153         unsigned int            width;
 154         unsigned int            bank;
 155
 156         enum access_mode        mode;
 157
 158         void                    (*select_bank)(uint32_t bank, uint32_t busw);
 159
 160         /* priv structures for dma accesses */
 161         void                    *read_dma_priv;
 162         void                    *write_dma_priv;
 163 };
 164
 165 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 166                                    struct mtd_oob_region *oobregion)
 167 {
 168         struct nand_chip *chip = mtd_to_nand(mtd);
 169
 170         if (section >= chip->ecc.steps)
 171                 return -ERANGE;
 172
 173         oobregion->offset = (section * 16) + 2;
 174         oobregion->length = 3;
 175
 176         return 0;
 177 }
 178
 179 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 180                                     struct mtd_oob_region *oobregion)
 181 {
 182         struct nand_chip *chip = mtd_to_nand(mtd);
 183
 184         if (section >= chip->ecc.steps)
 185                 return -ERANGE;
 186
 187         oobregion->offset = (section * 16) + 8;
 188
 189         if (section < chip->ecc.steps - 1)
 190                 oobregion->length = 8;
 191         else
 192                 oobregion->length = mtd->oobsize - oobregion->offset;
 193
 194         return 0;
 195 }
 196
 197 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 198         .ecc = fsmc_ecc1_ooblayout_ecc,
 199         .free = fsmc_ecc1_ooblayout_free,
 200 };
 201
 202 /*
 203  * ECC placement definitions in oobfree type format.
 204  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 205  * consecutively and immediately after the 512 byte data block for hardware to
 206  * generate the error bit offsets in 512 byte data.
 207  */
 208 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 209                                    struct mtd_oob_region *oobregion)
 210 {
 211         struct nand_chip *chip = mtd_to_nand(mtd);
 212
 213         if (section >= chip->ecc.steps)
 214                 return -ERANGE;
 215
 216         oobregion->length = chip->ecc.bytes;
 217
 218         if (!section && mtd->writesize <= 512)
 219                 oobregion->offset = 0;
 220         else
 221                 oobregion->offset = (section * 16) + 2;
 222
 223         return 0;
 224 }
 225
 226 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 227                                     struct mtd_oob_region *oobregion)
 228 {
 229         struct nand_chip *chip = mtd_to_nand(mtd);
 230
 231         if (section >= chip->ecc.steps)
 232                 return -ERANGE;
 233
 234         oobregion->offset = (section * 16) + 15;
 235
 236         if (section < chip->ecc.steps - 1)
 237                 oobregion->length = 3;
 238         else
 239                 oobregion->length = mtd->oobsize - oobregion->offset;
 240
 241         return 0;
 242 }
 243
 244 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 245         .ecc = fsmc_ecc4_ooblayout_ecc,
 246         .free = fsmc_ecc4_ooblayout_free,
 247 };
 248
 249 /**
 250  * struct fsmc_nand_data - structure for FSMC NAND device state
 251  *
 252  * @pid:                Part ID on the AMBA PrimeCell format
 253  * @mtd:                MTD info for a NAND flash.
 254  * @nand:               Chip related info for a NAND flash.
 255  * @partitions:         Partition info for a NAND Flash.
 256  * @nr_partitions:      Total number of partition of a NAND flash.
 257  *
 258  * @bank:               Bank number for probed device.
 259  * @clk:                Clock structure for FSMC.
 260  *
 261  * @read_dma_chan:      DMA channel for read access
 262  * @write_dma_chan:     DMA channel for write access to NAND
 263  * @dma_access_complete: Completion structure
 264  *
 265  * @data_pa:            NAND Physical port for Data.
 266  * @data_va:            NAND port for Data.
 267  * @cmd_va:             NAND port for Command.
 268  * @addr_va:            NAND port for Address.
 269  * @regs_va:            FSMC regs base address.
 270  */
 271 struct fsmc_nand_data {
 272         u32                     pid;
 273         struct nand_chip        nand;
 274         struct mtd_partition    *partitions;
 275         unsigned int            nr_partitions;
 276
 277         unsigned int            bank;
 278         struct device           *dev;
 279         enum access_mode        mode;
 280         struct clk              *clk;
 281
 282         /* DMA related objects */
 283         struct dma_chan         *read_dma_chan;
 284         struct dma_chan         *write_dma_chan;
 285         struct completion       dma_access_complete;
 286
 287         struct fsmc_nand_timings *dev_timings;
 288
 289         dma_addr_t              data_pa;
 290         void __iomem            *data_va;
 291         void __iomem            *cmd_va;
 292         void __iomem            *addr_va;
 293         void __iomem            *regs_va;
 294
 295         void                    (*select_chip)(uint32_t bank, uint32_t busw);
 296 };
 297
 298 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 299 {
 300         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 301 }
 302
 303 /* Assert CS signal based on chipnr */
 304 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
 305 {
 306         struct nand_chip *chip = mtd_to_nand(mtd);
 307         struct fsmc_nand_data *host;
 308
 309         host = mtd_to_fsmc(mtd);
 310
 311         switch (chipnr) {
 312         case -1:
 313                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 314                 break;
 315         case 0:
 316         case 1:
 317         case 2:
 318         case 3:
 319                 if (host->select_chip)
 320                         host->select_chip(chipnr,
 321                                         chip->options & NAND_BUSWIDTH_16);
 322                 break;
 323
 324         default:
 325                 dev_err(host->dev, "unsupported chip-select %d\n", chipnr);
 326         }
 327 }
 328
 329 /*
 330  * fsmc_cmd_ctrl - For facilitaing Hardware access
 331  * This routine allows hardware specific access to control-lines(ALE,CLE)
 332  */
 333 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 334 {
 335         struct nand_chip *this = mtd_to_nand(mtd);
 336         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 337         void __iomem *regs = host->regs_va;
 338         unsigned int bank = host->bank;
 339
 340         if (ctrl & NAND_CTRL_CHANGE) {
 341                 u32 pc;
 342
 343                 if (ctrl & NAND_CLE) {
 344                         this->IO_ADDR_R = host->cmd_va;
 345                         this->IO_ADDR_W = host->cmd_va;
 346                 } else if (ctrl & NAND_ALE) {
 347                         this->IO_ADDR_R = host->addr_va;
 348                         this->IO_ADDR_W = host->addr_va;
 349                 } else {
 350                         this->IO_ADDR_R = host->data_va;
 351                         this->IO_ADDR_W = host->data_va;
 352                 }
 353
 354                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 355                 if (ctrl & NAND_NCE)
 356                         pc |= FSMC_ENABLE;
 357                 else
 358                         pc &= ~FSMC_ENABLE;
 359                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 360         }
 361
 362         mb();
 363
 364         if (cmd != NAND_CMD_NONE)
 365                 writeb_relaxed(cmd, this->IO_ADDR_W);
 366 }
 367
 368 /*
 369  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 370  *
 371  * This routine initializes timing parameters related to NAND memory access in
 372  * FSMC registers
 373  */
 374 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
 375                            uint32_t busw, struct fsmc_nand_timings *timings)
 376 {
 377         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 378         uint32_t tclr, tar, thiz, thold, twait, tset;
 379         struct fsmc_nand_timings *tims;
 380         struct fsmc_nand_timings default_timings = {
 381                 .tclr   = FSMC_TCLR_1,
 382                 .tar    = FSMC_TAR_1,
 383                 .thiz   = FSMC_THIZ_1,
 384                 .thold  = FSMC_THOLD_4,
 385                 .twait  = FSMC_TWAIT_6,
 386                 .tset   = FSMC_TSET_0,
 387         };
 388
 389         if (timings)
 390                 tims = timings;
 391         else
 392                 tims = &default_timings;
 393
 394         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 395         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 396         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 397         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 398         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 399         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 400
 401         if (busw)
 402                 writel_relaxed(value | FSMC_DEVWID_16,
 403                                 FSMC_NAND_REG(regs, bank, PC));
 404         else
 405                 writel_relaxed(value | FSMC_DEVWID_8,
 406                                 FSMC_NAND_REG(regs, bank, PC));
 407
 408         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 409                         FSMC_NAND_REG(regs, bank, PC));
 410         writel_relaxed(thiz | thold | twait | tset,
 411                         FSMC_NAND_REG(regs, bank, COMM));
 412         writel_relaxed(thiz | thold | twait | tset,
 413                         FSMC_NAND_REG(regs, bank, ATTRIB));
 414 }
 415
 416 /*
 417  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 418  */
 419 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 420 {
 421         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 422         void __iomem *regs = host->regs_va;
 423         uint32_t bank = host->bank;
 424
 425         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 426                         FSMC_NAND_REG(regs, bank, PC));
 427         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 428                         FSMC_NAND_REG(regs, bank, PC));
 429         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 430                         FSMC_NAND_REG(regs, bank, PC));
 431 }
 432
 433 /*
 434  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 435  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 436  * max of 8-bits)
 437  */
 438 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 439                                 uint8_t *ecc)
 440 {
 441         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 442         void __iomem *regs = host->regs_va;
 443         uint32_t bank = host->bank;
 444         uint32_t ecc_tmp;
 445         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 446
 447         do {
 448                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 449                         break;
 450                 else
 451                         cond_resched();
 452         } while (!time_after_eq(jiffies, deadline));
 453
 454         if (time_after_eq(jiffies, deadline)) {
 455                 dev_err(host->dev, "calculate ecc timed out\n");
 456                 return -ETIMEDOUT;
 457         }
 458
 459         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 460         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 461         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 462         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 463         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 464
 465         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 466         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 467         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 468         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 469         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 470
 471         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 472         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 473         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 474         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 475         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 476
 477         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 478         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 479
 480         return 0;
 481 }
 482
 483 /*
 484  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 485  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 486  * max of 1-bit)
 487  */
 488 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 489                                 uint8_t *ecc)
 490 {
 491         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 492         void __iomem *regs = host->regs_va;
 493         uint32_t bank = host->bank;
 494         uint32_t ecc_tmp;
 495
 496         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 497         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 498         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 499         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 500
 501         return 0;
 502 }
 503
 504 /* Count the number of 0's in buff upto a max of max_bits */
 505 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 506 {
 507         int k, written_bits = 0;
 508
 509         for (k = 0; k < size; k++) {
 510                 written_bits += hweight8(~buff[k]);
 511                 if (written_bits > max_bits)
 512                         break;
 513         }
 514
 515         return written_bits;
 516 }
 517
 518 static void dma_complete(void *param)
 519 {
 520         struct fsmc_nand_data *host = param;
 521
 522         complete(&host->dma_access_complete);
 523 }
 524
 525 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 526                 enum dma_data_direction direction)
 527 {
 528         struct dma_chan *chan;
 529         struct dma_device *dma_dev;
 530         struct dma_async_tx_descriptor *tx;
 531         dma_addr_t dma_dst, dma_src, dma_addr;
 532         dma_cookie_t cookie;
 533         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 534         int ret;
 535         unsigned long time_left;
 536
 537         if (direction == DMA_TO_DEVICE)
 538                 chan = host->write_dma_chan;
 539         else if (direction == DMA_FROM_DEVICE)
 540                 chan = host->read_dma_chan;
 541         else
 542                 return -EINVAL;
 543
 544         dma_dev = chan->device;
 545         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 546
 547         if (direction == DMA_TO_DEVICE) {
 548                 dma_src = dma_addr;
 549                 dma_dst = host->data_pa;
 550         } else {
 551                 dma_src = host->data_pa;
 552                 dma_dst = dma_addr;
 553         }
 554
 555         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 556                         len, flags);
 557         if (!tx) {
 558                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 559                 ret = -EIO;
 560                 goto unmap_dma;
 561         }
 562
 563         tx->callback = dma_complete;
 564         tx->callback_param = host;
 565         cookie = tx->tx_submit(tx);
 566
 567         ret = dma_submit_error(cookie);
 568         if (ret) {
 569                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 570                 goto unmap_dma;
 571         }
 572
 573         dma_async_issue_pending(chan);
 574
 575         time_left =
 576         wait_for_completion_timeout(&host->dma_access_complete,
 577                                 msecs_to_jiffies(3000));
 578         if (time_left == 0) {
 579                 dmaengine_terminate_all(chan);
 580                 dev_err(host->dev, "wait_for_completion_timeout\n");
 581                 ret = -ETIMEDOUT;
 582                 goto unmap_dma;
 583         }
 584
 585         ret = 0;
 586
 587 unmap_dma:
 588         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 589
 590         return ret;
 591 }
 592
 593 /*
 594  * fsmc_write_buf - write buffer to chip
 595  * @mtd:        MTD device structure
 596  * @buf:        data buffer
 597  * @len:        number of bytes to write
 598  */
 599 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 600 {
 601         int i;
 602         struct nand_chip *chip = mtd_to_nand(mtd);
 603
 604         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 605                         IS_ALIGNED(len, sizeof(uint32_t))) {
 606                 uint32_t *p = (uint32_t *)buf;
 607                 len = len >> 2;
 608                 for (i = 0; i < len; i++)
 609                         writel_relaxed(p[i], chip->IO_ADDR_W);
 610         } else {
 611                 for (i = 0; i < len; i++)
 612                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 613         }
 614 }
 615
 616 /*
 617  * fsmc_read_buf - read chip data into buffer
 618  * @mtd:        MTD device structure
 619  * @buf:        buffer to store date
 620  * @len:        number of bytes to read
 621  */
 622 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 623 {
 624         int i;
 625         struct nand_chip *chip = mtd_to_nand(mtd);
 626
 627         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 628                         IS_ALIGNED(len, sizeof(uint32_t))) {
 629                 uint32_t *p = (uint32_t *)buf;
 630                 len = len >> 2;
 631                 for (i = 0; i < len; i++)
 632                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 633         } else {
 634                 for (i = 0; i < len; i++)
 635                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 636         }
 637 }
 638
 639 /*
 640  * fsmc_read_buf_dma - read chip data into buffer
 641  * @mtd:        MTD device structure
 642  * @buf:        buffer to store date
 643  * @len:        number of bytes to read
 644  */
 645 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 646 {
 647         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 648
 649         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 650 }
 651
 652 /*
 653  * fsmc_write_buf_dma - write buffer to chip
 654  * @mtd:        MTD device structure
 655  * @buf:        data buffer
 656  * @len:        number of bytes to write
 657  */
 658 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 659                 int len)
 660 {
 661         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 662
 663         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 664 }
 665
 666 /*
 667  * fsmc_read_page_hwecc
 668  * @mtd:        mtd info structure
 669  * @chip:       nand chip info structure
 670  * @buf:        buffer to store read data
 671  * @oob_required:       caller expects OOB data read to chip->oob_poi
 672  * @page:       page number to read
 673  *
 674  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 675  * performed in a strict sequence as follows:
 676  * data(512 byte) -> ecc(13 byte)
 677  * After this read, fsmc hardware generates and reports error data bits(up to a
 678  * max of 8 bits)
 679  */
 680 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 681                                  uint8_t *buf, int oob_required, int page)
 682 {
 683         int i, j, s, stat, eccsize = chip->ecc.size;
 684         int eccbytes = chip->ecc.bytes;
 685         int eccsteps = chip->ecc.steps;
 686         uint8_t *p = buf;
 687         uint8_t *ecc_calc = chip->buffers->ecccalc;
 688         uint8_t *ecc_code = chip->buffers->ecccode;
 689         int off, len, group = 0;
 690         /*
 691          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 692          * end up reading 14 bytes (7 words) from oob. The local array is
 693          * to maintain word alignment
 694          */
 695         uint16_t ecc_oob[7];
 696         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 697         unsigned int max_bitflips = 0;
 698
 699         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 700                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 701                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 702                 chip->read_buf(mtd, p, eccsize);
 703
 704                 for (j = 0; j < eccbytes;) {
 705                         struct mtd_oob_region oobregion;
 706                         int ret;
 707
 708                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 709                         if (ret)
 710                                 return ret;
 711
 712                         off = oobregion.offset;
 713                         len = oobregion.length;
 714
 715                         /*
 716                          * length is intentionally kept a higher multiple of 2
 717                          * to read at least 13 bytes even in case of 16 bit NAND
 718                          * devices
 719                          */
 720                         if (chip->options & NAND_BUSWIDTH_16)
 721                                 len = roundup(len, 2);
 722
 723                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 724                         chip->read_buf(mtd, oob + j, len);
 725                         j += len;
 726                 }
 727
 728                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 729                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 730
 731                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 732                 if (stat < 0) {
 733                         mtd->ecc_stats.failed++;
 734                 } else {
 735                         mtd->ecc_stats.corrected += stat;
 736                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 737                 }
 738         }
 739
 740         return max_bitflips;
 741 }
 742
 743 /*
 744  * fsmc_bch8_correct_data
 745  * @mtd:        mtd info structure
 746  * @dat:        buffer of read data
 747  * @read_ecc:   ecc read from device spare area
 748  * @calc_ecc:   ecc calculated from read data
 749  *
 750  * calc_ecc is a 104 bit information containing maximum of 8 error
 751  * offset informations of 13 bits each in 512 bytes of read data.
 752  */
 753 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 754                              uint8_t *read_ecc, uint8_t *calc_ecc)
 755 {
 756         struct nand_chip *chip = mtd_to_nand(mtd);
 757         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 758         void __iomem *regs = host->regs_va;
 759         unsigned int bank = host->bank;
 760         uint32_t err_idx[8];
 761         uint32_t num_err, i;
 762         uint32_t ecc1, ecc2, ecc3, ecc4;
 763
 764         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 765
 766         /* no bit flipping */
 767         if (likely(num_err == 0))
 768                 return 0;
 769
 770         /* too many errors */
 771         if (unlikely(num_err > 8)) {
 772                 /*
 773                  * This is a temporary erase check. A newly erased page read
 774                  * would result in an ecc error because the oob data is also
 775                  * erased to FF and the calculated ecc for an FF data is not
 776                  * FF..FF.
 777                  * This is a workaround to skip performing correction in case
 778                  * data is FF..FF
 779                  *
 780                  * Logic:
 781                  * For every page, each bit written as 0 is counted until these
 782                  * number of bits are greater than 8 (the maximum correction
 783                  * capability of FSMC for each 512 + 13 bytes)
 784                  */
 785
 786                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 787                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 788
 789                 if ((bits_ecc + bits_data) <= 8) {
 790                         if (bits_data)
 791                                 memset(dat, 0xff, chip->ecc.size);
 792                         return bits_data;
 793                 }
 794
 795                 return -EBADMSG;
 796         }
 797
 798         /*
 799          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 800          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 801          *
 802          * calc_ecc is a 104 bit information containing maximum of 8 error
 803          * offset informations of 13 bits each. calc_ecc is copied into a
 804          * uint64_t array and error offset indexes are populated in err_idx
 805          * array
 806          */
 807         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 808         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 809         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 810         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 811
 812         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 813         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 814         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 815         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 816         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 817         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 818         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 819         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 820
 821         i = 0;
 822         while (num_err--) {
 823                 change_bit(0, (unsigned long *)&err_idx[i]);
 824                 change_bit(1, (unsigned long *)&err_idx[i]);
 825
 826                 if (err_idx[i] < chip->ecc.size * 8) {
 827                         change_bit(err_idx[i], (unsigned long *)dat);
 828                         i++;
 829                 }
 830         }
 831         return i;
 832 }
 833
 834 static bool filter(struct dma_chan *chan, void *slave)
 835 {
 836         chan->private = slave;
 837         return true;
 838 }
 839
 840 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 841                                      struct device_node *np)
 842 {
 843         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 844         u32 val;
 845         int ret;
 846
 847         /* Set default NAND width to 8 bits */
 848         pdata->width = 8;
 849         if (!of_property_read_u32(np, "bank-width", &val)) {
 850                 if (val == 2) {
 851                         pdata->width = 16;
 852                 } else if (val != 1) {
 853                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 854                         return -EINVAL;
 855                 }
 856         }
 857         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 858                 pdata->options = NAND_SKIP_BBTSCAN;
 859
 860         pdata->nand_timings = devm_kzalloc(&pdev->dev,
 861                                 sizeof(*pdata->nand_timings), GFP_KERNEL);
 862         if (!pdata->nand_timings)
 863                 return -ENOMEM;
 864         ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
 865                                                 sizeof(*pdata->nand_timings));
 866         if (ret) {
 867                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 868                 pdata->nand_timings = NULL;
 869         }
 870
 871         /* Set default NAND bank to 0 */
 872         pdata->bank = 0;
 873         if (!of_property_read_u32(np, "bank", &val)) {
 874                 if (val > 3) {
 875                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 876                         return -EINVAL;
 877                 }
 878                 pdata->bank = val;
 879         }
 880         return 0;
 881 }
 882
 883 /*
 884  * fsmc_nand_probe - Probe function
 885  * @pdev:       platform device structure
 886  */
 887 static int __init fsmc_nand_probe(struct platform_device *pdev)
 888 {
 889         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 890         struct device_node __maybe_unused *np = pdev->dev.of_node;
 891         struct fsmc_nand_data *host;
 892         struct mtd_info *mtd;
 893         struct nand_chip *nand;
 894         struct resource *res;
 895         dma_cap_mask_t mask;
 896         int ret = 0;
 897         u32 pid;
 898         int i;
 899
 900         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 901         if (!pdata)
 902                 return -ENOMEM;
 903
 904         pdev->dev.platform_data = pdata;
 905         ret = fsmc_nand_probe_config_dt(pdev, np);
 906         if (ret) {
 907                 dev_err(&pdev->dev, "no platform data\n");
 908                 return -ENODEV;
 909         }
 910
 911         /* Allocate memory for the device structure (and zero it) */
 912         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 913         if (!host)
 914                 return -ENOMEM;
 915
 916         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 917         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 918         if (IS_ERR(host->data_va))
 919                 return PTR_ERR(host->data_va);
 920
 921         host->data_pa = (dma_addr_t)res->start;
 922
 923         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 924         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 925         if (IS_ERR(host->addr_va))
 926                 return PTR_ERR(host->addr_va);
 927
 928         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 929         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 930         if (IS_ERR(host->cmd_va))
 931                 return PTR_ERR(host->cmd_va);
 932
 933         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 934         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 935         if (IS_ERR(host->regs_va))
 936                 return PTR_ERR(host->regs_va);
 937
 938         host->clk = clk_get(&pdev->dev, NULL);
 939         if (IS_ERR(host->clk)) {
 940                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 941                 return PTR_ERR(host->clk);
 942         }
 943
 944         ret = clk_prepare_enable(host->clk);
 945         if (ret)
 946                 goto err_clk_prepare_enable;
 947
 948         /*
 949          * This device ID is actually a common AMBA ID as used on the
 950          * AMBA PrimeCell bus. However it is not a PrimeCell.
 951          */
 952         for (pid = 0, i = 0; i < 4; i++)
 953                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 954         host->pid = pid;
 955         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 956                  "revision %02x, config %02x\n",
 957                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 958                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 959
 960         host->bank = pdata->bank;
 961         host->select_chip = pdata->select_bank;
 962         host->partitions = pdata->partitions;
 963         host->nr_partitions = pdata->nr_partitions;
 964         host->dev = &pdev->dev;
 965         host->dev_timings = pdata->nand_timings;
 966         host->mode = pdata->mode;
 967
 968         if (host->mode == USE_DMA_ACCESS)
 969                 init_completion(&host->dma_access_complete);
 970
 971         /* Link all private pointers */
 972         mtd = nand_to_mtd(&host->nand);
 973         nand = &host->nand;
 974         nand_set_controller_data(nand, host);
 975         nand_set_flash_node(nand, np);
 976
 977         mtd->dev.parent = &pdev->dev;
 978         nand->IO_ADDR_R = host->data_va;
 979         nand->IO_ADDR_W = host->data_va;
 980         nand->cmd_ctrl = fsmc_cmd_ctrl;
 981         nand->chip_delay = 30;
 982
 983         /*
 984          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 985          * can overwrite this value if the DT provides a different value.
 986          */
 987         nand->ecc.mode = NAND_ECC_HW;
 988         nand->ecc.hwctl = fsmc_enable_hwecc;
 989         nand->ecc.size = 512;
 990         nand->options = pdata->options;
 991         nand->select_chip = fsmc_select_chip;
 992         nand->badblockbits = 7;
 993         nand_set_flash_node(nand, np);
 994
 995         if (pdata->width == FSMC_NAND_BW16)
 996                 nand->options |= NAND_BUSWIDTH_16;
 997
 998         switch (host->mode) {
 999         case USE_DMA_ACCESS:
1000                 dma_cap_zero(mask);
1001                 dma_cap_set(DMA_MEMCPY, mask);
1002                 host->read_dma_chan = dma_request_channel(mask, filter,
1003                                 pdata->read_dma_priv);
1004                 if (!host->read_dma_chan) {
1005                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1006                         goto err_req_read_chnl;
1007                 }
1008                 host->write_dma_chan = dma_request_channel(mask, filter,
1009                                 pdata->write_dma_priv);
1010                 if (!host->write_dma_chan) {
1011                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1012                         goto err_req_write_chnl;
1013                 }
1014                 nand->read_buf = fsmc_read_buf_dma;
1015                 nand->write_buf = fsmc_write_buf_dma;
1016                 break;
1017
1018         default:
1019         case USE_WORD_ACCESS:
1020                 nand->read_buf = fsmc_read_buf;
1021                 nand->write_buf = fsmc_write_buf;
1022                 break;
1023         }
1024
1025         fsmc_nand_setup(host->regs_va, host->bank,
1026                         nand->options & NAND_BUSWIDTH_16,
1027                         host->dev_timings);
1028
1029         if (AMBA_REV_BITS(host->pid) >= 8) {
1030                 nand->ecc.read_page = fsmc_read_page_hwecc;
1031                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1032                 nand->ecc.correct = fsmc_bch8_correct_data;
1033                 nand->ecc.bytes = 13;
1034                 nand->ecc.strength = 8;
1035         }
1036
1037         /*
1038          * Scan to find existence of the device
1039          */
1040         ret = nand_scan_ident(mtd, 1, NULL);
1041         if (ret) {
1042                 dev_err(&pdev->dev, "No NAND Device found!\n");
1043                 goto err_scan_ident;
1044         }
1045
1046         if (AMBA_REV_BITS(host->pid) >= 8) {
1047                 switch (mtd->oobsize) {
1048                 case 16:
1049                 case 64:
1050                 case 128:
1051                 case 224:
1052                 case 256:
1053                         break;
1054                 default:
1055                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1056                                  mtd->oobsize);
1057                         ret = -EINVAL;
1058                         goto err_probe;
1059                 }
1060
1061                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1062         } else {
1063                 switch (nand->ecc.mode) {
1064                 case NAND_ECC_HW:
1065                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1066                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1067                         nand->ecc.correct = nand_correct_data;
1068                         nand->ecc.bytes = 3;
1069                         nand->ecc.strength = 1;
1070                         break;
1071
1072                 case NAND_ECC_SOFT:
1073                         if (nand->ecc.algo == NAND_ECC_BCH) {
1074                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1075                                 break;
1076                         }
1077
1078                 default:
1079                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1080                         goto err_probe;
1081                 }
1082
1083                 /*
1084                  * Don't set layout for BCH4 SW ECC. This will be
1085                  * generated later in nand_bch_init() later.
1086                  */
1087                 if (nand->ecc.mode == NAND_ECC_HW) {
1088                         switch (mtd->oobsize) {
1089                         case 16:
1090                         case 64:
1091                         case 128:
1092                                 mtd_set_ooblayout(mtd,
1093                                                   &fsmc_ecc1_ooblayout_ops);
1094                                 break;
1095                         default:
1096                                 dev_warn(&pdev->dev,
1097                                          "No oob scheme defined for oobsize %d\n",
1098                                          mtd->oobsize);
1099                                 ret = -EINVAL;
1100                                 goto err_probe;
1101                         }
1102                 }
1103         }
1104
1105         /* Second stage of scan to fill MTD data-structures */
1106         ret = nand_scan_tail(mtd);
1107         if (ret)
1108                 goto err_probe;
1109
1110         /*
1111          * The partition information can is accessed by (in the same precedence)
1112          *
1113          * command line through Bootloader,
1114          * platform data,
1115          * default partition information present in driver.
1116          */
1117         /*
1118          * Check for partition info passed
1119          */
1120         mtd->name = "nand";
1121         ret = mtd_device_register(mtd, host->partitions, host->nr_partitions);
1122         if (ret)
1123                 goto err_probe;
1124
1125         platform_set_drvdata(pdev, host);
1126         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1127         return 0;
1128
1129 err_probe:
1130 err_scan_ident:
1131         if (host->mode == USE_DMA_ACCESS)
1132                 dma_release_channel(host->write_dma_chan);
1133 err_req_write_chnl:
1134         if (host->mode == USE_DMA_ACCESS)
1135                 dma_release_channel(host->read_dma_chan);
1136 err_req_read_chnl:
1137         clk_disable_unprepare(host->clk);
1138 err_clk_prepare_enable:
1139         clk_put(host->clk);
1140         return ret;
1141 }
1142
1143 /*
1144  * Clean up routine
1145  */
1146 static int fsmc_nand_remove(struct platform_device *pdev)
1147 {
1148         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1149
1150         if (host) {
1151                 nand_release(nand_to_mtd(&host->nand));
1152
1153                 if (host->mode == USE_DMA_ACCESS) {
1154                         dma_release_channel(host->write_dma_chan);
1155                         dma_release_channel(host->read_dma_chan);
1156                 }
1157                 clk_disable_unprepare(host->clk);
1158                 clk_put(host->clk);
1159         }
1160
1161         return 0;
1162 }
1163
1164 #ifdef CONFIG_PM_SLEEP
1165 static int fsmc_nand_suspend(struct device *dev)
1166 {
1167         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1168         if (host)
1169                 clk_disable_unprepare(host->clk);
1170         return 0;
1171 }
1172
1173 static int fsmc_nand_resume(struct device *dev)
1174 {
1175         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1176         if (host) {
1177                 clk_prepare_enable(host->clk);
1178                 fsmc_nand_setup(host->regs_va, host->bank,
1179                                 host->nand.options & NAND_BUSWIDTH_16,
1180                                 host->dev_timings);
1181         }
1182         return 0;
1183 }
1184 #endif
1185
1186 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1187
1188 #ifdef CONFIG_OF
1189 static const struct of_device_id fsmc_nand_id_table[] = {
1190         { .compatible = "st,spear600-fsmc-nand" },
1191         { .compatible = "stericsson,fsmc-nand" },
1192         {}
1193 };
1194 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1195 #endif
1196
1197 static struct platform_driver fsmc_nand_driver = {
1198         .remove = fsmc_nand_remove,
1199         .driver = {
1200                 .name = "fsmc-nand",
1201                 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1202                 .pm = &fsmc_nand_pm_ops,
1203         },
1204 };
1205
1206 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1207
1208 MODULE_LICENSE("GPL");
1209 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1210 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");