drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 /* fsmc controller registers for NOR flash */
  42 #define CTRL                    0x0
  43         /* ctrl register definitions */
  44         #define BANK_ENABLE             (1 << 0)
  45         #define MUXED                   (1 << 1)
  46         #define NOR_DEV                 (2 << 2)
  47         #define WIDTH_8                 (0 << 4)
  48         #define WIDTH_16                (1 << 4)
  49         #define RSTPWRDWN               (1 << 6)
  50         #define WPROT                   (1 << 7)
  51         #define WRT_ENABLE              (1 << 12)
  52         #define WAIT_ENB                (1 << 13)
  53
  54 #define CTRL_TIM                0x4
  55         /* ctrl_tim register definitions */
  56
  57 #define FSMC_NOR_BANK_SZ        0x8
  58 #define FSMC_NOR_REG_SIZE       0x40
  59
  60 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  61                                                 FSMC_NOR_BANK_SZ * (bank) + \
  62                                                 reg)
  63
  64 /* fsmc controller registers for NAND flash */
  65 #define PC                      0x00
  66         /* pc register definitions */
  67         #define FSMC_RESET              (1 << 0)
  68         #define FSMC_WAITON             (1 << 1)
  69         #define FSMC_ENABLE             (1 << 2)
  70         #define FSMC_DEVTYPE_NAND       (1 << 3)
  71         #define FSMC_DEVWID_8           (0 << 4)
  72         #define FSMC_DEVWID_16          (1 << 4)
  73         #define FSMC_ECCEN              (1 << 6)
  74         #define FSMC_ECCPLEN_512        (0 << 7)
  75         #define FSMC_ECCPLEN_256        (1 << 7)
  76         #define FSMC_TCLR_1             (1)
  77         #define FSMC_TCLR_SHIFT         (9)
  78         #define FSMC_TCLR_MASK          (0xF)
  79         #define FSMC_TAR_1              (1)
  80         #define FSMC_TAR_SHIFT          (13)
  81         #define FSMC_TAR_MASK           (0xF)
  82 #define STS                     0x04
  83         /* sts register definitions */
  84         #define FSMC_CODE_RDY           (1 << 15)
  85 #define COMM                    0x08
  86         /* comm register definitions */
  87         #define FSMC_TSET_0             0
  88         #define FSMC_TSET_SHIFT         0
  89         #define FSMC_TSET_MASK          0xFF
  90         #define FSMC_TWAIT_6            6
  91         #define FSMC_TWAIT_SHIFT        8
  92         #define FSMC_TWAIT_MASK         0xFF
  93         #define FSMC_THOLD_4            4
  94         #define FSMC_THOLD_SHIFT        16
  95         #define FSMC_THOLD_MASK         0xFF
  96         #define FSMC_THIZ_1             1
  97         #define FSMC_THIZ_SHIFT         24
  98         #define FSMC_THIZ_MASK          0xFF
  99 #define ATTRIB                  0x0C
 100 #define IOATA                   0x10
 101 #define ECC1                    0x14
 102 #define ECC2                    0x18
 103 #define ECC3                    0x1C
 104 #define FSMC_NAND_BANK_SZ       0x20
 105
 106 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 107                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 108                                                 reg)
 109
 110 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 111
 112 struct fsmc_nand_timings {
 113         uint8_t tclr;
 114         uint8_t tar;
 115         uint8_t thiz;
 116         uint8_t thold;
 117         uint8_t twait;
 118         uint8_t tset;
 119 };
 120
 121 enum access_mode {
 122         USE_DMA_ACCESS = 1,
 123         USE_WORD_ACCESS,
 124 };
 125
 126 /**
 127  * struct fsmc_nand_data - structure for FSMC NAND device state
 128  *
 129  * @pid:                Part ID on the AMBA PrimeCell format
 130  * @mtd:                MTD info for a NAND flash.
 131  * @nand:               Chip related info for a NAND flash.
 132  * @partitions:         Partition info for a NAND Flash.
 133  * @nr_partitions:      Total number of partition of a NAND flash.
 134  *
 135  * @bank:               Bank number for probed device.
 136  * @clk:                Clock structure for FSMC.
 137  *
 138  * @read_dma_chan:      DMA channel for read access
 139  * @write_dma_chan:     DMA channel for write access to NAND
 140  * @dma_access_complete: Completion structure
 141  *
 142  * @data_pa:            NAND Physical port for Data.
 143  * @data_va:            NAND port for Data.
 144  * @cmd_va:             NAND port for Command.
 145  * @addr_va:            NAND port for Address.
 146  * @regs_va:            FSMC regs base address.
 147  */
 148 struct fsmc_nand_data {
 149         u32                     pid;
 150         struct nand_chip        nand;
 151
 152         unsigned int            bank;
 153         struct device           *dev;
 154         enum access_mode        mode;
 155         struct clk              *clk;
 156
 157         /* DMA related objects */
 158         struct dma_chan         *read_dma_chan;
 159         struct dma_chan         *write_dma_chan;
 160         struct completion       dma_access_complete;
 161
 162         struct fsmc_nand_timings *dev_timings;
 163
 164         dma_addr_t              data_pa;
 165         void __iomem            *data_va;
 166         void __iomem            *cmd_va;
 167         void __iomem            *addr_va;
 168         void __iomem            *regs_va;
 169 };
 170
 171 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 172                                    struct mtd_oob_region *oobregion)
 173 {
 174         struct nand_chip *chip = mtd_to_nand(mtd);
 175
 176         if (section >= chip->ecc.steps)
 177                 return -ERANGE;
 178
 179         oobregion->offset = (section * 16) + 2;
 180         oobregion->length = 3;
 181
 182         return 0;
 183 }
 184
 185 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 186                                     struct mtd_oob_region *oobregion)
 187 {
 188         struct nand_chip *chip = mtd_to_nand(mtd);
 189
 190         if (section >= chip->ecc.steps)
 191                 return -ERANGE;
 192
 193         oobregion->offset = (section * 16) + 8;
 194
 195         if (section < chip->ecc.steps - 1)
 196                 oobregion->length = 8;
 197         else
 198                 oobregion->length = mtd->oobsize - oobregion->offset;
 199
 200         return 0;
 201 }
 202
 203 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 204         .ecc = fsmc_ecc1_ooblayout_ecc,
 205         .free = fsmc_ecc1_ooblayout_free,
 206 };
 207
 208 /*
 209  * ECC placement definitions in oobfree type format.
 210  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 211  * consecutively and immediately after the 512 byte data block for hardware to
 212  * generate the error bit offsets in 512 byte data.
 213  */
 214 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 215                                    struct mtd_oob_region *oobregion)
 216 {
 217         struct nand_chip *chip = mtd_to_nand(mtd);
 218
 219         if (section >= chip->ecc.steps)
 220                 return -ERANGE;
 221
 222         oobregion->length = chip->ecc.bytes;
 223
 224         if (!section && mtd->writesize <= 512)
 225                 oobregion->offset = 0;
 226         else
 227                 oobregion->offset = (section * 16) + 2;
 228
 229         return 0;
 230 }
 231
 232 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 233                                     struct mtd_oob_region *oobregion)
 234 {
 235         struct nand_chip *chip = mtd_to_nand(mtd);
 236
 237         if (section >= chip->ecc.steps)
 238                 return -ERANGE;
 239
 240         oobregion->offset = (section * 16) + 15;
 241
 242         if (section < chip->ecc.steps - 1)
 243                 oobregion->length = 3;
 244         else
 245                 oobregion->length = mtd->oobsize - oobregion->offset;
 246
 247         return 0;
 248 }
 249
 250 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 251         .ecc = fsmc_ecc4_ooblayout_ecc,
 252         .free = fsmc_ecc4_ooblayout_free,
 253 };
 254
 255 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 256 {
 257         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 258 }
 259
 260 /*
 261  * fsmc_cmd_ctrl - For facilitaing Hardware access
 262  * This routine allows hardware specific access to control-lines(ALE,CLE)
 263  */
 264 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 265 {
 266         struct nand_chip *this = mtd_to_nand(mtd);
 267         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 268         void __iomem *regs = host->regs_va;
 269         unsigned int bank = host->bank;
 270
 271         if (ctrl & NAND_CTRL_CHANGE) {
 272                 u32 pc;
 273
 274                 if (ctrl & NAND_CLE) {
 275                         this->IO_ADDR_R = host->cmd_va;
 276                         this->IO_ADDR_W = host->cmd_va;
 277                 } else if (ctrl & NAND_ALE) {
 278                         this->IO_ADDR_R = host->addr_va;
 279                         this->IO_ADDR_W = host->addr_va;
 280                 } else {
 281                         this->IO_ADDR_R = host->data_va;
 282                         this->IO_ADDR_W = host->data_va;
 283                 }
 284
 285                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 286                 if (ctrl & NAND_NCE)
 287                         pc |= FSMC_ENABLE;
 288                 else
 289                         pc &= ~FSMC_ENABLE;
 290                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 291         }
 292
 293         mb();
 294
 295         if (cmd != NAND_CMD_NONE)
 296                 writeb_relaxed(cmd, this->IO_ADDR_W);
 297 }
 298
 299 /*
 300  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 301  *
 302  * This routine initializes timing parameters related to NAND memory access in
 303  * FSMC registers
 304  */
 305 static void fsmc_nand_setup(struct fsmc_nand_data *host,
 306                             struct fsmc_nand_timings *timings)
 307 {
 308         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 309         uint32_t tclr, tar, thiz, thold, twait, tset;
 310         unsigned int bank = host->bank;
 311         void __iomem *regs = host->regs_va;
 312         struct fsmc_nand_timings *tims;
 313         struct fsmc_nand_timings default_timings = {
 314                 .tclr   = FSMC_TCLR_1,
 315                 .tar    = FSMC_TAR_1,
 316                 .thiz   = FSMC_THIZ_1,
 317                 .thold  = FSMC_THOLD_4,
 318                 .twait  = FSMC_TWAIT_6,
 319                 .tset   = FSMC_TSET_0,
 320         };
 321
 322         if (timings)
 323                 tims = host->dev_timings;
 324         else
 325                 tims = &default_timings;
 326
 327         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 328         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 329         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 330         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 331         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 332         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 333
 334         if (host->nand.options & NAND_BUSWIDTH_16)
 335                 writel_relaxed(value | FSMC_DEVWID_16,
 336                                 FSMC_NAND_REG(regs, bank, PC));
 337         else
 338                 writel_relaxed(value | FSMC_DEVWID_8,
 339                                 FSMC_NAND_REG(regs, bank, PC));
 340
 341         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 342                         FSMC_NAND_REG(regs, bank, PC));
 343         writel_relaxed(thiz | thold | twait | tset,
 344                         FSMC_NAND_REG(regs, bank, COMM));
 345         writel_relaxed(thiz | thold | twait | tset,
 346                         FSMC_NAND_REG(regs, bank, ATTRIB));
 347 }
 348
 349 /*
 350  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 351  */
 352 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 353 {
 354         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 355         void __iomem *regs = host->regs_va;
 356         uint32_t bank = host->bank;
 357
 358         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 359                         FSMC_NAND_REG(regs, bank, PC));
 360         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 361                         FSMC_NAND_REG(regs, bank, PC));
 362         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 363                         FSMC_NAND_REG(regs, bank, PC));
 364 }
 365
 366 /*
 367  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 368  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 369  * max of 8-bits)
 370  */
 371 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 372                                 uint8_t *ecc)
 373 {
 374         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 375         void __iomem *regs = host->regs_va;
 376         uint32_t bank = host->bank;
 377         uint32_t ecc_tmp;
 378         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 379
 380         do {
 381                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 382                         break;
 383                 else
 384                         cond_resched();
 385         } while (!time_after_eq(jiffies, deadline));
 386
 387         if (time_after_eq(jiffies, deadline)) {
 388                 dev_err(host->dev, "calculate ecc timed out\n");
 389                 return -ETIMEDOUT;
 390         }
 391
 392         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 393         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 394         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 395         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 396         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 397
 398         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 399         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 400         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 401         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 402         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 403
 404         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 405         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 406         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 407         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 408         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 409
 410         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 411         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 412
 413         return 0;
 414 }
 415
 416 /*
 417  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 418  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 419  * max of 1-bit)
 420  */
 421 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 422                                 uint8_t *ecc)
 423 {
 424         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 425         void __iomem *regs = host->regs_va;
 426         uint32_t bank = host->bank;
 427         uint32_t ecc_tmp;
 428
 429         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 430         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 431         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 432         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 433
 434         return 0;
 435 }
 436
 437 /* Count the number of 0's in buff upto a max of max_bits */
 438 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 439 {
 440         int k, written_bits = 0;
 441
 442         for (k = 0; k < size; k++) {
 443                 written_bits += hweight8(~buff[k]);
 444                 if (written_bits > max_bits)
 445                         break;
 446         }
 447
 448         return written_bits;
 449 }
 450
 451 static void dma_complete(void *param)
 452 {
 453         struct fsmc_nand_data *host = param;
 454
 455         complete(&host->dma_access_complete);
 456 }
 457
 458 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 459                 enum dma_data_direction direction)
 460 {
 461         struct dma_chan *chan;
 462         struct dma_device *dma_dev;
 463         struct dma_async_tx_descriptor *tx;
 464         dma_addr_t dma_dst, dma_src, dma_addr;
 465         dma_cookie_t cookie;
 466         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 467         int ret;
 468         unsigned long time_left;
 469
 470         if (direction == DMA_TO_DEVICE)
 471                 chan = host->write_dma_chan;
 472         else if (direction == DMA_FROM_DEVICE)
 473                 chan = host->read_dma_chan;
 474         else
 475                 return -EINVAL;
 476
 477         dma_dev = chan->device;
 478         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 479
 480         if (direction == DMA_TO_DEVICE) {
 481                 dma_src = dma_addr;
 482                 dma_dst = host->data_pa;
 483         } else {
 484                 dma_src = host->data_pa;
 485                 dma_dst = dma_addr;
 486         }
 487
 488         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 489                         len, flags);
 490         if (!tx) {
 491                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 492                 ret = -EIO;
 493                 goto unmap_dma;
 494         }
 495
 496         tx->callback = dma_complete;
 497         tx->callback_param = host;
 498         cookie = tx->tx_submit(tx);
 499
 500         ret = dma_submit_error(cookie);
 501         if (ret) {
 502                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 503                 goto unmap_dma;
 504         }
 505
 506         dma_async_issue_pending(chan);
 507
 508         time_left =
 509         wait_for_completion_timeout(&host->dma_access_complete,
 510                                 msecs_to_jiffies(3000));
 511         if (time_left == 0) {
 512                 dmaengine_terminate_all(chan);
 513                 dev_err(host->dev, "wait_for_completion_timeout\n");
 514                 ret = -ETIMEDOUT;
 515                 goto unmap_dma;
 516         }
 517
 518         ret = 0;
 519
 520 unmap_dma:
 521         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 522
 523         return ret;
 524 }
 525
 526 /*
 527  * fsmc_write_buf - write buffer to chip
 528  * @mtd:        MTD device structure
 529  * @buf:        data buffer
 530  * @len:        number of bytes to write
 531  */
 532 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 533 {
 534         int i;
 535         struct nand_chip *chip = mtd_to_nand(mtd);
 536
 537         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 538                         IS_ALIGNED(len, sizeof(uint32_t))) {
 539                 uint32_t *p = (uint32_t *)buf;
 540                 len = len >> 2;
 541                 for (i = 0; i < len; i++)
 542                         writel_relaxed(p[i], chip->IO_ADDR_W);
 543         } else {
 544                 for (i = 0; i < len; i++)
 545                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 546         }
 547 }
 548
 549 /*
 550  * fsmc_read_buf - read chip data into buffer
 551  * @mtd:        MTD device structure
 552  * @buf:        buffer to store date
 553  * @len:        number of bytes to read
 554  */
 555 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 556 {
 557         int i;
 558         struct nand_chip *chip = mtd_to_nand(mtd);
 559
 560         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 561                         IS_ALIGNED(len, sizeof(uint32_t))) {
 562                 uint32_t *p = (uint32_t *)buf;
 563                 len = len >> 2;
 564                 for (i = 0; i < len; i++)
 565                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 566         } else {
 567                 for (i = 0; i < len; i++)
 568                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 569         }
 570 }
 571
 572 /*
 573  * fsmc_read_buf_dma - read chip data into buffer
 574  * @mtd:        MTD device structure
 575  * @buf:        buffer to store date
 576  * @len:        number of bytes to read
 577  */
 578 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 579 {
 580         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 581
 582         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 583 }
 584
 585 /*
 586  * fsmc_write_buf_dma - write buffer to chip
 587  * @mtd:        MTD device structure
 588  * @buf:        data buffer
 589  * @len:        number of bytes to write
 590  */
 591 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 592                 int len)
 593 {
 594         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 595
 596         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 597 }
 598
 599 /*
 600  * fsmc_read_page_hwecc
 601  * @mtd:        mtd info structure
 602  * @chip:       nand chip info structure
 603  * @buf:        buffer to store read data
 604  * @oob_required:       caller expects OOB data read to chip->oob_poi
 605  * @page:       page number to read
 606  *
 607  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 608  * performed in a strict sequence as follows:
 609  * data(512 byte) -> ecc(13 byte)
 610  * After this read, fsmc hardware generates and reports error data bits(up to a
 611  * max of 8 bits)
 612  */
 613 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 614                                  uint8_t *buf, int oob_required, int page)
 615 {
 616         int i, j, s, stat, eccsize = chip->ecc.size;
 617         int eccbytes = chip->ecc.bytes;
 618         int eccsteps = chip->ecc.steps;
 619         uint8_t *p = buf;
 620         uint8_t *ecc_calc = chip->buffers->ecccalc;
 621         uint8_t *ecc_code = chip->buffers->ecccode;
 622         int off, len, group = 0;
 623         /*
 624          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 625          * end up reading 14 bytes (7 words) from oob. The local array is
 626          * to maintain word alignment
 627          */
 628         uint16_t ecc_oob[7];
 629         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 630         unsigned int max_bitflips = 0;
 631
 632         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 633                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 634                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 635                 chip->read_buf(mtd, p, eccsize);
 636
 637                 for (j = 0; j < eccbytes;) {
 638                         struct mtd_oob_region oobregion;
 639                         int ret;
 640
 641                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 642                         if (ret)
 643                                 return ret;
 644
 645                         off = oobregion.offset;
 646                         len = oobregion.length;
 647
 648                         /*
 649                          * length is intentionally kept a higher multiple of 2
 650                          * to read at least 13 bytes even in case of 16 bit NAND
 651                          * devices
 652                          */
 653                         if (chip->options & NAND_BUSWIDTH_16)
 654                                 len = roundup(len, 2);
 655
 656                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 657                         chip->read_buf(mtd, oob + j, len);
 658                         j += len;
 659                 }
 660
 661                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 662                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 663
 664                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 665                 if (stat < 0) {
 666                         mtd->ecc_stats.failed++;
 667                 } else {
 668                         mtd->ecc_stats.corrected += stat;
 669                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 670                 }
 671         }
 672
 673         return max_bitflips;
 674 }
 675
 676 /*
 677  * fsmc_bch8_correct_data
 678  * @mtd:        mtd info structure
 679  * @dat:        buffer of read data
 680  * @read_ecc:   ecc read from device spare area
 681  * @calc_ecc:   ecc calculated from read data
 682  *
 683  * calc_ecc is a 104 bit information containing maximum of 8 error
 684  * offset informations of 13 bits each in 512 bytes of read data.
 685  */
 686 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 687                              uint8_t *read_ecc, uint8_t *calc_ecc)
 688 {
 689         struct nand_chip *chip = mtd_to_nand(mtd);
 690         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 691         void __iomem *regs = host->regs_va;
 692         unsigned int bank = host->bank;
 693         uint32_t err_idx[8];
 694         uint32_t num_err, i;
 695         uint32_t ecc1, ecc2, ecc3, ecc4;
 696
 697         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 698
 699         /* no bit flipping */
 700         if (likely(num_err == 0))
 701                 return 0;
 702
 703         /* too many errors */
 704         if (unlikely(num_err > 8)) {
 705                 /*
 706                  * This is a temporary erase check. A newly erased page read
 707                  * would result in an ecc error because the oob data is also
 708                  * erased to FF and the calculated ecc for an FF data is not
 709                  * FF..FF.
 710                  * This is a workaround to skip performing correction in case
 711                  * data is FF..FF
 712                  *
 713                  * Logic:
 714                  * For every page, each bit written as 0 is counted until these
 715                  * number of bits are greater than 8 (the maximum correction
 716                  * capability of FSMC for each 512 + 13 bytes)
 717                  */
 718
 719                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 720                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 721
 722                 if ((bits_ecc + bits_data) <= 8) {
 723                         if (bits_data)
 724                                 memset(dat, 0xff, chip->ecc.size);
 725                         return bits_data;
 726                 }
 727
 728                 return -EBADMSG;
 729         }
 730
 731         /*
 732          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 733          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 734          *
 735          * calc_ecc is a 104 bit information containing maximum of 8 error
 736          * offset informations of 13 bits each. calc_ecc is copied into a
 737          * uint64_t array and error offset indexes are populated in err_idx
 738          * array
 739          */
 740         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 741         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 742         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 743         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 744
 745         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 746         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 747         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 748         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 749         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 750         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 751         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 752         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 753
 754         i = 0;
 755         while (num_err--) {
 756                 change_bit(0, (unsigned long *)&err_idx[i]);
 757                 change_bit(1, (unsigned long *)&err_idx[i]);
 758
 759                 if (err_idx[i] < chip->ecc.size * 8) {
 760                         change_bit(err_idx[i], (unsigned long *)dat);
 761                         i++;
 762                 }
 763         }
 764         return i;
 765 }
 766
 767 static bool filter(struct dma_chan *chan, void *slave)
 768 {
 769         chan->private = slave;
 770         return true;
 771 }
 772
 773 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 774                                      struct fsmc_nand_data *host,
 775                                      struct nand_chip *nand)
 776 {
 777         struct device_node *np = pdev->dev.of_node;
 778         u32 val;
 779         int ret;
 780
 781         nand->options = 0;
 782
 783         if (!of_property_read_u32(np, "bank-width", &val)) {
 784                 if (val == 2) {
 785                         nand->options |= NAND_BUSWIDTH_16;
 786                 } else if (val != 1) {
 787                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 788                         return -EINVAL;
 789                 }
 790         }
 791
 792         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 793                 nand->options |= NAND_SKIP_BBTSCAN;
 794
 795         host->dev_timings = devm_kzalloc(&pdev->dev,
 796                                 sizeof(*host->dev_timings), GFP_KERNEL);
 797         if (!host->dev_timings)
 798                 return -ENOMEM;
 799         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 800                                                 sizeof(*host->dev_timings));
 801         if (ret) {
 802                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 803                 host->dev_timings = NULL;
 804         }
 805
 806         /* Set default NAND bank to 0 */
 807         host->bank = 0;
 808         if (!of_property_read_u32(np, "bank", &val)) {
 809                 if (val > 3) {
 810                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 811                         return -EINVAL;
 812                 }
 813                 host->bank = val;
 814         }
 815         return 0;
 816 }
 817
 818 /*
 819  * fsmc_nand_probe - Probe function
 820  * @pdev:       platform device structure
 821  */
 822 static int __init fsmc_nand_probe(struct platform_device *pdev)
 823 {
 824         struct fsmc_nand_data *host;
 825         struct mtd_info *mtd;
 826         struct nand_chip *nand;
 827         struct resource *res;
 828         dma_cap_mask_t mask;
 829         int ret = 0;
 830         u32 pid;
 831         int i;
 832
 833         /* Allocate memory for the device structure (and zero it) */
 834         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 835         if (!host)
 836                 return -ENOMEM;
 837
 838         nand = &host->nand;
 839
 840         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
 841         if (ret)
 842                 return ret;
 843
 844         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 845         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 846         if (IS_ERR(host->data_va))
 847                 return PTR_ERR(host->data_va);
 848
 849         host->data_pa = (dma_addr_t)res->start;
 850
 851         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 852         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 853         if (IS_ERR(host->addr_va))
 854                 return PTR_ERR(host->addr_va);
 855
 856         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 857         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 858         if (IS_ERR(host->cmd_va))
 859                 return PTR_ERR(host->cmd_va);
 860
 861         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 862         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 863         if (IS_ERR(host->regs_va))
 864                 return PTR_ERR(host->regs_va);
 865
 866         host->clk = devm_clk_get(&pdev->dev, NULL);
 867         if (IS_ERR(host->clk)) {
 868                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 869                 return PTR_ERR(host->clk);
 870         }
 871
 872         ret = clk_prepare_enable(host->clk);
 873         if (ret)
 874                 return ret;
 875
 876         /*
 877          * This device ID is actually a common AMBA ID as used on the
 878          * AMBA PrimeCell bus. However it is not a PrimeCell.
 879          */
 880         for (pid = 0, i = 0; i < 4; i++)
 881                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 882         host->pid = pid;
 883         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 884                  "revision %02x, config %02x\n",
 885                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 886                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 887
 888         host->dev = &pdev->dev;
 889
 890         if (host->mode == USE_DMA_ACCESS)
 891                 init_completion(&host->dma_access_complete);
 892
 893         /* Link all private pointers */
 894         mtd = nand_to_mtd(&host->nand);
 895         nand_set_controller_data(nand, host);
 896         nand_set_flash_node(nand, pdev->dev.of_node);
 897
 898         mtd->dev.parent = &pdev->dev;
 899         nand->IO_ADDR_R = host->data_va;
 900         nand->IO_ADDR_W = host->data_va;
 901         nand->cmd_ctrl = fsmc_cmd_ctrl;
 902         nand->chip_delay = 30;
 903
 904         /*
 905          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 906          * can overwrite this value if the DT provides a different value.
 907          */
 908         nand->ecc.mode = NAND_ECC_HW;
 909         nand->ecc.hwctl = fsmc_enable_hwecc;
 910         nand->ecc.size = 512;
 911         nand->badblockbits = 7;
 912
 913         switch (host->mode) {
 914         case USE_DMA_ACCESS:
 915                 dma_cap_zero(mask);
 916                 dma_cap_set(DMA_MEMCPY, mask);
 917                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
 918                 if (!host->read_dma_chan) {
 919                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
 920                         goto err_req_read_chnl;
 921                 }
 922                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
 923                 if (!host->write_dma_chan) {
 924                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
 925                         goto err_req_write_chnl;
 926                 }
 927                 nand->read_buf = fsmc_read_buf_dma;
 928                 nand->write_buf = fsmc_write_buf_dma;
 929                 break;
 930
 931         default:
 932         case USE_WORD_ACCESS:
 933                 nand->read_buf = fsmc_read_buf;
 934                 nand->write_buf = fsmc_write_buf;
 935                 break;
 936         }
 937
 938         fsmc_nand_setup(host, host->dev_timings);
 939
 940         if (AMBA_REV_BITS(host->pid) >= 8) {
 941                 nand->ecc.read_page = fsmc_read_page_hwecc;
 942                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 943                 nand->ecc.correct = fsmc_bch8_correct_data;
 944                 nand->ecc.bytes = 13;
 945                 nand->ecc.strength = 8;
 946         }
 947
 948         /*
 949          * Scan to find existence of the device
 950          */
 951         ret = nand_scan_ident(mtd, 1, NULL);
 952         if (ret) {
 953                 dev_err(&pdev->dev, "No NAND Device found!\n");
 954                 goto err_scan_ident;
 955         }
 956
 957         if (AMBA_REV_BITS(host->pid) >= 8) {
 958                 switch (mtd->oobsize) {
 959                 case 16:
 960                 case 64:
 961                 case 128:
 962                 case 224:
 963                 case 256:
 964                         break;
 965                 default:
 966                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
 967                                  mtd->oobsize);
 968                         ret = -EINVAL;
 969                         goto err_probe;
 970                 }
 971
 972                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
 973         } else {
 974                 switch (nand->ecc.mode) {
 975                 case NAND_ECC_HW:
 976                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
 977                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
 978                         nand->ecc.correct = nand_correct_data;
 979                         nand->ecc.bytes = 3;
 980                         nand->ecc.strength = 1;
 981                         break;
 982
 983                 case NAND_ECC_SOFT:
 984                         if (nand->ecc.algo == NAND_ECC_BCH) {
 985                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 986                                 break;
 987                         }
 988
 989                 default:
 990                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
 991                         goto err_probe;
 992                 }
 993
 994                 /*
 995                  * Don't set layout for BCH4 SW ECC. This will be
 996                  * generated later in nand_bch_init() later.
 997                  */
 998                 if (nand->ecc.mode == NAND_ECC_HW) {
 999                         switch (mtd->oobsize) {
1000                         case 16:
1001                         case 64:
1002                         case 128:
1003                                 mtd_set_ooblayout(mtd,
1004                                                   &fsmc_ecc1_ooblayout_ops);
1005                                 break;
1006                         default:
1007                                 dev_warn(&pdev->dev,
1008                                          "No oob scheme defined for oobsize %d\n",
1009                                          mtd->oobsize);
1010                                 ret = -EINVAL;
1011                                 goto err_probe;
1012                         }
1013                 }
1014         }
1015
1016         /* Second stage of scan to fill MTD data-structures */
1017         ret = nand_scan_tail(mtd);
1018         if (ret)
1019                 goto err_probe;
1020
1021         mtd->name = "nand";
1022         ret = mtd_device_register(mtd, NULL, 0);
1023         if (ret)
1024                 goto err_probe;
1025
1026         platform_set_drvdata(pdev, host);
1027         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1028         return 0;
1029
1030 err_probe:
1031 err_scan_ident:
1032         if (host->mode == USE_DMA_ACCESS)
1033                 dma_release_channel(host->write_dma_chan);
1034 err_req_write_chnl:
1035         if (host->mode == USE_DMA_ACCESS)
1036                 dma_release_channel(host->read_dma_chan);
1037 err_req_read_chnl:
1038         clk_disable_unprepare(host->clk);
1039         return ret;
1040 }
1041
1042 /*
1043  * Clean up routine
1044  */
1045 static int fsmc_nand_remove(struct platform_device *pdev)
1046 {
1047         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1048
1049         if (host) {
1050                 nand_release(nand_to_mtd(&host->nand));
1051
1052                 if (host->mode == USE_DMA_ACCESS) {
1053                         dma_release_channel(host->write_dma_chan);
1054                         dma_release_channel(host->read_dma_chan);
1055                 }
1056                 clk_disable_unprepare(host->clk);
1057         }
1058
1059         return 0;
1060 }
1061
1062 #ifdef CONFIG_PM_SLEEP
1063 static int fsmc_nand_suspend(struct device *dev)
1064 {
1065         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1066         if (host)
1067                 clk_disable_unprepare(host->clk);
1068         return 0;
1069 }
1070
1071 static int fsmc_nand_resume(struct device *dev)
1072 {
1073         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1074         if (host) {
1075                 clk_prepare_enable(host->clk);
1076                 fsmc_nand_setup(host, host->dev_timings);
1077         }
1078         return 0;
1079 }
1080 #endif
1081
1082 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1083
1084 static const struct of_device_id fsmc_nand_id_table[] = {
1085         { .compatible = "st,spear600-fsmc-nand" },
1086         { .compatible = "stericsson,fsmc-nand" },
1087         {}
1088 };
1089 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1090
1091 static struct platform_driver fsmc_nand_driver = {
1092         .remove = fsmc_nand_remove,
1093         .driver = {
1094                 .name = "fsmc-nand",
1095                 .of_match_table = fsmc_nand_id_table,
1096                 .pm = &fsmc_nand_pm_ops,
1097         },
1098 };
1099
1100 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1101
1102 MODULE_LICENSE("GPL");
1103 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1104 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");