drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 #define FSMC_NAND_BW8           1
  42 #define FSMC_NAND_BW16          2
  43
  44 #define FSMC_MAX_NOR_BANKS      4
  45 #define FSMC_MAX_NAND_BANKS     4
  46
  47 #define FSMC_FLASH_WIDTH8       1
  48 #define FSMC_FLASH_WIDTH16      2
  49
  50 /* fsmc controller registers for NOR flash */
  51 #define CTRL                    0x0
  52         /* ctrl register definitions */
  53         #define BANK_ENABLE             (1 << 0)
  54         #define MUXED                   (1 << 1)
  55         #define NOR_DEV                 (2 << 2)
  56         #define WIDTH_8                 (0 << 4)
  57         #define WIDTH_16                (1 << 4)
  58         #define RSTPWRDWN               (1 << 6)
  59         #define WPROT                   (1 << 7)
  60         #define WRT_ENABLE              (1 << 12)
  61         #define WAIT_ENB                (1 << 13)
  62
  63 #define CTRL_TIM                0x4
  64         /* ctrl_tim register definitions */
  65
  66 #define FSMC_NOR_BANK_SZ        0x8
  67 #define FSMC_NOR_REG_SIZE       0x40
  68
  69 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  70                                                 FSMC_NOR_BANK_SZ * (bank) + \
  71                                                 reg)
  72
  73 /* fsmc controller registers for NAND flash */
  74 #define PC                      0x00
  75         /* pc register definitions */
  76         #define FSMC_RESET              (1 << 0)
  77         #define FSMC_WAITON             (1 << 1)
  78         #define FSMC_ENABLE             (1 << 2)
  79         #define FSMC_DEVTYPE_NAND       (1 << 3)
  80         #define FSMC_DEVWID_8           (0 << 4)
  81         #define FSMC_DEVWID_16          (1 << 4)
  82         #define FSMC_ECCEN              (1 << 6)
  83         #define FSMC_ECCPLEN_512        (0 << 7)
  84         #define FSMC_ECCPLEN_256        (1 << 7)
  85         #define FSMC_TCLR_1             (1)
  86         #define FSMC_TCLR_SHIFT         (9)
  87         #define FSMC_TCLR_MASK          (0xF)
  88         #define FSMC_TAR_1              (1)
  89         #define FSMC_TAR_SHIFT          (13)
  90         #define FSMC_TAR_MASK           (0xF)
  91 #define STS                     0x04
  92         /* sts register definitions */
  93         #define FSMC_CODE_RDY           (1 << 15)
  94 #define COMM                    0x08
  95         /* comm register definitions */
  96         #define FSMC_TSET_0             0
  97         #define FSMC_TSET_SHIFT         0
  98         #define FSMC_TSET_MASK          0xFF
  99         #define FSMC_TWAIT_6            6
 100         #define FSMC_TWAIT_SHIFT        8
 101         #define FSMC_TWAIT_MASK         0xFF
 102         #define FSMC_THOLD_4            4
 103         #define FSMC_THOLD_SHIFT        16
 104         #define FSMC_THOLD_MASK         0xFF
 105         #define FSMC_THIZ_1             1
 106         #define FSMC_THIZ_SHIFT         24
 107         #define FSMC_THIZ_MASK          0xFF
 108 #define ATTRIB                  0x0C
 109 #define IOATA                   0x10
 110 #define ECC1                    0x14
 111 #define ECC2                    0x18
 112 #define ECC3                    0x1C
 113 #define FSMC_NAND_BANK_SZ       0x20
 114
 115 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 116                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 117                                                 reg)
 118
 119 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 120
 121 struct fsmc_nand_timings {
 122         uint8_t tclr;
 123         uint8_t tar;
 124         uint8_t thiz;
 125         uint8_t thold;
 126         uint8_t twait;
 127         uint8_t tset;
 128 };
 129
 130 enum access_mode {
 131         USE_DMA_ACCESS = 1,
 132         USE_WORD_ACCESS,
 133 };
 134
 135 /**
 136  * fsmc_nand_platform_data - platform specific NAND controller config
 137  * @nand_timings: timing setup for the physical NAND interface
 138  * @partitions: partition table for the platform, use a default fallback
 139  * if this is NULL
 140  * @nr_partitions: the number of partitions in the previous entry
 141  * @options: different options for the driver
 142  * @width: bus width
 143  * @bank: default bank
 144  * platform-specific. If the controller only supports one bank
 145  * this may be set to NULL
 146  */
 147 struct fsmc_nand_platform_data {
 148         struct fsmc_nand_timings *nand_timings;
 149         struct mtd_partition    *partitions;
 150         unsigned int            nr_partitions;
 151         unsigned int            options;
 152         unsigned int            bank;
 153
 154         enum access_mode        mode;
 155
 156         /* priv structures for dma accesses */
 157         void                    *read_dma_priv;
 158         void                    *write_dma_priv;
 159 };
 160
 161 /**
 162  * struct fsmc_nand_data - structure for FSMC NAND device state
 163  *
 164  * @pid:                Part ID on the AMBA PrimeCell format
 165  * @mtd:                MTD info for a NAND flash.
 166  * @nand:               Chip related info for a NAND flash.
 167  * @partitions:         Partition info for a NAND Flash.
 168  * @nr_partitions:      Total number of partition of a NAND flash.
 169  *
 170  * @bank:               Bank number for probed device.
 171  * @clk:                Clock structure for FSMC.
 172  *
 173  * @read_dma_chan:      DMA channel for read access
 174  * @write_dma_chan:     DMA channel for write access to NAND
 175  * @dma_access_complete: Completion structure
 176  *
 177  * @data_pa:            NAND Physical port for Data.
 178  * @data_va:            NAND port for Data.
 179  * @cmd_va:             NAND port for Command.
 180  * @addr_va:            NAND port for Address.
 181  * @regs_va:            FSMC regs base address.
 182  */
 183 struct fsmc_nand_data {
 184         u32                     pid;
 185         struct nand_chip        nand;
 186         struct mtd_partition    *partitions;
 187         unsigned int            nr_partitions;
 188
 189         unsigned int            bank;
 190         struct device           *dev;
 191         enum access_mode        mode;
 192         struct clk              *clk;
 193
 194         /* DMA related objects */
 195         struct dma_chan         *read_dma_chan;
 196         struct dma_chan         *write_dma_chan;
 197         struct completion       dma_access_complete;
 198
 199         struct fsmc_nand_timings *dev_timings;
 200
 201         dma_addr_t              data_pa;
 202         void __iomem            *data_va;
 203         void __iomem            *cmd_va;
 204         void __iomem            *addr_va;
 205         void __iomem            *regs_va;
 206 };
 207
 208 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 209                                    struct mtd_oob_region *oobregion)
 210 {
 211         struct nand_chip *chip = mtd_to_nand(mtd);
 212
 213         if (section >= chip->ecc.steps)
 214                 return -ERANGE;
 215
 216         oobregion->offset = (section * 16) + 2;
 217         oobregion->length = 3;
 218
 219         return 0;
 220 }
 221
 222 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 223                                     struct mtd_oob_region *oobregion)
 224 {
 225         struct nand_chip *chip = mtd_to_nand(mtd);
 226
 227         if (section >= chip->ecc.steps)
 228                 return -ERANGE;
 229
 230         oobregion->offset = (section * 16) + 8;
 231
 232         if (section < chip->ecc.steps - 1)
 233                 oobregion->length = 8;
 234         else
 235                 oobregion->length = mtd->oobsize - oobregion->offset;
 236
 237         return 0;
 238 }
 239
 240 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 241         .ecc = fsmc_ecc1_ooblayout_ecc,
 242         .free = fsmc_ecc1_ooblayout_free,
 243 };
 244
 245 /*
 246  * ECC placement definitions in oobfree type format.
 247  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 248  * consecutively and immediately after the 512 byte data block for hardware to
 249  * generate the error bit offsets in 512 byte data.
 250  */
 251 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 252                                    struct mtd_oob_region *oobregion)
 253 {
 254         struct nand_chip *chip = mtd_to_nand(mtd);
 255
 256         if (section >= chip->ecc.steps)
 257                 return -ERANGE;
 258
 259         oobregion->length = chip->ecc.bytes;
 260
 261         if (!section && mtd->writesize <= 512)
 262                 oobregion->offset = 0;
 263         else
 264                 oobregion->offset = (section * 16) + 2;
 265
 266         return 0;
 267 }
 268
 269 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 270                                     struct mtd_oob_region *oobregion)
 271 {
 272         struct nand_chip *chip = mtd_to_nand(mtd);
 273
 274         if (section >= chip->ecc.steps)
 275                 return -ERANGE;
 276
 277         oobregion->offset = (section * 16) + 15;
 278
 279         if (section < chip->ecc.steps - 1)
 280                 oobregion->length = 3;
 281         else
 282                 oobregion->length = mtd->oobsize - oobregion->offset;
 283
 284         return 0;
 285 }
 286
 287 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 288         .ecc = fsmc_ecc4_ooblayout_ecc,
 289         .free = fsmc_ecc4_ooblayout_free,
 290 };
 291
 292 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 293 {
 294         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 295 }
 296
 297 /*
 298  * fsmc_cmd_ctrl - For facilitaing Hardware access
 299  * This routine allows hardware specific access to control-lines(ALE,CLE)
 300  */
 301 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 302 {
 303         struct nand_chip *this = mtd_to_nand(mtd);
 304         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 305         void __iomem *regs = host->regs_va;
 306         unsigned int bank = host->bank;
 307
 308         if (ctrl & NAND_CTRL_CHANGE) {
 309                 u32 pc;
 310
 311                 if (ctrl & NAND_CLE) {
 312                         this->IO_ADDR_R = host->cmd_va;
 313                         this->IO_ADDR_W = host->cmd_va;
 314                 } else if (ctrl & NAND_ALE) {
 315                         this->IO_ADDR_R = host->addr_va;
 316                         this->IO_ADDR_W = host->addr_va;
 317                 } else {
 318                         this->IO_ADDR_R = host->data_va;
 319                         this->IO_ADDR_W = host->data_va;
 320                 }
 321
 322                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 323                 if (ctrl & NAND_NCE)
 324                         pc |= FSMC_ENABLE;
 325                 else
 326                         pc &= ~FSMC_ENABLE;
 327                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 328         }
 329
 330         mb();
 331
 332         if (cmd != NAND_CMD_NONE)
 333                 writeb_relaxed(cmd, this->IO_ADDR_W);
 334 }
 335
 336 /*
 337  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 338  *
 339  * This routine initializes timing parameters related to NAND memory access in
 340  * FSMC registers
 341  */
 342 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
 343                            uint32_t busw, struct fsmc_nand_timings *timings)
 344 {
 345         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 346         uint32_t tclr, tar, thiz, thold, twait, tset;
 347         struct fsmc_nand_timings *tims;
 348         struct fsmc_nand_timings default_timings = {
 349                 .tclr   = FSMC_TCLR_1,
 350                 .tar    = FSMC_TAR_1,
 351                 .thiz   = FSMC_THIZ_1,
 352                 .thold  = FSMC_THOLD_4,
 353                 .twait  = FSMC_TWAIT_6,
 354                 .tset   = FSMC_TSET_0,
 355         };
 356
 357         if (timings)
 358                 tims = timings;
 359         else
 360                 tims = &default_timings;
 361
 362         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 363         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 364         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 365         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 366         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 367         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 368
 369         if (busw)
 370                 writel_relaxed(value | FSMC_DEVWID_16,
 371                                 FSMC_NAND_REG(regs, bank, PC));
 372         else
 373                 writel_relaxed(value | FSMC_DEVWID_8,
 374                                 FSMC_NAND_REG(regs, bank, PC));
 375
 376         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 377                         FSMC_NAND_REG(regs, bank, PC));
 378         writel_relaxed(thiz | thold | twait | tset,
 379                         FSMC_NAND_REG(regs, bank, COMM));
 380         writel_relaxed(thiz | thold | twait | tset,
 381                         FSMC_NAND_REG(regs, bank, ATTRIB));
 382 }
 383
 384 /*
 385  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 386  */
 387 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 388 {
 389         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 390         void __iomem *regs = host->regs_va;
 391         uint32_t bank = host->bank;
 392
 393         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 394                         FSMC_NAND_REG(regs, bank, PC));
 395         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 396                         FSMC_NAND_REG(regs, bank, PC));
 397         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 398                         FSMC_NAND_REG(regs, bank, PC));
 399 }
 400
 401 /*
 402  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 403  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 404  * max of 8-bits)
 405  */
 406 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 407                                 uint8_t *ecc)
 408 {
 409         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 410         void __iomem *regs = host->regs_va;
 411         uint32_t bank = host->bank;
 412         uint32_t ecc_tmp;
 413         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 414
 415         do {
 416                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 417                         break;
 418                 else
 419                         cond_resched();
 420         } while (!time_after_eq(jiffies, deadline));
 421
 422         if (time_after_eq(jiffies, deadline)) {
 423                 dev_err(host->dev, "calculate ecc timed out\n");
 424                 return -ETIMEDOUT;
 425         }
 426
 427         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 428         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 429         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 430         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 431         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 432
 433         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 434         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 435         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 436         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 437         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 438
 439         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 440         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 441         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 442         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 443         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 444
 445         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 446         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 447
 448         return 0;
 449 }
 450
 451 /*
 452  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 453  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 454  * max of 1-bit)
 455  */
 456 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 457                                 uint8_t *ecc)
 458 {
 459         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 460         void __iomem *regs = host->regs_va;
 461         uint32_t bank = host->bank;
 462         uint32_t ecc_tmp;
 463
 464         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 465         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 466         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 467         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 468
 469         return 0;
 470 }
 471
 472 /* Count the number of 0's in buff upto a max of max_bits */
 473 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 474 {
 475         int k, written_bits = 0;
 476
 477         for (k = 0; k < size; k++) {
 478                 written_bits += hweight8(~buff[k]);
 479                 if (written_bits > max_bits)
 480                         break;
 481         }
 482
 483         return written_bits;
 484 }
 485
 486 static void dma_complete(void *param)
 487 {
 488         struct fsmc_nand_data *host = param;
 489
 490         complete(&host->dma_access_complete);
 491 }
 492
 493 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 494                 enum dma_data_direction direction)
 495 {
 496         struct dma_chan *chan;
 497         struct dma_device *dma_dev;
 498         struct dma_async_tx_descriptor *tx;
 499         dma_addr_t dma_dst, dma_src, dma_addr;
 500         dma_cookie_t cookie;
 501         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 502         int ret;
 503         unsigned long time_left;
 504
 505         if (direction == DMA_TO_DEVICE)
 506                 chan = host->write_dma_chan;
 507         else if (direction == DMA_FROM_DEVICE)
 508                 chan = host->read_dma_chan;
 509         else
 510                 return -EINVAL;
 511
 512         dma_dev = chan->device;
 513         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 514
 515         if (direction == DMA_TO_DEVICE) {
 516                 dma_src = dma_addr;
 517                 dma_dst = host->data_pa;
 518         } else {
 519                 dma_src = host->data_pa;
 520                 dma_dst = dma_addr;
 521         }
 522
 523         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 524                         len, flags);
 525         if (!tx) {
 526                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 527                 ret = -EIO;
 528                 goto unmap_dma;
 529         }
 530
 531         tx->callback = dma_complete;
 532         tx->callback_param = host;
 533         cookie = tx->tx_submit(tx);
 534
 535         ret = dma_submit_error(cookie);
 536         if (ret) {
 537                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 538                 goto unmap_dma;
 539         }
 540
 541         dma_async_issue_pending(chan);
 542
 543         time_left =
 544         wait_for_completion_timeout(&host->dma_access_complete,
 545                                 msecs_to_jiffies(3000));
 546         if (time_left == 0) {
 547                 dmaengine_terminate_all(chan);
 548                 dev_err(host->dev, "wait_for_completion_timeout\n");
 549                 ret = -ETIMEDOUT;
 550                 goto unmap_dma;
 551         }
 552
 553         ret = 0;
 554
 555 unmap_dma:
 556         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 557
 558         return ret;
 559 }
 560
 561 /*
 562  * fsmc_write_buf - write buffer to chip
 563  * @mtd:        MTD device structure
 564  * @buf:        data buffer
 565  * @len:        number of bytes to write
 566  */
 567 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 568 {
 569         int i;
 570         struct nand_chip *chip = mtd_to_nand(mtd);
 571
 572         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 573                         IS_ALIGNED(len, sizeof(uint32_t))) {
 574                 uint32_t *p = (uint32_t *)buf;
 575                 len = len >> 2;
 576                 for (i = 0; i < len; i++)
 577                         writel_relaxed(p[i], chip->IO_ADDR_W);
 578         } else {
 579                 for (i = 0; i < len; i++)
 580                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 581         }
 582 }
 583
 584 /*
 585  * fsmc_read_buf - read chip data into buffer
 586  * @mtd:        MTD device structure
 587  * @buf:        buffer to store date
 588  * @len:        number of bytes to read
 589  */
 590 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 591 {
 592         int i;
 593         struct nand_chip *chip = mtd_to_nand(mtd);
 594
 595         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 596                         IS_ALIGNED(len, sizeof(uint32_t))) {
 597                 uint32_t *p = (uint32_t *)buf;
 598                 len = len >> 2;
 599                 for (i = 0; i < len; i++)
 600                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 601         } else {
 602                 for (i = 0; i < len; i++)
 603                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 604         }
 605 }
 606
 607 /*
 608  * fsmc_read_buf_dma - read chip data into buffer
 609  * @mtd:        MTD device structure
 610  * @buf:        buffer to store date
 611  * @len:        number of bytes to read
 612  */
 613 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 614 {
 615         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 616
 617         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 618 }
 619
 620 /*
 621  * fsmc_write_buf_dma - write buffer to chip
 622  * @mtd:        MTD device structure
 623  * @buf:        data buffer
 624  * @len:        number of bytes to write
 625  */
 626 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 627                 int len)
 628 {
 629         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 630
 631         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 632 }
 633
 634 /*
 635  * fsmc_read_page_hwecc
 636  * @mtd:        mtd info structure
 637  * @chip:       nand chip info structure
 638  * @buf:        buffer to store read data
 639  * @oob_required:       caller expects OOB data read to chip->oob_poi
 640  * @page:       page number to read
 641  *
 642  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 643  * performed in a strict sequence as follows:
 644  * data(512 byte) -> ecc(13 byte)
 645  * After this read, fsmc hardware generates and reports error data bits(up to a
 646  * max of 8 bits)
 647  */
 648 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 649                                  uint8_t *buf, int oob_required, int page)
 650 {
 651         int i, j, s, stat, eccsize = chip->ecc.size;
 652         int eccbytes = chip->ecc.bytes;
 653         int eccsteps = chip->ecc.steps;
 654         uint8_t *p = buf;
 655         uint8_t *ecc_calc = chip->buffers->ecccalc;
 656         uint8_t *ecc_code = chip->buffers->ecccode;
 657         int off, len, group = 0;
 658         /*
 659          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 660          * end up reading 14 bytes (7 words) from oob. The local array is
 661          * to maintain word alignment
 662          */
 663         uint16_t ecc_oob[7];
 664         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 665         unsigned int max_bitflips = 0;
 666
 667         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 668                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 669                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 670                 chip->read_buf(mtd, p, eccsize);
 671
 672                 for (j = 0; j < eccbytes;) {
 673                         struct mtd_oob_region oobregion;
 674                         int ret;
 675
 676                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 677                         if (ret)
 678                                 return ret;
 679
 680                         off = oobregion.offset;
 681                         len = oobregion.length;
 682
 683                         /*
 684                          * length is intentionally kept a higher multiple of 2
 685                          * to read at least 13 bytes even in case of 16 bit NAND
 686                          * devices
 687                          */
 688                         if (chip->options & NAND_BUSWIDTH_16)
 689                                 len = roundup(len, 2);
 690
 691                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 692                         chip->read_buf(mtd, oob + j, len);
 693                         j += len;
 694                 }
 695
 696                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 697                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 698
 699                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 700                 if (stat < 0) {
 701                         mtd->ecc_stats.failed++;
 702                 } else {
 703                         mtd->ecc_stats.corrected += stat;
 704                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 705                 }
 706         }
 707
 708         return max_bitflips;
 709 }
 710
 711 /*
 712  * fsmc_bch8_correct_data
 713  * @mtd:        mtd info structure
 714  * @dat:        buffer of read data
 715  * @read_ecc:   ecc read from device spare area
 716  * @calc_ecc:   ecc calculated from read data
 717  *
 718  * calc_ecc is a 104 bit information containing maximum of 8 error
 719  * offset informations of 13 bits each in 512 bytes of read data.
 720  */
 721 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 722                              uint8_t *read_ecc, uint8_t *calc_ecc)
 723 {
 724         struct nand_chip *chip = mtd_to_nand(mtd);
 725         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 726         void __iomem *regs = host->regs_va;
 727         unsigned int bank = host->bank;
 728         uint32_t err_idx[8];
 729         uint32_t num_err, i;
 730         uint32_t ecc1, ecc2, ecc3, ecc4;
 731
 732         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 733
 734         /* no bit flipping */
 735         if (likely(num_err == 0))
 736                 return 0;
 737
 738         /* too many errors */
 739         if (unlikely(num_err > 8)) {
 740                 /*
 741                  * This is a temporary erase check. A newly erased page read
 742                  * would result in an ecc error because the oob data is also
 743                  * erased to FF and the calculated ecc for an FF data is not
 744                  * FF..FF.
 745                  * This is a workaround to skip performing correction in case
 746                  * data is FF..FF
 747                  *
 748                  * Logic:
 749                  * For every page, each bit written as 0 is counted until these
 750                  * number of bits are greater than 8 (the maximum correction
 751                  * capability of FSMC for each 512 + 13 bytes)
 752                  */
 753
 754                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 755                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 756
 757                 if ((bits_ecc + bits_data) <= 8) {
 758                         if (bits_data)
 759                                 memset(dat, 0xff, chip->ecc.size);
 760                         return bits_data;
 761                 }
 762
 763                 return -EBADMSG;
 764         }
 765
 766         /*
 767          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 768          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 769          *
 770          * calc_ecc is a 104 bit information containing maximum of 8 error
 771          * offset informations of 13 bits each. calc_ecc is copied into a
 772          * uint64_t array and error offset indexes are populated in err_idx
 773          * array
 774          */
 775         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 776         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 777         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 778         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 779
 780         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 781         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 782         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 783         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 784         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 785         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 786         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 787         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 788
 789         i = 0;
 790         while (num_err--) {
 791                 change_bit(0, (unsigned long *)&err_idx[i]);
 792                 change_bit(1, (unsigned long *)&err_idx[i]);
 793
 794                 if (err_idx[i] < chip->ecc.size * 8) {
 795                         change_bit(err_idx[i], (unsigned long *)dat);
 796                         i++;
 797                 }
 798         }
 799         return i;
 800 }
 801
 802 static bool filter(struct dma_chan *chan, void *slave)
 803 {
 804         chan->private = slave;
 805         return true;
 806 }
 807
 808 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 809                                      struct device_node *np)
 810 {
 811         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 812         u32 val;
 813         int ret;
 814
 815         pdata->options = 0;
 816
 817         if (!of_property_read_u32(np, "bank-width", &val)) {
 818                 if (val == 2) {
 819                         pdata->options |= NAND_BUSWIDTH_16;
 820                 } else if (val != 1) {
 821                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 822                         return -EINVAL;
 823                 }
 824         }
 825
 826         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 827                 pdata->options |= NAND_SKIP_BBTSCAN;
 828
 829         pdata->nand_timings = devm_kzalloc(&pdev->dev,
 830                                 sizeof(*pdata->nand_timings), GFP_KERNEL);
 831         if (!pdata->nand_timings)
 832                 return -ENOMEM;
 833         ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
 834                                                 sizeof(*pdata->nand_timings));
 835         if (ret) {
 836                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 837                 pdata->nand_timings = NULL;
 838         }
 839
 840         /* Set default NAND bank to 0 */
 841         pdata->bank = 0;
 842         if (!of_property_read_u32(np, "bank", &val)) {
 843                 if (val > 3) {
 844                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 845                         return -EINVAL;
 846                 }
 847                 pdata->bank = val;
 848         }
 849         return 0;
 850 }
 851
 852 /*
 853  * fsmc_nand_probe - Probe function
 854  * @pdev:       platform device structure
 855  */
 856 static int __init fsmc_nand_probe(struct platform_device *pdev)
 857 {
 858         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 859         struct device_node __maybe_unused *np = pdev->dev.of_node;
 860         struct fsmc_nand_data *host;
 861         struct mtd_info *mtd;
 862         struct nand_chip *nand;
 863         struct resource *res;
 864         dma_cap_mask_t mask;
 865         int ret = 0;
 866         u32 pid;
 867         int i;
 868
 869         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 870         if (!pdata)
 871                 return -ENOMEM;
 872
 873         pdev->dev.platform_data = pdata;
 874         ret = fsmc_nand_probe_config_dt(pdev, np);
 875         if (ret) {
 876                 dev_err(&pdev->dev, "no platform data\n");
 877                 return -ENODEV;
 878         }
 879
 880         /* Allocate memory for the device structure (and zero it) */
 881         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 882         if (!host)
 883                 return -ENOMEM;
 884
 885         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 886         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 887         if (IS_ERR(host->data_va))
 888                 return PTR_ERR(host->data_va);
 889
 890         host->data_pa = (dma_addr_t)res->start;
 891
 892         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 893         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 894         if (IS_ERR(host->addr_va))
 895                 return PTR_ERR(host->addr_va);
 896
 897         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 898         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 899         if (IS_ERR(host->cmd_va))
 900                 return PTR_ERR(host->cmd_va);
 901
 902         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 903         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 904         if (IS_ERR(host->regs_va))
 905                 return PTR_ERR(host->regs_va);
 906
 907         host->clk = clk_get(&pdev->dev, NULL);
 908         if (IS_ERR(host->clk)) {
 909                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 910                 return PTR_ERR(host->clk);
 911         }
 912
 913         ret = clk_prepare_enable(host->clk);
 914         if (ret)
 915                 goto err_clk_prepare_enable;
 916
 917         /*
 918          * This device ID is actually a common AMBA ID as used on the
 919          * AMBA PrimeCell bus. However it is not a PrimeCell.
 920          */
 921         for (pid = 0, i = 0; i < 4; i++)
 922                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 923         host->pid = pid;
 924         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 925                  "revision %02x, config %02x\n",
 926                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 927                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 928
 929         host->bank = pdata->bank;
 930         host->partitions = pdata->partitions;
 931         host->nr_partitions = pdata->nr_partitions;
 932         host->dev = &pdev->dev;
 933         host->dev_timings = pdata->nand_timings;
 934         host->mode = pdata->mode;
 935
 936         if (host->mode == USE_DMA_ACCESS)
 937                 init_completion(&host->dma_access_complete);
 938
 939         /* Link all private pointers */
 940         mtd = nand_to_mtd(&host->nand);
 941         nand = &host->nand;
 942         nand_set_controller_data(nand, host);
 943         nand_set_flash_node(nand, np);
 944
 945         mtd->dev.parent = &pdev->dev;
 946         nand->IO_ADDR_R = host->data_va;
 947         nand->IO_ADDR_W = host->data_va;
 948         nand->cmd_ctrl = fsmc_cmd_ctrl;
 949         nand->chip_delay = 30;
 950
 951         /*
 952          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 953          * can overwrite this value if the DT provides a different value.
 954          */
 955         nand->ecc.mode = NAND_ECC_HW;
 956         nand->ecc.hwctl = fsmc_enable_hwecc;
 957         nand->ecc.size = 512;
 958         nand->options = pdata->options;
 959         nand->badblockbits = 7;
 960         nand_set_flash_node(nand, np);
 961
 962         switch (host->mode) {
 963         case USE_DMA_ACCESS:
 964                 dma_cap_zero(mask);
 965                 dma_cap_set(DMA_MEMCPY, mask);
 966                 host->read_dma_chan = dma_request_channel(mask, filter,
 967                                 pdata->read_dma_priv);
 968                 if (!host->read_dma_chan) {
 969                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
 970                         goto err_req_read_chnl;
 971                 }
 972                 host->write_dma_chan = dma_request_channel(mask, filter,
 973                                 pdata->write_dma_priv);
 974                 if (!host->write_dma_chan) {
 975                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
 976                         goto err_req_write_chnl;
 977                 }
 978                 nand->read_buf = fsmc_read_buf_dma;
 979                 nand->write_buf = fsmc_write_buf_dma;
 980                 break;
 981
 982         default:
 983         case USE_WORD_ACCESS:
 984                 nand->read_buf = fsmc_read_buf;
 985                 nand->write_buf = fsmc_write_buf;
 986                 break;
 987         }
 988
 989         fsmc_nand_setup(host->regs_va, host->bank,
 990                         nand->options & NAND_BUSWIDTH_16,
 991                         host->dev_timings);
 992
 993         if (AMBA_REV_BITS(host->pid) >= 8) {
 994                 nand->ecc.read_page = fsmc_read_page_hwecc;
 995                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 996                 nand->ecc.correct = fsmc_bch8_correct_data;
 997                 nand->ecc.bytes = 13;
 998                 nand->ecc.strength = 8;
 999         }
1000
1001         /*
1002          * Scan to find existence of the device
1003          */
1004         ret = nand_scan_ident(mtd, 1, NULL);
1005         if (ret) {
1006                 dev_err(&pdev->dev, "No NAND Device found!\n");
1007                 goto err_scan_ident;
1008         }
1009
1010         if (AMBA_REV_BITS(host->pid) >= 8) {
1011                 switch (mtd->oobsize) {
1012                 case 16:
1013                 case 64:
1014                 case 128:
1015                 case 224:
1016                 case 256:
1017                         break;
1018                 default:
1019                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1020                                  mtd->oobsize);
1021                         ret = -EINVAL;
1022                         goto err_probe;
1023                 }
1024
1025                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1026         } else {
1027                 switch (nand->ecc.mode) {
1028                 case NAND_ECC_HW:
1029                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1030                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1031                         nand->ecc.correct = nand_correct_data;
1032                         nand->ecc.bytes = 3;
1033                         nand->ecc.strength = 1;
1034                         break;
1035
1036                 case NAND_ECC_SOFT:
1037                         if (nand->ecc.algo == NAND_ECC_BCH) {
1038                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1039                                 break;
1040                         }
1041
1042                 default:
1043                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1044                         goto err_probe;
1045                 }
1046
1047                 /*
1048                  * Don't set layout for BCH4 SW ECC. This will be
1049                  * generated later in nand_bch_init() later.
1050                  */
1051                 if (nand->ecc.mode == NAND_ECC_HW) {
1052                         switch (mtd->oobsize) {
1053                         case 16:
1054                         case 64:
1055                         case 128:
1056                                 mtd_set_ooblayout(mtd,
1057                                                   &fsmc_ecc1_ooblayout_ops);
1058                                 break;
1059                         default:
1060                                 dev_warn(&pdev->dev,
1061                                          "No oob scheme defined for oobsize %d\n",
1062                                          mtd->oobsize);
1063                                 ret = -EINVAL;
1064                                 goto err_probe;
1065                         }
1066                 }
1067         }
1068
1069         /* Second stage of scan to fill MTD data-structures */
1070         ret = nand_scan_tail(mtd);
1071         if (ret)
1072                 goto err_probe;
1073
1074         /*
1075          * The partition information can is accessed by (in the same precedence)
1076          *
1077          * command line through Bootloader,
1078          * platform data,
1079          * default partition information present in driver.
1080          */
1081         /*
1082          * Check for partition info passed
1083          */
1084         mtd->name = "nand";
1085         ret = mtd_device_register(mtd, host->partitions, host->nr_partitions);
1086         if (ret)
1087                 goto err_probe;
1088
1089         platform_set_drvdata(pdev, host);
1090         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1091         return 0;
1092
1093 err_probe:
1094 err_scan_ident:
1095         if (host->mode == USE_DMA_ACCESS)
1096                 dma_release_channel(host->write_dma_chan);
1097 err_req_write_chnl:
1098         if (host->mode == USE_DMA_ACCESS)
1099                 dma_release_channel(host->read_dma_chan);
1100 err_req_read_chnl:
1101         clk_disable_unprepare(host->clk);
1102 err_clk_prepare_enable:
1103         clk_put(host->clk);
1104         return ret;
1105 }
1106
1107 /*
1108  * Clean up routine
1109  */
1110 static int fsmc_nand_remove(struct platform_device *pdev)
1111 {
1112         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1113
1114         if (host) {
1115                 nand_release(nand_to_mtd(&host->nand));
1116
1117                 if (host->mode == USE_DMA_ACCESS) {
1118                         dma_release_channel(host->write_dma_chan);
1119                         dma_release_channel(host->read_dma_chan);
1120                 }
1121                 clk_disable_unprepare(host->clk);
1122                 clk_put(host->clk);
1123         }
1124
1125         return 0;
1126 }
1127
1128 #ifdef CONFIG_PM_SLEEP
1129 static int fsmc_nand_suspend(struct device *dev)
1130 {
1131         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1132         if (host)
1133                 clk_disable_unprepare(host->clk);
1134         return 0;
1135 }
1136
1137 static int fsmc_nand_resume(struct device *dev)
1138 {
1139         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1140         if (host) {
1141                 clk_prepare_enable(host->clk);
1142                 fsmc_nand_setup(host->regs_va, host->bank,
1143                                 host->nand.options & NAND_BUSWIDTH_16,
1144                                 host->dev_timings);
1145         }
1146         return 0;
1147 }
1148 #endif
1149
1150 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1151
1152 #ifdef CONFIG_OF
1153 static const struct of_device_id fsmc_nand_id_table[] = {
1154         { .compatible = "st,spear600-fsmc-nand" },
1155         { .compatible = "stericsson,fsmc-nand" },
1156         {}
1157 };
1158 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1159 #endif
1160
1161 static struct platform_driver fsmc_nand_driver = {
1162         .remove = fsmc_nand_remove,
1163         .driver = {
1164                 .name = "fsmc-nand",
1165                 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1166                 .pm = &fsmc_nand_pm_ops,
1167         },
1168 };
1169
1170 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1171
1172 MODULE_LICENSE("GPL");
1173 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1174 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");