drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 #define FSMC_NAND_BW8           1
  42 #define FSMC_NAND_BW16          2
  43
  44 #define FSMC_MAX_NOR_BANKS      4
  45 #define FSMC_MAX_NAND_BANKS     4
  46
  47 #define FSMC_FLASH_WIDTH8       1
  48 #define FSMC_FLASH_WIDTH16      2
  49
  50 /* fsmc controller registers for NOR flash */
  51 #define CTRL                    0x0
  52         /* ctrl register definitions */
  53         #define BANK_ENABLE             (1 << 0)
  54         #define MUXED                   (1 << 1)
  55         #define NOR_DEV                 (2 << 2)
  56         #define WIDTH_8                 (0 << 4)
  57         #define WIDTH_16                (1 << 4)
  58         #define RSTPWRDWN               (1 << 6)
  59         #define WPROT                   (1 << 7)
  60         #define WRT_ENABLE              (1 << 12)
  61         #define WAIT_ENB                (1 << 13)
  62
  63 #define CTRL_TIM                0x4
  64         /* ctrl_tim register definitions */
  65
  66 #define FSMC_NOR_BANK_SZ        0x8
  67 #define FSMC_NOR_REG_SIZE       0x40
  68
  69 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  70                                                 FSMC_NOR_BANK_SZ * (bank) + \
  71                                                 reg)
  72
  73 /* fsmc controller registers for NAND flash */
  74 #define PC                      0x00
  75         /* pc register definitions */
  76         #define FSMC_RESET              (1 << 0)
  77         #define FSMC_WAITON             (1 << 1)
  78         #define FSMC_ENABLE             (1 << 2)
  79         #define FSMC_DEVTYPE_NAND       (1 << 3)
  80         #define FSMC_DEVWID_8           (0 << 4)
  81         #define FSMC_DEVWID_16          (1 << 4)
  82         #define FSMC_ECCEN              (1 << 6)
  83         #define FSMC_ECCPLEN_512        (0 << 7)
  84         #define FSMC_ECCPLEN_256        (1 << 7)
  85         #define FSMC_TCLR_1             (1)
  86         #define FSMC_TCLR_SHIFT         (9)
  87         #define FSMC_TCLR_MASK          (0xF)
  88         #define FSMC_TAR_1              (1)
  89         #define FSMC_TAR_SHIFT          (13)
  90         #define FSMC_TAR_MASK           (0xF)
  91 #define STS                     0x04
  92         /* sts register definitions */
  93         #define FSMC_CODE_RDY           (1 << 15)
  94 #define COMM                    0x08
  95         /* comm register definitions */
  96         #define FSMC_TSET_0             0
  97         #define FSMC_TSET_SHIFT         0
  98         #define FSMC_TSET_MASK          0xFF
  99         #define FSMC_TWAIT_6            6
 100         #define FSMC_TWAIT_SHIFT        8
 101         #define FSMC_TWAIT_MASK         0xFF
 102         #define FSMC_THOLD_4            4
 103         #define FSMC_THOLD_SHIFT        16
 104         #define FSMC_THOLD_MASK         0xFF
 105         #define FSMC_THIZ_1             1
 106         #define FSMC_THIZ_SHIFT         24
 107         #define FSMC_THIZ_MASK          0xFF
 108 #define ATTRIB                  0x0C
 109 #define IOATA                   0x10
 110 #define ECC1                    0x14
 111 #define ECC2                    0x18
 112 #define ECC3                    0x1C
 113 #define FSMC_NAND_BANK_SZ       0x20
 114
 115 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 116                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 117                                                 reg)
 118
 119 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 120
 121 struct fsmc_nand_timings {
 122         uint8_t tclr;
 123         uint8_t tar;
 124         uint8_t thiz;
 125         uint8_t thold;
 126         uint8_t twait;
 127         uint8_t tset;
 128 };
 129
 130 enum access_mode {
 131         USE_DMA_ACCESS = 1,
 132         USE_WORD_ACCESS,
 133 };
 134
 135 /**
 136  * struct fsmc_nand_data - structure for FSMC NAND device state
 137  *
 138  * @pid:                Part ID on the AMBA PrimeCell format
 139  * @mtd:                MTD info for a NAND flash.
 140  * @nand:               Chip related info for a NAND flash.
 141  * @partitions:         Partition info for a NAND Flash.
 142  * @nr_partitions:      Total number of partition of a NAND flash.
 143  *
 144  * @bank:               Bank number for probed device.
 145  * @clk:                Clock structure for FSMC.
 146  *
 147  * @read_dma_chan:      DMA channel for read access
 148  * @write_dma_chan:     DMA channel for write access to NAND
 149  * @dma_access_complete: Completion structure
 150  *
 151  * @data_pa:            NAND Physical port for Data.
 152  * @data_va:            NAND port for Data.
 153  * @cmd_va:             NAND port for Command.
 154  * @addr_va:            NAND port for Address.
 155  * @regs_va:            FSMC regs base address.
 156  */
 157 struct fsmc_nand_data {
 158         u32                     pid;
 159         struct nand_chip        nand;
 160
 161         unsigned int            bank;
 162         struct device           *dev;
 163         enum access_mode        mode;
 164         struct clk              *clk;
 165
 166         /* DMA related objects */
 167         struct dma_chan         *read_dma_chan;
 168         struct dma_chan         *write_dma_chan;
 169         struct completion       dma_access_complete;
 170
 171         struct fsmc_nand_timings *dev_timings;
 172
 173         dma_addr_t              data_pa;
 174         void __iomem            *data_va;
 175         void __iomem            *cmd_va;
 176         void __iomem            *addr_va;
 177         void __iomem            *regs_va;
 178 };
 179
 180 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 181                                    struct mtd_oob_region *oobregion)
 182 {
 183         struct nand_chip *chip = mtd_to_nand(mtd);
 184
 185         if (section >= chip->ecc.steps)
 186                 return -ERANGE;
 187
 188         oobregion->offset = (section * 16) + 2;
 189         oobregion->length = 3;
 190
 191         return 0;
 192 }
 193
 194 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 195                                     struct mtd_oob_region *oobregion)
 196 {
 197         struct nand_chip *chip = mtd_to_nand(mtd);
 198
 199         if (section >= chip->ecc.steps)
 200                 return -ERANGE;
 201
 202         oobregion->offset = (section * 16) + 8;
 203
 204         if (section < chip->ecc.steps - 1)
 205                 oobregion->length = 8;
 206         else
 207                 oobregion->length = mtd->oobsize - oobregion->offset;
 208
 209         return 0;
 210 }
 211
 212 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 213         .ecc = fsmc_ecc1_ooblayout_ecc,
 214         .free = fsmc_ecc1_ooblayout_free,
 215 };
 216
 217 /*
 218  * ECC placement definitions in oobfree type format.
 219  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 220  * consecutively and immediately after the 512 byte data block for hardware to
 221  * generate the error bit offsets in 512 byte data.
 222  */
 223 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 224                                    struct mtd_oob_region *oobregion)
 225 {
 226         struct nand_chip *chip = mtd_to_nand(mtd);
 227
 228         if (section >= chip->ecc.steps)
 229                 return -ERANGE;
 230
 231         oobregion->length = chip->ecc.bytes;
 232
 233         if (!section && mtd->writesize <= 512)
 234                 oobregion->offset = 0;
 235         else
 236                 oobregion->offset = (section * 16) + 2;
 237
 238         return 0;
 239 }
 240
 241 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 242                                     struct mtd_oob_region *oobregion)
 243 {
 244         struct nand_chip *chip = mtd_to_nand(mtd);
 245
 246         if (section >= chip->ecc.steps)
 247                 return -ERANGE;
 248
 249         oobregion->offset = (section * 16) + 15;
 250
 251         if (section < chip->ecc.steps - 1)
 252                 oobregion->length = 3;
 253         else
 254                 oobregion->length = mtd->oobsize - oobregion->offset;
 255
 256         return 0;
 257 }
 258
 259 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 260         .ecc = fsmc_ecc4_ooblayout_ecc,
 261         .free = fsmc_ecc4_ooblayout_free,
 262 };
 263
 264 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 265 {
 266         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 267 }
 268
 269 /*
 270  * fsmc_cmd_ctrl - For facilitaing Hardware access
 271  * This routine allows hardware specific access to control-lines(ALE,CLE)
 272  */
 273 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 274 {
 275         struct nand_chip *this = mtd_to_nand(mtd);
 276         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 277         void __iomem *regs = host->regs_va;
 278         unsigned int bank = host->bank;
 279
 280         if (ctrl & NAND_CTRL_CHANGE) {
 281                 u32 pc;
 282
 283                 if (ctrl & NAND_CLE) {
 284                         this->IO_ADDR_R = host->cmd_va;
 285                         this->IO_ADDR_W = host->cmd_va;
 286                 } else if (ctrl & NAND_ALE) {
 287                         this->IO_ADDR_R = host->addr_va;
 288                         this->IO_ADDR_W = host->addr_va;
 289                 } else {
 290                         this->IO_ADDR_R = host->data_va;
 291                         this->IO_ADDR_W = host->data_va;
 292                 }
 293
 294                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 295                 if (ctrl & NAND_NCE)
 296                         pc |= FSMC_ENABLE;
 297                 else
 298                         pc &= ~FSMC_ENABLE;
 299                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 300         }
 301
 302         mb();
 303
 304         if (cmd != NAND_CMD_NONE)
 305                 writeb_relaxed(cmd, this->IO_ADDR_W);
 306 }
 307
 308 /*
 309  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 310  *
 311  * This routine initializes timing parameters related to NAND memory access in
 312  * FSMC registers
 313  */
 314 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
 315                            uint32_t busw, struct fsmc_nand_timings *timings)
 316 {
 317         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 318         uint32_t tclr, tar, thiz, thold, twait, tset;
 319         struct fsmc_nand_timings *tims;
 320         struct fsmc_nand_timings default_timings = {
 321                 .tclr   = FSMC_TCLR_1,
 322                 .tar    = FSMC_TAR_1,
 323                 .thiz   = FSMC_THIZ_1,
 324                 .thold  = FSMC_THOLD_4,
 325                 .twait  = FSMC_TWAIT_6,
 326                 .tset   = FSMC_TSET_0,
 327         };
 328
 329         if (timings)
 330                 tims = timings;
 331         else
 332                 tims = &default_timings;
 333
 334         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 335         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 336         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 337         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 338         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 339         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 340
 341         if (busw)
 342                 writel_relaxed(value | FSMC_DEVWID_16,
 343                                 FSMC_NAND_REG(regs, bank, PC));
 344         else
 345                 writel_relaxed(value | FSMC_DEVWID_8,
 346                                 FSMC_NAND_REG(regs, bank, PC));
 347
 348         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 349                         FSMC_NAND_REG(regs, bank, PC));
 350         writel_relaxed(thiz | thold | twait | tset,
 351                         FSMC_NAND_REG(regs, bank, COMM));
 352         writel_relaxed(thiz | thold | twait | tset,
 353                         FSMC_NAND_REG(regs, bank, ATTRIB));
 354 }
 355
 356 /*
 357  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 358  */
 359 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 360 {
 361         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 362         void __iomem *regs = host->regs_va;
 363         uint32_t bank = host->bank;
 364
 365         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 366                         FSMC_NAND_REG(regs, bank, PC));
 367         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 368                         FSMC_NAND_REG(regs, bank, PC));
 369         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 370                         FSMC_NAND_REG(regs, bank, PC));
 371 }
 372
 373 /*
 374  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 375  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 376  * max of 8-bits)
 377  */
 378 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 379                                 uint8_t *ecc)
 380 {
 381         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 382         void __iomem *regs = host->regs_va;
 383         uint32_t bank = host->bank;
 384         uint32_t ecc_tmp;
 385         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 386
 387         do {
 388                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 389                         break;
 390                 else
 391                         cond_resched();
 392         } while (!time_after_eq(jiffies, deadline));
 393
 394         if (time_after_eq(jiffies, deadline)) {
 395                 dev_err(host->dev, "calculate ecc timed out\n");
 396                 return -ETIMEDOUT;
 397         }
 398
 399         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 400         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 401         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 402         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 403         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 404
 405         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 406         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 407         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 408         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 409         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 410
 411         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 412         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 413         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 414         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 415         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 416
 417         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 418         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 419
 420         return 0;
 421 }
 422
 423 /*
 424  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 425  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 426  * max of 1-bit)
 427  */
 428 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 429                                 uint8_t *ecc)
 430 {
 431         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 432         void __iomem *regs = host->regs_va;
 433         uint32_t bank = host->bank;
 434         uint32_t ecc_tmp;
 435
 436         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 437         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 438         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 439         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 440
 441         return 0;
 442 }
 443
 444 /* Count the number of 0's in buff upto a max of max_bits */
 445 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 446 {
 447         int k, written_bits = 0;
 448
 449         for (k = 0; k < size; k++) {
 450                 written_bits += hweight8(~buff[k]);
 451                 if (written_bits > max_bits)
 452                         break;
 453         }
 454
 455         return written_bits;
 456 }
 457
 458 static void dma_complete(void *param)
 459 {
 460         struct fsmc_nand_data *host = param;
 461
 462         complete(&host->dma_access_complete);
 463 }
 464
 465 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 466                 enum dma_data_direction direction)
 467 {
 468         struct dma_chan *chan;
 469         struct dma_device *dma_dev;
 470         struct dma_async_tx_descriptor *tx;
 471         dma_addr_t dma_dst, dma_src, dma_addr;
 472         dma_cookie_t cookie;
 473         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 474         int ret;
 475         unsigned long time_left;
 476
 477         if (direction == DMA_TO_DEVICE)
 478                 chan = host->write_dma_chan;
 479         else if (direction == DMA_FROM_DEVICE)
 480                 chan = host->read_dma_chan;
 481         else
 482                 return -EINVAL;
 483
 484         dma_dev = chan->device;
 485         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 486
 487         if (direction == DMA_TO_DEVICE) {
 488                 dma_src = dma_addr;
 489                 dma_dst = host->data_pa;
 490         } else {
 491                 dma_src = host->data_pa;
 492                 dma_dst = dma_addr;
 493         }
 494
 495         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 496                         len, flags);
 497         if (!tx) {
 498                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 499                 ret = -EIO;
 500                 goto unmap_dma;
 501         }
 502
 503         tx->callback = dma_complete;
 504         tx->callback_param = host;
 505         cookie = tx->tx_submit(tx);
 506
 507         ret = dma_submit_error(cookie);
 508         if (ret) {
 509                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 510                 goto unmap_dma;
 511         }
 512
 513         dma_async_issue_pending(chan);
 514
 515         time_left =
 516         wait_for_completion_timeout(&host->dma_access_complete,
 517                                 msecs_to_jiffies(3000));
 518         if (time_left == 0) {
 519                 dmaengine_terminate_all(chan);
 520                 dev_err(host->dev, "wait_for_completion_timeout\n");
 521                 ret = -ETIMEDOUT;
 522                 goto unmap_dma;
 523         }
 524
 525         ret = 0;
 526
 527 unmap_dma:
 528         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 529
 530         return ret;
 531 }
 532
 533 /*
 534  * fsmc_write_buf - write buffer to chip
 535  * @mtd:        MTD device structure
 536  * @buf:        data buffer
 537  * @len:        number of bytes to write
 538  */
 539 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 540 {
 541         int i;
 542         struct nand_chip *chip = mtd_to_nand(mtd);
 543
 544         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 545                         IS_ALIGNED(len, sizeof(uint32_t))) {
 546                 uint32_t *p = (uint32_t *)buf;
 547                 len = len >> 2;
 548                 for (i = 0; i < len; i++)
 549                         writel_relaxed(p[i], chip->IO_ADDR_W);
 550         } else {
 551                 for (i = 0; i < len; i++)
 552                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 553         }
 554 }
 555
 556 /*
 557  * fsmc_read_buf - read chip data into buffer
 558  * @mtd:        MTD device structure
 559  * @buf:        buffer to store date
 560  * @len:        number of bytes to read
 561  */
 562 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 563 {
 564         int i;
 565         struct nand_chip *chip = mtd_to_nand(mtd);
 566
 567         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 568                         IS_ALIGNED(len, sizeof(uint32_t))) {
 569                 uint32_t *p = (uint32_t *)buf;
 570                 len = len >> 2;
 571                 for (i = 0; i < len; i++)
 572                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 573         } else {
 574                 for (i = 0; i < len; i++)
 575                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 576         }
 577 }
 578
 579 /*
 580  * fsmc_read_buf_dma - read chip data into buffer
 581  * @mtd:        MTD device structure
 582  * @buf:        buffer to store date
 583  * @len:        number of bytes to read
 584  */
 585 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 586 {
 587         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 588
 589         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 590 }
 591
 592 /*
 593  * fsmc_write_buf_dma - write buffer to chip
 594  * @mtd:        MTD device structure
 595  * @buf:        data buffer
 596  * @len:        number of bytes to write
 597  */
 598 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 599                 int len)
 600 {
 601         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 602
 603         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 604 }
 605
 606 /*
 607  * fsmc_read_page_hwecc
 608  * @mtd:        mtd info structure
 609  * @chip:       nand chip info structure
 610  * @buf:        buffer to store read data
 611  * @oob_required:       caller expects OOB data read to chip->oob_poi
 612  * @page:       page number to read
 613  *
 614  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 615  * performed in a strict sequence as follows:
 616  * data(512 byte) -> ecc(13 byte)
 617  * After this read, fsmc hardware generates and reports error data bits(up to a
 618  * max of 8 bits)
 619  */
 620 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 621                                  uint8_t *buf, int oob_required, int page)
 622 {
 623         int i, j, s, stat, eccsize = chip->ecc.size;
 624         int eccbytes = chip->ecc.bytes;
 625         int eccsteps = chip->ecc.steps;
 626         uint8_t *p = buf;
 627         uint8_t *ecc_calc = chip->buffers->ecccalc;
 628         uint8_t *ecc_code = chip->buffers->ecccode;
 629         int off, len, group = 0;
 630         /*
 631          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 632          * end up reading 14 bytes (7 words) from oob. The local array is
 633          * to maintain word alignment
 634          */
 635         uint16_t ecc_oob[7];
 636         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 637         unsigned int max_bitflips = 0;
 638
 639         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 640                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 641                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 642                 chip->read_buf(mtd, p, eccsize);
 643
 644                 for (j = 0; j < eccbytes;) {
 645                         struct mtd_oob_region oobregion;
 646                         int ret;
 647
 648                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 649                         if (ret)
 650                                 return ret;
 651
 652                         off = oobregion.offset;
 653                         len = oobregion.length;
 654
 655                         /*
 656                          * length is intentionally kept a higher multiple of 2
 657                          * to read at least 13 bytes even in case of 16 bit NAND
 658                          * devices
 659                          */
 660                         if (chip->options & NAND_BUSWIDTH_16)
 661                                 len = roundup(len, 2);
 662
 663                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 664                         chip->read_buf(mtd, oob + j, len);
 665                         j += len;
 666                 }
 667
 668                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 669                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 670
 671                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 672                 if (stat < 0) {
 673                         mtd->ecc_stats.failed++;
 674                 } else {
 675                         mtd->ecc_stats.corrected += stat;
 676                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 677                 }
 678         }
 679
 680         return max_bitflips;
 681 }
 682
 683 /*
 684  * fsmc_bch8_correct_data
 685  * @mtd:        mtd info structure
 686  * @dat:        buffer of read data
 687  * @read_ecc:   ecc read from device spare area
 688  * @calc_ecc:   ecc calculated from read data
 689  *
 690  * calc_ecc is a 104 bit information containing maximum of 8 error
 691  * offset informations of 13 bits each in 512 bytes of read data.
 692  */
 693 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 694                              uint8_t *read_ecc, uint8_t *calc_ecc)
 695 {
 696         struct nand_chip *chip = mtd_to_nand(mtd);
 697         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 698         void __iomem *regs = host->regs_va;
 699         unsigned int bank = host->bank;
 700         uint32_t err_idx[8];
 701         uint32_t num_err, i;
 702         uint32_t ecc1, ecc2, ecc3, ecc4;
 703
 704         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 705
 706         /* no bit flipping */
 707         if (likely(num_err == 0))
 708                 return 0;
 709
 710         /* too many errors */
 711         if (unlikely(num_err > 8)) {
 712                 /*
 713                  * This is a temporary erase check. A newly erased page read
 714                  * would result in an ecc error because the oob data is also
 715                  * erased to FF and the calculated ecc for an FF data is not
 716                  * FF..FF.
 717                  * This is a workaround to skip performing correction in case
 718                  * data is FF..FF
 719                  *
 720                  * Logic:
 721                  * For every page, each bit written as 0 is counted until these
 722                  * number of bits are greater than 8 (the maximum correction
 723                  * capability of FSMC for each 512 + 13 bytes)
 724                  */
 725
 726                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 727                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 728
 729                 if ((bits_ecc + bits_data) <= 8) {
 730                         if (bits_data)
 731                                 memset(dat, 0xff, chip->ecc.size);
 732                         return bits_data;
 733                 }
 734
 735                 return -EBADMSG;
 736         }
 737
 738         /*
 739          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 740          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 741          *
 742          * calc_ecc is a 104 bit information containing maximum of 8 error
 743          * offset informations of 13 bits each. calc_ecc is copied into a
 744          * uint64_t array and error offset indexes are populated in err_idx
 745          * array
 746          */
 747         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 748         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 749         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 750         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 751
 752         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 753         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 754         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 755         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 756         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 757         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 758         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 759         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 760
 761         i = 0;
 762         while (num_err--) {
 763                 change_bit(0, (unsigned long *)&err_idx[i]);
 764                 change_bit(1, (unsigned long *)&err_idx[i]);
 765
 766                 if (err_idx[i] < chip->ecc.size * 8) {
 767                         change_bit(err_idx[i], (unsigned long *)dat);
 768                         i++;
 769                 }
 770         }
 771         return i;
 772 }
 773
 774 static bool filter(struct dma_chan *chan, void *slave)
 775 {
 776         chan->private = slave;
 777         return true;
 778 }
 779
 780 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 781                                      struct fsmc_nand_data *host,
 782                                      struct nand_chip *nand)
 783 {
 784         struct device_node *np = pdev->dev.of_node;
 785         u32 val;
 786         int ret;
 787
 788         nand->options = 0;
 789
 790         if (!of_property_read_u32(np, "bank-width", &val)) {
 791                 if (val == 2) {
 792                         nand->options |= NAND_BUSWIDTH_16;
 793                 } else if (val != 1) {
 794                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 795                         return -EINVAL;
 796                 }
 797         }
 798
 799         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 800                 nand->options |= NAND_SKIP_BBTSCAN;
 801
 802         host->dev_timings = devm_kzalloc(&pdev->dev,
 803                                 sizeof(*host->dev_timings), GFP_KERNEL);
 804         if (!host->dev_timings)
 805                 return -ENOMEM;
 806         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 807                                                 sizeof(*host->dev_timings));
 808         if (ret) {
 809                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 810                 host->dev_timings = NULL;
 811         }
 812
 813         /* Set default NAND bank to 0 */
 814         host->bank = 0;
 815         if (!of_property_read_u32(np, "bank", &val)) {
 816                 if (val > 3) {
 817                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 818                         return -EINVAL;
 819                 }
 820                 host->bank = val;
 821         }
 822         return 0;
 823 }
 824
 825 /*
 826  * fsmc_nand_probe - Probe function
 827  * @pdev:       platform device structure
 828  */
 829 static int __init fsmc_nand_probe(struct platform_device *pdev)
 830 {
 831         struct fsmc_nand_data *host;
 832         struct mtd_info *mtd;
 833         struct nand_chip *nand;
 834         struct resource *res;
 835         dma_cap_mask_t mask;
 836         int ret = 0;
 837         u32 pid;
 838         int i;
 839
 840         /* Allocate memory for the device structure (and zero it) */
 841         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 842         if (!host)
 843                 return -ENOMEM;
 844
 845         nand = &host->nand;
 846
 847         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
 848         if (ret)
 849                 return ret;
 850
 851         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 852         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 853         if (IS_ERR(host->data_va))
 854                 return PTR_ERR(host->data_va);
 855
 856         host->data_pa = (dma_addr_t)res->start;
 857
 858         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 859         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 860         if (IS_ERR(host->addr_va))
 861                 return PTR_ERR(host->addr_va);
 862
 863         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 864         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 865         if (IS_ERR(host->cmd_va))
 866                 return PTR_ERR(host->cmd_va);
 867
 868         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 869         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 870         if (IS_ERR(host->regs_va))
 871                 return PTR_ERR(host->regs_va);
 872
 873         host->clk = clk_get(&pdev->dev, NULL);
 874         if (IS_ERR(host->clk)) {
 875                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 876                 return PTR_ERR(host->clk);
 877         }
 878
 879         ret = clk_prepare_enable(host->clk);
 880         if (ret)
 881                 goto err_clk_prepare_enable;
 882
 883         /*
 884          * This device ID is actually a common AMBA ID as used on the
 885          * AMBA PrimeCell bus. However it is not a PrimeCell.
 886          */
 887         for (pid = 0, i = 0; i < 4; i++)
 888                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 889         host->pid = pid;
 890         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 891                  "revision %02x, config %02x\n",
 892                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 893                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 894
 895         host->dev = &pdev->dev;
 896
 897         if (host->mode == USE_DMA_ACCESS)
 898                 init_completion(&host->dma_access_complete);
 899
 900         /* Link all private pointers */
 901         mtd = nand_to_mtd(&host->nand);
 902         nand_set_controller_data(nand, host);
 903         nand_set_flash_node(nand, pdev->dev.of_node);
 904
 905         mtd->dev.parent = &pdev->dev;
 906         nand->IO_ADDR_R = host->data_va;
 907         nand->IO_ADDR_W = host->data_va;
 908         nand->cmd_ctrl = fsmc_cmd_ctrl;
 909         nand->chip_delay = 30;
 910
 911         /*
 912          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 913          * can overwrite this value if the DT provides a different value.
 914          */
 915         nand->ecc.mode = NAND_ECC_HW;
 916         nand->ecc.hwctl = fsmc_enable_hwecc;
 917         nand->ecc.size = 512;
 918         nand->badblockbits = 7;
 919
 920         switch (host->mode) {
 921         case USE_DMA_ACCESS:
 922                 dma_cap_zero(mask);
 923                 dma_cap_set(DMA_MEMCPY, mask);
 924                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
 925                 if (!host->read_dma_chan) {
 926                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
 927                         goto err_req_read_chnl;
 928                 }
 929                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
 930                 if (!host->write_dma_chan) {
 931                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
 932                         goto err_req_write_chnl;
 933                 }
 934                 nand->read_buf = fsmc_read_buf_dma;
 935                 nand->write_buf = fsmc_write_buf_dma;
 936                 break;
 937
 938         default:
 939         case USE_WORD_ACCESS:
 940                 nand->read_buf = fsmc_read_buf;
 941                 nand->write_buf = fsmc_write_buf;
 942                 break;
 943         }
 944
 945         fsmc_nand_setup(host->regs_va, host->bank,
 946                         nand->options & NAND_BUSWIDTH_16,
 947                         host->dev_timings);
 948
 949         if (AMBA_REV_BITS(host->pid) >= 8) {
 950                 nand->ecc.read_page = fsmc_read_page_hwecc;
 951                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 952                 nand->ecc.correct = fsmc_bch8_correct_data;
 953                 nand->ecc.bytes = 13;
 954                 nand->ecc.strength = 8;
 955         }
 956
 957         /*
 958          * Scan to find existence of the device
 959          */
 960         ret = nand_scan_ident(mtd, 1, NULL);
 961         if (ret) {
 962                 dev_err(&pdev->dev, "No NAND Device found!\n");
 963                 goto err_scan_ident;
 964         }
 965
 966         if (AMBA_REV_BITS(host->pid) >= 8) {
 967                 switch (mtd->oobsize) {
 968                 case 16:
 969                 case 64:
 970                 case 128:
 971                 case 224:
 972                 case 256:
 973                         break;
 974                 default:
 975                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
 976                                  mtd->oobsize);
 977                         ret = -EINVAL;
 978                         goto err_probe;
 979                 }
 980
 981                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
 982         } else {
 983                 switch (nand->ecc.mode) {
 984                 case NAND_ECC_HW:
 985                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
 986                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
 987                         nand->ecc.correct = nand_correct_data;
 988                         nand->ecc.bytes = 3;
 989                         nand->ecc.strength = 1;
 990                         break;
 991
 992                 case NAND_ECC_SOFT:
 993                         if (nand->ecc.algo == NAND_ECC_BCH) {
 994                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
 995                                 break;
 996                         }
 997
 998                 default:
 999                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1000                         goto err_probe;
1001                 }
1002
1003                 /*
1004                  * Don't set layout for BCH4 SW ECC. This will be
1005                  * generated later in nand_bch_init() later.
1006                  */
1007                 if (nand->ecc.mode == NAND_ECC_HW) {
1008                         switch (mtd->oobsize) {
1009                         case 16:
1010                         case 64:
1011                         case 128:
1012                                 mtd_set_ooblayout(mtd,
1013                                                   &fsmc_ecc1_ooblayout_ops);
1014                                 break;
1015                         default:
1016                                 dev_warn(&pdev->dev,
1017                                          "No oob scheme defined for oobsize %d\n",
1018                                          mtd->oobsize);
1019                                 ret = -EINVAL;
1020                                 goto err_probe;
1021                         }
1022                 }
1023         }
1024
1025         /* Second stage of scan to fill MTD data-structures */
1026         ret = nand_scan_tail(mtd);
1027         if (ret)
1028                 goto err_probe;
1029
1030         mtd->name = "nand";
1031         ret = mtd_device_register(mtd, NULL, 0);
1032         if (ret)
1033                 goto err_probe;
1034
1035         platform_set_drvdata(pdev, host);
1036         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1037         return 0;
1038
1039 err_probe:
1040 err_scan_ident:
1041         if (host->mode == USE_DMA_ACCESS)
1042                 dma_release_channel(host->write_dma_chan);
1043 err_req_write_chnl:
1044         if (host->mode == USE_DMA_ACCESS)
1045                 dma_release_channel(host->read_dma_chan);
1046 err_req_read_chnl:
1047         clk_disable_unprepare(host->clk);
1048 err_clk_prepare_enable:
1049         clk_put(host->clk);
1050         return ret;
1051 }
1052
1053 /*
1054  * Clean up routine
1055  */
1056 static int fsmc_nand_remove(struct platform_device *pdev)
1057 {
1058         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1059
1060         if (host) {
1061                 nand_release(nand_to_mtd(&host->nand));
1062
1063                 if (host->mode == USE_DMA_ACCESS) {
1064                         dma_release_channel(host->write_dma_chan);
1065                         dma_release_channel(host->read_dma_chan);
1066                 }
1067                 clk_disable_unprepare(host->clk);
1068                 clk_put(host->clk);
1069         }
1070
1071         return 0;
1072 }
1073
1074 #ifdef CONFIG_PM_SLEEP
1075 static int fsmc_nand_suspend(struct device *dev)
1076 {
1077         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1078         if (host)
1079                 clk_disable_unprepare(host->clk);
1080         return 0;
1081 }
1082
1083 static int fsmc_nand_resume(struct device *dev)
1084 {
1085         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1086         if (host) {
1087                 clk_prepare_enable(host->clk);
1088                 fsmc_nand_setup(host->regs_va, host->bank,
1089                                 host->nand.options & NAND_BUSWIDTH_16,
1090                                 host->dev_timings);
1091         }
1092         return 0;
1093 }
1094 #endif
1095
1096 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1097
1098 #ifdef CONFIG_OF
1099 static const struct of_device_id fsmc_nand_id_table[] = {
1100         { .compatible = "st,spear600-fsmc-nand" },
1101         { .compatible = "stericsson,fsmc-nand" },
1102         {}
1103 };
1104 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1105 #endif
1106
1107 static struct platform_driver fsmc_nand_driver = {
1108         .remove = fsmc_nand_remove,
1109         .driver = {
1110                 .name = "fsmc-nand",
1111                 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1112                 .pm = &fsmc_nand_pm_ops,
1113         },
1114 };
1115
1116 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1117
1118 MODULE_LICENSE("GPL");
1119 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1120 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");