drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 /* fsmc controller registers for NOR flash */
  42 #define CTRL                    0x0
  43         /* ctrl register definitions */
  44         #define BANK_ENABLE             (1 << 0)
  45         #define MUXED                   (1 << 1)
  46         #define NOR_DEV                 (2 << 2)
  47         #define WIDTH_8                 (0 << 4)
  48         #define WIDTH_16                (1 << 4)
  49         #define RSTPWRDWN               (1 << 6)
  50         #define WPROT                   (1 << 7)
  51         #define WRT_ENABLE              (1 << 12)
  52         #define WAIT_ENB                (1 << 13)
  53
  54 #define CTRL_TIM                0x4
  55         /* ctrl_tim register definitions */
  56
  57 #define FSMC_NOR_BANK_SZ        0x8
  58 #define FSMC_NOR_REG_SIZE       0x40
  59
  60 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  61                                                 FSMC_NOR_BANK_SZ * (bank) + \
  62                                                 reg)
  63
  64 /* fsmc controller registers for NAND flash */
  65 #define PC                      0x00
  66         /* pc register definitions */
  67         #define FSMC_RESET              (1 << 0)
  68         #define FSMC_WAITON             (1 << 1)
  69         #define FSMC_ENABLE             (1 << 2)
  70         #define FSMC_DEVTYPE_NAND       (1 << 3)
  71         #define FSMC_DEVWID_8           (0 << 4)
  72         #define FSMC_DEVWID_16          (1 << 4)
  73         #define FSMC_ECCEN              (1 << 6)
  74         #define FSMC_ECCPLEN_512        (0 << 7)
  75         #define FSMC_ECCPLEN_256        (1 << 7)
  76         #define FSMC_TCLR_1             (1)
  77         #define FSMC_TCLR_SHIFT         (9)
  78         #define FSMC_TCLR_MASK          (0xF)
  79         #define FSMC_TAR_1              (1)
  80         #define FSMC_TAR_SHIFT          (13)
  81         #define FSMC_TAR_MASK           (0xF)
  82 #define STS                     0x04
  83         /* sts register definitions */
  84         #define FSMC_CODE_RDY           (1 << 15)
  85 #define COMM                    0x08
  86         /* comm register definitions */
  87         #define FSMC_TSET_0             0
  88         #define FSMC_TSET_SHIFT         0
  89         #define FSMC_TSET_MASK          0xFF
  90         #define FSMC_TWAIT_6            6
  91         #define FSMC_TWAIT_SHIFT        8
  92         #define FSMC_TWAIT_MASK         0xFF
  93         #define FSMC_THOLD_4            4
  94         #define FSMC_THOLD_SHIFT        16
  95         #define FSMC_THOLD_MASK         0xFF
  96         #define FSMC_THIZ_1             1
  97         #define FSMC_THIZ_SHIFT         24
  98         #define FSMC_THIZ_MASK          0xFF
  99 #define ATTRIB                  0x0C
 100 #define IOATA                   0x10
 101 #define ECC1                    0x14
 102 #define ECC2                    0x18
 103 #define ECC3                    0x1C
 104 #define FSMC_NAND_BANK_SZ       0x20
 105
 106 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 107                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 108                                                 reg)
 109
 110 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 111
 112 struct fsmc_nand_timings {
 113         uint8_t tclr;
 114         uint8_t tar;
 115         uint8_t thiz;
 116         uint8_t thold;
 117         uint8_t twait;
 118         uint8_t tset;
 119 };
 120
 121 enum access_mode {
 122         USE_DMA_ACCESS = 1,
 123         USE_WORD_ACCESS,
 124 };
 125
 126 /**
 127  * struct fsmc_nand_data - structure for FSMC NAND device state
 128  *
 129  * @pid:                Part ID on the AMBA PrimeCell format
 130  * @mtd:                MTD info for a NAND flash.
 131  * @nand:               Chip related info for a NAND flash.
 132  * @partitions:         Partition info for a NAND Flash.
 133  * @nr_partitions:      Total number of partition of a NAND flash.
 134  *
 135  * @bank:               Bank number for probed device.
 136  * @clk:                Clock structure for FSMC.
 137  *
 138  * @read_dma_chan:      DMA channel for read access
 139  * @write_dma_chan:     DMA channel for write access to NAND
 140  * @dma_access_complete: Completion structure
 141  *
 142  * @data_pa:            NAND Physical port for Data.
 143  * @data_va:            NAND port for Data.
 144  * @cmd_va:             NAND port for Command.
 145  * @addr_va:            NAND port for Address.
 146  * @regs_va:            FSMC regs base address.
 147  */
 148 struct fsmc_nand_data {
 149         u32                     pid;
 150         struct nand_chip        nand;
 151
 152         unsigned int            bank;
 153         struct device           *dev;
 154         enum access_mode        mode;
 155         struct clk              *clk;
 156
 157         /* DMA related objects */
 158         struct dma_chan         *read_dma_chan;
 159         struct dma_chan         *write_dma_chan;
 160         struct completion       dma_access_complete;
 161
 162         struct fsmc_nand_timings *dev_timings;
 163
 164         dma_addr_t              data_pa;
 165         void __iomem            *data_va;
 166         void __iomem            *cmd_va;
 167         void __iomem            *addr_va;
 168         void __iomem            *regs_va;
 169 };
 170
 171 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 172                                    struct mtd_oob_region *oobregion)
 173 {
 174         struct nand_chip *chip = mtd_to_nand(mtd);
 175
 176         if (section >= chip->ecc.steps)
 177                 return -ERANGE;
 178
 179         oobregion->offset = (section * 16) + 2;
 180         oobregion->length = 3;
 181
 182         return 0;
 183 }
 184
 185 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 186                                     struct mtd_oob_region *oobregion)
 187 {
 188         struct nand_chip *chip = mtd_to_nand(mtd);
 189
 190         if (section >= chip->ecc.steps)
 191                 return -ERANGE;
 192
 193         oobregion->offset = (section * 16) + 8;
 194
 195         if (section < chip->ecc.steps - 1)
 196                 oobregion->length = 8;
 197         else
 198                 oobregion->length = mtd->oobsize - oobregion->offset;
 199
 200         return 0;
 201 }
 202
 203 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 204         .ecc = fsmc_ecc1_ooblayout_ecc,
 205         .free = fsmc_ecc1_ooblayout_free,
 206 };
 207
 208 /*
 209  * ECC placement definitions in oobfree type format.
 210  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 211  * consecutively and immediately after the 512 byte data block for hardware to
 212  * generate the error bit offsets in 512 byte data.
 213  */
 214 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 215                                    struct mtd_oob_region *oobregion)
 216 {
 217         struct nand_chip *chip = mtd_to_nand(mtd);
 218
 219         if (section >= chip->ecc.steps)
 220                 return -ERANGE;
 221
 222         oobregion->length = chip->ecc.bytes;
 223
 224         if (!section && mtd->writesize <= 512)
 225                 oobregion->offset = 0;
 226         else
 227                 oobregion->offset = (section * 16) + 2;
 228
 229         return 0;
 230 }
 231
 232 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 233                                     struct mtd_oob_region *oobregion)
 234 {
 235         struct nand_chip *chip = mtd_to_nand(mtd);
 236
 237         if (section >= chip->ecc.steps)
 238                 return -ERANGE;
 239
 240         oobregion->offset = (section * 16) + 15;
 241
 242         if (section < chip->ecc.steps - 1)
 243                 oobregion->length = 3;
 244         else
 245                 oobregion->length = mtd->oobsize - oobregion->offset;
 246
 247         return 0;
 248 }
 249
 250 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 251         .ecc = fsmc_ecc4_ooblayout_ecc,
 252         .free = fsmc_ecc4_ooblayout_free,
 253 };
 254
 255 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 256 {
 257         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 258 }
 259
 260 /*
 261  * fsmc_cmd_ctrl - For facilitaing Hardware access
 262  * This routine allows hardware specific access to control-lines(ALE,CLE)
 263  */
 264 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 265 {
 266         struct nand_chip *this = mtd_to_nand(mtd);
 267         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 268         void __iomem *regs = host->regs_va;
 269         unsigned int bank = host->bank;
 270
 271         if (ctrl & NAND_CTRL_CHANGE) {
 272                 u32 pc;
 273
 274                 if (ctrl & NAND_CLE) {
 275                         this->IO_ADDR_R = host->cmd_va;
 276                         this->IO_ADDR_W = host->cmd_va;
 277                 } else if (ctrl & NAND_ALE) {
 278                         this->IO_ADDR_R = host->addr_va;
 279                         this->IO_ADDR_W = host->addr_va;
 280                 } else {
 281                         this->IO_ADDR_R = host->data_va;
 282                         this->IO_ADDR_W = host->data_va;
 283                 }
 284
 285                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 286                 if (ctrl & NAND_NCE)
 287                         pc |= FSMC_ENABLE;
 288                 else
 289                         pc &= ~FSMC_ENABLE;
 290                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 291         }
 292
 293         mb();
 294
 295         if (cmd != NAND_CMD_NONE)
 296                 writeb_relaxed(cmd, this->IO_ADDR_W);
 297 }
 298
 299 /*
 300  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 301  *
 302  * This routine initializes timing parameters related to NAND memory access in
 303  * FSMC registers
 304  */
 305 static void fsmc_nand_setup(struct fsmc_nand_data *host,
 306                             struct fsmc_nand_timings *timings)
 307 {
 308         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 309         uint32_t tclr, tar, thiz, thold, twait, tset;
 310         unsigned int bank = host->bank;
 311         void __iomem *regs = host->regs_va;
 312         struct fsmc_nand_timings *tims;
 313         struct fsmc_nand_timings default_timings = {
 314                 .tclr   = FSMC_TCLR_1,
 315                 .tar    = FSMC_TAR_1,
 316                 .thiz   = FSMC_THIZ_1,
 317                 .thold  = FSMC_THOLD_4,
 318                 .twait  = FSMC_TWAIT_6,
 319                 .tset   = FSMC_TSET_0,
 320         };
 321
 322         if (timings)
 323                 tims = host->dev_timings;
 324         else
 325                 tims = &default_timings;
 326
 327         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 328         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 329         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 330         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 331         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 332         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 333
 334         if (host->nand.options & NAND_BUSWIDTH_16)
 335                 writel_relaxed(value | FSMC_DEVWID_16,
 336                                 FSMC_NAND_REG(regs, bank, PC));
 337         else
 338                 writel_relaxed(value | FSMC_DEVWID_8,
 339                                 FSMC_NAND_REG(regs, bank, PC));
 340
 341         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 342                         FSMC_NAND_REG(regs, bank, PC));
 343         writel_relaxed(thiz | thold | twait | tset,
 344                         FSMC_NAND_REG(regs, bank, COMM));
 345         writel_relaxed(thiz | thold | twait | tset,
 346                         FSMC_NAND_REG(regs, bank, ATTRIB));
 347 }
 348
 349 static int fsmc_calc_timings(struct fsmc_nand_data *host,
 350                              const struct nand_sdr_timings *sdrt,
 351                              struct fsmc_nand_timings *tims)
 352 {
 353         unsigned long hclk = clk_get_rate(host->clk);
 354         unsigned long hclkn = NSEC_PER_SEC / hclk;
 355         uint32_t thiz, thold, twait, tset;
 356
 357         if (sdrt->tRC_min < 30000)
 358                 return -EOPNOTSUPP;
 359
 360         tims->tar = DIV_ROUND_UP(sdrt->tAR_min / 1000, hclkn) - 1;
 361         if (tims->tar > FSMC_TAR_MASK)
 362                 tims->tar = FSMC_TAR_MASK;
 363         tims->tclr = DIV_ROUND_UP(sdrt->tCLR_min / 1000, hclkn) - 1;
 364         if (tims->tclr > FSMC_TCLR_MASK)
 365                 tims->tclr = FSMC_TCLR_MASK;
 366
 367         thiz = sdrt->tCS_min - sdrt->tWP_min;
 368         tims->thiz = DIV_ROUND_UP(thiz / 1000, hclkn);
 369
 370         thold = sdrt->tDH_min;
 371         if (thold < sdrt->tCH_min)
 372                 thold = sdrt->tCH_min;
 373         if (thold < sdrt->tCLH_min)
 374                 thold = sdrt->tCLH_min;
 375         if (thold < sdrt->tWH_min)
 376                 thold = sdrt->tWH_min;
 377         if (thold < sdrt->tALH_min)
 378                 thold = sdrt->tALH_min;
 379         if (thold < sdrt->tREH_min)
 380                 thold = sdrt->tREH_min;
 381         tims->thold = DIV_ROUND_UP(thold / 1000, hclkn);
 382         if (tims->thold == 0)
 383                 tims->thold = 1;
 384         else if (tims->thold > FSMC_THOLD_MASK)
 385                 tims->thold = FSMC_THOLD_MASK;
 386
 387         twait = max(sdrt->tRP_min, sdrt->tWP_min);
 388         tims->twait = DIV_ROUND_UP(twait / 1000, hclkn) - 1;
 389         if (tims->twait == 0)
 390                 tims->twait = 1;
 391         else if (tims->twait > FSMC_TWAIT_MASK)
 392                 tims->twait = FSMC_TWAIT_MASK;
 393
 394         tset = max(sdrt->tCS_min - sdrt->tWP_min,
 395                    sdrt->tCEA_max - sdrt->tREA_max);
 396         tims->tset = DIV_ROUND_UP(tset / 1000, hclkn) - 1;
 397         if (tims->tset == 0)
 398                 tims->tset = 1;
 399         else if (tims->tset > FSMC_TSET_MASK)
 400                 tims->tset = FSMC_TSET_MASK;
 401
 402         return 0;
 403 }
 404
 405 static int fsmc_setup_data_interface(struct mtd_info *mtd,
 406                                      const struct nand_data_interface *conf,
 407                                      bool check_only)
 408 {
 409         struct nand_chip *nand = mtd_to_nand(mtd);
 410         struct fsmc_nand_data *host = nand_get_controller_data(nand);
 411         struct fsmc_nand_timings tims;
 412         const struct nand_sdr_timings *sdrt;
 413         int ret;
 414
 415         sdrt = nand_get_sdr_timings(conf);
 416         if (IS_ERR(sdrt))
 417                 return PTR_ERR(sdrt);
 418
 419         ret = fsmc_calc_timings(host, sdrt, &tims);
 420         if (ret)
 421                 return ret;
 422
 423         if (check_only)
 424                 return 0;
 425
 426         fsmc_nand_setup(host, &tims);
 427
 428         return 0;
 429 }
 430
 431 /*
 432  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 433  */
 434 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 435 {
 436         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 437         void __iomem *regs = host->regs_va;
 438         uint32_t bank = host->bank;
 439
 440         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 441                         FSMC_NAND_REG(regs, bank, PC));
 442         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 443                         FSMC_NAND_REG(regs, bank, PC));
 444         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 445                         FSMC_NAND_REG(regs, bank, PC));
 446 }
 447
 448 /*
 449  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 450  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 451  * max of 8-bits)
 452  */
 453 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 454                                 uint8_t *ecc)
 455 {
 456         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 457         void __iomem *regs = host->regs_va;
 458         uint32_t bank = host->bank;
 459         uint32_t ecc_tmp;
 460         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 461
 462         do {
 463                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 464                         break;
 465                 else
 466                         cond_resched();
 467         } while (!time_after_eq(jiffies, deadline));
 468
 469         if (time_after_eq(jiffies, deadline)) {
 470                 dev_err(host->dev, "calculate ecc timed out\n");
 471                 return -ETIMEDOUT;
 472         }
 473
 474         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 475         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 476         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 477         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 478         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 479
 480         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 481         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 482         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 483         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 484         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 485
 486         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 487         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 488         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 489         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 490         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 491
 492         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 493         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 494
 495         return 0;
 496 }
 497
 498 /*
 499  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 500  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 501  * max of 1-bit)
 502  */
 503 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 504                                 uint8_t *ecc)
 505 {
 506         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 507         void __iomem *regs = host->regs_va;
 508         uint32_t bank = host->bank;
 509         uint32_t ecc_tmp;
 510
 511         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 512         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 513         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 514         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 515
 516         return 0;
 517 }
 518
 519 /* Count the number of 0's in buff upto a max of max_bits */
 520 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 521 {
 522         int k, written_bits = 0;
 523
 524         for (k = 0; k < size; k++) {
 525                 written_bits += hweight8(~buff[k]);
 526                 if (written_bits > max_bits)
 527                         break;
 528         }
 529
 530         return written_bits;
 531 }
 532
 533 static void dma_complete(void *param)
 534 {
 535         struct fsmc_nand_data *host = param;
 536
 537         complete(&host->dma_access_complete);
 538 }
 539
 540 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 541                 enum dma_data_direction direction)
 542 {
 543         struct dma_chan *chan;
 544         struct dma_device *dma_dev;
 545         struct dma_async_tx_descriptor *tx;
 546         dma_addr_t dma_dst, dma_src, dma_addr;
 547         dma_cookie_t cookie;
 548         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 549         int ret;
 550         unsigned long time_left;
 551
 552         if (direction == DMA_TO_DEVICE)
 553                 chan = host->write_dma_chan;
 554         else if (direction == DMA_FROM_DEVICE)
 555                 chan = host->read_dma_chan;
 556         else
 557                 return -EINVAL;
 558
 559         dma_dev = chan->device;
 560         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 561
 562         if (direction == DMA_TO_DEVICE) {
 563                 dma_src = dma_addr;
 564                 dma_dst = host->data_pa;
 565         } else {
 566                 dma_src = host->data_pa;
 567                 dma_dst = dma_addr;
 568         }
 569
 570         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 571                         len, flags);
 572         if (!tx) {
 573                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 574                 ret = -EIO;
 575                 goto unmap_dma;
 576         }
 577
 578         tx->callback = dma_complete;
 579         tx->callback_param = host;
 580         cookie = tx->tx_submit(tx);
 581
 582         ret = dma_submit_error(cookie);
 583         if (ret) {
 584                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 585                 goto unmap_dma;
 586         }
 587
 588         dma_async_issue_pending(chan);
 589
 590         time_left =
 591         wait_for_completion_timeout(&host->dma_access_complete,
 592                                 msecs_to_jiffies(3000));
 593         if (time_left == 0) {
 594                 dmaengine_terminate_all(chan);
 595                 dev_err(host->dev, "wait_for_completion_timeout\n");
 596                 ret = -ETIMEDOUT;
 597                 goto unmap_dma;
 598         }
 599
 600         ret = 0;
 601
 602 unmap_dma:
 603         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 604
 605         return ret;
 606 }
 607
 608 /*
 609  * fsmc_write_buf - write buffer to chip
 610  * @mtd:        MTD device structure
 611  * @buf:        data buffer
 612  * @len:        number of bytes to write
 613  */
 614 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 615 {
 616         int i;
 617         struct nand_chip *chip = mtd_to_nand(mtd);
 618
 619         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 620                         IS_ALIGNED(len, sizeof(uint32_t))) {
 621                 uint32_t *p = (uint32_t *)buf;
 622                 len = len >> 2;
 623                 for (i = 0; i < len; i++)
 624                         writel_relaxed(p[i], chip->IO_ADDR_W);
 625         } else {
 626                 for (i = 0; i < len; i++)
 627                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 628         }
 629 }
 630
 631 /*
 632  * fsmc_read_buf - read chip data into buffer
 633  * @mtd:        MTD device structure
 634  * @buf:        buffer to store date
 635  * @len:        number of bytes to read
 636  */
 637 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 638 {
 639         int i;
 640         struct nand_chip *chip = mtd_to_nand(mtd);
 641
 642         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 643                         IS_ALIGNED(len, sizeof(uint32_t))) {
 644                 uint32_t *p = (uint32_t *)buf;
 645                 len = len >> 2;
 646                 for (i = 0; i < len; i++)
 647                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 648         } else {
 649                 for (i = 0; i < len; i++)
 650                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 651         }
 652 }
 653
 654 /*
 655  * fsmc_read_buf_dma - read chip data into buffer
 656  * @mtd:        MTD device structure
 657  * @buf:        buffer to store date
 658  * @len:        number of bytes to read
 659  */
 660 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 661 {
 662         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 663
 664         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 665 }
 666
 667 /*
 668  * fsmc_write_buf_dma - write buffer to chip
 669  * @mtd:        MTD device structure
 670  * @buf:        data buffer
 671  * @len:        number of bytes to write
 672  */
 673 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 674                 int len)
 675 {
 676         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 677
 678         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 679 }
 680
 681 /*
 682  * fsmc_read_page_hwecc
 683  * @mtd:        mtd info structure
 684  * @chip:       nand chip info structure
 685  * @buf:        buffer to store read data
 686  * @oob_required:       caller expects OOB data read to chip->oob_poi
 687  * @page:       page number to read
 688  *
 689  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 690  * performed in a strict sequence as follows:
 691  * data(512 byte) -> ecc(13 byte)
 692  * After this read, fsmc hardware generates and reports error data bits(up to a
 693  * max of 8 bits)
 694  */
 695 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 696                                  uint8_t *buf, int oob_required, int page)
 697 {
 698         int i, j, s, stat, eccsize = chip->ecc.size;
 699         int eccbytes = chip->ecc.bytes;
 700         int eccsteps = chip->ecc.steps;
 701         uint8_t *p = buf;
 702         uint8_t *ecc_calc = chip->buffers->ecccalc;
 703         uint8_t *ecc_code = chip->buffers->ecccode;
 704         int off, len, group = 0;
 705         /*
 706          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 707          * end up reading 14 bytes (7 words) from oob. The local array is
 708          * to maintain word alignment
 709          */
 710         uint16_t ecc_oob[7];
 711         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 712         unsigned int max_bitflips = 0;
 713
 714         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 715                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 716                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 717                 chip->read_buf(mtd, p, eccsize);
 718
 719                 for (j = 0; j < eccbytes;) {
 720                         struct mtd_oob_region oobregion;
 721                         int ret;
 722
 723                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 724                         if (ret)
 725                                 return ret;
 726
 727                         off = oobregion.offset;
 728                         len = oobregion.length;
 729
 730                         /*
 731                          * length is intentionally kept a higher multiple of 2
 732                          * to read at least 13 bytes even in case of 16 bit NAND
 733                          * devices
 734                          */
 735                         if (chip->options & NAND_BUSWIDTH_16)
 736                                 len = roundup(len, 2);
 737
 738                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 739                         chip->read_buf(mtd, oob + j, len);
 740                         j += len;
 741                 }
 742
 743                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 744                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 745
 746                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 747                 if (stat < 0) {
 748                         mtd->ecc_stats.failed++;
 749                 } else {
 750                         mtd->ecc_stats.corrected += stat;
 751                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 752                 }
 753         }
 754
 755         return max_bitflips;
 756 }
 757
 758 /*
 759  * fsmc_bch8_correct_data
 760  * @mtd:        mtd info structure
 761  * @dat:        buffer of read data
 762  * @read_ecc:   ecc read from device spare area
 763  * @calc_ecc:   ecc calculated from read data
 764  *
 765  * calc_ecc is a 104 bit information containing maximum of 8 error
 766  * offset informations of 13 bits each in 512 bytes of read data.
 767  */
 768 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 769                              uint8_t *read_ecc, uint8_t *calc_ecc)
 770 {
 771         struct nand_chip *chip = mtd_to_nand(mtd);
 772         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 773         void __iomem *regs = host->regs_va;
 774         unsigned int bank = host->bank;
 775         uint32_t err_idx[8];
 776         uint32_t num_err, i;
 777         uint32_t ecc1, ecc2, ecc3, ecc4;
 778
 779         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 780
 781         /* no bit flipping */
 782         if (likely(num_err == 0))
 783                 return 0;
 784
 785         /* too many errors */
 786         if (unlikely(num_err > 8)) {
 787                 /*
 788                  * This is a temporary erase check. A newly erased page read
 789                  * would result in an ecc error because the oob data is also
 790                  * erased to FF and the calculated ecc for an FF data is not
 791                  * FF..FF.
 792                  * This is a workaround to skip performing correction in case
 793                  * data is FF..FF
 794                  *
 795                  * Logic:
 796                  * For every page, each bit written as 0 is counted until these
 797                  * number of bits are greater than 8 (the maximum correction
 798                  * capability of FSMC for each 512 + 13 bytes)
 799                  */
 800
 801                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 802                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 803
 804                 if ((bits_ecc + bits_data) <= 8) {
 805                         if (bits_data)
 806                                 memset(dat, 0xff, chip->ecc.size);
 807                         return bits_data;
 808                 }
 809
 810                 return -EBADMSG;
 811         }
 812
 813         /*
 814          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 815          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 816          *
 817          * calc_ecc is a 104 bit information containing maximum of 8 error
 818          * offset informations of 13 bits each. calc_ecc is copied into a
 819          * uint64_t array and error offset indexes are populated in err_idx
 820          * array
 821          */
 822         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 823         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 824         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 825         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 826
 827         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 828         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 829         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 830         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 831         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 832         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 833         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 834         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 835
 836         i = 0;
 837         while (num_err--) {
 838                 change_bit(0, (unsigned long *)&err_idx[i]);
 839                 change_bit(1, (unsigned long *)&err_idx[i]);
 840
 841                 if (err_idx[i] < chip->ecc.size * 8) {
 842                         change_bit(err_idx[i], (unsigned long *)dat);
 843                         i++;
 844                 }
 845         }
 846         return i;
 847 }
 848
 849 static bool filter(struct dma_chan *chan, void *slave)
 850 {
 851         chan->private = slave;
 852         return true;
 853 }
 854
 855 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 856                                      struct fsmc_nand_data *host,
 857                                      struct nand_chip *nand)
 858 {
 859         struct device_node *np = pdev->dev.of_node;
 860         u32 val;
 861         int ret;
 862
 863         nand->options = 0;
 864
 865         if (!of_property_read_u32(np, "bank-width", &val)) {
 866                 if (val == 2) {
 867                         nand->options |= NAND_BUSWIDTH_16;
 868                 } else if (val != 1) {
 869                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 870                         return -EINVAL;
 871                 }
 872         }
 873
 874         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 875                 nand->options |= NAND_SKIP_BBTSCAN;
 876
 877         host->dev_timings = devm_kzalloc(&pdev->dev,
 878                                 sizeof(*host->dev_timings), GFP_KERNEL);
 879         if (!host->dev_timings)
 880                 return -ENOMEM;
 881         ret = of_property_read_u8_array(np, "timings", (u8 *)host->dev_timings,
 882                                                 sizeof(*host->dev_timings));
 883         if (ret)
 884                 host->dev_timings = NULL;
 885
 886         /* Set default NAND bank to 0 */
 887         host->bank = 0;
 888         if (!of_property_read_u32(np, "bank", &val)) {
 889                 if (val > 3) {
 890                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 891                         return -EINVAL;
 892                 }
 893                 host->bank = val;
 894         }
 895         return 0;
 896 }
 897
 898 /*
 899  * fsmc_nand_probe - Probe function
 900  * @pdev:       platform device structure
 901  */
 902 static int __init fsmc_nand_probe(struct platform_device *pdev)
 903 {
 904         struct fsmc_nand_data *host;
 905         struct mtd_info *mtd;
 906         struct nand_chip *nand;
 907         struct resource *res;
 908         dma_cap_mask_t mask;
 909         int ret = 0;
 910         u32 pid;
 911         int i;
 912
 913         /* Allocate memory for the device structure (and zero it) */
 914         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 915         if (!host)
 916                 return -ENOMEM;
 917
 918         nand = &host->nand;
 919
 920         ret = fsmc_nand_probe_config_dt(pdev, host, nand);
 921         if (ret)
 922                 return ret;
 923
 924         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 925         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 926         if (IS_ERR(host->data_va))
 927                 return PTR_ERR(host->data_va);
 928
 929         host->data_pa = (dma_addr_t)res->start;
 930
 931         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 932         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 933         if (IS_ERR(host->addr_va))
 934                 return PTR_ERR(host->addr_va);
 935
 936         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 937         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 938         if (IS_ERR(host->cmd_va))
 939                 return PTR_ERR(host->cmd_va);
 940
 941         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 942         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 943         if (IS_ERR(host->regs_va))
 944                 return PTR_ERR(host->regs_va);
 945
 946         host->clk = devm_clk_get(&pdev->dev, NULL);
 947         if (IS_ERR(host->clk)) {
 948                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 949                 return PTR_ERR(host->clk);
 950         }
 951
 952         ret = clk_prepare_enable(host->clk);
 953         if (ret)
 954                 return ret;
 955
 956         /*
 957          * This device ID is actually a common AMBA ID as used on the
 958          * AMBA PrimeCell bus. However it is not a PrimeCell.
 959          */
 960         for (pid = 0, i = 0; i < 4; i++)
 961                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 962         host->pid = pid;
 963         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 964                  "revision %02x, config %02x\n",
 965                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 966                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 967
 968         host->dev = &pdev->dev;
 969
 970         if (host->mode == USE_DMA_ACCESS)
 971                 init_completion(&host->dma_access_complete);
 972
 973         /* Link all private pointers */
 974         mtd = nand_to_mtd(&host->nand);
 975         nand_set_controller_data(nand, host);
 976         nand_set_flash_node(nand, pdev->dev.of_node);
 977
 978         mtd->dev.parent = &pdev->dev;
 979         nand->IO_ADDR_R = host->data_va;
 980         nand->IO_ADDR_W = host->data_va;
 981         nand->cmd_ctrl = fsmc_cmd_ctrl;
 982         nand->chip_delay = 30;
 983
 984         /*
 985          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 986          * can overwrite this value if the DT provides a different value.
 987          */
 988         nand->ecc.mode = NAND_ECC_HW;
 989         nand->ecc.hwctl = fsmc_enable_hwecc;
 990         nand->ecc.size = 512;
 991         nand->badblockbits = 7;
 992
 993         switch (host->mode) {
 994         case USE_DMA_ACCESS:
 995                 dma_cap_zero(mask);
 996                 dma_cap_set(DMA_MEMCPY, mask);
 997                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
 998                 if (!host->read_dma_chan) {
 999                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1000                         goto err_req_read_chnl;
1001                 }
1002                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
1003                 if (!host->write_dma_chan) {
1004                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1005                         goto err_req_write_chnl;
1006                 }
1007                 nand->read_buf = fsmc_read_buf_dma;
1008                 nand->write_buf = fsmc_write_buf_dma;
1009                 break;
1010
1011         default:
1012         case USE_WORD_ACCESS:
1013                 nand->read_buf = fsmc_read_buf;
1014                 nand->write_buf = fsmc_write_buf;
1015                 break;
1016         }
1017
1018         if (host->dev_timings)
1019                 fsmc_nand_setup(host, host->dev_timings);
1020         else
1021                 nand->setup_data_interface = fsmc_setup_data_interface;
1022
1023         if (AMBA_REV_BITS(host->pid) >= 8) {
1024                 nand->ecc.read_page = fsmc_read_page_hwecc;
1025                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1026                 nand->ecc.correct = fsmc_bch8_correct_data;
1027                 nand->ecc.bytes = 13;
1028                 nand->ecc.strength = 8;
1029         }
1030
1031         /*
1032          * Scan to find existence of the device
1033          */
1034         ret = nand_scan_ident(mtd, 1, NULL);
1035         if (ret) {
1036                 dev_err(&pdev->dev, "No NAND Device found!\n");
1037                 goto err_scan_ident;
1038         }
1039
1040         if (AMBA_REV_BITS(host->pid) >= 8) {
1041                 switch (mtd->oobsize) {
1042                 case 16:
1043                 case 64:
1044                 case 128:
1045                 case 224:
1046                 case 256:
1047                         break;
1048                 default:
1049                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1050                                  mtd->oobsize);
1051                         ret = -EINVAL;
1052                         goto err_probe;
1053                 }
1054
1055                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1056         } else {
1057                 switch (nand->ecc.mode) {
1058                 case NAND_ECC_HW:
1059                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1060                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1061                         nand->ecc.correct = nand_correct_data;
1062                         nand->ecc.bytes = 3;
1063                         nand->ecc.strength = 1;
1064                         break;
1065
1066                 case NAND_ECC_SOFT:
1067                         if (nand->ecc.algo == NAND_ECC_BCH) {
1068                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1069                                 break;
1070                         }
1071
1072                 default:
1073                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1074                         goto err_probe;
1075                 }
1076
1077                 /*
1078                  * Don't set layout for BCH4 SW ECC. This will be
1079                  * generated later in nand_bch_init() later.
1080                  */
1081                 if (nand->ecc.mode == NAND_ECC_HW) {
1082                         switch (mtd->oobsize) {
1083                         case 16:
1084                         case 64:
1085                         case 128:
1086                                 mtd_set_ooblayout(mtd,
1087                                                   &fsmc_ecc1_ooblayout_ops);
1088                                 break;
1089                         default:
1090                                 dev_warn(&pdev->dev,
1091                                          "No oob scheme defined for oobsize %d\n",
1092                                          mtd->oobsize);
1093                                 ret = -EINVAL;
1094                                 goto err_probe;
1095                         }
1096                 }
1097         }
1098
1099         /* Second stage of scan to fill MTD data-structures */
1100         ret = nand_scan_tail(mtd);
1101         if (ret)
1102                 goto err_probe;
1103
1104         mtd->name = "nand";
1105         ret = mtd_device_register(mtd, NULL, 0);
1106         if (ret)
1107                 goto err_probe;
1108
1109         platform_set_drvdata(pdev, host);
1110         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1111         return 0;
1112
1113 err_probe:
1114 err_scan_ident:
1115         if (host->mode == USE_DMA_ACCESS)
1116                 dma_release_channel(host->write_dma_chan);
1117 err_req_write_chnl:
1118         if (host->mode == USE_DMA_ACCESS)
1119                 dma_release_channel(host->read_dma_chan);
1120 err_req_read_chnl:
1121         clk_disable_unprepare(host->clk);
1122         return ret;
1123 }
1124
1125 /*
1126  * Clean up routine
1127  */
1128 static int fsmc_nand_remove(struct platform_device *pdev)
1129 {
1130         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1131
1132         if (host) {
1133                 nand_release(nand_to_mtd(&host->nand));
1134
1135                 if (host->mode == USE_DMA_ACCESS) {
1136                         dma_release_channel(host->write_dma_chan);
1137                         dma_release_channel(host->read_dma_chan);
1138                 }
1139                 clk_disable_unprepare(host->clk);
1140         }
1141
1142         return 0;
1143 }
1144
1145 #ifdef CONFIG_PM_SLEEP
1146 static int fsmc_nand_suspend(struct device *dev)
1147 {
1148         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1149         if (host)
1150                 clk_disable_unprepare(host->clk);
1151         return 0;
1152 }
1153
1154 static int fsmc_nand_resume(struct device *dev)
1155 {
1156         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1157         if (host) {
1158                 clk_prepare_enable(host->clk);
1159                 if (host->dev_timings)
1160                         fsmc_nand_setup(host, host->dev_timings);
1161         }
1162         return 0;
1163 }
1164 #endif
1165
1166 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1167
1168 static const struct of_device_id fsmc_nand_id_table[] = {
1169         { .compatible = "st,spear600-fsmc-nand" },
1170         { .compatible = "stericsson,fsmc-nand" },
1171         {}
1172 };
1173 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1174
1175 static struct platform_driver fsmc_nand_driver = {
1176         .remove = fsmc_nand_remove,
1177         .driver = {
1178                 .name = "fsmc-nand",
1179                 .of_match_table = fsmc_nand_id_table,
1180                 .pm = &fsmc_nand_pm_ops,
1181         },
1182 };
1183
1184 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1185
1186 MODULE_LICENSE("GPL");
1187 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1188 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");