drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 #define FSMC_NAND_BW8           1
  42 #define FSMC_NAND_BW16          2
  43
  44 #define FSMC_MAX_NOR_BANKS      4
  45 #define FSMC_MAX_NAND_BANKS     4
  46
  47 #define FSMC_FLASH_WIDTH8       1
  48 #define FSMC_FLASH_WIDTH16      2
  49
  50 /* fsmc controller registers for NOR flash */
  51 #define CTRL                    0x0
  52         /* ctrl register definitions */
  53         #define BANK_ENABLE             (1 << 0)
  54         #define MUXED                   (1 << 1)
  55         #define NOR_DEV                 (2 << 2)
  56         #define WIDTH_8                 (0 << 4)
  57         #define WIDTH_16                (1 << 4)
  58         #define RSTPWRDWN               (1 << 6)
  59         #define WPROT                   (1 << 7)
  60         #define WRT_ENABLE              (1 << 12)
  61         #define WAIT_ENB                (1 << 13)
  62
  63 #define CTRL_TIM                0x4
  64         /* ctrl_tim register definitions */
  65
  66 #define FSMC_NOR_BANK_SZ        0x8
  67 #define FSMC_NOR_REG_SIZE       0x40
  68
  69 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  70                                                 FSMC_NOR_BANK_SZ * (bank) + \
  71                                                 reg)
  72
  73 /* fsmc controller registers for NAND flash */
  74 #define PC                      0x00
  75         /* pc register definitions */
  76         #define FSMC_RESET              (1 << 0)
  77         #define FSMC_WAITON             (1 << 1)
  78         #define FSMC_ENABLE             (1 << 2)
  79         #define FSMC_DEVTYPE_NAND       (1 << 3)
  80         #define FSMC_DEVWID_8           (0 << 4)
  81         #define FSMC_DEVWID_16          (1 << 4)
  82         #define FSMC_ECCEN              (1 << 6)
  83         #define FSMC_ECCPLEN_512        (0 << 7)
  84         #define FSMC_ECCPLEN_256        (1 << 7)
  85         #define FSMC_TCLR_1             (1)
  86         #define FSMC_TCLR_SHIFT         (9)
  87         #define FSMC_TCLR_MASK          (0xF)
  88         #define FSMC_TAR_1              (1)
  89         #define FSMC_TAR_SHIFT          (13)
  90         #define FSMC_TAR_MASK           (0xF)
  91 #define STS                     0x04
  92         /* sts register definitions */
  93         #define FSMC_CODE_RDY           (1 << 15)
  94 #define COMM                    0x08
  95         /* comm register definitions */
  96         #define FSMC_TSET_0             0
  97         #define FSMC_TSET_SHIFT         0
  98         #define FSMC_TSET_MASK          0xFF
  99         #define FSMC_TWAIT_6            6
 100         #define FSMC_TWAIT_SHIFT        8
 101         #define FSMC_TWAIT_MASK         0xFF
 102         #define FSMC_THOLD_4            4
 103         #define FSMC_THOLD_SHIFT        16
 104         #define FSMC_THOLD_MASK         0xFF
 105         #define FSMC_THIZ_1             1
 106         #define FSMC_THIZ_SHIFT         24
 107         #define FSMC_THIZ_MASK          0xFF
 108 #define ATTRIB                  0x0C
 109 #define IOATA                   0x10
 110 #define ECC1                    0x14
 111 #define ECC2                    0x18
 112 #define ECC3                    0x1C
 113 #define FSMC_NAND_BANK_SZ       0x20
 114
 115 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 116                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 117                                                 reg)
 118
 119 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 120
 121 struct fsmc_nand_timings {
 122         uint8_t tclr;
 123         uint8_t tar;
 124         uint8_t thiz;
 125         uint8_t thold;
 126         uint8_t twait;
 127         uint8_t tset;
 128 };
 129
 130 enum access_mode {
 131         USE_DMA_ACCESS = 1,
 132         USE_WORD_ACCESS,
 133 };
 134
 135 /**
 136  * fsmc_nand_platform_data - platform specific NAND controller config
 137  * @nand_timings: timing setup for the physical NAND interface
 138  * @partitions: partition table for the platform, use a default fallback
 139  * if this is NULL
 140  * @nr_partitions: the number of partitions in the previous entry
 141  * @options: different options for the driver
 142  * @width: bus width
 143  * @bank: default bank
 144  * @select_bank: callback to select a certain bank, this is
 145  * platform-specific. If the controller only supports one bank
 146  * this may be set to NULL
 147  */
 148 struct fsmc_nand_platform_data {
 149         struct fsmc_nand_timings *nand_timings;
 150         struct mtd_partition    *partitions;
 151         unsigned int            nr_partitions;
 152         unsigned int            options;
 153         unsigned int            bank;
 154
 155         enum access_mode        mode;
 156
 157         void                    (*select_bank)(uint32_t bank, uint32_t busw);
 158
 159         /* priv structures for dma accesses */
 160         void                    *read_dma_priv;
 161         void                    *write_dma_priv;
 162 };
 163
 164 /**
 165  * struct fsmc_nand_data - structure for FSMC NAND device state
 166  *
 167  * @pid:                Part ID on the AMBA PrimeCell format
 168  * @mtd:                MTD info for a NAND flash.
 169  * @nand:               Chip related info for a NAND flash.
 170  * @partitions:         Partition info for a NAND Flash.
 171  * @nr_partitions:      Total number of partition of a NAND flash.
 172  *
 173  * @bank:               Bank number for probed device.
 174  * @clk:                Clock structure for FSMC.
 175  *
 176  * @read_dma_chan:      DMA channel for read access
 177  * @write_dma_chan:     DMA channel for write access to NAND
 178  * @dma_access_complete: Completion structure
 179  *
 180  * @data_pa:            NAND Physical port for Data.
 181  * @data_va:            NAND port for Data.
 182  * @cmd_va:             NAND port for Command.
 183  * @addr_va:            NAND port for Address.
 184  * @regs_va:            FSMC regs base address.
 185  */
 186 struct fsmc_nand_data {
 187         u32                     pid;
 188         struct nand_chip        nand;
 189         struct mtd_partition    *partitions;
 190         unsigned int            nr_partitions;
 191
 192         unsigned int            bank;
 193         struct device           *dev;
 194         enum access_mode        mode;
 195         struct clk              *clk;
 196
 197         /* DMA related objects */
 198         struct dma_chan         *read_dma_chan;
 199         struct dma_chan         *write_dma_chan;
 200         struct completion       dma_access_complete;
 201
 202         struct fsmc_nand_timings *dev_timings;
 203
 204         dma_addr_t              data_pa;
 205         void __iomem            *data_va;
 206         void __iomem            *cmd_va;
 207         void __iomem            *addr_va;
 208         void __iomem            *regs_va;
 209
 210         void                    (*select_chip)(uint32_t bank, uint32_t busw);
 211 };
 212
 213 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 214                                    struct mtd_oob_region *oobregion)
 215 {
 216         struct nand_chip *chip = mtd_to_nand(mtd);
 217
 218         if (section >= chip->ecc.steps)
 219                 return -ERANGE;
 220
 221         oobregion->offset = (section * 16) + 2;
 222         oobregion->length = 3;
 223
 224         return 0;
 225 }
 226
 227 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 228                                     struct mtd_oob_region *oobregion)
 229 {
 230         struct nand_chip *chip = mtd_to_nand(mtd);
 231
 232         if (section >= chip->ecc.steps)
 233                 return -ERANGE;
 234
 235         oobregion->offset = (section * 16) + 8;
 236
 237         if (section < chip->ecc.steps - 1)
 238                 oobregion->length = 8;
 239         else
 240                 oobregion->length = mtd->oobsize - oobregion->offset;
 241
 242         return 0;
 243 }
 244
 245 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 246         .ecc = fsmc_ecc1_ooblayout_ecc,
 247         .free = fsmc_ecc1_ooblayout_free,
 248 };
 249
 250 /*
 251  * ECC placement definitions in oobfree type format.
 252  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 253  * consecutively and immediately after the 512 byte data block for hardware to
 254  * generate the error bit offsets in 512 byte data.
 255  */
 256 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 257                                    struct mtd_oob_region *oobregion)
 258 {
 259         struct nand_chip *chip = mtd_to_nand(mtd);
 260
 261         if (section >= chip->ecc.steps)
 262                 return -ERANGE;
 263
 264         oobregion->length = chip->ecc.bytes;
 265
 266         if (!section && mtd->writesize <= 512)
 267                 oobregion->offset = 0;
 268         else
 269                 oobregion->offset = (section * 16) + 2;
 270
 271         return 0;
 272 }
 273
 274 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 275                                     struct mtd_oob_region *oobregion)
 276 {
 277         struct nand_chip *chip = mtd_to_nand(mtd);
 278
 279         if (section >= chip->ecc.steps)
 280                 return -ERANGE;
 281
 282         oobregion->offset = (section * 16) + 15;
 283
 284         if (section < chip->ecc.steps - 1)
 285                 oobregion->length = 3;
 286         else
 287                 oobregion->length = mtd->oobsize - oobregion->offset;
 288
 289         return 0;
 290 }
 291
 292 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 293         .ecc = fsmc_ecc4_ooblayout_ecc,
 294         .free = fsmc_ecc4_ooblayout_free,
 295 };
 296
 297 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 298 {
 299         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 300 }
 301
 302 /* Assert CS signal based on chipnr */
 303 static void fsmc_select_chip(struct mtd_info *mtd, int chipnr)
 304 {
 305         struct nand_chip *chip = mtd_to_nand(mtd);
 306         struct fsmc_nand_data *host;
 307
 308         host = mtd_to_fsmc(mtd);
 309
 310         switch (chipnr) {
 311         case -1:
 312                 chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
 313                 break;
 314         case 0:
 315         case 1:
 316         case 2:
 317         case 3:
 318                 if (host->select_chip)
 319                         host->select_chip(chipnr,
 320                                         chip->options & NAND_BUSWIDTH_16);
 321                 break;
 322
 323         default:
 324                 dev_err(host->dev, "unsupported chip-select %d\n", chipnr);
 325         }
 326 }
 327
 328 /*
 329  * fsmc_cmd_ctrl - For facilitaing Hardware access
 330  * This routine allows hardware specific access to control-lines(ALE,CLE)
 331  */
 332 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 333 {
 334         struct nand_chip *this = mtd_to_nand(mtd);
 335         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 336         void __iomem *regs = host->regs_va;
 337         unsigned int bank = host->bank;
 338
 339         if (ctrl & NAND_CTRL_CHANGE) {
 340                 u32 pc;
 341
 342                 if (ctrl & NAND_CLE) {
 343                         this->IO_ADDR_R = host->cmd_va;
 344                         this->IO_ADDR_W = host->cmd_va;
 345                 } else if (ctrl & NAND_ALE) {
 346                         this->IO_ADDR_R = host->addr_va;
 347                         this->IO_ADDR_W = host->addr_va;
 348                 } else {
 349                         this->IO_ADDR_R = host->data_va;
 350                         this->IO_ADDR_W = host->data_va;
 351                 }
 352
 353                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 354                 if (ctrl & NAND_NCE)
 355                         pc |= FSMC_ENABLE;
 356                 else
 357                         pc &= ~FSMC_ENABLE;
 358                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 359         }
 360
 361         mb();
 362
 363         if (cmd != NAND_CMD_NONE)
 364                 writeb_relaxed(cmd, this->IO_ADDR_W);
 365 }
 366
 367 /*
 368  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 369  *
 370  * This routine initializes timing parameters related to NAND memory access in
 371  * FSMC registers
 372  */
 373 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
 374                            uint32_t busw, struct fsmc_nand_timings *timings)
 375 {
 376         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 377         uint32_t tclr, tar, thiz, thold, twait, tset;
 378         struct fsmc_nand_timings *tims;
 379         struct fsmc_nand_timings default_timings = {
 380                 .tclr   = FSMC_TCLR_1,
 381                 .tar    = FSMC_TAR_1,
 382                 .thiz   = FSMC_THIZ_1,
 383                 .thold  = FSMC_THOLD_4,
 384                 .twait  = FSMC_TWAIT_6,
 385                 .tset   = FSMC_TSET_0,
 386         };
 387
 388         if (timings)
 389                 tims = timings;
 390         else
 391                 tims = &default_timings;
 392
 393         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 394         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 395         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 396         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 397         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 398         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 399
 400         if (busw)
 401                 writel_relaxed(value | FSMC_DEVWID_16,
 402                                 FSMC_NAND_REG(regs, bank, PC));
 403         else
 404                 writel_relaxed(value | FSMC_DEVWID_8,
 405                                 FSMC_NAND_REG(regs, bank, PC));
 406
 407         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 408                         FSMC_NAND_REG(regs, bank, PC));
 409         writel_relaxed(thiz | thold | twait | tset,
 410                         FSMC_NAND_REG(regs, bank, COMM));
 411         writel_relaxed(thiz | thold | twait | tset,
 412                         FSMC_NAND_REG(regs, bank, ATTRIB));
 413 }
 414
 415 /*
 416  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 417  */
 418 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 419 {
 420         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 421         void __iomem *regs = host->regs_va;
 422         uint32_t bank = host->bank;
 423
 424         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 425                         FSMC_NAND_REG(regs, bank, PC));
 426         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 427                         FSMC_NAND_REG(regs, bank, PC));
 428         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 429                         FSMC_NAND_REG(regs, bank, PC));
 430 }
 431
 432 /*
 433  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 434  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 435  * max of 8-bits)
 436  */
 437 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 438                                 uint8_t *ecc)
 439 {
 440         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 441         void __iomem *regs = host->regs_va;
 442         uint32_t bank = host->bank;
 443         uint32_t ecc_tmp;
 444         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 445
 446         do {
 447                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 448                         break;
 449                 else
 450                         cond_resched();
 451         } while (!time_after_eq(jiffies, deadline));
 452
 453         if (time_after_eq(jiffies, deadline)) {
 454                 dev_err(host->dev, "calculate ecc timed out\n");
 455                 return -ETIMEDOUT;
 456         }
 457
 458         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 459         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 460         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 461         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 462         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 463
 464         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 465         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 466         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 467         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 468         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 469
 470         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 471         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 472         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 473         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 474         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 475
 476         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 477         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 478
 479         return 0;
 480 }
 481
 482 /*
 483  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 484  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 485  * max of 1-bit)
 486  */
 487 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 488                                 uint8_t *ecc)
 489 {
 490         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 491         void __iomem *regs = host->regs_va;
 492         uint32_t bank = host->bank;
 493         uint32_t ecc_tmp;
 494
 495         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 496         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 497         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 498         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 499
 500         return 0;
 501 }
 502
 503 /* Count the number of 0's in buff upto a max of max_bits */
 504 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 505 {
 506         int k, written_bits = 0;
 507
 508         for (k = 0; k < size; k++) {
 509                 written_bits += hweight8(~buff[k]);
 510                 if (written_bits > max_bits)
 511                         break;
 512         }
 513
 514         return written_bits;
 515 }
 516
 517 static void dma_complete(void *param)
 518 {
 519         struct fsmc_nand_data *host = param;
 520
 521         complete(&host->dma_access_complete);
 522 }
 523
 524 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 525                 enum dma_data_direction direction)
 526 {
 527         struct dma_chan *chan;
 528         struct dma_device *dma_dev;
 529         struct dma_async_tx_descriptor *tx;
 530         dma_addr_t dma_dst, dma_src, dma_addr;
 531         dma_cookie_t cookie;
 532         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 533         int ret;
 534         unsigned long time_left;
 535
 536         if (direction == DMA_TO_DEVICE)
 537                 chan = host->write_dma_chan;
 538         else if (direction == DMA_FROM_DEVICE)
 539                 chan = host->read_dma_chan;
 540         else
 541                 return -EINVAL;
 542
 543         dma_dev = chan->device;
 544         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 545
 546         if (direction == DMA_TO_DEVICE) {
 547                 dma_src = dma_addr;
 548                 dma_dst = host->data_pa;
 549         } else {
 550                 dma_src = host->data_pa;
 551                 dma_dst = dma_addr;
 552         }
 553
 554         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 555                         len, flags);
 556         if (!tx) {
 557                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 558                 ret = -EIO;
 559                 goto unmap_dma;
 560         }
 561
 562         tx->callback = dma_complete;
 563         tx->callback_param = host;
 564         cookie = tx->tx_submit(tx);
 565
 566         ret = dma_submit_error(cookie);
 567         if (ret) {
 568                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 569                 goto unmap_dma;
 570         }
 571
 572         dma_async_issue_pending(chan);
 573
 574         time_left =
 575         wait_for_completion_timeout(&host->dma_access_complete,
 576                                 msecs_to_jiffies(3000));
 577         if (time_left == 0) {
 578                 dmaengine_terminate_all(chan);
 579                 dev_err(host->dev, "wait_for_completion_timeout\n");
 580                 ret = -ETIMEDOUT;
 581                 goto unmap_dma;
 582         }
 583
 584         ret = 0;
 585
 586 unmap_dma:
 587         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 588
 589         return ret;
 590 }
 591
 592 /*
 593  * fsmc_write_buf - write buffer to chip
 594  * @mtd:        MTD device structure
 595  * @buf:        data buffer
 596  * @len:        number of bytes to write
 597  */
 598 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 599 {
 600         int i;
 601         struct nand_chip *chip = mtd_to_nand(mtd);
 602
 603         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 604                         IS_ALIGNED(len, sizeof(uint32_t))) {
 605                 uint32_t *p = (uint32_t *)buf;
 606                 len = len >> 2;
 607                 for (i = 0; i < len; i++)
 608                         writel_relaxed(p[i], chip->IO_ADDR_W);
 609         } else {
 610                 for (i = 0; i < len; i++)
 611                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 612         }
 613 }
 614
 615 /*
 616  * fsmc_read_buf - read chip data into buffer
 617  * @mtd:        MTD device structure
 618  * @buf:        buffer to store date
 619  * @len:        number of bytes to read
 620  */
 621 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 622 {
 623         int i;
 624         struct nand_chip *chip = mtd_to_nand(mtd);
 625
 626         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 627                         IS_ALIGNED(len, sizeof(uint32_t))) {
 628                 uint32_t *p = (uint32_t *)buf;
 629                 len = len >> 2;
 630                 for (i = 0; i < len; i++)
 631                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 632         } else {
 633                 for (i = 0; i < len; i++)
 634                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 635         }
 636 }
 637
 638 /*
 639  * fsmc_read_buf_dma - read chip data into buffer
 640  * @mtd:        MTD device structure
 641  * @buf:        buffer to store date
 642  * @len:        number of bytes to read
 643  */
 644 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 645 {
 646         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 647
 648         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 649 }
 650
 651 /*
 652  * fsmc_write_buf_dma - write buffer to chip
 653  * @mtd:        MTD device structure
 654  * @buf:        data buffer
 655  * @len:        number of bytes to write
 656  */
 657 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 658                 int len)
 659 {
 660         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 661
 662         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 663 }
 664
 665 /*
 666  * fsmc_read_page_hwecc
 667  * @mtd:        mtd info structure
 668  * @chip:       nand chip info structure
 669  * @buf:        buffer to store read data
 670  * @oob_required:       caller expects OOB data read to chip->oob_poi
 671  * @page:       page number to read
 672  *
 673  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 674  * performed in a strict sequence as follows:
 675  * data(512 byte) -> ecc(13 byte)
 676  * After this read, fsmc hardware generates and reports error data bits(up to a
 677  * max of 8 bits)
 678  */
 679 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 680                                  uint8_t *buf, int oob_required, int page)
 681 {
 682         int i, j, s, stat, eccsize = chip->ecc.size;
 683         int eccbytes = chip->ecc.bytes;
 684         int eccsteps = chip->ecc.steps;
 685         uint8_t *p = buf;
 686         uint8_t *ecc_calc = chip->buffers->ecccalc;
 687         uint8_t *ecc_code = chip->buffers->ecccode;
 688         int off, len, group = 0;
 689         /*
 690          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 691          * end up reading 14 bytes (7 words) from oob. The local array is
 692          * to maintain word alignment
 693          */
 694         uint16_t ecc_oob[7];
 695         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 696         unsigned int max_bitflips = 0;
 697
 698         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 699                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 700                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 701                 chip->read_buf(mtd, p, eccsize);
 702
 703                 for (j = 0; j < eccbytes;) {
 704                         struct mtd_oob_region oobregion;
 705                         int ret;
 706
 707                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 708                         if (ret)
 709                                 return ret;
 710
 711                         off = oobregion.offset;
 712                         len = oobregion.length;
 713
 714                         /*
 715                          * length is intentionally kept a higher multiple of 2
 716                          * to read at least 13 bytes even in case of 16 bit NAND
 717                          * devices
 718                          */
 719                         if (chip->options & NAND_BUSWIDTH_16)
 720                                 len = roundup(len, 2);
 721
 722                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 723                         chip->read_buf(mtd, oob + j, len);
 724                         j += len;
 725                 }
 726
 727                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 728                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 729
 730                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 731                 if (stat < 0) {
 732                         mtd->ecc_stats.failed++;
 733                 } else {
 734                         mtd->ecc_stats.corrected += stat;
 735                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 736                 }
 737         }
 738
 739         return max_bitflips;
 740 }
 741
 742 /*
 743  * fsmc_bch8_correct_data
 744  * @mtd:        mtd info structure
 745  * @dat:        buffer of read data
 746  * @read_ecc:   ecc read from device spare area
 747  * @calc_ecc:   ecc calculated from read data
 748  *
 749  * calc_ecc is a 104 bit information containing maximum of 8 error
 750  * offset informations of 13 bits each in 512 bytes of read data.
 751  */
 752 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 753                              uint8_t *read_ecc, uint8_t *calc_ecc)
 754 {
 755         struct nand_chip *chip = mtd_to_nand(mtd);
 756         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 757         void __iomem *regs = host->regs_va;
 758         unsigned int bank = host->bank;
 759         uint32_t err_idx[8];
 760         uint32_t num_err, i;
 761         uint32_t ecc1, ecc2, ecc3, ecc4;
 762
 763         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 764
 765         /* no bit flipping */
 766         if (likely(num_err == 0))
 767                 return 0;
 768
 769         /* too many errors */
 770         if (unlikely(num_err > 8)) {
 771                 /*
 772                  * This is a temporary erase check. A newly erased page read
 773                  * would result in an ecc error because the oob data is also
 774                  * erased to FF and the calculated ecc for an FF data is not
 775                  * FF..FF.
 776                  * This is a workaround to skip performing correction in case
 777                  * data is FF..FF
 778                  *
 779                  * Logic:
 780                  * For every page, each bit written as 0 is counted until these
 781                  * number of bits are greater than 8 (the maximum correction
 782                  * capability of FSMC for each 512 + 13 bytes)
 783                  */
 784
 785                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 786                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 787
 788                 if ((bits_ecc + bits_data) <= 8) {
 789                         if (bits_data)
 790                                 memset(dat, 0xff, chip->ecc.size);
 791                         return bits_data;
 792                 }
 793
 794                 return -EBADMSG;
 795         }
 796
 797         /*
 798          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 799          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 800          *
 801          * calc_ecc is a 104 bit information containing maximum of 8 error
 802          * offset informations of 13 bits each. calc_ecc is copied into a
 803          * uint64_t array and error offset indexes are populated in err_idx
 804          * array
 805          */
 806         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 807         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 808         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 809         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 810
 811         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 812         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 813         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 814         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 815         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 816         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 817         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 818         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 819
 820         i = 0;
 821         while (num_err--) {
 822                 change_bit(0, (unsigned long *)&err_idx[i]);
 823                 change_bit(1, (unsigned long *)&err_idx[i]);
 824
 825                 if (err_idx[i] < chip->ecc.size * 8) {
 826                         change_bit(err_idx[i], (unsigned long *)dat);
 827                         i++;
 828                 }
 829         }
 830         return i;
 831 }
 832
 833 static bool filter(struct dma_chan *chan, void *slave)
 834 {
 835         chan->private = slave;
 836         return true;
 837 }
 838
 839 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 840                                      struct device_node *np)
 841 {
 842         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 843         u32 val;
 844         int ret;
 845
 846         pdata->options = 0;
 847
 848         if (!of_property_read_u32(np, "bank-width", &val)) {
 849                 if (val == 2) {
 850                         pdata->options |= NAND_BUSWIDTH_16;
 851                 } else if (val != 1) {
 852                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 853                         return -EINVAL;
 854                 }
 855         }
 856
 857         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 858                 pdata->options |= NAND_SKIP_BBTSCAN;
 859
 860         pdata->nand_timings = devm_kzalloc(&pdev->dev,
 861                                 sizeof(*pdata->nand_timings), GFP_KERNEL);
 862         if (!pdata->nand_timings)
 863                 return -ENOMEM;
 864         ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
 865                                                 sizeof(*pdata->nand_timings));
 866         if (ret) {
 867                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 868                 pdata->nand_timings = NULL;
 869         }
 870
 871         /* Set default NAND bank to 0 */
 872         pdata->bank = 0;
 873         if (!of_property_read_u32(np, "bank", &val)) {
 874                 if (val > 3) {
 875                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 876                         return -EINVAL;
 877                 }
 878                 pdata->bank = val;
 879         }
 880         return 0;
 881 }
 882
 883 /*
 884  * fsmc_nand_probe - Probe function
 885  * @pdev:       platform device structure
 886  */
 887 static int __init fsmc_nand_probe(struct platform_device *pdev)
 888 {
 889         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 890         struct device_node __maybe_unused *np = pdev->dev.of_node;
 891         struct fsmc_nand_data *host;
 892         struct mtd_info *mtd;
 893         struct nand_chip *nand;
 894         struct resource *res;
 895         dma_cap_mask_t mask;
 896         int ret = 0;
 897         u32 pid;
 898         int i;
 899
 900         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 901         if (!pdata)
 902                 return -ENOMEM;
 903
 904         pdev->dev.platform_data = pdata;
 905         ret = fsmc_nand_probe_config_dt(pdev, np);
 906         if (ret) {
 907                 dev_err(&pdev->dev, "no platform data\n");
 908                 return -ENODEV;
 909         }
 910
 911         /* Allocate memory for the device structure (and zero it) */
 912         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 913         if (!host)
 914                 return -ENOMEM;
 915
 916         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 917         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 918         if (IS_ERR(host->data_va))
 919                 return PTR_ERR(host->data_va);
 920
 921         host->data_pa = (dma_addr_t)res->start;
 922
 923         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 924         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 925         if (IS_ERR(host->addr_va))
 926                 return PTR_ERR(host->addr_va);
 927
 928         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 929         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 930         if (IS_ERR(host->cmd_va))
 931                 return PTR_ERR(host->cmd_va);
 932
 933         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 934         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 935         if (IS_ERR(host->regs_va))
 936                 return PTR_ERR(host->regs_va);
 937
 938         host->clk = clk_get(&pdev->dev, NULL);
 939         if (IS_ERR(host->clk)) {
 940                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 941                 return PTR_ERR(host->clk);
 942         }
 943
 944         ret = clk_prepare_enable(host->clk);
 945         if (ret)
 946                 goto err_clk_prepare_enable;
 947
 948         /*
 949          * This device ID is actually a common AMBA ID as used on the
 950          * AMBA PrimeCell bus. However it is not a PrimeCell.
 951          */
 952         for (pid = 0, i = 0; i < 4; i++)
 953                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 954         host->pid = pid;
 955         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 956                  "revision %02x, config %02x\n",
 957                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 958                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 959
 960         host->bank = pdata->bank;
 961         host->select_chip = pdata->select_bank;
 962         host->partitions = pdata->partitions;
 963         host->nr_partitions = pdata->nr_partitions;
 964         host->dev = &pdev->dev;
 965         host->dev_timings = pdata->nand_timings;
 966         host->mode = pdata->mode;
 967
 968         if (host->mode == USE_DMA_ACCESS)
 969                 init_completion(&host->dma_access_complete);
 970
 971         /* Link all private pointers */
 972         mtd = nand_to_mtd(&host->nand);
 973         nand = &host->nand;
 974         nand_set_controller_data(nand, host);
 975         nand_set_flash_node(nand, np);
 976
 977         mtd->dev.parent = &pdev->dev;
 978         nand->IO_ADDR_R = host->data_va;
 979         nand->IO_ADDR_W = host->data_va;
 980         nand->cmd_ctrl = fsmc_cmd_ctrl;
 981         nand->chip_delay = 30;
 982
 983         /*
 984          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 985          * can overwrite this value if the DT provides a different value.
 986          */
 987         nand->ecc.mode = NAND_ECC_HW;
 988         nand->ecc.hwctl = fsmc_enable_hwecc;
 989         nand->ecc.size = 512;
 990         nand->options = pdata->options;
 991         nand->select_chip = fsmc_select_chip;
 992         nand->badblockbits = 7;
 993         nand_set_flash_node(nand, np);
 994
 995         switch (host->mode) {
 996         case USE_DMA_ACCESS:
 997                 dma_cap_zero(mask);
 998                 dma_cap_set(DMA_MEMCPY, mask);
 999                 host->read_dma_chan = dma_request_channel(mask, filter,
1000                                 pdata->read_dma_priv);
1001                 if (!host->read_dma_chan) {
1002                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
1003                         goto err_req_read_chnl;
1004                 }
1005                 host->write_dma_chan = dma_request_channel(mask, filter,
1006                                 pdata->write_dma_priv);
1007                 if (!host->write_dma_chan) {
1008                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
1009                         goto err_req_write_chnl;
1010                 }
1011                 nand->read_buf = fsmc_read_buf_dma;
1012                 nand->write_buf = fsmc_write_buf_dma;
1013                 break;
1014
1015         default:
1016         case USE_WORD_ACCESS:
1017                 nand->read_buf = fsmc_read_buf;
1018                 nand->write_buf = fsmc_write_buf;
1019                 break;
1020         }
1021
1022         fsmc_nand_setup(host->regs_va, host->bank,
1023                         nand->options & NAND_BUSWIDTH_16,
1024                         host->dev_timings);
1025
1026         if (AMBA_REV_BITS(host->pid) >= 8) {
1027                 nand->ecc.read_page = fsmc_read_page_hwecc;
1028                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
1029                 nand->ecc.correct = fsmc_bch8_correct_data;
1030                 nand->ecc.bytes = 13;
1031                 nand->ecc.strength = 8;
1032         }
1033
1034         /*
1035          * Scan to find existence of the device
1036          */
1037         ret = nand_scan_ident(mtd, 1, NULL);
1038         if (ret) {
1039                 dev_err(&pdev->dev, "No NAND Device found!\n");
1040                 goto err_scan_ident;
1041         }
1042
1043         if (AMBA_REV_BITS(host->pid) >= 8) {
1044                 switch (mtd->oobsize) {
1045                 case 16:
1046                 case 64:
1047                 case 128:
1048                 case 224:
1049                 case 256:
1050                         break;
1051                 default:
1052                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1053                                  mtd->oobsize);
1054                         ret = -EINVAL;
1055                         goto err_probe;
1056                 }
1057
1058                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1059         } else {
1060                 switch (nand->ecc.mode) {
1061                 case NAND_ECC_HW:
1062                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1063                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1064                         nand->ecc.correct = nand_correct_data;
1065                         nand->ecc.bytes = 3;
1066                         nand->ecc.strength = 1;
1067                         break;
1068
1069                 case NAND_ECC_SOFT:
1070                         if (nand->ecc.algo == NAND_ECC_BCH) {
1071                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1072                                 break;
1073                         }
1074
1075                 default:
1076                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1077                         goto err_probe;
1078                 }
1079
1080                 /*
1081                  * Don't set layout for BCH4 SW ECC. This will be
1082                  * generated later in nand_bch_init() later.
1083                  */
1084                 if (nand->ecc.mode == NAND_ECC_HW) {
1085                         switch (mtd->oobsize) {
1086                         case 16:
1087                         case 64:
1088                         case 128:
1089                                 mtd_set_ooblayout(mtd,
1090                                                   &fsmc_ecc1_ooblayout_ops);
1091                                 break;
1092                         default:
1093                                 dev_warn(&pdev->dev,
1094                                          "No oob scheme defined for oobsize %d\n",
1095                                          mtd->oobsize);
1096                                 ret = -EINVAL;
1097                                 goto err_probe;
1098                         }
1099                 }
1100         }
1101
1102         /* Second stage of scan to fill MTD data-structures */
1103         ret = nand_scan_tail(mtd);
1104         if (ret)
1105                 goto err_probe;
1106
1107         /*
1108          * The partition information can is accessed by (in the same precedence)
1109          *
1110          * command line through Bootloader,
1111          * platform data,
1112          * default partition information present in driver.
1113          */
1114         /*
1115          * Check for partition info passed
1116          */
1117         mtd->name = "nand";
1118         ret = mtd_device_register(mtd, host->partitions, host->nr_partitions);
1119         if (ret)
1120                 goto err_probe;
1121
1122         platform_set_drvdata(pdev, host);
1123         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1124         return 0;
1125
1126 err_probe:
1127 err_scan_ident:
1128         if (host->mode == USE_DMA_ACCESS)
1129                 dma_release_channel(host->write_dma_chan);
1130 err_req_write_chnl:
1131         if (host->mode == USE_DMA_ACCESS)
1132                 dma_release_channel(host->read_dma_chan);
1133 err_req_read_chnl:
1134         clk_disable_unprepare(host->clk);
1135 err_clk_prepare_enable:
1136         clk_put(host->clk);
1137         return ret;
1138 }
1139
1140 /*
1141  * Clean up routine
1142  */
1143 static int fsmc_nand_remove(struct platform_device *pdev)
1144 {
1145         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1146
1147         if (host) {
1148                 nand_release(nand_to_mtd(&host->nand));
1149
1150                 if (host->mode == USE_DMA_ACCESS) {
1151                         dma_release_channel(host->write_dma_chan);
1152                         dma_release_channel(host->read_dma_chan);
1153                 }
1154                 clk_disable_unprepare(host->clk);
1155                 clk_put(host->clk);
1156         }
1157
1158         return 0;
1159 }
1160
1161 #ifdef CONFIG_PM_SLEEP
1162 static int fsmc_nand_suspend(struct device *dev)
1163 {
1164         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1165         if (host)
1166                 clk_disable_unprepare(host->clk);
1167         return 0;
1168 }
1169
1170 static int fsmc_nand_resume(struct device *dev)
1171 {
1172         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1173         if (host) {
1174                 clk_prepare_enable(host->clk);
1175                 fsmc_nand_setup(host->regs_va, host->bank,
1176                                 host->nand.options & NAND_BUSWIDTH_16,
1177                                 host->dev_timings);
1178         }
1179         return 0;
1180 }
1181 #endif
1182
1183 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1184
1185 #ifdef CONFIG_OF
1186 static const struct of_device_id fsmc_nand_id_table[] = {
1187         { .compatible = "st,spear600-fsmc-nand" },
1188         { .compatible = "stericsson,fsmc-nand" },
1189         {}
1190 };
1191 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1192 #endif
1193
1194 static struct platform_driver fsmc_nand_driver = {
1195         .remove = fsmc_nand_remove,
1196         .driver = {
1197                 .name = "fsmc-nand",
1198                 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1199                 .pm = &fsmc_nand_pm_ops,
1200         },
1201 };
1202
1203 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1204
1205 MODULE_LICENSE("GPL");
1206 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1207 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");