drivers/mtd/nand/fsmc_nand.c

   1 /*
   2  * drivers/mtd/nand/fsmc_nand.c
   3  *
   4  * ST Microelectronics
   5  * Flexible Static Memory Controller (FSMC)
   6  * Driver for NAND portions
   7  *
   8  * Copyright © 2010 ST Microelectronics
   9  * Vipin Kumar <vipin.kumar@st.com>
  10  * Ashish Priyadarshi
  11  *
  12  * Based on drivers/mtd/nand/nomadik_nand.c
  13  *
  14  * This file is licensed under the terms of the GNU General Public
  15  * License version 2. This program is licensed "as is" without any
  16  * warranty of any kind, whether express or implied.
  17  */
  18
  19 #include <linux/clk.h>
  20 #include <linux/completion.h>
  21 #include <linux/dmaengine.h>
  22 #include <linux/dma-direction.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/err.h>
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/resource.h>
  28 #include <linux/sched.h>
  29 #include <linux/types.h>
  30 #include <linux/mtd/mtd.h>
  31 #include <linux/mtd/nand.h>
  32 #include <linux/mtd/nand_ecc.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/of.h>
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/io.h>
  37 #include <linux/slab.h>
  38 #include <linux/amba/bus.h>
  39 #include <mtd/mtd-abi.h>
  40
  41 #define FSMC_NAND_BW8           1
  42 #define FSMC_NAND_BW16          2
  43
  44 #define FSMC_MAX_NOR_BANKS      4
  45 #define FSMC_MAX_NAND_BANKS     4
  46
  47 #define FSMC_FLASH_WIDTH8       1
  48 #define FSMC_FLASH_WIDTH16      2
  49
  50 /* fsmc controller registers for NOR flash */
  51 #define CTRL                    0x0
  52         /* ctrl register definitions */
  53         #define BANK_ENABLE             (1 << 0)
  54         #define MUXED                   (1 << 1)
  55         #define NOR_DEV                 (2 << 2)
  56         #define WIDTH_8                 (0 << 4)
  57         #define WIDTH_16                (1 << 4)
  58         #define RSTPWRDWN               (1 << 6)
  59         #define WPROT                   (1 << 7)
  60         #define WRT_ENABLE              (1 << 12)
  61         #define WAIT_ENB                (1 << 13)
  62
  63 #define CTRL_TIM                0x4
  64         /* ctrl_tim register definitions */
  65
  66 #define FSMC_NOR_BANK_SZ        0x8
  67 #define FSMC_NOR_REG_SIZE       0x40
  68
  69 #define FSMC_NOR_REG(base, bank, reg)           (base + \
  70                                                 FSMC_NOR_BANK_SZ * (bank) + \
  71                                                 reg)
  72
  73 /* fsmc controller registers for NAND flash */
  74 #define PC                      0x00
  75         /* pc register definitions */
  76         #define FSMC_RESET              (1 << 0)
  77         #define FSMC_WAITON             (1 << 1)
  78         #define FSMC_ENABLE             (1 << 2)
  79         #define FSMC_DEVTYPE_NAND       (1 << 3)
  80         #define FSMC_DEVWID_8           (0 << 4)
  81         #define FSMC_DEVWID_16          (1 << 4)
  82         #define FSMC_ECCEN              (1 << 6)
  83         #define FSMC_ECCPLEN_512        (0 << 7)
  84         #define FSMC_ECCPLEN_256        (1 << 7)
  85         #define FSMC_TCLR_1             (1)
  86         #define FSMC_TCLR_SHIFT         (9)
  87         #define FSMC_TCLR_MASK          (0xF)
  88         #define FSMC_TAR_1              (1)
  89         #define FSMC_TAR_SHIFT          (13)
  90         #define FSMC_TAR_MASK           (0xF)
  91 #define STS                     0x04
  92         /* sts register definitions */
  93         #define FSMC_CODE_RDY           (1 << 15)
  94 #define COMM                    0x08
  95         /* comm register definitions */
  96         #define FSMC_TSET_0             0
  97         #define FSMC_TSET_SHIFT         0
  98         #define FSMC_TSET_MASK          0xFF
  99         #define FSMC_TWAIT_6            6
 100         #define FSMC_TWAIT_SHIFT        8
 101         #define FSMC_TWAIT_MASK         0xFF
 102         #define FSMC_THOLD_4            4
 103         #define FSMC_THOLD_SHIFT        16
 104         #define FSMC_THOLD_MASK         0xFF
 105         #define FSMC_THIZ_1             1
 106         #define FSMC_THIZ_SHIFT         24
 107         #define FSMC_THIZ_MASK          0xFF
 108 #define ATTRIB                  0x0C
 109 #define IOATA                   0x10
 110 #define ECC1                    0x14
 111 #define ECC2                    0x18
 112 #define ECC3                    0x1C
 113 #define FSMC_NAND_BANK_SZ       0x20
 114
 115 #define FSMC_NAND_REG(base, bank, reg)          (base + FSMC_NOR_REG_SIZE + \
 116                                                 (FSMC_NAND_BANK_SZ * (bank)) + \
 117                                                 reg)
 118
 119 #define FSMC_BUSY_WAIT_TIMEOUT  (1 * HZ)
 120
 121 struct fsmc_nand_timings {
 122         uint8_t tclr;
 123         uint8_t tar;
 124         uint8_t thiz;
 125         uint8_t thold;
 126         uint8_t twait;
 127         uint8_t tset;
 128 };
 129
 130 enum access_mode {
 131         USE_DMA_ACCESS = 1,
 132         USE_WORD_ACCESS,
 133 };
 134
 135 /**
 136  * fsmc_nand_platform_data - platform specific NAND controller config
 137  * @nand_timings: timing setup for the physical NAND interface
 138  * @partitions: partition table for the platform, use a default fallback
 139  * if this is NULL
 140  * @nr_partitions: the number of partitions in the previous entry
 141  * @options: different options for the driver
 142  * @width: bus width
 143  * @bank: default bank
 144  * platform-specific. If the controller only supports one bank
 145  * this may be set to NULL
 146  */
 147 struct fsmc_nand_platform_data {
 148         struct fsmc_nand_timings *nand_timings;
 149         unsigned int            options;
 150         unsigned int            bank;
 151
 152         enum access_mode        mode;
 153 };
 154
 155 /**
 156  * struct fsmc_nand_data - structure for FSMC NAND device state
 157  *
 158  * @pid:                Part ID on the AMBA PrimeCell format
 159  * @mtd:                MTD info for a NAND flash.
 160  * @nand:               Chip related info for a NAND flash.
 161  * @partitions:         Partition info for a NAND Flash.
 162  * @nr_partitions:      Total number of partition of a NAND flash.
 163  *
 164  * @bank:               Bank number for probed device.
 165  * @clk:                Clock structure for FSMC.
 166  *
 167  * @read_dma_chan:      DMA channel for read access
 168  * @write_dma_chan:     DMA channel for write access to NAND
 169  * @dma_access_complete: Completion structure
 170  *
 171  * @data_pa:            NAND Physical port for Data.
 172  * @data_va:            NAND port for Data.
 173  * @cmd_va:             NAND port for Command.
 174  * @addr_va:            NAND port for Address.
 175  * @regs_va:            FSMC regs base address.
 176  */
 177 struct fsmc_nand_data {
 178         u32                     pid;
 179         struct nand_chip        nand;
 180
 181         unsigned int            bank;
 182         struct device           *dev;
 183         enum access_mode        mode;
 184         struct clk              *clk;
 185
 186         /* DMA related objects */
 187         struct dma_chan         *read_dma_chan;
 188         struct dma_chan         *write_dma_chan;
 189         struct completion       dma_access_complete;
 190
 191         struct fsmc_nand_timings *dev_timings;
 192
 193         dma_addr_t              data_pa;
 194         void __iomem            *data_va;
 195         void __iomem            *cmd_va;
 196         void __iomem            *addr_va;
 197         void __iomem            *regs_va;
 198 };
 199
 200 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
 201                                    struct mtd_oob_region *oobregion)
 202 {
 203         struct nand_chip *chip = mtd_to_nand(mtd);
 204
 205         if (section >= chip->ecc.steps)
 206                 return -ERANGE;
 207
 208         oobregion->offset = (section * 16) + 2;
 209         oobregion->length = 3;
 210
 211         return 0;
 212 }
 213
 214 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
 215                                     struct mtd_oob_region *oobregion)
 216 {
 217         struct nand_chip *chip = mtd_to_nand(mtd);
 218
 219         if (section >= chip->ecc.steps)
 220                 return -ERANGE;
 221
 222         oobregion->offset = (section * 16) + 8;
 223
 224         if (section < chip->ecc.steps - 1)
 225                 oobregion->length = 8;
 226         else
 227                 oobregion->length = mtd->oobsize - oobregion->offset;
 228
 229         return 0;
 230 }
 231
 232 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
 233         .ecc = fsmc_ecc1_ooblayout_ecc,
 234         .free = fsmc_ecc1_ooblayout_free,
 235 };
 236
 237 /*
 238  * ECC placement definitions in oobfree type format.
 239  * There are 13 bytes of ecc for every 512 byte block and it has to be read
 240  * consecutively and immediately after the 512 byte data block for hardware to
 241  * generate the error bit offsets in 512 byte data.
 242  */
 243 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
 244                                    struct mtd_oob_region *oobregion)
 245 {
 246         struct nand_chip *chip = mtd_to_nand(mtd);
 247
 248         if (section >= chip->ecc.steps)
 249                 return -ERANGE;
 250
 251         oobregion->length = chip->ecc.bytes;
 252
 253         if (!section && mtd->writesize <= 512)
 254                 oobregion->offset = 0;
 255         else
 256                 oobregion->offset = (section * 16) + 2;
 257
 258         return 0;
 259 }
 260
 261 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
 262                                     struct mtd_oob_region *oobregion)
 263 {
 264         struct nand_chip *chip = mtd_to_nand(mtd);
 265
 266         if (section >= chip->ecc.steps)
 267                 return -ERANGE;
 268
 269         oobregion->offset = (section * 16) + 15;
 270
 271         if (section < chip->ecc.steps - 1)
 272                 oobregion->length = 3;
 273         else
 274                 oobregion->length = mtd->oobsize - oobregion->offset;
 275
 276         return 0;
 277 }
 278
 279 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
 280         .ecc = fsmc_ecc4_ooblayout_ecc,
 281         .free = fsmc_ecc4_ooblayout_free,
 282 };
 283
 284 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
 285 {
 286         return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
 287 }
 288
 289 /*
 290  * fsmc_cmd_ctrl - For facilitaing Hardware access
 291  * This routine allows hardware specific access to control-lines(ALE,CLE)
 292  */
 293 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
 294 {
 295         struct nand_chip *this = mtd_to_nand(mtd);
 296         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 297         void __iomem *regs = host->regs_va;
 298         unsigned int bank = host->bank;
 299
 300         if (ctrl & NAND_CTRL_CHANGE) {
 301                 u32 pc;
 302
 303                 if (ctrl & NAND_CLE) {
 304                         this->IO_ADDR_R = host->cmd_va;
 305                         this->IO_ADDR_W = host->cmd_va;
 306                 } else if (ctrl & NAND_ALE) {
 307                         this->IO_ADDR_R = host->addr_va;
 308                         this->IO_ADDR_W = host->addr_va;
 309                 } else {
 310                         this->IO_ADDR_R = host->data_va;
 311                         this->IO_ADDR_W = host->data_va;
 312                 }
 313
 314                 pc = readl(FSMC_NAND_REG(regs, bank, PC));
 315                 if (ctrl & NAND_NCE)
 316                         pc |= FSMC_ENABLE;
 317                 else
 318                         pc &= ~FSMC_ENABLE;
 319                 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
 320         }
 321
 322         mb();
 323
 324         if (cmd != NAND_CMD_NONE)
 325                 writeb_relaxed(cmd, this->IO_ADDR_W);
 326 }
 327
 328 /*
 329  * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
 330  *
 331  * This routine initializes timing parameters related to NAND memory access in
 332  * FSMC registers
 333  */
 334 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
 335                            uint32_t busw, struct fsmc_nand_timings *timings)
 336 {
 337         uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
 338         uint32_t tclr, tar, thiz, thold, twait, tset;
 339         struct fsmc_nand_timings *tims;
 340         struct fsmc_nand_timings default_timings = {
 341                 .tclr   = FSMC_TCLR_1,
 342                 .tar    = FSMC_TAR_1,
 343                 .thiz   = FSMC_THIZ_1,
 344                 .thold  = FSMC_THOLD_4,
 345                 .twait  = FSMC_TWAIT_6,
 346                 .tset   = FSMC_TSET_0,
 347         };
 348
 349         if (timings)
 350                 tims = timings;
 351         else
 352                 tims = &default_timings;
 353
 354         tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
 355         tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
 356         thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
 357         thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
 358         twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
 359         tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
 360
 361         if (busw)
 362                 writel_relaxed(value | FSMC_DEVWID_16,
 363                                 FSMC_NAND_REG(regs, bank, PC));
 364         else
 365                 writel_relaxed(value | FSMC_DEVWID_8,
 366                                 FSMC_NAND_REG(regs, bank, PC));
 367
 368         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
 369                         FSMC_NAND_REG(regs, bank, PC));
 370         writel_relaxed(thiz | thold | twait | tset,
 371                         FSMC_NAND_REG(regs, bank, COMM));
 372         writel_relaxed(thiz | thold | twait | tset,
 373                         FSMC_NAND_REG(regs, bank, ATTRIB));
 374 }
 375
 376 /*
 377  * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
 378  */
 379 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
 380 {
 381         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 382         void __iomem *regs = host->regs_va;
 383         uint32_t bank = host->bank;
 384
 385         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
 386                         FSMC_NAND_REG(regs, bank, PC));
 387         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
 388                         FSMC_NAND_REG(regs, bank, PC));
 389         writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
 390                         FSMC_NAND_REG(regs, bank, PC));
 391 }
 392
 393 /*
 394  * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
 395  * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
 396  * max of 8-bits)
 397  */
 398 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
 399                                 uint8_t *ecc)
 400 {
 401         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 402         void __iomem *regs = host->regs_va;
 403         uint32_t bank = host->bank;
 404         uint32_t ecc_tmp;
 405         unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
 406
 407         do {
 408                 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
 409                         break;
 410                 else
 411                         cond_resched();
 412         } while (!time_after_eq(jiffies, deadline));
 413
 414         if (time_after_eq(jiffies, deadline)) {
 415                 dev_err(host->dev, "calculate ecc timed out\n");
 416                 return -ETIMEDOUT;
 417         }
 418
 419         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 420         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 421         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 422         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 423         ecc[3] = (uint8_t) (ecc_tmp >> 24);
 424
 425         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 426         ecc[4] = (uint8_t) (ecc_tmp >> 0);
 427         ecc[5] = (uint8_t) (ecc_tmp >> 8);
 428         ecc[6] = (uint8_t) (ecc_tmp >> 16);
 429         ecc[7] = (uint8_t) (ecc_tmp >> 24);
 430
 431         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 432         ecc[8] = (uint8_t) (ecc_tmp >> 0);
 433         ecc[9] = (uint8_t) (ecc_tmp >> 8);
 434         ecc[10] = (uint8_t) (ecc_tmp >> 16);
 435         ecc[11] = (uint8_t) (ecc_tmp >> 24);
 436
 437         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 438         ecc[12] = (uint8_t) (ecc_tmp >> 16);
 439
 440         return 0;
 441 }
 442
 443 /*
 444  * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
 445  * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
 446  * max of 1-bit)
 447  */
 448 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
 449                                 uint8_t *ecc)
 450 {
 451         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 452         void __iomem *regs = host->regs_va;
 453         uint32_t bank = host->bank;
 454         uint32_t ecc_tmp;
 455
 456         ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 457         ecc[0] = (uint8_t) (ecc_tmp >> 0);
 458         ecc[1] = (uint8_t) (ecc_tmp >> 8);
 459         ecc[2] = (uint8_t) (ecc_tmp >> 16);
 460
 461         return 0;
 462 }
 463
 464 /* Count the number of 0's in buff upto a max of max_bits */
 465 static int count_written_bits(uint8_t *buff, int size, int max_bits)
 466 {
 467         int k, written_bits = 0;
 468
 469         for (k = 0; k < size; k++) {
 470                 written_bits += hweight8(~buff[k]);
 471                 if (written_bits > max_bits)
 472                         break;
 473         }
 474
 475         return written_bits;
 476 }
 477
 478 static void dma_complete(void *param)
 479 {
 480         struct fsmc_nand_data *host = param;
 481
 482         complete(&host->dma_access_complete);
 483 }
 484
 485 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
 486                 enum dma_data_direction direction)
 487 {
 488         struct dma_chan *chan;
 489         struct dma_device *dma_dev;
 490         struct dma_async_tx_descriptor *tx;
 491         dma_addr_t dma_dst, dma_src, dma_addr;
 492         dma_cookie_t cookie;
 493         unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
 494         int ret;
 495         unsigned long time_left;
 496
 497         if (direction == DMA_TO_DEVICE)
 498                 chan = host->write_dma_chan;
 499         else if (direction == DMA_FROM_DEVICE)
 500                 chan = host->read_dma_chan;
 501         else
 502                 return -EINVAL;
 503
 504         dma_dev = chan->device;
 505         dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
 506
 507         if (direction == DMA_TO_DEVICE) {
 508                 dma_src = dma_addr;
 509                 dma_dst = host->data_pa;
 510         } else {
 511                 dma_src = host->data_pa;
 512                 dma_dst = dma_addr;
 513         }
 514
 515         tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
 516                         len, flags);
 517         if (!tx) {
 518                 dev_err(host->dev, "device_prep_dma_memcpy error\n");
 519                 ret = -EIO;
 520                 goto unmap_dma;
 521         }
 522
 523         tx->callback = dma_complete;
 524         tx->callback_param = host;
 525         cookie = tx->tx_submit(tx);
 526
 527         ret = dma_submit_error(cookie);
 528         if (ret) {
 529                 dev_err(host->dev, "dma_submit_error %d\n", cookie);
 530                 goto unmap_dma;
 531         }
 532
 533         dma_async_issue_pending(chan);
 534
 535         time_left =
 536         wait_for_completion_timeout(&host->dma_access_complete,
 537                                 msecs_to_jiffies(3000));
 538         if (time_left == 0) {
 539                 dmaengine_terminate_all(chan);
 540                 dev_err(host->dev, "wait_for_completion_timeout\n");
 541                 ret = -ETIMEDOUT;
 542                 goto unmap_dma;
 543         }
 544
 545         ret = 0;
 546
 547 unmap_dma:
 548         dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
 549
 550         return ret;
 551 }
 552
 553 /*
 554  * fsmc_write_buf - write buffer to chip
 555  * @mtd:        MTD device structure
 556  * @buf:        data buffer
 557  * @len:        number of bytes to write
 558  */
 559 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
 560 {
 561         int i;
 562         struct nand_chip *chip = mtd_to_nand(mtd);
 563
 564         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 565                         IS_ALIGNED(len, sizeof(uint32_t))) {
 566                 uint32_t *p = (uint32_t *)buf;
 567                 len = len >> 2;
 568                 for (i = 0; i < len; i++)
 569                         writel_relaxed(p[i], chip->IO_ADDR_W);
 570         } else {
 571                 for (i = 0; i < len; i++)
 572                         writeb_relaxed(buf[i], chip->IO_ADDR_W);
 573         }
 574 }
 575
 576 /*
 577  * fsmc_read_buf - read chip data into buffer
 578  * @mtd:        MTD device structure
 579  * @buf:        buffer to store date
 580  * @len:        number of bytes to read
 581  */
 582 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
 583 {
 584         int i;
 585         struct nand_chip *chip = mtd_to_nand(mtd);
 586
 587         if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
 588                         IS_ALIGNED(len, sizeof(uint32_t))) {
 589                 uint32_t *p = (uint32_t *)buf;
 590                 len = len >> 2;
 591                 for (i = 0; i < len; i++)
 592                         p[i] = readl_relaxed(chip->IO_ADDR_R);
 593         } else {
 594                 for (i = 0; i < len; i++)
 595                         buf[i] = readb_relaxed(chip->IO_ADDR_R);
 596         }
 597 }
 598
 599 /*
 600  * fsmc_read_buf_dma - read chip data into buffer
 601  * @mtd:        MTD device structure
 602  * @buf:        buffer to store date
 603  * @len:        number of bytes to read
 604  */
 605 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
 606 {
 607         struct fsmc_nand_data *host  = mtd_to_fsmc(mtd);
 608
 609         dma_xfer(host, buf, len, DMA_FROM_DEVICE);
 610 }
 611
 612 /*
 613  * fsmc_write_buf_dma - write buffer to chip
 614  * @mtd:        MTD device structure
 615  * @buf:        data buffer
 616  * @len:        number of bytes to write
 617  */
 618 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
 619                 int len)
 620 {
 621         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 622
 623         dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
 624 }
 625
 626 /*
 627  * fsmc_read_page_hwecc
 628  * @mtd:        mtd info structure
 629  * @chip:       nand chip info structure
 630  * @buf:        buffer to store read data
 631  * @oob_required:       caller expects OOB data read to chip->oob_poi
 632  * @page:       page number to read
 633  *
 634  * This routine is needed for fsmc version 8 as reading from NAND chip has to be
 635  * performed in a strict sequence as follows:
 636  * data(512 byte) -> ecc(13 byte)
 637  * After this read, fsmc hardware generates and reports error data bits(up to a
 638  * max of 8 bits)
 639  */
 640 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
 641                                  uint8_t *buf, int oob_required, int page)
 642 {
 643         int i, j, s, stat, eccsize = chip->ecc.size;
 644         int eccbytes = chip->ecc.bytes;
 645         int eccsteps = chip->ecc.steps;
 646         uint8_t *p = buf;
 647         uint8_t *ecc_calc = chip->buffers->ecccalc;
 648         uint8_t *ecc_code = chip->buffers->ecccode;
 649         int off, len, group = 0;
 650         /*
 651          * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
 652          * end up reading 14 bytes (7 words) from oob. The local array is
 653          * to maintain word alignment
 654          */
 655         uint16_t ecc_oob[7];
 656         uint8_t *oob = (uint8_t *)&ecc_oob[0];
 657         unsigned int max_bitflips = 0;
 658
 659         for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
 660                 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
 661                 chip->ecc.hwctl(mtd, NAND_ECC_READ);
 662                 chip->read_buf(mtd, p, eccsize);
 663
 664                 for (j = 0; j < eccbytes;) {
 665                         struct mtd_oob_region oobregion;
 666                         int ret;
 667
 668                         ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
 669                         if (ret)
 670                                 return ret;
 671
 672                         off = oobregion.offset;
 673                         len = oobregion.length;
 674
 675                         /*
 676                          * length is intentionally kept a higher multiple of 2
 677                          * to read at least 13 bytes even in case of 16 bit NAND
 678                          * devices
 679                          */
 680                         if (chip->options & NAND_BUSWIDTH_16)
 681                                 len = roundup(len, 2);
 682
 683                         chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
 684                         chip->read_buf(mtd, oob + j, len);
 685                         j += len;
 686                 }
 687
 688                 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
 689                 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
 690
 691                 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
 692                 if (stat < 0) {
 693                         mtd->ecc_stats.failed++;
 694                 } else {
 695                         mtd->ecc_stats.corrected += stat;
 696                         max_bitflips = max_t(unsigned int, max_bitflips, stat);
 697                 }
 698         }
 699
 700         return max_bitflips;
 701 }
 702
 703 /*
 704  * fsmc_bch8_correct_data
 705  * @mtd:        mtd info structure
 706  * @dat:        buffer of read data
 707  * @read_ecc:   ecc read from device spare area
 708  * @calc_ecc:   ecc calculated from read data
 709  *
 710  * calc_ecc is a 104 bit information containing maximum of 8 error
 711  * offset informations of 13 bits each in 512 bytes of read data.
 712  */
 713 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
 714                              uint8_t *read_ecc, uint8_t *calc_ecc)
 715 {
 716         struct nand_chip *chip = mtd_to_nand(mtd);
 717         struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
 718         void __iomem *regs = host->regs_va;
 719         unsigned int bank = host->bank;
 720         uint32_t err_idx[8];
 721         uint32_t num_err, i;
 722         uint32_t ecc1, ecc2, ecc3, ecc4;
 723
 724         num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
 725
 726         /* no bit flipping */
 727         if (likely(num_err == 0))
 728                 return 0;
 729
 730         /* too many errors */
 731         if (unlikely(num_err > 8)) {
 732                 /*
 733                  * This is a temporary erase check. A newly erased page read
 734                  * would result in an ecc error because the oob data is also
 735                  * erased to FF and the calculated ecc for an FF data is not
 736                  * FF..FF.
 737                  * This is a workaround to skip performing correction in case
 738                  * data is FF..FF
 739                  *
 740                  * Logic:
 741                  * For every page, each bit written as 0 is counted until these
 742                  * number of bits are greater than 8 (the maximum correction
 743                  * capability of FSMC for each 512 + 13 bytes)
 744                  */
 745
 746                 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
 747                 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
 748
 749                 if ((bits_ecc + bits_data) <= 8) {
 750                         if (bits_data)
 751                                 memset(dat, 0xff, chip->ecc.size);
 752                         return bits_data;
 753                 }
 754
 755                 return -EBADMSG;
 756         }
 757
 758         /*
 759          * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
 760          * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
 761          *
 762          * calc_ecc is a 104 bit information containing maximum of 8 error
 763          * offset informations of 13 bits each. calc_ecc is copied into a
 764          * uint64_t array and error offset indexes are populated in err_idx
 765          * array
 766          */
 767         ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
 768         ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
 769         ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
 770         ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
 771
 772         err_idx[0] = (ecc1 >> 0) & 0x1FFF;
 773         err_idx[1] = (ecc1 >> 13) & 0x1FFF;
 774         err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
 775         err_idx[3] = (ecc2 >> 7) & 0x1FFF;
 776         err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
 777         err_idx[5] = (ecc3 >> 1) & 0x1FFF;
 778         err_idx[6] = (ecc3 >> 14) & 0x1FFF;
 779         err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
 780
 781         i = 0;
 782         while (num_err--) {
 783                 change_bit(0, (unsigned long *)&err_idx[i]);
 784                 change_bit(1, (unsigned long *)&err_idx[i]);
 785
 786                 if (err_idx[i] < chip->ecc.size * 8) {
 787                         change_bit(err_idx[i], (unsigned long *)dat);
 788                         i++;
 789                 }
 790         }
 791         return i;
 792 }
 793
 794 static bool filter(struct dma_chan *chan, void *slave)
 795 {
 796         chan->private = slave;
 797         return true;
 798 }
 799
 800 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
 801                                      struct device_node *np)
 802 {
 803         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 804         u32 val;
 805         int ret;
 806
 807         pdata->options = 0;
 808
 809         if (!of_property_read_u32(np, "bank-width", &val)) {
 810                 if (val == 2) {
 811                         pdata->options |= NAND_BUSWIDTH_16;
 812                 } else if (val != 1) {
 813                         dev_err(&pdev->dev, "invalid bank-width %u\n", val);
 814                         return -EINVAL;
 815                 }
 816         }
 817
 818         if (of_get_property(np, "nand-skip-bbtscan", NULL))
 819                 pdata->options |= NAND_SKIP_BBTSCAN;
 820
 821         pdata->nand_timings = devm_kzalloc(&pdev->dev,
 822                                 sizeof(*pdata->nand_timings), GFP_KERNEL);
 823         if (!pdata->nand_timings)
 824                 return -ENOMEM;
 825         ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
 826                                                 sizeof(*pdata->nand_timings));
 827         if (ret) {
 828                 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
 829                 pdata->nand_timings = NULL;
 830         }
 831
 832         /* Set default NAND bank to 0 */
 833         pdata->bank = 0;
 834         if (!of_property_read_u32(np, "bank", &val)) {
 835                 if (val > 3) {
 836                         dev_err(&pdev->dev, "invalid bank %u\n", val);
 837                         return -EINVAL;
 838                 }
 839                 pdata->bank = val;
 840         }
 841         return 0;
 842 }
 843
 844 /*
 845  * fsmc_nand_probe - Probe function
 846  * @pdev:       platform device structure
 847  */
 848 static int __init fsmc_nand_probe(struct platform_device *pdev)
 849 {
 850         struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
 851         struct device_node __maybe_unused *np = pdev->dev.of_node;
 852         struct fsmc_nand_data *host;
 853         struct mtd_info *mtd;
 854         struct nand_chip *nand;
 855         struct resource *res;
 856         dma_cap_mask_t mask;
 857         int ret = 0;
 858         u32 pid;
 859         int i;
 860
 861         pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
 862         if (!pdata)
 863                 return -ENOMEM;
 864
 865         pdev->dev.platform_data = pdata;
 866         ret = fsmc_nand_probe_config_dt(pdev, np);
 867         if (ret) {
 868                 dev_err(&pdev->dev, "no platform data\n");
 869                 return -ENODEV;
 870         }
 871
 872         /* Allocate memory for the device structure (and zero it) */
 873         host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
 874         if (!host)
 875                 return -ENOMEM;
 876
 877         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
 878         host->data_va = devm_ioremap_resource(&pdev->dev, res);
 879         if (IS_ERR(host->data_va))
 880                 return PTR_ERR(host->data_va);
 881
 882         host->data_pa = (dma_addr_t)res->start;
 883
 884         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
 885         host->addr_va = devm_ioremap_resource(&pdev->dev, res);
 886         if (IS_ERR(host->addr_va))
 887                 return PTR_ERR(host->addr_va);
 888
 889         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
 890         host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
 891         if (IS_ERR(host->cmd_va))
 892                 return PTR_ERR(host->cmd_va);
 893
 894         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
 895         host->regs_va = devm_ioremap_resource(&pdev->dev, res);
 896         if (IS_ERR(host->regs_va))
 897                 return PTR_ERR(host->regs_va);
 898
 899         host->clk = clk_get(&pdev->dev, NULL);
 900         if (IS_ERR(host->clk)) {
 901                 dev_err(&pdev->dev, "failed to fetch block clock\n");
 902                 return PTR_ERR(host->clk);
 903         }
 904
 905         ret = clk_prepare_enable(host->clk);
 906         if (ret)
 907                 goto err_clk_prepare_enable;
 908
 909         /*
 910          * This device ID is actually a common AMBA ID as used on the
 911          * AMBA PrimeCell bus. However it is not a PrimeCell.
 912          */
 913         for (pid = 0, i = 0; i < 4; i++)
 914                 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
 915         host->pid = pid;
 916         dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
 917                  "revision %02x, config %02x\n",
 918                  AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
 919                  AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
 920
 921         host->bank = pdata->bank;
 922         host->dev = &pdev->dev;
 923         host->dev_timings = pdata->nand_timings;
 924         host->mode = pdata->mode;
 925
 926         if (host->mode == USE_DMA_ACCESS)
 927                 init_completion(&host->dma_access_complete);
 928
 929         /* Link all private pointers */
 930         mtd = nand_to_mtd(&host->nand);
 931         nand = &host->nand;
 932         nand_set_controller_data(nand, host);
 933         nand_set_flash_node(nand, np);
 934
 935         mtd->dev.parent = &pdev->dev;
 936         nand->IO_ADDR_R = host->data_va;
 937         nand->IO_ADDR_W = host->data_va;
 938         nand->cmd_ctrl = fsmc_cmd_ctrl;
 939         nand->chip_delay = 30;
 940
 941         /*
 942          * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
 943          * can overwrite this value if the DT provides a different value.
 944          */
 945         nand->ecc.mode = NAND_ECC_HW;
 946         nand->ecc.hwctl = fsmc_enable_hwecc;
 947         nand->ecc.size = 512;
 948         nand->options = pdata->options;
 949         nand->badblockbits = 7;
 950         nand_set_flash_node(nand, np);
 951
 952         switch (host->mode) {
 953         case USE_DMA_ACCESS:
 954                 dma_cap_zero(mask);
 955                 dma_cap_set(DMA_MEMCPY, mask);
 956                 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
 957                 if (!host->read_dma_chan) {
 958                         dev_err(&pdev->dev, "Unable to get read dma channel\n");
 959                         goto err_req_read_chnl;
 960                 }
 961                 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
 962                 if (!host->write_dma_chan) {
 963                         dev_err(&pdev->dev, "Unable to get write dma channel\n");
 964                         goto err_req_write_chnl;
 965                 }
 966                 nand->read_buf = fsmc_read_buf_dma;
 967                 nand->write_buf = fsmc_write_buf_dma;
 968                 break;
 969
 970         default:
 971         case USE_WORD_ACCESS:
 972                 nand->read_buf = fsmc_read_buf;
 973                 nand->write_buf = fsmc_write_buf;
 974                 break;
 975         }
 976
 977         fsmc_nand_setup(host->regs_va, host->bank,
 978                         nand->options & NAND_BUSWIDTH_16,
 979                         host->dev_timings);
 980
 981         if (AMBA_REV_BITS(host->pid) >= 8) {
 982                 nand->ecc.read_page = fsmc_read_page_hwecc;
 983                 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
 984                 nand->ecc.correct = fsmc_bch8_correct_data;
 985                 nand->ecc.bytes = 13;
 986                 nand->ecc.strength = 8;
 987         }
 988
 989         /*
 990          * Scan to find existence of the device
 991          */
 992         ret = nand_scan_ident(mtd, 1, NULL);
 993         if (ret) {
 994                 dev_err(&pdev->dev, "No NAND Device found!\n");
 995                 goto err_scan_ident;
 996         }
 997
 998         if (AMBA_REV_BITS(host->pid) >= 8) {
 999                 switch (mtd->oobsize) {
1000                 case 16:
1001                 case 64:
1002                 case 128:
1003                 case 224:
1004                 case 256:
1005                         break;
1006                 default:
1007                         dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1008                                  mtd->oobsize);
1009                         ret = -EINVAL;
1010                         goto err_probe;
1011                 }
1012
1013                 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1014         } else {
1015                 switch (nand->ecc.mode) {
1016                 case NAND_ECC_HW:
1017                         dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1018                         nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1019                         nand->ecc.correct = nand_correct_data;
1020                         nand->ecc.bytes = 3;
1021                         nand->ecc.strength = 1;
1022                         break;
1023
1024                 case NAND_ECC_SOFT:
1025                         if (nand->ecc.algo == NAND_ECC_BCH) {
1026                                 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1027                                 break;
1028                         }
1029
1030                 default:
1031                         dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1032                         goto err_probe;
1033                 }
1034
1035                 /*
1036                  * Don't set layout for BCH4 SW ECC. This will be
1037                  * generated later in nand_bch_init() later.
1038                  */
1039                 if (nand->ecc.mode == NAND_ECC_HW) {
1040                         switch (mtd->oobsize) {
1041                         case 16:
1042                         case 64:
1043                         case 128:
1044                                 mtd_set_ooblayout(mtd,
1045                                                   &fsmc_ecc1_ooblayout_ops);
1046                                 break;
1047                         default:
1048                                 dev_warn(&pdev->dev,
1049                                          "No oob scheme defined for oobsize %d\n",
1050                                          mtd->oobsize);
1051                                 ret = -EINVAL;
1052                                 goto err_probe;
1053                         }
1054                 }
1055         }
1056
1057         /* Second stage of scan to fill MTD data-structures */
1058         ret = nand_scan_tail(mtd);
1059         if (ret)
1060                 goto err_probe;
1061
1062         mtd->name = "nand";
1063         ret = mtd_device_register(mtd, NULL, 0);
1064         if (ret)
1065                 goto err_probe;
1066
1067         platform_set_drvdata(pdev, host);
1068         dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1069         return 0;
1070
1071 err_probe:
1072 err_scan_ident:
1073         if (host->mode == USE_DMA_ACCESS)
1074                 dma_release_channel(host->write_dma_chan);
1075 err_req_write_chnl:
1076         if (host->mode == USE_DMA_ACCESS)
1077                 dma_release_channel(host->read_dma_chan);
1078 err_req_read_chnl:
1079         clk_disable_unprepare(host->clk);
1080 err_clk_prepare_enable:
1081         clk_put(host->clk);
1082         return ret;
1083 }
1084
1085 /*
1086  * Clean up routine
1087  */
1088 static int fsmc_nand_remove(struct platform_device *pdev)
1089 {
1090         struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1091
1092         if (host) {
1093                 nand_release(nand_to_mtd(&host->nand));
1094
1095                 if (host->mode == USE_DMA_ACCESS) {
1096                         dma_release_channel(host->write_dma_chan);
1097                         dma_release_channel(host->read_dma_chan);
1098                 }
1099                 clk_disable_unprepare(host->clk);
1100                 clk_put(host->clk);
1101         }
1102
1103         return 0;
1104 }
1105
1106 #ifdef CONFIG_PM_SLEEP
1107 static int fsmc_nand_suspend(struct device *dev)
1108 {
1109         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1110         if (host)
1111                 clk_disable_unprepare(host->clk);
1112         return 0;
1113 }
1114
1115 static int fsmc_nand_resume(struct device *dev)
1116 {
1117         struct fsmc_nand_data *host = dev_get_drvdata(dev);
1118         if (host) {
1119                 clk_prepare_enable(host->clk);
1120                 fsmc_nand_setup(host->regs_va, host->bank,
1121                                 host->nand.options & NAND_BUSWIDTH_16,
1122                                 host->dev_timings);
1123         }
1124         return 0;
1125 }
1126 #endif
1127
1128 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1129
1130 #ifdef CONFIG_OF
1131 static const struct of_device_id fsmc_nand_id_table[] = {
1132         { .compatible = "st,spear600-fsmc-nand" },
1133         { .compatible = "stericsson,fsmc-nand" },
1134         {}
1135 };
1136 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1137 #endif
1138
1139 static struct platform_driver fsmc_nand_driver = {
1140         .remove = fsmc_nand_remove,
1141         .driver = {
1142                 .name = "fsmc-nand",
1143                 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1144                 .pm = &fsmc_nand_pm_ops,
1145         },
1146 };
1147
1148 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1149
1150 MODULE_LICENSE("GPL");
1151 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1152 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");