2 * drivers/mtd/nand/fsmc_nand.c
5 * Flexible Static Memory Controller (FSMC)
6 * Driver for NAND portions
8 * Copyright © 2010 ST Microelectronics
9 * Vipin Kumar <vipin.kumar@st.com>
12 * Based on drivers/mtd/nand/nomadik_nand.c
14 * This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/dmaengine.h>
22 #include <linux/dma-direction.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/err.h>
25 #include <linux/init.h>
26 #include <linux/module.h>
27 #include <linux/resource.h>
28 #include <linux/sched.h>
29 #include <linux/types.h>
30 #include <linux/mtd/mtd.h>
31 #include <linux/mtd/nand.h>
32 #include <linux/mtd/nand_ecc.h>
33 #include <linux/platform_device.h>
35 #include <linux/mtd/partitions.h>
37 #include <linux/slab.h>
38 #include <linux/amba/bus.h>
39 #include <mtd/mtd-abi.h>
41 #define FSMC_NAND_BW8 1
42 #define FSMC_NAND_BW16 2
44 #define FSMC_MAX_NOR_BANKS 4
45 #define FSMC_MAX_NAND_BANKS 4
47 #define FSMC_FLASH_WIDTH8 1
48 #define FSMC_FLASH_WIDTH16 2
50 /* fsmc controller registers for NOR flash */
52 /* ctrl register definitions */
53 #define BANK_ENABLE (1 << 0)
54 #define MUXED (1 << 1)
55 #define NOR_DEV (2 << 2)
56 #define WIDTH_8 (0 << 4)
57 #define WIDTH_16 (1 << 4)
58 #define RSTPWRDWN (1 << 6)
59 #define WPROT (1 << 7)
60 #define WRT_ENABLE (1 << 12)
61 #define WAIT_ENB (1 << 13)
64 /* ctrl_tim register definitions */
66 #define FSMC_NOR_BANK_SZ 0x8
67 #define FSMC_NOR_REG_SIZE 0x40
69 #define FSMC_NOR_REG(base, bank, reg) (base + \
70 FSMC_NOR_BANK_SZ * (bank) + \
73 /* fsmc controller registers for NAND flash */
75 /* pc register definitions */
76 #define FSMC_RESET (1 << 0)
77 #define FSMC_WAITON (1 << 1)
78 #define FSMC_ENABLE (1 << 2)
79 #define FSMC_DEVTYPE_NAND (1 << 3)
80 #define FSMC_DEVWID_8 (0 << 4)
81 #define FSMC_DEVWID_16 (1 << 4)
82 #define FSMC_ECCEN (1 << 6)
83 #define FSMC_ECCPLEN_512 (0 << 7)
84 #define FSMC_ECCPLEN_256 (1 << 7)
85 #define FSMC_TCLR_1 (1)
86 #define FSMC_TCLR_SHIFT (9)
87 #define FSMC_TCLR_MASK (0xF)
88 #define FSMC_TAR_1 (1)
89 #define FSMC_TAR_SHIFT (13)
90 #define FSMC_TAR_MASK (0xF)
92 /* sts register definitions */
93 #define FSMC_CODE_RDY (1 << 15)
95 /* comm register definitions */
97 #define FSMC_TSET_SHIFT 0
98 #define FSMC_TSET_MASK 0xFF
99 #define FSMC_TWAIT_6 6
100 #define FSMC_TWAIT_SHIFT 8
101 #define FSMC_TWAIT_MASK 0xFF
102 #define FSMC_THOLD_4 4
103 #define FSMC_THOLD_SHIFT 16
104 #define FSMC_THOLD_MASK 0xFF
105 #define FSMC_THIZ_1 1
106 #define FSMC_THIZ_SHIFT 24
107 #define FSMC_THIZ_MASK 0xFF
113 #define FSMC_NAND_BANK_SZ 0x20
115 #define FSMC_NAND_REG(base, bank, reg) (base + FSMC_NOR_REG_SIZE + \
116 (FSMC_NAND_BANK_SZ * (bank)) + \
119 #define FSMC_BUSY_WAIT_TIMEOUT (1 * HZ)
121 struct fsmc_nand_timings {
136 * fsmc_nand_platform_data - platform specific NAND controller config
137 * @nand_timings: timing setup for the physical NAND interface
138 * @partitions: partition table for the platform, use a default fallback
140 * @nr_partitions: the number of partitions in the previous entry
141 * @options: different options for the driver
143 * @bank: default bank
144 * platform-specific. If the controller only supports one bank
145 * this may be set to NULL
147 struct fsmc_nand_platform_data {
148 struct fsmc_nand_timings *nand_timings;
149 unsigned int options;
152 enum access_mode mode;
156 * struct fsmc_nand_data - structure for FSMC NAND device state
158 * @pid: Part ID on the AMBA PrimeCell format
159 * @mtd: MTD info for a NAND flash.
160 * @nand: Chip related info for a NAND flash.
161 * @partitions: Partition info for a NAND Flash.
162 * @nr_partitions: Total number of partition of a NAND flash.
164 * @bank: Bank number for probed device.
165 * @clk: Clock structure for FSMC.
167 * @read_dma_chan: DMA channel for read access
168 * @write_dma_chan: DMA channel for write access to NAND
169 * @dma_access_complete: Completion structure
171 * @data_pa: NAND Physical port for Data.
172 * @data_va: NAND port for Data.
173 * @cmd_va: NAND port for Command.
174 * @addr_va: NAND port for Address.
175 * @regs_va: FSMC regs base address.
177 struct fsmc_nand_data {
179 struct nand_chip nand;
183 enum access_mode mode;
186 /* DMA related objects */
187 struct dma_chan *read_dma_chan;
188 struct dma_chan *write_dma_chan;
189 struct completion dma_access_complete;
191 struct fsmc_nand_timings *dev_timings;
194 void __iomem *data_va;
195 void __iomem *cmd_va;
196 void __iomem *addr_va;
197 void __iomem *regs_va;
200 static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section,
201 struct mtd_oob_region *oobregion)
203 struct nand_chip *chip = mtd_to_nand(mtd);
205 if (section >= chip->ecc.steps)
208 oobregion->offset = (section * 16) + 2;
209 oobregion->length = 3;
214 static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section,
215 struct mtd_oob_region *oobregion)
217 struct nand_chip *chip = mtd_to_nand(mtd);
219 if (section >= chip->ecc.steps)
222 oobregion->offset = (section * 16) + 8;
224 if (section < chip->ecc.steps - 1)
225 oobregion->length = 8;
227 oobregion->length = mtd->oobsize - oobregion->offset;
232 static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = {
233 .ecc = fsmc_ecc1_ooblayout_ecc,
234 .free = fsmc_ecc1_ooblayout_free,
238 * ECC placement definitions in oobfree type format.
239 * There are 13 bytes of ecc for every 512 byte block and it has to be read
240 * consecutively and immediately after the 512 byte data block for hardware to
241 * generate the error bit offsets in 512 byte data.
243 static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section,
244 struct mtd_oob_region *oobregion)
246 struct nand_chip *chip = mtd_to_nand(mtd);
248 if (section >= chip->ecc.steps)
251 oobregion->length = chip->ecc.bytes;
253 if (!section && mtd->writesize <= 512)
254 oobregion->offset = 0;
256 oobregion->offset = (section * 16) + 2;
261 static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section,
262 struct mtd_oob_region *oobregion)
264 struct nand_chip *chip = mtd_to_nand(mtd);
266 if (section >= chip->ecc.steps)
269 oobregion->offset = (section * 16) + 15;
271 if (section < chip->ecc.steps - 1)
272 oobregion->length = 3;
274 oobregion->length = mtd->oobsize - oobregion->offset;
279 static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = {
280 .ecc = fsmc_ecc4_ooblayout_ecc,
281 .free = fsmc_ecc4_ooblayout_free,
284 static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd)
286 return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand);
290 * fsmc_cmd_ctrl - For facilitaing Hardware access
291 * This routine allows hardware specific access to control-lines(ALE,CLE)
293 static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
295 struct nand_chip *this = mtd_to_nand(mtd);
296 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
297 void __iomem *regs = host->regs_va;
298 unsigned int bank = host->bank;
300 if (ctrl & NAND_CTRL_CHANGE) {
303 if (ctrl & NAND_CLE) {
304 this->IO_ADDR_R = host->cmd_va;
305 this->IO_ADDR_W = host->cmd_va;
306 } else if (ctrl & NAND_ALE) {
307 this->IO_ADDR_R = host->addr_va;
308 this->IO_ADDR_W = host->addr_va;
310 this->IO_ADDR_R = host->data_va;
311 this->IO_ADDR_W = host->data_va;
314 pc = readl(FSMC_NAND_REG(regs, bank, PC));
319 writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC));
324 if (cmd != NAND_CMD_NONE)
325 writeb_relaxed(cmd, this->IO_ADDR_W);
329 * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine
331 * This routine initializes timing parameters related to NAND memory access in
334 static void fsmc_nand_setup(void __iomem *regs, uint32_t bank,
335 uint32_t busw, struct fsmc_nand_timings *timings)
337 uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON;
338 uint32_t tclr, tar, thiz, thold, twait, tset;
339 struct fsmc_nand_timings *tims;
340 struct fsmc_nand_timings default_timings = {
344 .thold = FSMC_THOLD_4,
345 .twait = FSMC_TWAIT_6,
352 tims = &default_timings;
354 tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT;
355 tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT;
356 thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT;
357 thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT;
358 twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT;
359 tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT;
362 writel_relaxed(value | FSMC_DEVWID_16,
363 FSMC_NAND_REG(regs, bank, PC));
365 writel_relaxed(value | FSMC_DEVWID_8,
366 FSMC_NAND_REG(regs, bank, PC));
368 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar,
369 FSMC_NAND_REG(regs, bank, PC));
370 writel_relaxed(thiz | thold | twait | tset,
371 FSMC_NAND_REG(regs, bank, COMM));
372 writel_relaxed(thiz | thold | twait | tset,
373 FSMC_NAND_REG(regs, bank, ATTRIB));
377 * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers
379 static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode)
381 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
382 void __iomem *regs = host->regs_va;
383 uint32_t bank = host->bank;
385 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256,
386 FSMC_NAND_REG(regs, bank, PC));
387 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN,
388 FSMC_NAND_REG(regs, bank, PC));
389 writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN,
390 FSMC_NAND_REG(regs, bank, PC));
394 * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by
395 * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to
398 static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data,
401 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
402 void __iomem *regs = host->regs_va;
403 uint32_t bank = host->bank;
405 unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT;
408 if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY)
412 } while (!time_after_eq(jiffies, deadline));
414 if (time_after_eq(jiffies, deadline)) {
415 dev_err(host->dev, "calculate ecc timed out\n");
419 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
420 ecc[0] = (uint8_t) (ecc_tmp >> 0);
421 ecc[1] = (uint8_t) (ecc_tmp >> 8);
422 ecc[2] = (uint8_t) (ecc_tmp >> 16);
423 ecc[3] = (uint8_t) (ecc_tmp >> 24);
425 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
426 ecc[4] = (uint8_t) (ecc_tmp >> 0);
427 ecc[5] = (uint8_t) (ecc_tmp >> 8);
428 ecc[6] = (uint8_t) (ecc_tmp >> 16);
429 ecc[7] = (uint8_t) (ecc_tmp >> 24);
431 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
432 ecc[8] = (uint8_t) (ecc_tmp >> 0);
433 ecc[9] = (uint8_t) (ecc_tmp >> 8);
434 ecc[10] = (uint8_t) (ecc_tmp >> 16);
435 ecc[11] = (uint8_t) (ecc_tmp >> 24);
437 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
438 ecc[12] = (uint8_t) (ecc_tmp >> 16);
444 * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by
445 * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to
448 static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data,
451 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
452 void __iomem *regs = host->regs_va;
453 uint32_t bank = host->bank;
456 ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
457 ecc[0] = (uint8_t) (ecc_tmp >> 0);
458 ecc[1] = (uint8_t) (ecc_tmp >> 8);
459 ecc[2] = (uint8_t) (ecc_tmp >> 16);
464 /* Count the number of 0's in buff upto a max of max_bits */
465 static int count_written_bits(uint8_t *buff, int size, int max_bits)
467 int k, written_bits = 0;
469 for (k = 0; k < size; k++) {
470 written_bits += hweight8(~buff[k]);
471 if (written_bits > max_bits)
478 static void dma_complete(void *param)
480 struct fsmc_nand_data *host = param;
482 complete(&host->dma_access_complete);
485 static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len,
486 enum dma_data_direction direction)
488 struct dma_chan *chan;
489 struct dma_device *dma_dev;
490 struct dma_async_tx_descriptor *tx;
491 dma_addr_t dma_dst, dma_src, dma_addr;
493 unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT;
495 unsigned long time_left;
497 if (direction == DMA_TO_DEVICE)
498 chan = host->write_dma_chan;
499 else if (direction == DMA_FROM_DEVICE)
500 chan = host->read_dma_chan;
504 dma_dev = chan->device;
505 dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction);
507 if (direction == DMA_TO_DEVICE) {
509 dma_dst = host->data_pa;
511 dma_src = host->data_pa;
515 tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src,
518 dev_err(host->dev, "device_prep_dma_memcpy error\n");
523 tx->callback = dma_complete;
524 tx->callback_param = host;
525 cookie = tx->tx_submit(tx);
527 ret = dma_submit_error(cookie);
529 dev_err(host->dev, "dma_submit_error %d\n", cookie);
533 dma_async_issue_pending(chan);
536 wait_for_completion_timeout(&host->dma_access_complete,
537 msecs_to_jiffies(3000));
538 if (time_left == 0) {
539 dmaengine_terminate_all(chan);
540 dev_err(host->dev, "wait_for_completion_timeout\n");
548 dma_unmap_single(dma_dev->dev, dma_addr, len, direction);
554 * fsmc_write_buf - write buffer to chip
555 * @mtd: MTD device structure
557 * @len: number of bytes to write
559 static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
562 struct nand_chip *chip = mtd_to_nand(mtd);
564 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
565 IS_ALIGNED(len, sizeof(uint32_t))) {
566 uint32_t *p = (uint32_t *)buf;
568 for (i = 0; i < len; i++)
569 writel_relaxed(p[i], chip->IO_ADDR_W);
571 for (i = 0; i < len; i++)
572 writeb_relaxed(buf[i], chip->IO_ADDR_W);
577 * fsmc_read_buf - read chip data into buffer
578 * @mtd: MTD device structure
579 * @buf: buffer to store date
580 * @len: number of bytes to read
582 static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
585 struct nand_chip *chip = mtd_to_nand(mtd);
587 if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) &&
588 IS_ALIGNED(len, sizeof(uint32_t))) {
589 uint32_t *p = (uint32_t *)buf;
591 for (i = 0; i < len; i++)
592 p[i] = readl_relaxed(chip->IO_ADDR_R);
594 for (i = 0; i < len; i++)
595 buf[i] = readb_relaxed(chip->IO_ADDR_R);
600 * fsmc_read_buf_dma - read chip data into buffer
601 * @mtd: MTD device structure
602 * @buf: buffer to store date
603 * @len: number of bytes to read
605 static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len)
607 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
609 dma_xfer(host, buf, len, DMA_FROM_DEVICE);
613 * fsmc_write_buf_dma - write buffer to chip
614 * @mtd: MTD device structure
616 * @len: number of bytes to write
618 static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf,
621 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
623 dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE);
627 * fsmc_read_page_hwecc
628 * @mtd: mtd info structure
629 * @chip: nand chip info structure
630 * @buf: buffer to store read data
631 * @oob_required: caller expects OOB data read to chip->oob_poi
632 * @page: page number to read
634 * This routine is needed for fsmc version 8 as reading from NAND chip has to be
635 * performed in a strict sequence as follows:
636 * data(512 byte) -> ecc(13 byte)
637 * After this read, fsmc hardware generates and reports error data bits(up to a
640 static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
641 uint8_t *buf, int oob_required, int page)
643 int i, j, s, stat, eccsize = chip->ecc.size;
644 int eccbytes = chip->ecc.bytes;
645 int eccsteps = chip->ecc.steps;
647 uint8_t *ecc_calc = chip->buffers->ecccalc;
648 uint8_t *ecc_code = chip->buffers->ecccode;
649 int off, len, group = 0;
651 * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we
652 * end up reading 14 bytes (7 words) from oob. The local array is
653 * to maintain word alignment
656 uint8_t *oob = (uint8_t *)&ecc_oob[0];
657 unsigned int max_bitflips = 0;
659 for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) {
660 chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page);
661 chip->ecc.hwctl(mtd, NAND_ECC_READ);
662 chip->read_buf(mtd, p, eccsize);
664 for (j = 0; j < eccbytes;) {
665 struct mtd_oob_region oobregion;
668 ret = mtd_ooblayout_ecc(mtd, group++, &oobregion);
672 off = oobregion.offset;
673 len = oobregion.length;
676 * length is intentionally kept a higher multiple of 2
677 * to read at least 13 bytes even in case of 16 bit NAND
680 if (chip->options & NAND_BUSWIDTH_16)
681 len = roundup(len, 2);
683 chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page);
684 chip->read_buf(mtd, oob + j, len);
688 memcpy(&ecc_code[i], oob, chip->ecc.bytes);
689 chip->ecc.calculate(mtd, p, &ecc_calc[i]);
691 stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
693 mtd->ecc_stats.failed++;
695 mtd->ecc_stats.corrected += stat;
696 max_bitflips = max_t(unsigned int, max_bitflips, stat);
704 * fsmc_bch8_correct_data
705 * @mtd: mtd info structure
706 * @dat: buffer of read data
707 * @read_ecc: ecc read from device spare area
708 * @calc_ecc: ecc calculated from read data
710 * calc_ecc is a 104 bit information containing maximum of 8 error
711 * offset informations of 13 bits each in 512 bytes of read data.
713 static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat,
714 uint8_t *read_ecc, uint8_t *calc_ecc)
716 struct nand_chip *chip = mtd_to_nand(mtd);
717 struct fsmc_nand_data *host = mtd_to_fsmc(mtd);
718 void __iomem *regs = host->regs_va;
719 unsigned int bank = host->bank;
722 uint32_t ecc1, ecc2, ecc3, ecc4;
724 num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF;
726 /* no bit flipping */
727 if (likely(num_err == 0))
730 /* too many errors */
731 if (unlikely(num_err > 8)) {
733 * This is a temporary erase check. A newly erased page read
734 * would result in an ecc error because the oob data is also
735 * erased to FF and the calculated ecc for an FF data is not
737 * This is a workaround to skip performing correction in case
741 * For every page, each bit written as 0 is counted until these
742 * number of bits are greater than 8 (the maximum correction
743 * capability of FSMC for each 512 + 13 bytes)
746 int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8);
747 int bits_data = count_written_bits(dat, chip->ecc.size, 8);
749 if ((bits_ecc + bits_data) <= 8) {
751 memset(dat, 0xff, chip->ecc.size);
759 * ------------------- calc_ecc[] bit wise -----------|--13 bits--|
760 * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--|
762 * calc_ecc is a 104 bit information containing maximum of 8 error
763 * offset informations of 13 bits each. calc_ecc is copied into a
764 * uint64_t array and error offset indexes are populated in err_idx
767 ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1));
768 ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2));
769 ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3));
770 ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS));
772 err_idx[0] = (ecc1 >> 0) & 0x1FFF;
773 err_idx[1] = (ecc1 >> 13) & 0x1FFF;
774 err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F);
775 err_idx[3] = (ecc2 >> 7) & 0x1FFF;
776 err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF);
777 err_idx[5] = (ecc3 >> 1) & 0x1FFF;
778 err_idx[6] = (ecc3 >> 14) & 0x1FFF;
779 err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F);
783 change_bit(0, (unsigned long *)&err_idx[i]);
784 change_bit(1, (unsigned long *)&err_idx[i]);
786 if (err_idx[i] < chip->ecc.size * 8) {
787 change_bit(err_idx[i], (unsigned long *)dat);
794 static bool filter(struct dma_chan *chan, void *slave)
796 chan->private = slave;
800 static int fsmc_nand_probe_config_dt(struct platform_device *pdev,
801 struct device_node *np)
803 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
809 if (!of_property_read_u32(np, "bank-width", &val)) {
811 pdata->options |= NAND_BUSWIDTH_16;
812 } else if (val != 1) {
813 dev_err(&pdev->dev, "invalid bank-width %u\n", val);
818 if (of_get_property(np, "nand-skip-bbtscan", NULL))
819 pdata->options |= NAND_SKIP_BBTSCAN;
821 pdata->nand_timings = devm_kzalloc(&pdev->dev,
822 sizeof(*pdata->nand_timings), GFP_KERNEL);
823 if (!pdata->nand_timings)
825 ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings,
826 sizeof(*pdata->nand_timings));
828 dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n");
829 pdata->nand_timings = NULL;
832 /* Set default NAND bank to 0 */
834 if (!of_property_read_u32(np, "bank", &val)) {
836 dev_err(&pdev->dev, "invalid bank %u\n", val);
845 * fsmc_nand_probe - Probe function
846 * @pdev: platform device structure
848 static int __init fsmc_nand_probe(struct platform_device *pdev)
850 struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev);
851 struct device_node __maybe_unused *np = pdev->dev.of_node;
852 struct fsmc_nand_data *host;
853 struct mtd_info *mtd;
854 struct nand_chip *nand;
855 struct resource *res;
861 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
865 pdev->dev.platform_data = pdata;
866 ret = fsmc_nand_probe_config_dt(pdev, np);
868 dev_err(&pdev->dev, "no platform data\n");
872 /* Allocate memory for the device structure (and zero it) */
873 host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
877 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
878 host->data_va = devm_ioremap_resource(&pdev->dev, res);
879 if (IS_ERR(host->data_va))
880 return PTR_ERR(host->data_va);
882 host->data_pa = (dma_addr_t)res->start;
884 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
885 host->addr_va = devm_ioremap_resource(&pdev->dev, res);
886 if (IS_ERR(host->addr_va))
887 return PTR_ERR(host->addr_va);
889 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
890 host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
891 if (IS_ERR(host->cmd_va))
892 return PTR_ERR(host->cmd_va);
894 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
895 host->regs_va = devm_ioremap_resource(&pdev->dev, res);
896 if (IS_ERR(host->regs_va))
897 return PTR_ERR(host->regs_va);
899 host->clk = clk_get(&pdev->dev, NULL);
900 if (IS_ERR(host->clk)) {
901 dev_err(&pdev->dev, "failed to fetch block clock\n");
902 return PTR_ERR(host->clk);
905 ret = clk_prepare_enable(host->clk);
907 goto err_clk_prepare_enable;
910 * This device ID is actually a common AMBA ID as used on the
911 * AMBA PrimeCell bus. However it is not a PrimeCell.
913 for (pid = 0, i = 0; i < 4; i++)
914 pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
916 dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, "
917 "revision %02x, config %02x\n",
918 AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid),
919 AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
921 host->bank = pdata->bank;
922 host->dev = &pdev->dev;
923 host->dev_timings = pdata->nand_timings;
924 host->mode = pdata->mode;
926 if (host->mode == USE_DMA_ACCESS)
927 init_completion(&host->dma_access_complete);
929 /* Link all private pointers */
930 mtd = nand_to_mtd(&host->nand);
932 nand_set_controller_data(nand, host);
933 nand_set_flash_node(nand, np);
935 mtd->dev.parent = &pdev->dev;
936 nand->IO_ADDR_R = host->data_va;
937 nand->IO_ADDR_W = host->data_va;
938 nand->cmd_ctrl = fsmc_cmd_ctrl;
939 nand->chip_delay = 30;
942 * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
943 * can overwrite this value if the DT provides a different value.
945 nand->ecc.mode = NAND_ECC_HW;
946 nand->ecc.hwctl = fsmc_enable_hwecc;
947 nand->ecc.size = 512;
948 nand->options = pdata->options;
949 nand->badblockbits = 7;
950 nand_set_flash_node(nand, np);
952 switch (host->mode) {
955 dma_cap_set(DMA_MEMCPY, mask);
956 host->read_dma_chan = dma_request_channel(mask, filter, NULL);
957 if (!host->read_dma_chan) {
958 dev_err(&pdev->dev, "Unable to get read dma channel\n");
959 goto err_req_read_chnl;
961 host->write_dma_chan = dma_request_channel(mask, filter, NULL);
962 if (!host->write_dma_chan) {
963 dev_err(&pdev->dev, "Unable to get write dma channel\n");
964 goto err_req_write_chnl;
966 nand->read_buf = fsmc_read_buf_dma;
967 nand->write_buf = fsmc_write_buf_dma;
971 case USE_WORD_ACCESS:
972 nand->read_buf = fsmc_read_buf;
973 nand->write_buf = fsmc_write_buf;
977 fsmc_nand_setup(host->regs_va, host->bank,
978 nand->options & NAND_BUSWIDTH_16,
981 if (AMBA_REV_BITS(host->pid) >= 8) {
982 nand->ecc.read_page = fsmc_read_page_hwecc;
983 nand->ecc.calculate = fsmc_read_hwecc_ecc4;
984 nand->ecc.correct = fsmc_bch8_correct_data;
985 nand->ecc.bytes = 13;
986 nand->ecc.strength = 8;
990 * Scan to find existence of the device
992 ret = nand_scan_ident(mtd, 1, NULL);
994 dev_err(&pdev->dev, "No NAND Device found!\n");
998 if (AMBA_REV_BITS(host->pid) >= 8) {
999 switch (mtd->oobsize) {
1007 dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n",
1013 mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops);
1015 switch (nand->ecc.mode) {
1017 dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n");
1018 nand->ecc.calculate = fsmc_read_hwecc_ecc1;
1019 nand->ecc.correct = nand_correct_data;
1020 nand->ecc.bytes = 3;
1021 nand->ecc.strength = 1;
1025 if (nand->ecc.algo == NAND_ECC_BCH) {
1026 dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n");
1031 dev_err(&pdev->dev, "Unsupported ECC mode!\n");
1036 * Don't set layout for BCH4 SW ECC. This will be
1037 * generated later in nand_bch_init() later.
1039 if (nand->ecc.mode == NAND_ECC_HW) {
1040 switch (mtd->oobsize) {
1044 mtd_set_ooblayout(mtd,
1045 &fsmc_ecc1_ooblayout_ops);
1048 dev_warn(&pdev->dev,
1049 "No oob scheme defined for oobsize %d\n",
1057 /* Second stage of scan to fill MTD data-structures */
1058 ret = nand_scan_tail(mtd);
1063 ret = mtd_device_register(mtd, NULL, 0);
1067 platform_set_drvdata(pdev, host);
1068 dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
1073 if (host->mode == USE_DMA_ACCESS)
1074 dma_release_channel(host->write_dma_chan);
1076 if (host->mode == USE_DMA_ACCESS)
1077 dma_release_channel(host->read_dma_chan);
1079 clk_disable_unprepare(host->clk);
1080 err_clk_prepare_enable:
1088 static int fsmc_nand_remove(struct platform_device *pdev)
1090 struct fsmc_nand_data *host = platform_get_drvdata(pdev);
1093 nand_release(nand_to_mtd(&host->nand));
1095 if (host->mode == USE_DMA_ACCESS) {
1096 dma_release_channel(host->write_dma_chan);
1097 dma_release_channel(host->read_dma_chan);
1099 clk_disable_unprepare(host->clk);
1106 #ifdef CONFIG_PM_SLEEP
1107 static int fsmc_nand_suspend(struct device *dev)
1109 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1111 clk_disable_unprepare(host->clk);
1115 static int fsmc_nand_resume(struct device *dev)
1117 struct fsmc_nand_data *host = dev_get_drvdata(dev);
1119 clk_prepare_enable(host->clk);
1120 fsmc_nand_setup(host->regs_va, host->bank,
1121 host->nand.options & NAND_BUSWIDTH_16,
1128 static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume);
1131 static const struct of_device_id fsmc_nand_id_table[] = {
1132 { .compatible = "st,spear600-fsmc-nand" },
1133 { .compatible = "stericsson,fsmc-nand" },
1136 MODULE_DEVICE_TABLE(of, fsmc_nand_id_table);
1139 static struct platform_driver fsmc_nand_driver = {
1140 .remove = fsmc_nand_remove,
1142 .name = "fsmc-nand",
1143 .of_match_table = of_match_ptr(fsmc_nand_id_table),
1144 .pm = &fsmc_nand_pm_ops,
1148 module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe);
1150 MODULE_LICENSE("GPL");
1151 MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi");
1152 MODULE_DESCRIPTION("NAND driver for SPEAr Platforms");