drivers/mtd/nand/mxc_nand.c

   1 /*
   2  * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   3  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/delay.h>
  21 #include <linux/slab.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/mtd/mtd.h>
  25 #include <linux/mtd/nand.h>
  26 #include <linux/mtd/partitions.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/device.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/clk.h>
  31 #include <linux/err.h>
  32 #include <linux/io.h>
  33 #include <linux/irq.h>
  34 #include <linux/completion.h>
  35 #include <linux/of.h>
  36 #include <linux/of_device.h>
  37
  38 #include <asm/mach/flash.h>
  39 #include <linux/platform_data/mtd-mxc_nand.h>
  40
  41 #define DRIVER_NAME "mxc_nand"
  42
  43 /* Addresses for NFC registers */
  44 #define NFC_V1_V2_BUF_SIZE              (host->regs + 0x00)
  45 #define NFC_V1_V2_BUF_ADDR              (host->regs + 0x04)
  46 #define NFC_V1_V2_FLASH_ADDR            (host->regs + 0x06)
  47 #define NFC_V1_V2_FLASH_CMD             (host->regs + 0x08)
  48 #define NFC_V1_V2_CONFIG                (host->regs + 0x0a)
  49 #define NFC_V1_V2_ECC_STATUS_RESULT     (host->regs + 0x0c)
  50 #define NFC_V1_V2_RSLTMAIN_AREA         (host->regs + 0x0e)
  51 #define NFC_V1_V2_RSLTSPARE_AREA        (host->regs + 0x10)
  52 #define NFC_V1_V2_WRPROT                (host->regs + 0x12)
  53 #define NFC_V1_UNLOCKSTART_BLKADDR      (host->regs + 0x14)
  54 #define NFC_V1_UNLOCKEND_BLKADDR        (host->regs + 0x16)
  55 #define NFC_V21_UNLOCKSTART_BLKADDR0    (host->regs + 0x20)
  56 #define NFC_V21_UNLOCKSTART_BLKADDR1    (host->regs + 0x24)
  57 #define NFC_V21_UNLOCKSTART_BLKADDR2    (host->regs + 0x28)
  58 #define NFC_V21_UNLOCKSTART_BLKADDR3    (host->regs + 0x2c)
  59 #define NFC_V21_UNLOCKEND_BLKADDR0      (host->regs + 0x22)
  60 #define NFC_V21_UNLOCKEND_BLKADDR1      (host->regs + 0x26)
  61 #define NFC_V21_UNLOCKEND_BLKADDR2      (host->regs + 0x2a)
  62 #define NFC_V21_UNLOCKEND_BLKADDR3      (host->regs + 0x2e)
  63 #define NFC_V1_V2_NF_WRPRST             (host->regs + 0x18)
  64 #define NFC_V1_V2_CONFIG1               (host->regs + 0x1a)
  65 #define NFC_V1_V2_CONFIG2               (host->regs + 0x1c)
  66
  67 #define NFC_V2_CONFIG1_ECC_MODE_4       (1 << 0)
  68 #define NFC_V1_V2_CONFIG1_SP_EN         (1 << 2)
  69 #define NFC_V1_V2_CONFIG1_ECC_EN        (1 << 3)
  70 #define NFC_V1_V2_CONFIG1_INT_MSK       (1 << 4)
  71 #define NFC_V1_V2_CONFIG1_BIG           (1 << 5)
  72 #define NFC_V1_V2_CONFIG1_RST           (1 << 6)
  73 #define NFC_V1_V2_CONFIG1_CE            (1 << 7)
  74 #define NFC_V2_CONFIG1_ONE_CYCLE        (1 << 8)
  75 #define NFC_V2_CONFIG1_PPB(x)           (((x) & 0x3) << 9)
  76 #define NFC_V2_CONFIG1_FP_INT           (1 << 11)
  77
  78 #define NFC_V1_V2_CONFIG2_INT           (1 << 15)
  79
  80 /*
  81  * Operation modes for the NFC. Valid for v1, v2 and v3
  82  * type controllers.
  83  */
  84 #define NFC_CMD                         (1 << 0)
  85 #define NFC_ADDR                        (1 << 1)
  86 #define NFC_INPUT                       (1 << 2)
  87 #define NFC_OUTPUT                      (1 << 3)
  88 #define NFC_ID                          (1 << 4)
  89 #define NFC_STATUS                      (1 << 5)
  90
  91 #define NFC_V3_FLASH_CMD                (host->regs_axi + 0x00)
  92 #define NFC_V3_FLASH_ADDR0              (host->regs_axi + 0x04)
  93
  94 #define NFC_V3_CONFIG1                  (host->regs_axi + 0x34)
  95 #define NFC_V3_CONFIG1_SP_EN            (1 << 0)
  96 #define NFC_V3_CONFIG1_RBA(x)           (((x) & 0x7 ) << 4)
  97
  98 #define NFC_V3_ECC_STATUS_RESULT        (host->regs_axi + 0x38)
  99
 100 #define NFC_V3_LAUNCH                   (host->regs_axi + 0x40)
 101
 102 #define NFC_V3_WRPROT                   (host->regs_ip + 0x0)
 103 #define NFC_V3_WRPROT_LOCK_TIGHT        (1 << 0)
 104 #define NFC_V3_WRPROT_LOCK              (1 << 1)
 105 #define NFC_V3_WRPROT_UNLOCK            (1 << 2)
 106 #define NFC_V3_WRPROT_BLS_UNLOCK        (2 << 6)
 107
 108 #define NFC_V3_WRPROT_UNLOCK_BLK_ADD0   (host->regs_ip + 0x04)
 109
 110 #define NFC_V3_CONFIG2                  (host->regs_ip + 0x24)
 111 #define NFC_V3_CONFIG2_PS_512                   (0 << 0)
 112 #define NFC_V3_CONFIG2_PS_2048                  (1 << 0)
 113 #define NFC_V3_CONFIG2_PS_4096                  (2 << 0)
 114 #define NFC_V3_CONFIG2_ONE_CYCLE                (1 << 2)
 115 #define NFC_V3_CONFIG2_ECC_EN                   (1 << 3)
 116 #define NFC_V3_CONFIG2_2CMD_PHASES              (1 << 4)
 117 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE0          (1 << 5)
 118 #define NFC_V3_CONFIG2_ECC_MODE_8               (1 << 6)
 119 #define NFC_V3_CONFIG2_PPB(x, shift)            (((x) & 0x3) << shift)
 120 #define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x)       (((x) & 0x3) << 12)
 121 #define NFC_V3_CONFIG2_INT_MSK                  (1 << 15)
 122 #define NFC_V3_CONFIG2_ST_CMD(x)                (((x) & 0xff) << 24)
 123 #define NFC_V3_CONFIG2_SPAS(x)                  (((x) & 0xff) << 16)
 124
 125 #define NFC_V3_CONFIG3                          (host->regs_ip + 0x28)
 126 #define NFC_V3_CONFIG3_ADD_OP(x)                (((x) & 0x3) << 0)
 127 #define NFC_V3_CONFIG3_FW8                      (1 << 3)
 128 #define NFC_V3_CONFIG3_SBB(x)                   (((x) & 0x7) << 8)
 129 #define NFC_V3_CONFIG3_NUM_OF_DEVICES(x)        (((x) & 0x7) << 12)
 130 #define NFC_V3_CONFIG3_RBB_MODE                 (1 << 15)
 131 #define NFC_V3_CONFIG3_NO_SDMA                  (1 << 20)
 132
 133 #define NFC_V3_IPC                      (host->regs_ip + 0x2C)
 134 #define NFC_V3_IPC_CREQ                 (1 << 0)
 135 #define NFC_V3_IPC_INT                  (1 << 31)
 136
 137 #define NFC_V3_DELAY_LINE               (host->regs_ip + 0x34)
 138
 139 struct mxc_nand_host;
 140
 141 struct mxc_nand_devtype_data {
 142         void (*preset)(struct mtd_info *);
 143         void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
 144         void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
 145         void (*send_page)(struct mtd_info *, unsigned int);
 146         void (*send_read_id)(struct mxc_nand_host *);
 147         uint16_t (*get_dev_status)(struct mxc_nand_host *);
 148         int (*check_int)(struct mxc_nand_host *);
 149         void (*irq_control)(struct mxc_nand_host *, int);
 150         u32 (*get_ecc_status)(struct mxc_nand_host *);
 151         const struct mtd_ooblayout_ops *ooblayout;
 152         void (*select_chip)(struct mtd_info *mtd, int chip);
 153         int (*correct_data)(struct mtd_info *mtd, u_char *dat,
 154                         u_char *read_ecc, u_char *calc_ecc);
 155         int (*setup_data_interface)(struct mtd_info *mtd,
 156                                     const struct nand_data_interface *conf,
 157                                     bool check_only);
 158
 159         /*
 160          * On i.MX21 the CONFIG2:INT bit cannot be read if interrupts are masked
 161          * (CONFIG1:INT_MSK is set). To handle this the driver uses
 162          * enable_irq/disable_irq_nosync instead of CONFIG1:INT_MSK
 163          */
 164         int irqpending_quirk;
 165         int needs_ip;
 166
 167         size_t regs_offset;
 168         size_t spare0_offset;
 169         size_t axi_offset;
 170
 171         int spare_len;
 172         int eccbytes;
 173         int eccsize;
 174         int ppb_shift;
 175 };
 176
 177 struct mxc_nand_host {
 178         struct nand_chip        nand;
 179         struct device           *dev;
 180
 181         void __iomem            *spare0;
 182         void __iomem            *main_area0;
 183
 184         void __iomem            *base;
 185         void __iomem            *regs;
 186         void __iomem            *regs_axi;
 187         void __iomem            *regs_ip;
 188         int                     status_request;
 189         struct clk              *clk;
 190         int                     clk_act;
 191         int                     irq;
 192         int                     eccsize;
 193         int                     used_oobsize;
 194         int                     active_cs;
 195
 196         struct completion       op_completion;
 197
 198         uint8_t                 *data_buf;
 199         unsigned int            buf_start;
 200
 201         const struct mxc_nand_devtype_data *devtype_data;
 202         struct mxc_nand_platform_data pdata;
 203 };
 204
 205 static const char * const part_probes[] = {
 206         "cmdlinepart", "RedBoot", "ofpart", NULL };
 207
 208 static void memcpy32_fromio(void *trg, const void __iomem  *src, size_t size)
 209 {
 210         int i;
 211         u32 *t = trg;
 212         const __iomem u32 *s = src;
 213
 214         for (i = 0; i < (size >> 2); i++)
 215                 *t++ = __raw_readl(s++);
 216 }
 217
 218 static void memcpy16_fromio(void *trg, const void __iomem  *src, size_t size)
 219 {
 220         int i;
 221         u16 *t = trg;
 222         const __iomem u16 *s = src;
 223
 224         /* We assume that src (IO) is always 32bit aligned */
 225         if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
 226                 memcpy32_fromio(trg, src, size);
 227                 return;
 228         }
 229
 230         for (i = 0; i < (size >> 1); i++)
 231                 *t++ = __raw_readw(s++);
 232 }
 233
 234 static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
 235 {
 236         /* __iowrite32_copy use 32bit size values so divide by 4 */
 237         __iowrite32_copy(trg, src, size / 4);
 238 }
 239
 240 static void memcpy16_toio(void __iomem *trg, const void *src, int size)
 241 {
 242         int i;
 243         __iomem u16 *t = trg;
 244         const u16 *s = src;
 245
 246         /* We assume that trg (IO) is always 32bit aligned */
 247         if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
 248                 memcpy32_toio(trg, src, size);
 249                 return;
 250         }
 251
 252         for (i = 0; i < (size >> 1); i++)
 253                 __raw_writew(*s++, t++);
 254 }
 255
 256 static int check_int_v3(struct mxc_nand_host *host)
 257 {
 258         uint32_t tmp;
 259
 260         tmp = readl(NFC_V3_IPC);
 261         if (!(tmp & NFC_V3_IPC_INT))
 262                 return 0;
 263
 264         tmp &= ~NFC_V3_IPC_INT;
 265         writel(tmp, NFC_V3_IPC);
 266
 267         return 1;
 268 }
 269
 270 static int check_int_v1_v2(struct mxc_nand_host *host)
 271 {
 272         uint32_t tmp;
 273
 274         tmp = readw(NFC_V1_V2_CONFIG2);
 275         if (!(tmp & NFC_V1_V2_CONFIG2_INT))
 276                 return 0;
 277
 278         if (!host->devtype_data->irqpending_quirk)
 279                 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
 280
 281         return 1;
 282 }
 283
 284 static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
 285 {
 286         uint16_t tmp;
 287
 288         tmp = readw(NFC_V1_V2_CONFIG1);
 289
 290         if (activate)
 291                 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
 292         else
 293                 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
 294
 295         writew(tmp, NFC_V1_V2_CONFIG1);
 296 }
 297
 298 static void irq_control_v3(struct mxc_nand_host *host, int activate)
 299 {
 300         uint32_t tmp;
 301
 302         tmp = readl(NFC_V3_CONFIG2);
 303
 304         if (activate)
 305                 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
 306         else
 307                 tmp |= NFC_V3_CONFIG2_INT_MSK;
 308
 309         writel(tmp, NFC_V3_CONFIG2);
 310 }
 311
 312 static void irq_control(struct mxc_nand_host *host, int activate)
 313 {
 314         if (host->devtype_data->irqpending_quirk) {
 315                 if (activate)
 316                         enable_irq(host->irq);
 317                 else
 318                         disable_irq_nosync(host->irq);
 319         } else {
 320                 host->devtype_data->irq_control(host, activate);
 321         }
 322 }
 323
 324 static u32 get_ecc_status_v1(struct mxc_nand_host *host)
 325 {
 326         return readw(NFC_V1_V2_ECC_STATUS_RESULT);
 327 }
 328
 329 static u32 get_ecc_status_v2(struct mxc_nand_host *host)
 330 {
 331         return readl(NFC_V1_V2_ECC_STATUS_RESULT);
 332 }
 333
 334 static u32 get_ecc_status_v3(struct mxc_nand_host *host)
 335 {
 336         return readl(NFC_V3_ECC_STATUS_RESULT);
 337 }
 338
 339 static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
 340 {
 341         struct mxc_nand_host *host = dev_id;
 342
 343         if (!host->devtype_data->check_int(host))
 344                 return IRQ_NONE;
 345
 346         irq_control(host, 0);
 347
 348         complete(&host->op_completion);
 349
 350         return IRQ_HANDLED;
 351 }
 352
 353 /* This function polls the NANDFC to wait for the basic operation to
 354  * complete by checking the INT bit of config2 register.
 355  */
 356 static int wait_op_done(struct mxc_nand_host *host, int useirq)
 357 {
 358         int ret = 0;
 359
 360         /*
 361          * If operation is already complete, don't bother to setup an irq or a
 362          * loop.
 363          */
 364         if (host->devtype_data->check_int(host))
 365                 return 0;
 366
 367         if (useirq) {
 368                 unsigned long timeout;
 369
 370                 reinit_completion(&host->op_completion);
 371
 372                 irq_control(host, 1);
 373
 374                 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
 375                 if (!timeout && !host->devtype_data->check_int(host)) {
 376                         dev_dbg(host->dev, "timeout waiting for irq\n");
 377                         ret = -ETIMEDOUT;
 378                 }
 379         } else {
 380                 int max_retries = 8000;
 381                 int done;
 382
 383                 do {
 384                         udelay(1);
 385
 386                         done = host->devtype_data->check_int(host);
 387                         if (done)
 388                                 break;
 389
 390                 } while (--max_retries);
 391
 392                 if (!done) {
 393                         dev_dbg(host->dev, "timeout polling for completion\n");
 394                         ret = -ETIMEDOUT;
 395                 }
 396         }
 397
 398         WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
 399
 400         return ret;
 401 }
 402
 403 static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 404 {
 405         /* fill command */
 406         writel(cmd, NFC_V3_FLASH_CMD);
 407
 408         /* send out command */
 409         writel(NFC_CMD, NFC_V3_LAUNCH);
 410
 411         /* Wait for operation to complete */
 412         wait_op_done(host, useirq);
 413 }
 414
 415 /* This function issues the specified command to the NAND device and
 416  * waits for completion. */
 417 static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
 418 {
 419         pr_debug("send_cmd(host, 0x%x, %d)\n", cmd, useirq);
 420
 421         writew(cmd, NFC_V1_V2_FLASH_CMD);
 422         writew(NFC_CMD, NFC_V1_V2_CONFIG2);
 423
 424         if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
 425                 int max_retries = 100;
 426                 /* Reset completion is indicated by NFC_CONFIG2 */
 427                 /* being set to 0 */
 428                 while (max_retries-- > 0) {
 429                         if (readw(NFC_V1_V2_CONFIG2) == 0) {
 430                                 break;
 431                         }
 432                         udelay(1);
 433                 }
 434                 if (max_retries < 0)
 435                         pr_debug("%s: RESET failed\n", __func__);
 436         } else {
 437                 /* Wait for operation to complete */
 438                 wait_op_done(host, useirq);
 439         }
 440 }
 441
 442 static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
 443 {
 444         /* fill address */
 445         writel(addr, NFC_V3_FLASH_ADDR0);
 446
 447         /* send out address */
 448         writel(NFC_ADDR, NFC_V3_LAUNCH);
 449
 450         wait_op_done(host, 0);
 451 }
 452
 453 /* This function sends an address (or partial address) to the
 454  * NAND device. The address is used to select the source/destination for
 455  * a NAND command. */
 456 static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
 457 {
 458         pr_debug("send_addr(host, 0x%x %d)\n", addr, islast);
 459
 460         writew(addr, NFC_V1_V2_FLASH_ADDR);
 461         writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
 462
 463         /* Wait for operation to complete */
 464         wait_op_done(host, islast);
 465 }
 466
 467 static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
 468 {
 469         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 470         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 471         uint32_t tmp;
 472
 473         tmp = readl(NFC_V3_CONFIG1);
 474         tmp &= ~(7 << 4);
 475         writel(tmp, NFC_V3_CONFIG1);
 476
 477         /* transfer data from NFC ram to nand */
 478         writel(ops, NFC_V3_LAUNCH);
 479
 480         wait_op_done(host, false);
 481 }
 482
 483 static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
 484 {
 485         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 486         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 487
 488         /* NANDFC buffer 0 is used for page read/write */
 489         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 490
 491         writew(ops, NFC_V1_V2_CONFIG2);
 492
 493         /* Wait for operation to complete */
 494         wait_op_done(host, true);
 495 }
 496
 497 static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
 498 {
 499         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 500         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 501         int bufs, i;
 502
 503         if (mtd->writesize > 512)
 504                 bufs = 4;
 505         else
 506                 bufs = 1;
 507
 508         for (i = 0; i < bufs; i++) {
 509
 510                 /* NANDFC buffer 0 is used for page read/write */
 511                 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
 512
 513                 writew(ops, NFC_V1_V2_CONFIG2);
 514
 515                 /* Wait for operation to complete */
 516                 wait_op_done(host, true);
 517         }
 518 }
 519
 520 static void send_read_id_v3(struct mxc_nand_host *host)
 521 {
 522         /* Read ID into main buffer */
 523         writel(NFC_ID, NFC_V3_LAUNCH);
 524
 525         wait_op_done(host, true);
 526
 527         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 528 }
 529
 530 /* Request the NANDFC to perform a read of the NAND device ID. */
 531 static void send_read_id_v1_v2(struct mxc_nand_host *host)
 532 {
 533         /* NANDFC buffer 0 is used for device ID output */
 534         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 535
 536         writew(NFC_ID, NFC_V1_V2_CONFIG2);
 537
 538         /* Wait for operation to complete */
 539         wait_op_done(host, true);
 540
 541         memcpy32_fromio(host->data_buf, host->main_area0, 16);
 542 }
 543
 544 static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
 545 {
 546         writew(NFC_STATUS, NFC_V3_LAUNCH);
 547         wait_op_done(host, true);
 548
 549         return readl(NFC_V3_CONFIG1) >> 16;
 550 }
 551
 552 /* This function requests the NANDFC to perform a read of the
 553  * NAND device status and returns the current status. */
 554 static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
 555 {
 556         void __iomem *main_buf = host->main_area0;
 557         uint32_t store;
 558         uint16_t ret;
 559
 560         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 561
 562         /*
 563          * The device status is stored in main_area0. To
 564          * prevent corruption of the buffer save the value
 565          * and restore it afterwards.
 566          */
 567         store = readl(main_buf);
 568
 569         writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
 570         wait_op_done(host, true);
 571
 572         ret = readw(main_buf);
 573
 574         writel(store, main_buf);
 575
 576         return ret;
 577 }
 578
 579 /* This functions is used by upper layer to checks if device is ready */
 580 static int mxc_nand_dev_ready(struct mtd_info *mtd)
 581 {
 582         /*
 583          * NFC handles R/B internally. Therefore, this function
 584          * always returns status as ready.
 585          */
 586         return 1;
 587 }
 588
 589 static void mxc_nand_enable_hwecc(struct mtd_info *mtd, int mode)
 590 {
 591         /*
 592          * If HW ECC is enabled, we turn it on during init. There is
 593          * no need to enable again here.
 594          */
 595 }
 596
 597 static int mxc_nand_correct_data_v1(struct mtd_info *mtd, u_char *dat,
 598                                  u_char *read_ecc, u_char *calc_ecc)
 599 {
 600         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 601         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 602
 603         /*
 604          * 1-Bit errors are automatically corrected in HW.  No need for
 605          * additional correction.  2-Bit errors cannot be corrected by
 606          * HW ECC, so we need to return failure
 607          */
 608         uint16_t ecc_status = get_ecc_status_v1(host);
 609
 610         if (((ecc_status & 0x3) == 2) || ((ecc_status >> 2) == 2)) {
 611                 pr_debug("MXC_NAND: HWECC uncorrectable 2-bit ECC error\n");
 612                 return -EBADMSG;
 613         }
 614
 615         return 0;
 616 }
 617
 618 static int mxc_nand_correct_data_v2_v3(struct mtd_info *mtd, u_char *dat,
 619                                  u_char *read_ecc, u_char *calc_ecc)
 620 {
 621         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 622         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 623         u32 ecc_stat, err;
 624         int no_subpages = 1;
 625         int ret = 0;
 626         u8 ecc_bit_mask, err_limit;
 627
 628         ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
 629         err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
 630
 631         no_subpages = mtd->writesize >> 9;
 632
 633         ecc_stat = host->devtype_data->get_ecc_status(host);
 634
 635         do {
 636                 err = ecc_stat & ecc_bit_mask;
 637                 if (err > err_limit) {
 638                         printk(KERN_WARNING "UnCorrectable RS-ECC Error\n");
 639                         return -EBADMSG;
 640                 } else {
 641                         ret += err;
 642                 }
 643                 ecc_stat >>= 4;
 644         } while (--no_subpages);
 645
 646         pr_debug("%d Symbol Correctable RS-ECC Error\n", ret);
 647
 648         return ret;
 649 }
 650
 651 static int mxc_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
 652                                   u_char *ecc_code)
 653 {
 654         return 0;
 655 }
 656
 657 static u_char mxc_nand_read_byte(struct mtd_info *mtd)
 658 {
 659         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 660         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 661         uint8_t ret;
 662
 663         /* Check for status request */
 664         if (host->status_request)
 665                 return host->devtype_data->get_dev_status(host) & 0xFF;
 666
 667         if (nand_chip->options & NAND_BUSWIDTH_16) {
 668                 /* only take the lower byte of each word */
 669                 ret = *(uint16_t *)(host->data_buf + host->buf_start);
 670
 671                 host->buf_start += 2;
 672         } else {
 673                 ret = *(uint8_t *)(host->data_buf + host->buf_start);
 674                 host->buf_start++;
 675         }
 676
 677         pr_debug("%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
 678         return ret;
 679 }
 680
 681 static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
 682 {
 683         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 684         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 685         uint16_t ret;
 686
 687         ret = *(uint16_t *)(host->data_buf + host->buf_start);
 688         host->buf_start += 2;
 689
 690         return ret;
 691 }
 692
 693 /* Write data of length len to buffer buf. The data to be
 694  * written on NAND Flash is first copied to RAMbuffer. After the Data Input
 695  * Operation by the NFC, the data is written to NAND Flash */
 696 static void mxc_nand_write_buf(struct mtd_info *mtd,
 697                                 const u_char *buf, int len)
 698 {
 699         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 700         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 701         u16 col = host->buf_start;
 702         int n = mtd->oobsize + mtd->writesize - col;
 703
 704         n = min(n, len);
 705
 706         memcpy(host->data_buf + col, buf, n);
 707
 708         host->buf_start += n;
 709 }
 710
 711 /* Read the data buffer from the NAND Flash. To read the data from NAND
 712  * Flash first the data output cycle is initiated by the NFC, which copies
 713  * the data to RAMbuffer. This data of length len is then copied to buffer buf.
 714  */
 715 static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
 716 {
 717         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 718         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 719         u16 col = host->buf_start;
 720         int n = mtd->oobsize + mtd->writesize - col;
 721
 722         n = min(n, len);
 723
 724         memcpy(buf, host->data_buf + col, n);
 725
 726         host->buf_start += n;
 727 }
 728
 729 /* This function is used by upper layer for select and
 730  * deselect of the NAND chip */
 731 static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
 732 {
 733         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 734         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 735
 736         if (chip == -1) {
 737                 /* Disable the NFC clock */
 738                 if (host->clk_act) {
 739                         clk_disable_unprepare(host->clk);
 740                         host->clk_act = 0;
 741                 }
 742                 return;
 743         }
 744
 745         if (!host->clk_act) {
 746                 /* Enable the NFC clock */
 747                 clk_prepare_enable(host->clk);
 748                 host->clk_act = 1;
 749         }
 750 }
 751
 752 static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
 753 {
 754         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 755         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 756
 757         if (chip == -1) {
 758                 /* Disable the NFC clock */
 759                 if (host->clk_act) {
 760                         clk_disable_unprepare(host->clk);
 761                         host->clk_act = 0;
 762                 }
 763                 return;
 764         }
 765
 766         if (!host->clk_act) {
 767                 /* Enable the NFC clock */
 768                 clk_prepare_enable(host->clk);
 769                 host->clk_act = 1;
 770         }
 771
 772         host->active_cs = chip;
 773         writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
 774 }
 775
 776 /*
 777  * The controller splits a page into data chunks of 512 bytes + partial oob.
 778  * There are writesize / 512 such chunks, the size of the partial oob parts is
 779  * oobsize / #chunks rounded down to a multiple of 2. The last oob chunk then
 780  * contains additionally the byte lost by rounding (if any).
 781  * This function handles the needed shuffling between host->data_buf (which
 782  * holds a page in natural order, i.e. writesize bytes data + oobsize bytes
 783  * spare) and the NFC buffer.
 784  */
 785 static void copy_spare(struct mtd_info *mtd, bool bfrom)
 786 {
 787         struct nand_chip *this = mtd_to_nand(mtd);
 788         struct mxc_nand_host *host = nand_get_controller_data(this);
 789         u16 i, oob_chunk_size;
 790         u16 num_chunks = mtd->writesize / 512;
 791
 792         u8 *d = host->data_buf + mtd->writesize;
 793         u8 __iomem *s = host->spare0;
 794         u16 sparebuf_size = host->devtype_data->spare_len;
 795
 796         /* size of oob chunk for all but possibly the last one */
 797         oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
 798
 799         if (bfrom) {
 800                 for (i = 0; i < num_chunks - 1; i++)
 801                         memcpy16_fromio(d + i * oob_chunk_size,
 802                                         s + i * sparebuf_size,
 803                                         oob_chunk_size);
 804
 805                 /* the last chunk */
 806                 memcpy16_fromio(d + i * oob_chunk_size,
 807                                 s + i * sparebuf_size,
 808                                 host->used_oobsize - i * oob_chunk_size);
 809         } else {
 810                 for (i = 0; i < num_chunks - 1; i++)
 811                         memcpy16_toio(&s[i * sparebuf_size],
 812                                       &d[i * oob_chunk_size],
 813                                       oob_chunk_size);
 814
 815                 /* the last chunk */
 816                 memcpy16_toio(&s[i * sparebuf_size],
 817                               &d[i * oob_chunk_size],
 818                               host->used_oobsize - i * oob_chunk_size);
 819         }
 820 }
 821
 822 /*
 823  * MXC NANDFC can only perform full page+spare or spare-only read/write.  When
 824  * the upper layers perform a read/write buf operation, the saved column address
 825  * is used to index into the full page. So usually this function is called with
 826  * column == 0 (unless no column cycle is needed indicated by column == -1)
 827  */
 828 static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
 829 {
 830         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 831         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 832
 833         /* Write out column address, if necessary */
 834         if (column != -1) {
 835                 host->devtype_data->send_addr(host, column & 0xff,
 836                                               page_addr == -1);
 837                 if (mtd->writesize > 512)
 838                         /* another col addr cycle for 2k page */
 839                         host->devtype_data->send_addr(host,
 840                                                       (column >> 8) & 0xff,
 841                                                       false);
 842         }
 843
 844         /* Write out page address, if necessary */
 845         if (page_addr != -1) {
 846                 /* paddr_0 - p_addr_7 */
 847                 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
 848
 849                 if (mtd->writesize > 512) {
 850                         if (mtd->size >= 0x10000000) {
 851                                 /* paddr_8 - paddr_15 */
 852                                 host->devtype_data->send_addr(host,
 853                                                 (page_addr >> 8) & 0xff,
 854                                                 false);
 855                                 host->devtype_data->send_addr(host,
 856                                                 (page_addr >> 16) & 0xff,
 857                                                 true);
 858                         } else
 859                                 /* paddr_8 - paddr_15 */
 860                                 host->devtype_data->send_addr(host,
 861                                                 (page_addr >> 8) & 0xff, true);
 862                 } else {
 863                         /* One more address cycle for higher density devices */
 864                         if (mtd->size >= 0x4000000) {
 865                                 /* paddr_8 - paddr_15 */
 866                                 host->devtype_data->send_addr(host,
 867                                                 (page_addr >> 8) & 0xff,
 868                                                 false);
 869                                 host->devtype_data->send_addr(host,
 870                                                 (page_addr >> 16) & 0xff,
 871                                                 true);
 872                         } else
 873                                 /* paddr_8 - paddr_15 */
 874                                 host->devtype_data->send_addr(host,
 875                                                 (page_addr >> 8) & 0xff, true);
 876                 }
 877         }
 878 }
 879
 880 static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
 881                                 struct mtd_oob_region *oobregion)
 882 {
 883         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 884
 885         if (section >= nand_chip->ecc.steps)
 886                 return -ERANGE;
 887
 888         oobregion->offset = (section * 16) + 6;
 889         oobregion->length = nand_chip->ecc.bytes;
 890
 891         return 0;
 892 }
 893
 894 static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
 895                                  struct mtd_oob_region *oobregion)
 896 {
 897         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 898
 899         if (section > nand_chip->ecc.steps)
 900                 return -ERANGE;
 901
 902         if (!section) {
 903                 if (mtd->writesize <= 512) {
 904                         oobregion->offset = 0;
 905                         oobregion->length = 5;
 906                 } else {
 907                         oobregion->offset = 2;
 908                         oobregion->length = 4;
 909                 }
 910         } else {
 911                 oobregion->offset = ((section - 1) * 16) +
 912                                     nand_chip->ecc.bytes + 6;
 913                 if (section < nand_chip->ecc.steps)
 914                         oobregion->length = (section * 16) + 6 -
 915                                             oobregion->offset;
 916                 else
 917                         oobregion->length = mtd->oobsize - oobregion->offset;
 918         }
 919
 920         return 0;
 921 }
 922
 923 static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
 924         .ecc = mxc_v1_ooblayout_ecc,
 925         .free = mxc_v1_ooblayout_free,
 926 };
 927
 928 static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
 929                                 struct mtd_oob_region *oobregion)
 930 {
 931         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 932         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
 933
 934         if (section >= nand_chip->ecc.steps)
 935                 return -ERANGE;
 936
 937         oobregion->offset = (section * stepsize) + 7;
 938         oobregion->length = nand_chip->ecc.bytes;
 939
 940         return 0;
 941 }
 942
 943 static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
 944                                  struct mtd_oob_region *oobregion)
 945 {
 946         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 947         int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
 948
 949         if (section >= nand_chip->ecc.steps)
 950                 return -ERANGE;
 951
 952         if (!section) {
 953                 if (mtd->writesize <= 512) {
 954                         oobregion->offset = 0;
 955                         oobregion->length = 5;
 956                 } else {
 957                         oobregion->offset = 2;
 958                         oobregion->length = 4;
 959                 }
 960         } else {
 961                 oobregion->offset = section * stepsize;
 962                 oobregion->length = 7;
 963         }
 964
 965         return 0;
 966 }
 967
 968 static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
 969         .ecc = mxc_v2_ooblayout_ecc,
 970         .free = mxc_v2_ooblayout_free,
 971 };
 972
 973 /*
 974  * v2 and v3 type controllers can do 4bit or 8bit ecc depending
 975  * on how much oob the nand chip has. For 8bit ecc we need at least
 976  * 26 bytes of oob data per 512 byte block.
 977  */
 978 static int get_eccsize(struct mtd_info *mtd)
 979 {
 980         int oobbytes_per_512 = 0;
 981
 982         oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
 983
 984         if (oobbytes_per_512 < 26)
 985                 return 4;
 986         else
 987                 return 8;
 988 }
 989
 990 static void preset_v1(struct mtd_info *mtd)
 991 {
 992         struct nand_chip *nand_chip = mtd_to_nand(mtd);
 993         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
 994         uint16_t config1 = 0;
 995
 996         if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
 997                 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
 998
 999         if (!host->devtype_data->irqpending_quirk)
1000                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1001
1002         host->eccsize = 1;
1003
1004         writew(config1, NFC_V1_V2_CONFIG1);
1005         /* preset operation */
1006
1007         /* Unlock the internal RAM Buffer */
1008         writew(0x2, NFC_V1_V2_CONFIG);
1009
1010         /* Blocks to be unlocked */
1011         writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1012         writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1013
1014         /* Unlock Block Command for given address range */
1015         writew(0x4, NFC_V1_V2_WRPROT);
1016 }
1017
1018 static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd,
1019                                         const struct nand_data_interface *conf,
1020                                         bool check_only)
1021 {
1022         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1023         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1024         int tRC_min_ns, tRC_ps, ret;
1025         unsigned long rate, rate_round;
1026         const struct nand_sdr_timings *timings;
1027         u16 config1;
1028
1029         timings = nand_get_sdr_timings(conf);
1030         if (IS_ERR(timings))
1031                 return -ENOTSUPP;
1032
1033         config1 = readw(NFC_V1_V2_CONFIG1);
1034
1035         tRC_min_ns = timings->tRC_min / 1000;
1036         rate = 1000000000 / tRC_min_ns;
1037
1038         /*
1039          * For tRC < 30ns we have to use EDO mode. In this case the controller
1040          * does one access per clock cycle. Otherwise the controller does one
1041          * access in two clock cycles, thus we have to double the rate to the
1042          * controller.
1043          */
1044         if (tRC_min_ns < 30) {
1045                 rate_round = clk_round_rate(host->clk, rate);
1046                 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1047                 tRC_ps = 1000000000 / (rate_round / 1000);
1048         } else {
1049                 rate *= 2;
1050                 rate_round = clk_round_rate(host->clk, rate);
1051                 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1052                 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1053         }
1054
1055         /*
1056          * The timing values compared against are from the i.MX25 Automotive
1057          * datasheet, Table 50. NFC Timing Parameters
1058          */
1059         if (timings->tCLS_min > tRC_ps - 1000 ||
1060             timings->tCLH_min > tRC_ps - 2000 ||
1061             timings->tCS_min > tRC_ps - 1000 ||
1062             timings->tCH_min > tRC_ps - 2000 ||
1063             timings->tWP_min > tRC_ps - 1500 ||
1064             timings->tALS_min > tRC_ps ||
1065             timings->tALH_min > tRC_ps - 3000 ||
1066             timings->tDS_min > tRC_ps ||
1067             timings->tDH_min > tRC_ps - 5000 ||
1068             timings->tWC_min > 2 * tRC_ps ||
1069             timings->tWH_min > tRC_ps - 2500 ||
1070             timings->tRR_min > 6 * tRC_ps ||
1071             timings->tRP_min > 3 * tRC_ps / 2 ||
1072             timings->tRC_min > 2 * tRC_ps ||
1073             timings->tREH_min > (tRC_ps / 2) - 2500) {
1074                 dev_dbg(host->dev, "Timing out of bounds\n");
1075                 return -EINVAL;
1076         }
1077
1078         if (check_only)
1079                 return 0;
1080
1081         ret = clk_set_rate(host->clk, rate);
1082         if (ret)
1083                 return ret;
1084
1085         writew(config1, NFC_V1_V2_CONFIG1);
1086
1087         dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1088                 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1089                 "normal");
1090
1091         return 0;
1092 }
1093
1094 static void preset_v2(struct mtd_info *mtd)
1095 {
1096         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1097         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1098         uint16_t config1 = 0;
1099
1100         config1 |= NFC_V2_CONFIG1_FP_INT;
1101
1102         if (!host->devtype_data->irqpending_quirk)
1103                 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1104
1105         if (mtd->writesize) {
1106                 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1107
1108                 if (nand_chip->ecc.mode == NAND_ECC_HW)
1109                         config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1110
1111                 host->eccsize = get_eccsize(mtd);
1112                 if (host->eccsize == 4)
1113                         config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1114
1115                 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1116         } else {
1117                 host->eccsize = 1;
1118         }
1119
1120         writew(config1, NFC_V1_V2_CONFIG1);
1121         /* preset operation */
1122
1123         /* Unlock the internal RAM Buffer */
1124         writew(0x2, NFC_V1_V2_CONFIG);
1125
1126         /* Blocks to be unlocked */
1127         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1128         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1129         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1130         writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1131         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1132         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1133         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1134         writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1135
1136         /* Unlock Block Command for given address range */
1137         writew(0x4, NFC_V1_V2_WRPROT);
1138 }
1139
1140 static void preset_v3(struct mtd_info *mtd)
1141 {
1142         struct nand_chip *chip = mtd_to_nand(mtd);
1143         struct mxc_nand_host *host = nand_get_controller_data(chip);
1144         uint32_t config2, config3;
1145         int i, addr_phases;
1146
1147         writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1148         writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1149
1150         /* Unlock the internal RAM Buffer */
1151         writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1152                         NFC_V3_WRPROT);
1153
1154         /* Blocks to be unlocked */
1155         for (i = 0; i < NAND_MAX_CHIPS; i++)
1156                 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1157
1158         writel(0, NFC_V3_IPC);
1159
1160         config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1161                 NFC_V3_CONFIG2_2CMD_PHASES |
1162                 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1163                 NFC_V3_CONFIG2_ST_CMD(0x70) |
1164                 NFC_V3_CONFIG2_INT_MSK |
1165                 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1166
1167         addr_phases = fls(chip->pagemask) >> 3;
1168
1169         if (mtd->writesize == 2048) {
1170                 config2 |= NFC_V3_CONFIG2_PS_2048;
1171                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1172         } else if (mtd->writesize == 4096) {
1173                 config2 |= NFC_V3_CONFIG2_PS_4096;
1174                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1175         } else {
1176                 config2 |= NFC_V3_CONFIG2_PS_512;
1177                 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1178         }
1179
1180         if (mtd->writesize) {
1181                 if (chip->ecc.mode == NAND_ECC_HW)
1182                         config2 |= NFC_V3_CONFIG2_ECC_EN;
1183
1184                 config2 |= NFC_V3_CONFIG2_PPB(
1185                                 ffs(mtd->erasesize / mtd->writesize) - 6,
1186                                 host->devtype_data->ppb_shift);
1187                 host->eccsize = get_eccsize(mtd);
1188                 if (host->eccsize == 8)
1189                         config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1190         }
1191
1192         writel(config2, NFC_V3_CONFIG2);
1193
1194         config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1195                         NFC_V3_CONFIG3_NO_SDMA |
1196                         NFC_V3_CONFIG3_RBB_MODE |
1197                         NFC_V3_CONFIG3_SBB(6) | /* Reset default */
1198                         NFC_V3_CONFIG3_ADD_OP(0);
1199
1200         if (!(chip->options & NAND_BUSWIDTH_16))
1201                 config3 |= NFC_V3_CONFIG3_FW8;
1202
1203         writel(config3, NFC_V3_CONFIG3);
1204
1205         writel(0, NFC_V3_DELAY_LINE);
1206 }
1207
1208 /* Used by the upper layer to write command to NAND Flash for
1209  * different operations to be carried out on NAND Flash */
1210 static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1211                                 int column, int page_addr)
1212 {
1213         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1214         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1215
1216         pr_debug("mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1217               command, column, page_addr);
1218
1219         /* Reset command state information */
1220         host->status_request = false;
1221
1222         /* Command pre-processing step */
1223         switch (command) {
1224         case NAND_CMD_RESET:
1225                 host->devtype_data->preset(mtd);
1226                 host->devtype_data->send_cmd(host, command, false);
1227                 break;
1228
1229         case NAND_CMD_STATUS:
1230                 host->buf_start = 0;
1231                 host->status_request = true;
1232
1233                 host->devtype_data->send_cmd(host, command, true);
1234                 WARN_ONCE(column != -1 || page_addr != -1,
1235                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1236                           command, column, page_addr);
1237                 mxc_do_addr_cycle(mtd, column, page_addr);
1238                 break;
1239
1240         case NAND_CMD_READ0:
1241         case NAND_CMD_READOOB:
1242                 if (command == NAND_CMD_READ0)
1243                         host->buf_start = column;
1244                 else
1245                         host->buf_start = column + mtd->writesize;
1246
1247                 command = NAND_CMD_READ0; /* only READ0 is valid */
1248
1249                 host->devtype_data->send_cmd(host, command, false);
1250                 WARN_ONCE(column < 0,
1251                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1252                           command, column, page_addr);
1253                 mxc_do_addr_cycle(mtd, 0, page_addr);
1254
1255                 if (mtd->writesize > 512)
1256                         host->devtype_data->send_cmd(host,
1257                                         NAND_CMD_READSTART, true);
1258
1259                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1260
1261                 memcpy32_fromio(host->data_buf, host->main_area0,
1262                                 mtd->writesize);
1263                 copy_spare(mtd, true);
1264                 break;
1265
1266         case NAND_CMD_SEQIN:
1267                 if (column >= mtd->writesize)
1268                         /* call ourself to read a page */
1269                         mxc_nand_command(mtd, NAND_CMD_READ0, 0, page_addr);
1270
1271                 host->buf_start = column;
1272
1273                 host->devtype_data->send_cmd(host, command, false);
1274                 WARN_ONCE(column < -1,
1275                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1276                           command, column, page_addr);
1277                 mxc_do_addr_cycle(mtd, 0, page_addr);
1278                 break;
1279
1280         case NAND_CMD_PAGEPROG:
1281                 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1282                 copy_spare(mtd, false);
1283                 host->devtype_data->send_page(mtd, NFC_INPUT);
1284                 host->devtype_data->send_cmd(host, command, true);
1285                 WARN_ONCE(column != -1 || page_addr != -1,
1286                           "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1287                           command, column, page_addr);
1288                 mxc_do_addr_cycle(mtd, column, page_addr);
1289                 break;
1290
1291         case NAND_CMD_READID:
1292                 host->devtype_data->send_cmd(host, command, true);
1293                 mxc_do_addr_cycle(mtd, column, page_addr);
1294                 host->devtype_data->send_read_id(host);
1295                 host->buf_start = 0;
1296                 break;
1297
1298         case NAND_CMD_ERASE1:
1299         case NAND_CMD_ERASE2:
1300                 host->devtype_data->send_cmd(host, command, false);
1301                 WARN_ONCE(column != -1,
1302                           "Unexpected column value (cmd=%u, col=%d)\n",
1303                           command, column);
1304                 mxc_do_addr_cycle(mtd, column, page_addr);
1305
1306                 break;
1307         case NAND_CMD_PARAM:
1308                 host->devtype_data->send_cmd(host, command, false);
1309                 mxc_do_addr_cycle(mtd, column, page_addr);
1310                 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1311                 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1312                 host->buf_start = 0;
1313                 break;
1314         default:
1315                 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1316                           command);
1317                 break;
1318         }
1319 }
1320
1321 static int mxc_nand_onfi_set_features(struct mtd_info *mtd,
1322                                       struct nand_chip *chip, int addr,
1323                                       u8 *subfeature_param)
1324 {
1325         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1326         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1327         int i;
1328
1329         if (!chip->onfi_version ||
1330             !(le16_to_cpu(chip->onfi_params.opt_cmd)
1331               & ONFI_OPT_CMD_SET_GET_FEATURES))
1332                 return -EINVAL;
1333
1334         host->buf_start = 0;
1335
1336         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1337                 chip->write_byte(mtd, subfeature_param[i]);
1338
1339         memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1340         host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1341         mxc_do_addr_cycle(mtd, addr, -1);
1342         host->devtype_data->send_page(mtd, NFC_INPUT);
1343
1344         return 0;
1345 }
1346
1347 static int mxc_nand_onfi_get_features(struct mtd_info *mtd,
1348                                       struct nand_chip *chip, int addr,
1349                                       u8 *subfeature_param)
1350 {
1351         struct nand_chip *nand_chip = mtd_to_nand(mtd);
1352         struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1353         int i;
1354
1355         if (!chip->onfi_version ||
1356             !(le16_to_cpu(chip->onfi_params.opt_cmd)
1357               & ONFI_OPT_CMD_SET_GET_FEATURES))
1358                 return -EINVAL;
1359
1360         host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1361         mxc_do_addr_cycle(mtd, addr, -1);
1362         host->devtype_data->send_page(mtd, NFC_OUTPUT);
1363         memcpy32_fromio(host->data_buf, host->main_area0, 512);
1364         host->buf_start = 0;
1365
1366         for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1367                 *subfeature_param++ = chip->read_byte(mtd);
1368
1369         return 0;
1370 }
1371
1372 /*
1373  * The generic flash bbt decriptors overlap with our ecc
1374  * hardware, so define some i.MX specific ones.
1375  */
1376 static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1377 static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1378
1379 static struct nand_bbt_descr bbt_main_descr = {
1380         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1381             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1382         .offs = 0,
1383         .len = 4,
1384         .veroffs = 4,
1385         .maxblocks = 4,
1386         .pattern = bbt_pattern,
1387 };
1388
1389 static struct nand_bbt_descr bbt_mirror_descr = {
1390         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1391             | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1392         .offs = 0,
1393         .len = 4,
1394         .veroffs = 4,
1395         .maxblocks = 4,
1396         .pattern = mirror_pattern,
1397 };
1398
1399 /* v1 + irqpending_quirk: i.MX21 */
1400 static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1401         .preset = preset_v1,
1402         .send_cmd = send_cmd_v1_v2,
1403         .send_addr = send_addr_v1_v2,
1404         .send_page = send_page_v1,
1405         .send_read_id = send_read_id_v1_v2,
1406         .get_dev_status = get_dev_status_v1_v2,
1407         .check_int = check_int_v1_v2,
1408         .irq_control = irq_control_v1_v2,
1409         .get_ecc_status = get_ecc_status_v1,
1410         .ooblayout = &mxc_v1_ooblayout_ops,
1411         .select_chip = mxc_nand_select_chip_v1_v3,
1412         .correct_data = mxc_nand_correct_data_v1,
1413         .irqpending_quirk = 1,
1414         .needs_ip = 0,
1415         .regs_offset = 0xe00,
1416         .spare0_offset = 0x800,
1417         .spare_len = 16,
1418         .eccbytes = 3,
1419         .eccsize = 1,
1420 };
1421
1422 /* v1 + !irqpending_quirk: i.MX27, i.MX31 */
1423 static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1424         .preset = preset_v1,
1425         .send_cmd = send_cmd_v1_v2,
1426         .send_addr = send_addr_v1_v2,
1427         .send_page = send_page_v1,
1428         .send_read_id = send_read_id_v1_v2,
1429         .get_dev_status = get_dev_status_v1_v2,
1430         .check_int = check_int_v1_v2,
1431         .irq_control = irq_control_v1_v2,
1432         .get_ecc_status = get_ecc_status_v1,
1433         .ooblayout = &mxc_v1_ooblayout_ops,
1434         .select_chip = mxc_nand_select_chip_v1_v3,
1435         .correct_data = mxc_nand_correct_data_v1,
1436         .irqpending_quirk = 0,
1437         .needs_ip = 0,
1438         .regs_offset = 0xe00,
1439         .spare0_offset = 0x800,
1440         .axi_offset = 0,
1441         .spare_len = 16,
1442         .eccbytes = 3,
1443         .eccsize = 1,
1444 };
1445
1446 /* v21: i.MX25, i.MX35 */
1447 static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1448         .preset = preset_v2,
1449         .send_cmd = send_cmd_v1_v2,
1450         .send_addr = send_addr_v1_v2,
1451         .send_page = send_page_v2,
1452         .send_read_id = send_read_id_v1_v2,
1453         .get_dev_status = get_dev_status_v1_v2,
1454         .check_int = check_int_v1_v2,
1455         .irq_control = irq_control_v1_v2,
1456         .get_ecc_status = get_ecc_status_v2,
1457         .ooblayout = &mxc_v2_ooblayout_ops,
1458         .select_chip = mxc_nand_select_chip_v2,
1459         .correct_data = mxc_nand_correct_data_v2_v3,
1460         .setup_data_interface = mxc_nand_v2_setup_data_interface,
1461         .irqpending_quirk = 0,
1462         .needs_ip = 0,
1463         .regs_offset = 0x1e00,
1464         .spare0_offset = 0x1000,
1465         .axi_offset = 0,
1466         .spare_len = 64,
1467         .eccbytes = 9,
1468         .eccsize = 0,
1469 };
1470
1471 /* v3.2a: i.MX51 */
1472 static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1473         .preset = preset_v3,
1474         .send_cmd = send_cmd_v3,
1475         .send_addr = send_addr_v3,
1476         .send_page = send_page_v3,
1477         .send_read_id = send_read_id_v3,
1478         .get_dev_status = get_dev_status_v3,
1479         .check_int = check_int_v3,
1480         .irq_control = irq_control_v3,
1481         .get_ecc_status = get_ecc_status_v3,
1482         .ooblayout = &mxc_v2_ooblayout_ops,
1483         .select_chip = mxc_nand_select_chip_v1_v3,
1484         .correct_data = mxc_nand_correct_data_v2_v3,
1485         .irqpending_quirk = 0,
1486         .needs_ip = 1,
1487         .regs_offset = 0,
1488         .spare0_offset = 0x1000,
1489         .axi_offset = 0x1e00,
1490         .spare_len = 64,
1491         .eccbytes = 0,
1492         .eccsize = 0,
1493         .ppb_shift = 7,
1494 };
1495
1496 /* v3.2b: i.MX53 */
1497 static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1498         .preset = preset_v3,
1499         .send_cmd = send_cmd_v3,
1500         .send_addr = send_addr_v3,
1501         .send_page = send_page_v3,
1502         .send_read_id = send_read_id_v3,
1503         .get_dev_status = get_dev_status_v3,
1504         .check_int = check_int_v3,
1505         .irq_control = irq_control_v3,
1506         .get_ecc_status = get_ecc_status_v3,
1507         .ooblayout = &mxc_v2_ooblayout_ops,
1508         .select_chip = mxc_nand_select_chip_v1_v3,
1509         .correct_data = mxc_nand_correct_data_v2_v3,
1510         .irqpending_quirk = 0,
1511         .needs_ip = 1,
1512         .regs_offset = 0,
1513         .spare0_offset = 0x1000,
1514         .axi_offset = 0x1e00,
1515         .spare_len = 64,
1516         .eccbytes = 0,
1517         .eccsize = 0,
1518         .ppb_shift = 8,
1519 };
1520
1521 static inline int is_imx21_nfc(struct mxc_nand_host *host)
1522 {
1523         return host->devtype_data == &imx21_nand_devtype_data;
1524 }
1525
1526 static inline int is_imx27_nfc(struct mxc_nand_host *host)
1527 {
1528         return host->devtype_data == &imx27_nand_devtype_data;
1529 }
1530
1531 static inline int is_imx25_nfc(struct mxc_nand_host *host)
1532 {
1533         return host->devtype_data == &imx25_nand_devtype_data;
1534 }
1535
1536 static inline int is_imx51_nfc(struct mxc_nand_host *host)
1537 {
1538         return host->devtype_data == &imx51_nand_devtype_data;
1539 }
1540
1541 static inline int is_imx53_nfc(struct mxc_nand_host *host)
1542 {
1543         return host->devtype_data == &imx53_nand_devtype_data;
1544 }
1545
1546 static const struct platform_device_id mxcnd_devtype[] = {
1547         {
1548                 .name = "imx21-nand",
1549                 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1550         }, {
1551                 .name = "imx27-nand",
1552                 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1553         }, {
1554                 .name = "imx25-nand",
1555                 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1556         }, {
1557                 .name = "imx51-nand",
1558                 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1559         }, {
1560                 .name = "imx53-nand",
1561                 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1562         }, {
1563                 /* sentinel */
1564         }
1565 };
1566 MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1567
1568 #ifdef CONFIG_OF
1569 static const struct of_device_id mxcnd_dt_ids[] = {
1570         {
1571                 .compatible = "fsl,imx21-nand",
1572                 .data = &imx21_nand_devtype_data,
1573         }, {
1574                 .compatible = "fsl,imx27-nand",
1575                 .data = &imx27_nand_devtype_data,
1576         }, {
1577                 .compatible = "fsl,imx25-nand",
1578                 .data = &imx25_nand_devtype_data,
1579         }, {
1580                 .compatible = "fsl,imx51-nand",
1581                 .data = &imx51_nand_devtype_data,
1582         }, {
1583                 .compatible = "fsl,imx53-nand",
1584                 .data = &imx53_nand_devtype_data,
1585         },
1586         { /* sentinel */ }
1587 };
1588 MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1589
1590 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1591 {
1592         struct device_node *np = host->dev->of_node;
1593         const struct of_device_id *of_id =
1594                 of_match_device(mxcnd_dt_ids, host->dev);
1595
1596         if (!np)
1597                 return 1;
1598
1599         host->devtype_data = of_id->data;
1600
1601         return 0;
1602 }
1603 #else
1604 static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1605 {
1606         return 1;
1607 }
1608 #endif
1609
1610 static int mxcnd_probe(struct platform_device *pdev)
1611 {
1612         struct nand_chip *this;
1613         struct mtd_info *mtd;
1614         struct mxc_nand_host *host;
1615         struct resource *res;
1616         int err = 0;
1617
1618         /* Allocate memory for MTD device structure and private data */
1619         host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1620                         GFP_KERNEL);
1621         if (!host)
1622                 return -ENOMEM;
1623
1624         /* allocate a temporary buffer for the nand_scan_ident() */
1625         host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1626         if (!host->data_buf)
1627                 return -ENOMEM;
1628
1629         host->dev = &pdev->dev;
1630         /* structures must be linked */
1631         this = &host->nand;
1632         mtd = nand_to_mtd(this);
1633         mtd->dev.parent = &pdev->dev;
1634         mtd->name = DRIVER_NAME;
1635
1636         /* 50 us command delay time */
1637         this->chip_delay = 5;
1638
1639         nand_set_controller_data(this, host);
1640         nand_set_flash_node(this, pdev->dev.of_node),
1641         this->dev_ready = mxc_nand_dev_ready;
1642         this->cmdfunc = mxc_nand_command;
1643         this->read_byte = mxc_nand_read_byte;
1644         this->read_word = mxc_nand_read_word;
1645         this->write_buf = mxc_nand_write_buf;
1646         this->read_buf = mxc_nand_read_buf;
1647         this->onfi_set_features = mxc_nand_onfi_set_features;
1648         this->onfi_get_features = mxc_nand_onfi_get_features;
1649
1650         host->clk = devm_clk_get(&pdev->dev, NULL);
1651         if (IS_ERR(host->clk))
1652                 return PTR_ERR(host->clk);
1653
1654         err = mxcnd_probe_dt(host);
1655         if (err > 0) {
1656                 struct mxc_nand_platform_data *pdata =
1657                                         dev_get_platdata(&pdev->dev);
1658                 if (pdata) {
1659                         host->pdata = *pdata;
1660                         host->devtype_data = (struct mxc_nand_devtype_data *)
1661                                                 pdev->id_entry->driver_data;
1662                 } else {
1663                         err = -ENODEV;
1664                 }
1665         }
1666         if (err < 0)
1667                 return err;
1668
1669         this->setup_data_interface = host->devtype_data->setup_data_interface;
1670
1671         if (host->devtype_data->needs_ip) {
1672                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1673                 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1674                 if (IS_ERR(host->regs_ip))
1675                         return PTR_ERR(host->regs_ip);
1676
1677                 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1678         } else {
1679                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1680         }
1681
1682         host->base = devm_ioremap_resource(&pdev->dev, res);
1683         if (IS_ERR(host->base))
1684                 return PTR_ERR(host->base);
1685
1686         host->main_area0 = host->base;
1687
1688         if (host->devtype_data->regs_offset)
1689                 host->regs = host->base + host->devtype_data->regs_offset;
1690         host->spare0 = host->base + host->devtype_data->spare0_offset;
1691         if (host->devtype_data->axi_offset)
1692                 host->regs_axi = host->base + host->devtype_data->axi_offset;
1693
1694         this->ecc.bytes = host->devtype_data->eccbytes;
1695         host->eccsize = host->devtype_data->eccsize;
1696
1697         this->select_chip = host->devtype_data->select_chip;
1698         this->ecc.size = 512;
1699         mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1700
1701         if (host->pdata.hw_ecc) {
1702                 this->ecc.mode = NAND_ECC_HW;
1703         } else {
1704                 this->ecc.mode = NAND_ECC_SOFT;
1705                 this->ecc.algo = NAND_ECC_HAMMING;
1706         }
1707
1708         /* NAND bus width determines access functions used by upper layer */
1709         if (host->pdata.width == 2)
1710                 this->options |= NAND_BUSWIDTH_16;
1711
1712         /* update flash based bbt */
1713         if (host->pdata.flash_bbt)
1714                 this->bbt_options |= NAND_BBT_USE_FLASH;
1715
1716         init_completion(&host->op_completion);
1717
1718         host->irq = platform_get_irq(pdev, 0);
1719         if (host->irq < 0)
1720                 return host->irq;
1721
1722         /*
1723          * Use host->devtype_data->irq_control() here instead of irq_control()
1724          * because we must not disable_irq_nosync without having requested the
1725          * irq.
1726          */
1727         host->devtype_data->irq_control(host, 0);
1728
1729         err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1730                         0, DRIVER_NAME, host);
1731         if (err)
1732                 return err;
1733
1734         err = clk_prepare_enable(host->clk);
1735         if (err)
1736                 return err;
1737         host->clk_act = 1;
1738
1739         /*
1740          * Now that we "own" the interrupt make sure the interrupt mask bit is
1741          * cleared on i.MX21. Otherwise we can't read the interrupt status bit
1742          * on this machine.
1743          */
1744         if (host->devtype_data->irqpending_quirk) {
1745                 disable_irq_nosync(host->irq);
1746                 host->devtype_data->irq_control(host, 1);
1747         }
1748
1749         /* first scan to find the device and get the page size */
1750         err = nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL);
1751         if (err)
1752                 goto escan;
1753
1754         switch (this->ecc.mode) {
1755         case NAND_ECC_HW:
1756                 this->ecc.calculate = mxc_nand_calculate_ecc;
1757                 this->ecc.hwctl = mxc_nand_enable_hwecc;
1758                 this->ecc.correct = host->devtype_data->correct_data;
1759                 break;
1760
1761         case NAND_ECC_SOFT:
1762                 break;
1763
1764         default:
1765                 err = -EINVAL;
1766                 goto escan;
1767         }
1768
1769         if (this->bbt_options & NAND_BBT_USE_FLASH) {
1770                 this->bbt_td = &bbt_main_descr;
1771                 this->bbt_md = &bbt_mirror_descr;
1772         }
1773
1774         /* allocate the right size buffer now */
1775         devm_kfree(&pdev->dev, (void *)host->data_buf);
1776         host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1777                                         GFP_KERNEL);
1778         if (!host->data_buf) {
1779                 err = -ENOMEM;
1780                 goto escan;
1781         }
1782
1783         /* Call preset again, with correct writesize this time */
1784         host->devtype_data->preset(mtd);
1785
1786         if (!this->ecc.bytes) {
1787                 if (host->eccsize == 8)
1788                         this->ecc.bytes = 18;
1789                 else if (host->eccsize == 4)
1790                         this->ecc.bytes = 9;
1791         }
1792
1793         /*
1794          * Experimentation shows that i.MX NFC can only handle up to 218 oob
1795          * bytes. Limit used_oobsize to 218 so as to not confuse copy_spare()
1796          * into copying invalid data to/from the spare IO buffer, as this
1797          * might cause ECC data corruption when doing sub-page write to a
1798          * partially written page.
1799          */
1800         host->used_oobsize = min(mtd->oobsize, 218U);
1801
1802         if (this->ecc.mode == NAND_ECC_HW) {
1803                 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1804                         this->ecc.strength = 1;
1805                 else
1806                         this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1807         }
1808
1809         /* second phase scan */
1810         err = nand_scan_tail(mtd);
1811         if (err)
1812                 goto escan;
1813
1814         /* Register the partitions */
1815         mtd_device_parse_register(mtd, part_probes,
1816                         NULL,
1817                         host->pdata.parts,
1818                         host->pdata.nr_parts);
1819
1820         platform_set_drvdata(pdev, host);
1821
1822         return 0;
1823
1824 escan:
1825         if (host->clk_act)
1826                 clk_disable_unprepare(host->clk);
1827
1828         return err;
1829 }
1830
1831 static int mxcnd_remove(struct platform_device *pdev)
1832 {
1833         struct mxc_nand_host *host = platform_get_drvdata(pdev);
1834
1835         nand_release(nand_to_mtd(&host->nand));
1836         if (host->clk_act)
1837                 clk_disable_unprepare(host->clk);
1838
1839         return 0;
1840 }
1841
1842 static struct platform_driver mxcnd_driver = {
1843         .driver = {
1844                    .name = DRIVER_NAME,
1845                    .of_match_table = of_match_ptr(mxcnd_dt_ids),
1846         },
1847         .id_table = mxcnd_devtype,
1848         .probe = mxcnd_probe,
1849         .remove = mxcnd_remove,
1850 };
1851 module_platform_driver(mxcnd_driver);
1852
1853 MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1854 MODULE_DESCRIPTION("MXC NAND MTD driver");
1855 MODULE_LICENSE("GPL");