drivers/net/ethernet/mellanox/mlx5/core/cmd.c

   1 /*
   2  * Copyright (c) 2013-2016, Mellanox Technologies. All rights reserved.
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and/or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32
  33 #include <linux/highmem.h>
  34 #include <linux/module.h>
  35 #include <linux/errno.h>
  36 #include <linux/pci.h>
  37 #include <linux/dma-mapping.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/random.h>
  41 #include <linux/io-mapping.h>
  42 #include <linux/mlx5/driver.h>
  43 #include <linux/debugfs.h>
  44
  45 #include "mlx5_core.h"
  46
  47 enum {
  48         CMD_IF_REV = 5,
  49 };
  50
  51 enum {
  52         CMD_MODE_POLLING,
  53         CMD_MODE_EVENTS
  54 };
  55
  56 enum {
  57         MLX5_CMD_DELIVERY_STAT_OK                       = 0x0,
  58         MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR               = 0x1,
  59         MLX5_CMD_DELIVERY_STAT_TOK_ERR                  = 0x2,
  60         MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR          = 0x3,
  61         MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR        = 0x4,
  62         MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR         = 0x5,
  63         MLX5_CMD_DELIVERY_STAT_FW_ERR                   = 0x6,
  64         MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR            = 0x7,
  65         MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR           = 0x8,
  66         MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR      = 0x9,
  67         MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR            = 0x10,
  68 };
  69
  70 static struct mlx5_cmd_work_ent *alloc_cmd(struct mlx5_cmd *cmd,
  71                                            struct mlx5_cmd_msg *in,
  72                                            struct mlx5_cmd_msg *out,
  73                                            void *uout, int uout_size,
  74                                            mlx5_cmd_cbk_t cbk,
  75                                            void *context, int page_queue)
  76 {
  77         gfp_t alloc_flags = cbk ? GFP_ATOMIC : GFP_KERNEL;
  78         struct mlx5_cmd_work_ent *ent;
  79
  80         ent = kzalloc(sizeof(*ent), alloc_flags);
  81         if (!ent)
  82                 return ERR_PTR(-ENOMEM);
  83
  84         ent->in         = in;
  85         ent->out        = out;
  86         ent->uout       = uout;
  87         ent->uout_size  = uout_size;
  88         ent->callback   = cbk;
  89         ent->context    = context;
  90         ent->cmd        = cmd;
  91         ent->page_queue = page_queue;
  92
  93         return ent;
  94 }
  95
  96 static u8 alloc_token(struct mlx5_cmd *cmd)
  97 {
  98         u8 token;
  99
 100         spin_lock(&cmd->token_lock);
 101         cmd->token++;
 102         if (cmd->token == 0)
 103                 cmd->token++;
 104         token = cmd->token;
 105         spin_unlock(&cmd->token_lock);
 106
 107         return token;
 108 }
 109
 110 static int alloc_ent(struct mlx5_cmd *cmd)
 111 {
 112         unsigned long flags;
 113         int ret;
 114
 115         spin_lock_irqsave(&cmd->alloc_lock, flags);
 116         ret = find_first_bit(&cmd->bitmask, cmd->max_reg_cmds);
 117         if (ret < cmd->max_reg_cmds)
 118                 clear_bit(ret, &cmd->bitmask);
 119         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 120
 121         return ret < cmd->max_reg_cmds ? ret : -ENOMEM;
 122 }
 123
 124 static void free_ent(struct mlx5_cmd *cmd, int idx)
 125 {
 126         unsigned long flags;
 127
 128         spin_lock_irqsave(&cmd->alloc_lock, flags);
 129         set_bit(idx, &cmd->bitmask);
 130         spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 131 }
 132
 133 static struct mlx5_cmd_layout *get_inst(struct mlx5_cmd *cmd, int idx)
 134 {
 135         return cmd->cmd_buf + (idx << cmd->log_stride);
 136 }
 137
 138 static u8 xor8_buf(void *buf, size_t offset, int len)
 139 {
 140         u8 *ptr = buf;
 141         u8 sum = 0;
 142         int i;
 143         int end = len + offset;
 144
 145         for (i = offset; i < end; i++)
 146                 sum ^= ptr[i];
 147
 148         return sum;
 149 }
 150
 151 static int verify_block_sig(struct mlx5_cmd_prot_block *block)
 152 {
 153         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 154         int xor_len = sizeof(*block) - sizeof(block->data) - 1;
 155
 156         if (xor8_buf(block, rsvd0_off, xor_len) != 0xff)
 157                 return -EINVAL;
 158
 159         if (xor8_buf(block, 0, sizeof(*block)) != 0xff)
 160                 return -EINVAL;
 161
 162         return 0;
 163 }
 164
 165 static void calc_block_sig(struct mlx5_cmd_prot_block *block)
 166 {
 167         int ctrl_xor_len = sizeof(*block) - sizeof(block->data) - 2;
 168         size_t rsvd0_off = offsetof(struct mlx5_cmd_prot_block, rsvd0);
 169
 170         block->ctrl_sig = ~xor8_buf(block, rsvd0_off, ctrl_xor_len);
 171         block->sig = ~xor8_buf(block, 0, sizeof(*block) - 1);
 172 }
 173
 174 static void calc_chain_sig(struct mlx5_cmd_msg *msg)
 175 {
 176         struct mlx5_cmd_mailbox *next = msg->next;
 177         int size = msg->len;
 178         int blen = size - min_t(int, sizeof(msg->first.data), size);
 179         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 180                 / MLX5_CMD_DATA_BLOCK_SIZE;
 181         int i = 0;
 182
 183         for (i = 0; i < n && next; i++)  {
 184                 calc_block_sig(next->buf);
 185                 next = next->next;
 186         }
 187 }
 188
 189 static void set_signature(struct mlx5_cmd_work_ent *ent, int csum)
 190 {
 191         ent->lay->sig = ~xor8_buf(ent->lay, 0,  sizeof(*ent->lay));
 192         if (csum) {
 193                 calc_chain_sig(ent->in);
 194                 calc_chain_sig(ent->out);
 195         }
 196 }
 197
 198 static void poll_timeout(struct mlx5_cmd_work_ent *ent)
 199 {
 200         unsigned long poll_end = jiffies + msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC + 1000);
 201         u8 own;
 202
 203         do {
 204                 own = ent->lay->status_own;
 205                 if (!(own & CMD_OWNER_HW)) {
 206                         ent->ret = 0;
 207                         return;
 208                 }
 209                 usleep_range(5000, 10000);
 210         } while (time_before(jiffies, poll_end));
 211
 212         ent->ret = -ETIMEDOUT;
 213 }
 214
 215 static void free_cmd(struct mlx5_cmd_work_ent *ent)
 216 {
 217         kfree(ent);
 218 }
 219
 220 static int verify_signature(struct mlx5_cmd_work_ent *ent)
 221 {
 222         struct mlx5_cmd_mailbox *next = ent->out->next;
 223         int err;
 224         u8 sig;
 225         int size = ent->out->len;
 226         int blen = size - min_t(int, sizeof(ent->out->first.data), size);
 227         int n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1)
 228                 / MLX5_CMD_DATA_BLOCK_SIZE;
 229         int i = 0;
 230
 231         sig = xor8_buf(ent->lay, 0, sizeof(*ent->lay));
 232         if (sig != 0xff)
 233                 return -EINVAL;
 234
 235         for (i = 0; i < n && next; i++) {
 236                 err = verify_block_sig(next->buf);
 237                 if (err)
 238                         return err;
 239
 240                 next = next->next;
 241         }
 242
 243         return 0;
 244 }
 245
 246 static void dump_buf(void *buf, int size, int data_only, int offset)
 247 {
 248         __be32 *p = buf;
 249         int i;
 250
 251         for (i = 0; i < size; i += 16) {
 252                 pr_debug("%03x: %08x %08x %08x %08x\n", offset, be32_to_cpu(p[0]),
 253                          be32_to_cpu(p[1]), be32_to_cpu(p[2]),
 254                          be32_to_cpu(p[3]));
 255                 p += 4;
 256                 offset += 16;
 257         }
 258         if (!data_only)
 259                 pr_debug("\n");
 260 }
 261
 262 static int mlx5_internal_err_ret_value(struct mlx5_core_dev *dev, u16 op,
 263                                        u32 *synd, u8 *status)
 264 {
 265         *synd = 0;
 266         *status = 0;
 267
 268         switch (op) {
 269         case MLX5_CMD_OP_TEARDOWN_HCA:
 270         case MLX5_CMD_OP_DISABLE_HCA:
 271         case MLX5_CMD_OP_MANAGE_PAGES:
 272         case MLX5_CMD_OP_DESTROY_MKEY:
 273         case MLX5_CMD_OP_DESTROY_EQ:
 274         case MLX5_CMD_OP_DESTROY_CQ:
 275         case MLX5_CMD_OP_DESTROY_QP:
 276         case MLX5_CMD_OP_DESTROY_PSV:
 277         case MLX5_CMD_OP_DESTROY_SRQ:
 278         case MLX5_CMD_OP_DESTROY_XRC_SRQ:
 279         case MLX5_CMD_OP_DESTROY_DCT:
 280         case MLX5_CMD_OP_DEALLOC_Q_COUNTER:
 281         case MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT:
 282         case MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT:
 283         case MLX5_CMD_OP_DEALLOC_PD:
 284         case MLX5_CMD_OP_DEALLOC_UAR:
 285         case MLX5_CMD_OP_DETACH_FROM_MCG:
 286         case MLX5_CMD_OP_DEALLOC_XRCD:
 287         case MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN:
 288         case MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT:
 289         case MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY:
 290         case MLX5_CMD_OP_DESTROY_LAG:
 291         case MLX5_CMD_OP_DESTROY_VPORT_LAG:
 292         case MLX5_CMD_OP_DESTROY_TIR:
 293         case MLX5_CMD_OP_DESTROY_SQ:
 294         case MLX5_CMD_OP_DESTROY_RQ:
 295         case MLX5_CMD_OP_DESTROY_RMP:
 296         case MLX5_CMD_OP_DESTROY_TIS:
 297         case MLX5_CMD_OP_DESTROY_RQT:
 298         case MLX5_CMD_OP_DESTROY_FLOW_TABLE:
 299         case MLX5_CMD_OP_DESTROY_FLOW_GROUP:
 300         case MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY:
 301         case MLX5_CMD_OP_DEALLOC_FLOW_COUNTER:
 302         case MLX5_CMD_OP_2ERR_QP:
 303         case MLX5_CMD_OP_2RST_QP:
 304         case MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT:
 305         case MLX5_CMD_OP_MODIFY_FLOW_TABLE:
 306         case MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY:
 307         case MLX5_CMD_OP_SET_FLOW_TABLE_ROOT:
 308         case MLX5_CMD_OP_DEALLOC_ENCAP_HEADER:
 309         case MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT:
 310         case MLX5_CMD_OP_FPGA_DESTROY_QP:
 311                 return MLX5_CMD_STAT_OK;
 312
 313         case MLX5_CMD_OP_QUERY_HCA_CAP:
 314         case MLX5_CMD_OP_QUERY_ADAPTER:
 315         case MLX5_CMD_OP_INIT_HCA:
 316         case MLX5_CMD_OP_ENABLE_HCA:
 317         case MLX5_CMD_OP_QUERY_PAGES:
 318         case MLX5_CMD_OP_SET_HCA_CAP:
 319         case MLX5_CMD_OP_QUERY_ISSI:
 320         case MLX5_CMD_OP_SET_ISSI:
 321         case MLX5_CMD_OP_CREATE_MKEY:
 322         case MLX5_CMD_OP_QUERY_MKEY:
 323         case MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS:
 324         case MLX5_CMD_OP_PAGE_FAULT_RESUME:
 325         case MLX5_CMD_OP_CREATE_EQ:
 326         case MLX5_CMD_OP_QUERY_EQ:
 327         case MLX5_CMD_OP_GEN_EQE:
 328         case MLX5_CMD_OP_CREATE_CQ:
 329         case MLX5_CMD_OP_QUERY_CQ:
 330         case MLX5_CMD_OP_MODIFY_CQ:
 331         case MLX5_CMD_OP_CREATE_QP:
 332         case MLX5_CMD_OP_RST2INIT_QP:
 333         case MLX5_CMD_OP_INIT2RTR_QP:
 334         case MLX5_CMD_OP_RTR2RTS_QP:
 335         case MLX5_CMD_OP_RTS2RTS_QP:
 336         case MLX5_CMD_OP_SQERR2RTS_QP:
 337         case MLX5_CMD_OP_QUERY_QP:
 338         case MLX5_CMD_OP_SQD_RTS_QP:
 339         case MLX5_CMD_OP_INIT2INIT_QP:
 340         case MLX5_CMD_OP_CREATE_PSV:
 341         case MLX5_CMD_OP_CREATE_SRQ:
 342         case MLX5_CMD_OP_QUERY_SRQ:
 343         case MLX5_CMD_OP_ARM_RQ:
 344         case MLX5_CMD_OP_CREATE_XRC_SRQ:
 345         case MLX5_CMD_OP_QUERY_XRC_SRQ:
 346         case MLX5_CMD_OP_ARM_XRC_SRQ:
 347         case MLX5_CMD_OP_CREATE_DCT:
 348         case MLX5_CMD_OP_DRAIN_DCT:
 349         case MLX5_CMD_OP_QUERY_DCT:
 350         case MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION:
 351         case MLX5_CMD_OP_QUERY_VPORT_STATE:
 352         case MLX5_CMD_OP_MODIFY_VPORT_STATE:
 353         case MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT:
 354         case MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT:
 355         case MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT:
 356         case MLX5_CMD_OP_QUERY_ROCE_ADDRESS:
 357         case MLX5_CMD_OP_SET_ROCE_ADDRESS:
 358         case MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT:
 359         case MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT:
 360         case MLX5_CMD_OP_QUERY_HCA_VPORT_GID:
 361         case MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY:
 362         case MLX5_CMD_OP_QUERY_VPORT_COUNTER:
 363         case MLX5_CMD_OP_ALLOC_Q_COUNTER:
 364         case MLX5_CMD_OP_QUERY_Q_COUNTER:
 365         case MLX5_CMD_OP_SET_RATE_LIMIT:
 366         case MLX5_CMD_OP_QUERY_RATE_LIMIT:
 367         case MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT:
 368         case MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT:
 369         case MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT:
 370         case MLX5_CMD_OP_CREATE_QOS_PARA_VPORT:
 371         case MLX5_CMD_OP_ALLOC_PD:
 372         case MLX5_CMD_OP_ALLOC_UAR:
 373         case MLX5_CMD_OP_CONFIG_INT_MODERATION:
 374         case MLX5_CMD_OP_ACCESS_REG:
 375         case MLX5_CMD_OP_ATTACH_TO_MCG:
 376         case MLX5_CMD_OP_GET_DROPPED_PACKET_LOG:
 377         case MLX5_CMD_OP_MAD_IFC:
 378         case MLX5_CMD_OP_QUERY_MAD_DEMUX:
 379         case MLX5_CMD_OP_SET_MAD_DEMUX:
 380         case MLX5_CMD_OP_NOP:
 381         case MLX5_CMD_OP_ALLOC_XRCD:
 382         case MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN:
 383         case MLX5_CMD_OP_QUERY_CONG_STATUS:
 384         case MLX5_CMD_OP_MODIFY_CONG_STATUS:
 385         case MLX5_CMD_OP_QUERY_CONG_PARAMS:
 386         case MLX5_CMD_OP_MODIFY_CONG_PARAMS:
 387         case MLX5_CMD_OP_QUERY_CONG_STATISTICS:
 388         case MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT:
 389         case MLX5_CMD_OP_SET_L2_TABLE_ENTRY:
 390         case MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY:
 391         case MLX5_CMD_OP_CREATE_LAG:
 392         case MLX5_CMD_OP_MODIFY_LAG:
 393         case MLX5_CMD_OP_QUERY_LAG:
 394         case MLX5_CMD_OP_CREATE_VPORT_LAG:
 395         case MLX5_CMD_OP_CREATE_TIR:
 396         case MLX5_CMD_OP_MODIFY_TIR:
 397         case MLX5_CMD_OP_QUERY_TIR:
 398         case MLX5_CMD_OP_CREATE_SQ:
 399         case MLX5_CMD_OP_MODIFY_SQ:
 400         case MLX5_CMD_OP_QUERY_SQ:
 401         case MLX5_CMD_OP_CREATE_RQ:
 402         case MLX5_CMD_OP_MODIFY_RQ:
 403         case MLX5_CMD_OP_QUERY_RQ:
 404         case MLX5_CMD_OP_CREATE_RMP:
 405         case MLX5_CMD_OP_MODIFY_RMP:
 406         case MLX5_CMD_OP_QUERY_RMP:
 407         case MLX5_CMD_OP_CREATE_TIS:
 408         case MLX5_CMD_OP_MODIFY_TIS:
 409         case MLX5_CMD_OP_QUERY_TIS:
 410         case MLX5_CMD_OP_CREATE_RQT:
 411         case MLX5_CMD_OP_MODIFY_RQT:
 412         case MLX5_CMD_OP_QUERY_RQT:
 413
 414         case MLX5_CMD_OP_CREATE_FLOW_TABLE:
 415         case MLX5_CMD_OP_QUERY_FLOW_TABLE:
 416         case MLX5_CMD_OP_CREATE_FLOW_GROUP:
 417         case MLX5_CMD_OP_QUERY_FLOW_GROUP:
 418         case MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY:
 419         case MLX5_CMD_OP_ALLOC_FLOW_COUNTER:
 420         case MLX5_CMD_OP_QUERY_FLOW_COUNTER:
 421         case MLX5_CMD_OP_ALLOC_ENCAP_HEADER:
 422         case MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT:
 423         case MLX5_CMD_OP_FPGA_CREATE_QP:
 424         case MLX5_CMD_OP_FPGA_MODIFY_QP:
 425         case MLX5_CMD_OP_FPGA_QUERY_QP:
 426         case MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS:
 427                 *status = MLX5_DRIVER_STATUS_ABORTED;
 428                 *synd = MLX5_DRIVER_SYND;
 429                 return -EIO;
 430         default:
 431                 mlx5_core_err(dev, "Unknown FW command (%d)\n", op);
 432                 return -EINVAL;
 433         }
 434 }
 435
 436 const char *mlx5_command_str(int command)
 437 {
 438 #define MLX5_COMMAND_STR_CASE(__cmd) case MLX5_CMD_OP_ ## __cmd: return #__cmd
 439
 440         switch (command) {
 441         MLX5_COMMAND_STR_CASE(QUERY_HCA_CAP);
 442         MLX5_COMMAND_STR_CASE(QUERY_ADAPTER);
 443         MLX5_COMMAND_STR_CASE(INIT_HCA);
 444         MLX5_COMMAND_STR_CASE(TEARDOWN_HCA);
 445         MLX5_COMMAND_STR_CASE(ENABLE_HCA);
 446         MLX5_COMMAND_STR_CASE(DISABLE_HCA);
 447         MLX5_COMMAND_STR_CASE(QUERY_PAGES);
 448         MLX5_COMMAND_STR_CASE(MANAGE_PAGES);
 449         MLX5_COMMAND_STR_CASE(SET_HCA_CAP);
 450         MLX5_COMMAND_STR_CASE(QUERY_ISSI);
 451         MLX5_COMMAND_STR_CASE(SET_ISSI);
 452         MLX5_COMMAND_STR_CASE(CREATE_MKEY);
 453         MLX5_COMMAND_STR_CASE(QUERY_MKEY);
 454         MLX5_COMMAND_STR_CASE(DESTROY_MKEY);
 455         MLX5_COMMAND_STR_CASE(QUERY_SPECIAL_CONTEXTS);
 456         MLX5_COMMAND_STR_CASE(PAGE_FAULT_RESUME);
 457         MLX5_COMMAND_STR_CASE(CREATE_EQ);
 458         MLX5_COMMAND_STR_CASE(DESTROY_EQ);
 459         MLX5_COMMAND_STR_CASE(QUERY_EQ);
 460         MLX5_COMMAND_STR_CASE(GEN_EQE);
 461         MLX5_COMMAND_STR_CASE(CREATE_CQ);
 462         MLX5_COMMAND_STR_CASE(DESTROY_CQ);
 463         MLX5_COMMAND_STR_CASE(QUERY_CQ);
 464         MLX5_COMMAND_STR_CASE(MODIFY_CQ);
 465         MLX5_COMMAND_STR_CASE(CREATE_QP);
 466         MLX5_COMMAND_STR_CASE(DESTROY_QP);
 467         MLX5_COMMAND_STR_CASE(RST2INIT_QP);
 468         MLX5_COMMAND_STR_CASE(INIT2RTR_QP);
 469         MLX5_COMMAND_STR_CASE(RTR2RTS_QP);
 470         MLX5_COMMAND_STR_CASE(RTS2RTS_QP);
 471         MLX5_COMMAND_STR_CASE(SQERR2RTS_QP);
 472         MLX5_COMMAND_STR_CASE(2ERR_QP);
 473         MLX5_COMMAND_STR_CASE(2RST_QP);
 474         MLX5_COMMAND_STR_CASE(QUERY_QP);
 475         MLX5_COMMAND_STR_CASE(SQD_RTS_QP);
 476         MLX5_COMMAND_STR_CASE(INIT2INIT_QP);
 477         MLX5_COMMAND_STR_CASE(CREATE_PSV);
 478         MLX5_COMMAND_STR_CASE(DESTROY_PSV);
 479         MLX5_COMMAND_STR_CASE(CREATE_SRQ);
 480         MLX5_COMMAND_STR_CASE(DESTROY_SRQ);
 481         MLX5_COMMAND_STR_CASE(QUERY_SRQ);
 482         MLX5_COMMAND_STR_CASE(ARM_RQ);
 483         MLX5_COMMAND_STR_CASE(CREATE_XRC_SRQ);
 484         MLX5_COMMAND_STR_CASE(DESTROY_XRC_SRQ);
 485         MLX5_COMMAND_STR_CASE(QUERY_XRC_SRQ);
 486         MLX5_COMMAND_STR_CASE(ARM_XRC_SRQ);
 487         MLX5_COMMAND_STR_CASE(CREATE_DCT);
 488         MLX5_COMMAND_STR_CASE(DESTROY_DCT);
 489         MLX5_COMMAND_STR_CASE(DRAIN_DCT);
 490         MLX5_COMMAND_STR_CASE(QUERY_DCT);
 491         MLX5_COMMAND_STR_CASE(ARM_DCT_FOR_KEY_VIOLATION);
 492         MLX5_COMMAND_STR_CASE(QUERY_VPORT_STATE);
 493         MLX5_COMMAND_STR_CASE(MODIFY_VPORT_STATE);
 494         MLX5_COMMAND_STR_CASE(QUERY_ESW_VPORT_CONTEXT);
 495         MLX5_COMMAND_STR_CASE(MODIFY_ESW_VPORT_CONTEXT);
 496         MLX5_COMMAND_STR_CASE(QUERY_NIC_VPORT_CONTEXT);
 497         MLX5_COMMAND_STR_CASE(MODIFY_NIC_VPORT_CONTEXT);
 498         MLX5_COMMAND_STR_CASE(QUERY_ROCE_ADDRESS);
 499         MLX5_COMMAND_STR_CASE(SET_ROCE_ADDRESS);
 500         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_CONTEXT);
 501         MLX5_COMMAND_STR_CASE(MODIFY_HCA_VPORT_CONTEXT);
 502         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_GID);
 503         MLX5_COMMAND_STR_CASE(QUERY_HCA_VPORT_PKEY);
 504         MLX5_COMMAND_STR_CASE(QUERY_VPORT_COUNTER);
 505         MLX5_COMMAND_STR_CASE(ALLOC_Q_COUNTER);
 506         MLX5_COMMAND_STR_CASE(DEALLOC_Q_COUNTER);
 507         MLX5_COMMAND_STR_CASE(QUERY_Q_COUNTER);
 508         MLX5_COMMAND_STR_CASE(SET_RATE_LIMIT);
 509         MLX5_COMMAND_STR_CASE(QUERY_RATE_LIMIT);
 510         MLX5_COMMAND_STR_CASE(CREATE_SCHEDULING_ELEMENT);
 511         MLX5_COMMAND_STR_CASE(DESTROY_SCHEDULING_ELEMENT);
 512         MLX5_COMMAND_STR_CASE(QUERY_SCHEDULING_ELEMENT);
 513         MLX5_COMMAND_STR_CASE(MODIFY_SCHEDULING_ELEMENT);
 514         MLX5_COMMAND_STR_CASE(CREATE_QOS_PARA_VPORT);
 515         MLX5_COMMAND_STR_CASE(DESTROY_QOS_PARA_VPORT);
 516         MLX5_COMMAND_STR_CASE(ALLOC_PD);
 517         MLX5_COMMAND_STR_CASE(DEALLOC_PD);
 518         MLX5_COMMAND_STR_CASE(ALLOC_UAR);
 519         MLX5_COMMAND_STR_CASE(DEALLOC_UAR);
 520         MLX5_COMMAND_STR_CASE(CONFIG_INT_MODERATION);
 521         MLX5_COMMAND_STR_CASE(ACCESS_REG);
 522         MLX5_COMMAND_STR_CASE(ATTACH_TO_MCG);
 523         MLX5_COMMAND_STR_CASE(DETACH_FROM_MCG);
 524         MLX5_COMMAND_STR_CASE(GET_DROPPED_PACKET_LOG);
 525         MLX5_COMMAND_STR_CASE(MAD_IFC);
 526         MLX5_COMMAND_STR_CASE(QUERY_MAD_DEMUX);
 527         MLX5_COMMAND_STR_CASE(SET_MAD_DEMUX);
 528         MLX5_COMMAND_STR_CASE(NOP);
 529         MLX5_COMMAND_STR_CASE(ALLOC_XRCD);
 530         MLX5_COMMAND_STR_CASE(DEALLOC_XRCD);
 531         MLX5_COMMAND_STR_CASE(ALLOC_TRANSPORT_DOMAIN);
 532         MLX5_COMMAND_STR_CASE(DEALLOC_TRANSPORT_DOMAIN);
 533         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATUS);
 534         MLX5_COMMAND_STR_CASE(MODIFY_CONG_STATUS);
 535         MLX5_COMMAND_STR_CASE(QUERY_CONG_PARAMS);
 536         MLX5_COMMAND_STR_CASE(MODIFY_CONG_PARAMS);
 537         MLX5_COMMAND_STR_CASE(QUERY_CONG_STATISTICS);
 538         MLX5_COMMAND_STR_CASE(ADD_VXLAN_UDP_DPORT);
 539         MLX5_COMMAND_STR_CASE(DELETE_VXLAN_UDP_DPORT);
 540         MLX5_COMMAND_STR_CASE(SET_L2_TABLE_ENTRY);
 541         MLX5_COMMAND_STR_CASE(QUERY_L2_TABLE_ENTRY);
 542         MLX5_COMMAND_STR_CASE(DELETE_L2_TABLE_ENTRY);
 543         MLX5_COMMAND_STR_CASE(SET_WOL_ROL);
 544         MLX5_COMMAND_STR_CASE(QUERY_WOL_ROL);
 545         MLX5_COMMAND_STR_CASE(CREATE_LAG);
 546         MLX5_COMMAND_STR_CASE(MODIFY_LAG);
 547         MLX5_COMMAND_STR_CASE(QUERY_LAG);
 548         MLX5_COMMAND_STR_CASE(DESTROY_LAG);
 549         MLX5_COMMAND_STR_CASE(CREATE_VPORT_LAG);
 550         MLX5_COMMAND_STR_CASE(DESTROY_VPORT_LAG);
 551         MLX5_COMMAND_STR_CASE(CREATE_TIR);
 552         MLX5_COMMAND_STR_CASE(MODIFY_TIR);
 553         MLX5_COMMAND_STR_CASE(DESTROY_TIR);
 554         MLX5_COMMAND_STR_CASE(QUERY_TIR);
 555         MLX5_COMMAND_STR_CASE(CREATE_SQ);
 556         MLX5_COMMAND_STR_CASE(MODIFY_SQ);
 557         MLX5_COMMAND_STR_CASE(DESTROY_SQ);
 558         MLX5_COMMAND_STR_CASE(QUERY_SQ);
 559         MLX5_COMMAND_STR_CASE(CREATE_RQ);
 560         MLX5_COMMAND_STR_CASE(MODIFY_RQ);
 561         MLX5_COMMAND_STR_CASE(DESTROY_RQ);
 562         MLX5_COMMAND_STR_CASE(QUERY_RQ);
 563         MLX5_COMMAND_STR_CASE(CREATE_RMP);
 564         MLX5_COMMAND_STR_CASE(MODIFY_RMP);
 565         MLX5_COMMAND_STR_CASE(DESTROY_RMP);
 566         MLX5_COMMAND_STR_CASE(QUERY_RMP);
 567         MLX5_COMMAND_STR_CASE(CREATE_TIS);
 568         MLX5_COMMAND_STR_CASE(MODIFY_TIS);
 569         MLX5_COMMAND_STR_CASE(DESTROY_TIS);
 570         MLX5_COMMAND_STR_CASE(QUERY_TIS);
 571         MLX5_COMMAND_STR_CASE(CREATE_RQT);
 572         MLX5_COMMAND_STR_CASE(MODIFY_RQT);
 573         MLX5_COMMAND_STR_CASE(DESTROY_RQT);
 574         MLX5_COMMAND_STR_CASE(QUERY_RQT);
 575         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ROOT);
 576         MLX5_COMMAND_STR_CASE(CREATE_FLOW_TABLE);
 577         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_TABLE);
 578         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE);
 579         MLX5_COMMAND_STR_CASE(CREATE_FLOW_GROUP);
 580         MLX5_COMMAND_STR_CASE(DESTROY_FLOW_GROUP);
 581         MLX5_COMMAND_STR_CASE(QUERY_FLOW_GROUP);
 582         MLX5_COMMAND_STR_CASE(SET_FLOW_TABLE_ENTRY);
 583         MLX5_COMMAND_STR_CASE(QUERY_FLOW_TABLE_ENTRY);
 584         MLX5_COMMAND_STR_CASE(DELETE_FLOW_TABLE_ENTRY);
 585         MLX5_COMMAND_STR_CASE(ALLOC_FLOW_COUNTER);
 586         MLX5_COMMAND_STR_CASE(DEALLOC_FLOW_COUNTER);
 587         MLX5_COMMAND_STR_CASE(QUERY_FLOW_COUNTER);
 588         MLX5_COMMAND_STR_CASE(MODIFY_FLOW_TABLE);
 589         MLX5_COMMAND_STR_CASE(ALLOC_ENCAP_HEADER);
 590         MLX5_COMMAND_STR_CASE(DEALLOC_ENCAP_HEADER);
 591         MLX5_COMMAND_STR_CASE(ALLOC_MODIFY_HEADER_CONTEXT);
 592         MLX5_COMMAND_STR_CASE(DEALLOC_MODIFY_HEADER_CONTEXT);
 593         MLX5_COMMAND_STR_CASE(FPGA_CREATE_QP);
 594         MLX5_COMMAND_STR_CASE(FPGA_MODIFY_QP);
 595         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP);
 596         MLX5_COMMAND_STR_CASE(FPGA_QUERY_QP_COUNTERS);
 597         MLX5_COMMAND_STR_CASE(FPGA_DESTROY_QP);
 598         default: return "unknown command opcode";
 599         }
 600 }
 601
 602 static const char *cmd_status_str(u8 status)
 603 {
 604         switch (status) {
 605         case MLX5_CMD_STAT_OK:
 606                 return "OK";
 607         case MLX5_CMD_STAT_INT_ERR:
 608                 return "internal error";
 609         case MLX5_CMD_STAT_BAD_OP_ERR:
 610                 return "bad operation";
 611         case MLX5_CMD_STAT_BAD_PARAM_ERR:
 612                 return "bad parameter";
 613         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:
 614                 return "bad system state";
 615         case MLX5_CMD_STAT_BAD_RES_ERR:
 616                 return "bad resource";
 617         case MLX5_CMD_STAT_RES_BUSY:
 618                 return "resource busy";
 619         case MLX5_CMD_STAT_LIM_ERR:
 620                 return "limits exceeded";
 621         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:
 622                 return "bad resource state";
 623         case MLX5_CMD_STAT_IX_ERR:
 624                 return "bad index";
 625         case MLX5_CMD_STAT_NO_RES_ERR:
 626                 return "no resources";
 627         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:
 628                 return "bad input length";
 629         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:
 630                 return "bad output length";
 631         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:
 632                 return "bad QP state";
 633         case MLX5_CMD_STAT_BAD_PKT_ERR:
 634                 return "bad packet (discarded)";
 635         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:
 636                 return "bad size too many outstanding CQEs";
 637         default:
 638                 return "unknown status";
 639         }
 640 }
 641
 642 static int cmd_status_to_err(u8 status)
 643 {
 644         switch (status) {
 645         case MLX5_CMD_STAT_OK:                          return 0;
 646         case MLX5_CMD_STAT_INT_ERR:                     return -EIO;
 647         case MLX5_CMD_STAT_BAD_OP_ERR:                  return -EINVAL;
 648         case MLX5_CMD_STAT_BAD_PARAM_ERR:               return -EINVAL;
 649         case MLX5_CMD_STAT_BAD_SYS_STATE_ERR:           return -EIO;
 650         case MLX5_CMD_STAT_BAD_RES_ERR:                 return -EINVAL;
 651         case MLX5_CMD_STAT_RES_BUSY:                    return -EBUSY;
 652         case MLX5_CMD_STAT_LIM_ERR:                     return -ENOMEM;
 653         case MLX5_CMD_STAT_BAD_RES_STATE_ERR:           return -EINVAL;
 654         case MLX5_CMD_STAT_IX_ERR:                      return -EINVAL;
 655         case MLX5_CMD_STAT_NO_RES_ERR:                  return -EAGAIN;
 656         case MLX5_CMD_STAT_BAD_INP_LEN_ERR:             return -EIO;
 657         case MLX5_CMD_STAT_BAD_OUTP_LEN_ERR:            return -EIO;
 658         case MLX5_CMD_STAT_BAD_QP_STATE_ERR:            return -EINVAL;
 659         case MLX5_CMD_STAT_BAD_PKT_ERR:                 return -EINVAL;
 660         case MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR:      return -EINVAL;
 661         default:                                        return -EIO;
 662         }
 663 }
 664
 665 struct mlx5_ifc_mbox_out_bits {
 666         u8         status[0x8];
 667         u8         reserved_at_8[0x18];
 668
 669         u8         syndrome[0x20];
 670
 671         u8         reserved_at_40[0x40];
 672 };
 673
 674 struct mlx5_ifc_mbox_in_bits {
 675         u8         opcode[0x10];
 676         u8         reserved_at_10[0x10];
 677
 678         u8         reserved_at_20[0x10];
 679         u8         op_mod[0x10];
 680
 681         u8         reserved_at_40[0x40];
 682 };
 683
 684 void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome)
 685 {
 686         *status = MLX5_GET(mbox_out, out, status);
 687         *syndrome = MLX5_GET(mbox_out, out, syndrome);
 688 }
 689
 690 static int mlx5_cmd_check(struct mlx5_core_dev *dev, void *in, void *out)
 691 {
 692         u32 syndrome;
 693         u8  status;
 694         u16 opcode;
 695         u16 op_mod;
 696
 697         mlx5_cmd_mbox_status(out, &status, &syndrome);
 698         if (!status)
 699                 return 0;
 700
 701         opcode = MLX5_GET(mbox_in, in, opcode);
 702         op_mod = MLX5_GET(mbox_in, in, op_mod);
 703
 704         mlx5_core_err(dev,
 705                       "%s(0x%x) op_mod(0x%x) failed, status %s(0x%x), syndrome (0x%x)\n",
 706                       mlx5_command_str(opcode),
 707                       opcode, op_mod,
 708                       cmd_status_str(status),
 709                       status,
 710                       syndrome);
 711
 712         return cmd_status_to_err(status);
 713 }
 714
 715 static void dump_command(struct mlx5_core_dev *dev,
 716                          struct mlx5_cmd_work_ent *ent, int input)
 717 {
 718         struct mlx5_cmd_msg *msg = input ? ent->in : ent->out;
 719         u16 op = MLX5_GET(mbox_in, ent->lay->in, opcode);
 720         struct mlx5_cmd_mailbox *next = msg->next;
 721         int data_only;
 722         u32 offset = 0;
 723         int dump_len;
 724
 725         data_only = !!(mlx5_core_debug_mask & (1 << MLX5_CMD_DATA));
 726
 727         if (data_only)
 728                 mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_DATA,
 729                                    "dump command data %s(0x%x) %s\n",
 730                                    mlx5_command_str(op), op,
 731                                    input ? "INPUT" : "OUTPUT");
 732         else
 733                 mlx5_core_dbg(dev, "dump command %s(0x%x) %s\n",
 734                               mlx5_command_str(op), op,
 735                               input ? "INPUT" : "OUTPUT");
 736
 737         if (data_only) {
 738                 if (input) {
 739                         dump_buf(ent->lay->in, sizeof(ent->lay->in), 1, offset);
 740                         offset += sizeof(ent->lay->in);
 741                 } else {
 742                         dump_buf(ent->lay->out, sizeof(ent->lay->out), 1, offset);
 743                         offset += sizeof(ent->lay->out);
 744                 }
 745         } else {
 746                 dump_buf(ent->lay, sizeof(*ent->lay), 0, offset);
 747                 offset += sizeof(*ent->lay);
 748         }
 749
 750         while (next && offset < msg->len) {
 751                 if (data_only) {
 752                         dump_len = min_t(int, MLX5_CMD_DATA_BLOCK_SIZE, msg->len - offset);
 753                         dump_buf(next->buf, dump_len, 1, offset);
 754                         offset += MLX5_CMD_DATA_BLOCK_SIZE;
 755                 } else {
 756                         mlx5_core_dbg(dev, "command block:\n");
 757                         dump_buf(next->buf, sizeof(struct mlx5_cmd_prot_block), 0, offset);
 758                         offset += sizeof(struct mlx5_cmd_prot_block);
 759                 }
 760                 next = next->next;
 761         }
 762
 763         if (data_only)
 764                 pr_debug("\n");
 765 }
 766
 767 static u16 msg_to_opcode(struct mlx5_cmd_msg *in)
 768 {
 769         return MLX5_GET(mbox_in, in->first.data, opcode);
 770 }
 771
 772 static void cb_timeout_handler(struct work_struct *work)
 773 {
 774         struct delayed_work *dwork = container_of(work, struct delayed_work,
 775                                                   work);
 776         struct mlx5_cmd_work_ent *ent = container_of(dwork,
 777                                                      struct mlx5_cmd_work_ent,
 778                                                      cb_timeout_work);
 779         struct mlx5_core_dev *dev = container_of(ent->cmd, struct mlx5_core_dev,
 780                                                  cmd);
 781
 782         ent->ret = -ETIMEDOUT;
 783         mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 784                        mlx5_command_str(msg_to_opcode(ent->in)),
 785                        msg_to_opcode(ent->in));
 786         mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 787 }
 788
 789 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg);
 790 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
 791                               struct mlx5_cmd_msg *msg);
 792
 793 static void cmd_work_handler(struct work_struct *work)
 794 {
 795         struct mlx5_cmd_work_ent *ent = container_of(work, struct mlx5_cmd_work_ent, work);
 796         struct mlx5_cmd *cmd = ent->cmd;
 797         struct mlx5_core_dev *dev = container_of(cmd, struct mlx5_core_dev, cmd);
 798         unsigned long cb_timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 799         struct mlx5_cmd_layout *lay;
 800         struct semaphore *sem;
 801         unsigned long flags;
 802         bool poll_cmd = ent->polling;
 803         int alloc_ret;
 804
 805
 806         sem = ent->page_queue ? &cmd->pages_sem : &cmd->sem;
 807         down(sem);
 808         if (!ent->page_queue) {
 809                 alloc_ret = alloc_ent(cmd);
 810                 if (alloc_ret < 0) {
 811                         mlx5_core_err(dev, "failed to allocate command entry\n");
 812                         if (ent->callback) {
 813                                 ent->callback(-EAGAIN, ent->context);
 814                                 mlx5_free_cmd_msg(dev, ent->out);
 815                                 free_msg(dev, ent->in);
 816                                 free_cmd(ent);
 817                         } else {
 818                                 ent->ret = -EAGAIN;
 819                                 complete(&ent->done);
 820                         }
 821                         up(sem);
 822                         return;
 823                 }
 824                 ent->idx = alloc_ret;
 825         } else {
 826                 ent->idx = cmd->max_reg_cmds;
 827                 spin_lock_irqsave(&cmd->alloc_lock, flags);
 828                 clear_bit(ent->idx, &cmd->bitmask);
 829                 spin_unlock_irqrestore(&cmd->alloc_lock, flags);
 830         }
 831
 832         cmd->ent_arr[ent->idx] = ent;
 833         set_bit(MLX5_CMD_ENT_STATE_PENDING_COMP, &ent->state);
 834         lay = get_inst(cmd, ent->idx);
 835         ent->lay = lay;
 836         memset(lay, 0, sizeof(*lay));
 837         memcpy(lay->in, ent->in->first.data, sizeof(lay->in));
 838         ent->op = be32_to_cpu(lay->in[0]) >> 16;
 839         if (ent->in->next)
 840                 lay->in_ptr = cpu_to_be64(ent->in->next->dma);
 841         lay->inlen = cpu_to_be32(ent->in->len);
 842         if (ent->out->next)
 843                 lay->out_ptr = cpu_to_be64(ent->out->next->dma);
 844         lay->outlen = cpu_to_be32(ent->out->len);
 845         lay->type = MLX5_PCI_CMD_XPORT;
 846         lay->token = ent->token;
 847         lay->status_own = CMD_OWNER_HW;
 848         set_signature(ent, !cmd->checksum_disabled);
 849         dump_command(dev, ent, 1);
 850         ent->ts1 = ktime_get_ns();
 851
 852         if (ent->callback)
 853                 schedule_delayed_work(&ent->cb_timeout_work, cb_timeout);
 854
 855         /* Skip sending command to fw if internal error */
 856         if (pci_channel_offline(dev->pdev) ||
 857             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
 858                 u8 status = 0;
 859                 u32 drv_synd;
 860
 861                 ent->ret = mlx5_internal_err_ret_value(dev, msg_to_opcode(ent->in), &drv_synd, &status);
 862                 MLX5_SET(mbox_out, ent->out, status, status);
 863                 MLX5_SET(mbox_out, ent->out, syndrome, drv_synd);
 864
 865                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 866                 return;
 867         }
 868
 869         /* ring doorbell after the descriptor is valid */
 870         mlx5_core_dbg(dev, "writing 0x%x to command doorbell\n", 1 << ent->idx);
 871         wmb();
 872         iowrite32be(1 << ent->idx, &dev->iseg->cmd_dbell);
 873         mmiowb();
 874         /* if not in polling don't use ent after this point */
 875         if (cmd->mode == CMD_MODE_POLLING || poll_cmd) {
 876                 poll_timeout(ent);
 877                 /* make sure we read the descriptor after ownership is SW */
 878                 rmb();
 879                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, (ent->ret == -ETIMEDOUT));
 880         }
 881 }
 882
 883 static const char *deliv_status_to_str(u8 status)
 884 {
 885         switch (status) {
 886         case MLX5_CMD_DELIVERY_STAT_OK:
 887                 return "no errors";
 888         case MLX5_CMD_DELIVERY_STAT_SIGNAT_ERR:
 889                 return "signature error";
 890         case MLX5_CMD_DELIVERY_STAT_TOK_ERR:
 891                 return "token error";
 892         case MLX5_CMD_DELIVERY_STAT_BAD_BLK_NUM_ERR:
 893                 return "bad block number";
 894         case MLX5_CMD_DELIVERY_STAT_OUT_PTR_ALIGN_ERR:
 895                 return "output pointer not aligned to block size";
 896         case MLX5_CMD_DELIVERY_STAT_IN_PTR_ALIGN_ERR:
 897                 return "input pointer not aligned to block size";
 898         case MLX5_CMD_DELIVERY_STAT_FW_ERR:
 899                 return "firmware internal error";
 900         case MLX5_CMD_DELIVERY_STAT_IN_LENGTH_ERR:
 901                 return "command input length error";
 902         case MLX5_CMD_DELIVERY_STAT_OUT_LENGTH_ERR:
 903                 return "command output length error";
 904         case MLX5_CMD_DELIVERY_STAT_RES_FLD_NOT_CLR_ERR:
 905                 return "reserved fields not cleared";
 906         case MLX5_CMD_DELIVERY_STAT_CMD_DESCR_ERR:
 907                 return "bad command descriptor type";
 908         default:
 909                 return "unknown status code";
 910         }
 911 }
 912
 913 static int wait_func(struct mlx5_core_dev *dev, struct mlx5_cmd_work_ent *ent)
 914 {
 915         unsigned long timeout = msecs_to_jiffies(MLX5_CMD_TIMEOUT_MSEC);
 916         struct mlx5_cmd *cmd = &dev->cmd;
 917         int err;
 918
 919         if (cmd->mode == CMD_MODE_POLLING || ent->polling) {
 920                 wait_for_completion(&ent->done);
 921         } else if (!wait_for_completion_timeout(&ent->done, timeout)) {
 922                 ent->ret = -ETIMEDOUT;
 923                 mlx5_cmd_comp_handler(dev, 1UL << ent->idx, true);
 924         }
 925
 926         err = ent->ret;
 927
 928         if (err == -ETIMEDOUT) {
 929                 mlx5_core_warn(dev, "%s(0x%x) timeout. Will cause a leak of a command resource\n",
 930                                mlx5_command_str(msg_to_opcode(ent->in)),
 931                                msg_to_opcode(ent->in));
 932         }
 933         mlx5_core_dbg(dev, "err %d, delivery status %s(%d)\n",
 934                       err, deliv_status_to_str(ent->status), ent->status);
 935
 936         return err;
 937 }
 938
 939 /*  Notes:
 940  *    1. Callback functions may not sleep
 941  *    2. page queue commands do not support asynchrous completion
 942  */
 943 static int mlx5_cmd_invoke(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *in,
 944                            struct mlx5_cmd_msg *out, void *uout, int uout_size,
 945                            mlx5_cmd_cbk_t callback,
 946                            void *context, int page_queue, u8 *status,
 947                            u8 token, bool force_polling)
 948 {
 949         struct mlx5_cmd *cmd = &dev->cmd;
 950         struct mlx5_cmd_work_ent *ent;
 951         struct mlx5_cmd_stats *stats;
 952         int err = 0;
 953         s64 ds;
 954         u16 op;
 955
 956         if (callback && page_queue)
 957                 return -EINVAL;
 958
 959         ent = alloc_cmd(cmd, in, out, uout, uout_size, callback, context,
 960                         page_queue);
 961         if (IS_ERR(ent))
 962                 return PTR_ERR(ent);
 963
 964         ent->token = token;
 965         ent->polling = force_polling;
 966
 967         if (!callback)
 968                 init_completion(&ent->done);
 969
 970         INIT_DELAYED_WORK(&ent->cb_timeout_work, cb_timeout_handler);
 971         INIT_WORK(&ent->work, cmd_work_handler);
 972         if (page_queue) {
 973                 cmd_work_handler(&ent->work);
 974         } else if (!queue_work(cmd->wq, &ent->work)) {
 975                 mlx5_core_warn(dev, "failed to queue work\n");
 976                 err = -ENOMEM;
 977                 goto out_free;
 978         }
 979
 980         if (callback)
 981                 goto out;
 982
 983         err = wait_func(dev, ent);
 984         if (err == -ETIMEDOUT)
 985                 goto out;
 986
 987         ds = ent->ts2 - ent->ts1;
 988         op = MLX5_GET(mbox_in, in->first.data, opcode);
 989         if (op < ARRAY_SIZE(cmd->stats)) {
 990                 stats = &cmd->stats[op];
 991                 spin_lock_irq(&stats->lock);
 992                 stats->sum += ds;
 993                 ++stats->n;
 994                 spin_unlock_irq(&stats->lock);
 995         }
 996         mlx5_core_dbg_mask(dev, 1 << MLX5_CMD_TIME,
 997                            "fw exec time for %s is %lld nsec\n",
 998                            mlx5_command_str(op), ds);
 999         *status = ent->status;
1000
1001 out_free:
1002         free_cmd(ent);
1003 out:
1004         return err;
1005 }
1006
1007 static ssize_t dbg_write(struct file *filp, const char __user *buf,
1008                          size_t count, loff_t *pos)
1009 {
1010         struct mlx5_core_dev *dev = filp->private_data;
1011         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1012         char lbuf[3];
1013         int err;
1014
1015         if (!dbg->in_msg || !dbg->out_msg)
1016                 return -ENOMEM;
1017
1018         if (copy_from_user(lbuf, buf, sizeof(lbuf)))
1019                 return -EFAULT;
1020
1021         lbuf[sizeof(lbuf) - 1] = 0;
1022
1023         if (strcmp(lbuf, "go"))
1024                 return -EINVAL;
1025
1026         err = mlx5_cmd_exec(dev, dbg->in_msg, dbg->inlen, dbg->out_msg, dbg->outlen);
1027
1028         return err ? err : count;
1029 }
1030
1031 static const struct file_operations fops = {
1032         .owner  = THIS_MODULE,
1033         .open   = simple_open,
1034         .write  = dbg_write,
1035 };
1036
1037 static int mlx5_copy_to_msg(struct mlx5_cmd_msg *to, void *from, int size,
1038                             u8 token)
1039 {
1040         struct mlx5_cmd_prot_block *block;
1041         struct mlx5_cmd_mailbox *next;
1042         int copy;
1043
1044         if (!to || !from)
1045                 return -ENOMEM;
1046
1047         copy = min_t(int, size, sizeof(to->first.data));
1048         memcpy(to->first.data, from, copy);
1049         size -= copy;
1050         from += copy;
1051
1052         next = to->next;
1053         while (size) {
1054                 if (!next) {
1055                         /* this is a BUG */
1056                         return -ENOMEM;
1057                 }
1058
1059                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1060                 block = next->buf;
1061                 memcpy(block->data, from, copy);
1062                 from += copy;
1063                 size -= copy;
1064                 block->token = token;
1065                 next = next->next;
1066         }
1067
1068         return 0;
1069 }
1070
1071 static int mlx5_copy_from_msg(void *to, struct mlx5_cmd_msg *from, int size)
1072 {
1073         struct mlx5_cmd_prot_block *block;
1074         struct mlx5_cmd_mailbox *next;
1075         int copy;
1076
1077         if (!to || !from)
1078                 return -ENOMEM;
1079
1080         copy = min_t(int, size, sizeof(from->first.data));
1081         memcpy(to, from->first.data, copy);
1082         size -= copy;
1083         to += copy;
1084
1085         next = from->next;
1086         while (size) {
1087                 if (!next) {
1088                         /* this is a BUG */
1089                         return -ENOMEM;
1090                 }
1091
1092                 copy = min_t(int, size, MLX5_CMD_DATA_BLOCK_SIZE);
1093                 block = next->buf;
1094
1095                 memcpy(to, block->data, copy);
1096                 to += copy;
1097                 size -= copy;
1098                 next = next->next;
1099         }
1100
1101         return 0;
1102 }
1103
1104 static struct mlx5_cmd_mailbox *alloc_cmd_box(struct mlx5_core_dev *dev,
1105                                               gfp_t flags)
1106 {
1107         struct mlx5_cmd_mailbox *mailbox;
1108
1109         mailbox = kmalloc(sizeof(*mailbox), flags);
1110         if (!mailbox)
1111                 return ERR_PTR(-ENOMEM);
1112
1113         mailbox->buf = pci_pool_zalloc(dev->cmd.pool, flags,
1114                                        &mailbox->dma);
1115         if (!mailbox->buf) {
1116                 mlx5_core_dbg(dev, "failed allocation\n");
1117                 kfree(mailbox);
1118                 return ERR_PTR(-ENOMEM);
1119         }
1120         mailbox->next = NULL;
1121
1122         return mailbox;
1123 }
1124
1125 static void free_cmd_box(struct mlx5_core_dev *dev,
1126                          struct mlx5_cmd_mailbox *mailbox)
1127 {
1128         pci_pool_free(dev->cmd.pool, mailbox->buf, mailbox->dma);
1129         kfree(mailbox);
1130 }
1131
1132 static struct mlx5_cmd_msg *mlx5_alloc_cmd_msg(struct mlx5_core_dev *dev,
1133                                                gfp_t flags, int size,
1134                                                u8 token)
1135 {
1136         struct mlx5_cmd_mailbox *tmp, *head = NULL;
1137         struct mlx5_cmd_prot_block *block;
1138         struct mlx5_cmd_msg *msg;
1139         int blen;
1140         int err;
1141         int n;
1142         int i;
1143
1144         msg = kzalloc(sizeof(*msg), flags);
1145         if (!msg)
1146                 return ERR_PTR(-ENOMEM);
1147
1148         blen = size - min_t(int, sizeof(msg->first.data), size);
1149         n = (blen + MLX5_CMD_DATA_BLOCK_SIZE - 1) / MLX5_CMD_DATA_BLOCK_SIZE;
1150
1151         for (i = 0; i < n; i++) {
1152                 tmp = alloc_cmd_box(dev, flags);
1153                 if (IS_ERR(tmp)) {
1154                         mlx5_core_warn(dev, "failed allocating block\n");
1155                         err = PTR_ERR(tmp);
1156                         goto err_alloc;
1157                 }
1158
1159                 block = tmp->buf;
1160                 tmp->next = head;
1161                 block->next = cpu_to_be64(tmp->next ? tmp->next->dma : 0);
1162                 block->block_num = cpu_to_be32(n - i - 1);
1163                 block->token = token;
1164                 head = tmp;
1165         }
1166         msg->next = head;
1167         msg->len = size;
1168         return msg;
1169
1170 err_alloc:
1171         while (head) {
1172                 tmp = head->next;
1173                 free_cmd_box(dev, head);
1174                 head = tmp;
1175         }
1176         kfree(msg);
1177
1178         return ERR_PTR(err);
1179 }
1180
1181 static void mlx5_free_cmd_msg(struct mlx5_core_dev *dev,
1182                               struct mlx5_cmd_msg *msg)
1183 {
1184         struct mlx5_cmd_mailbox *head = msg->next;
1185         struct mlx5_cmd_mailbox *next;
1186
1187         while (head) {
1188                 next = head->next;
1189                 free_cmd_box(dev, head);
1190                 head = next;
1191         }
1192         kfree(msg);
1193 }
1194
1195 static ssize_t data_write(struct file *filp, const char __user *buf,
1196                           size_t count, loff_t *pos)
1197 {
1198         struct mlx5_core_dev *dev = filp->private_data;
1199         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1200         void *ptr;
1201
1202         if (*pos != 0)
1203                 return -EINVAL;
1204
1205         kfree(dbg->in_msg);
1206         dbg->in_msg = NULL;
1207         dbg->inlen = 0;
1208         ptr = memdup_user(buf, count);
1209         if (IS_ERR(ptr))
1210                 return PTR_ERR(ptr);
1211         dbg->in_msg = ptr;
1212         dbg->inlen = count;
1213
1214         *pos = count;
1215
1216         return count;
1217 }
1218
1219 static ssize_t data_read(struct file *filp, char __user *buf, size_t count,
1220                          loff_t *pos)
1221 {
1222         struct mlx5_core_dev *dev = filp->private_data;
1223         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1224         int copy;
1225
1226         if (*pos)
1227                 return 0;
1228
1229         if (!dbg->out_msg)
1230                 return -ENOMEM;
1231
1232         copy = min_t(int, count, dbg->outlen);
1233         if (copy_to_user(buf, dbg->out_msg, copy))
1234                 return -EFAULT;
1235
1236         *pos += copy;
1237
1238         return copy;
1239 }
1240
1241 static const struct file_operations dfops = {
1242         .owner  = THIS_MODULE,
1243         .open   = simple_open,
1244         .write  = data_write,
1245         .read   = data_read,
1246 };
1247
1248 static ssize_t outlen_read(struct file *filp, char __user *buf, size_t count,
1249                            loff_t *pos)
1250 {
1251         struct mlx5_core_dev *dev = filp->private_data;
1252         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1253         char outlen[8];
1254         int err;
1255
1256         if (*pos)
1257                 return 0;
1258
1259         err = snprintf(outlen, sizeof(outlen), "%d", dbg->outlen);
1260         if (err < 0)
1261                 return err;
1262
1263         if (copy_to_user(buf, &outlen, err))
1264                 return -EFAULT;
1265
1266         *pos += err;
1267
1268         return err;
1269 }
1270
1271 static ssize_t outlen_write(struct file *filp, const char __user *buf,
1272                             size_t count, loff_t *pos)
1273 {
1274         struct mlx5_core_dev *dev = filp->private_data;
1275         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1276         char outlen_str[8];
1277         int outlen;
1278         void *ptr;
1279         int err;
1280
1281         if (*pos != 0 || count > 6)
1282                 return -EINVAL;
1283
1284         kfree(dbg->out_msg);
1285         dbg->out_msg = NULL;
1286         dbg->outlen = 0;
1287
1288         if (copy_from_user(outlen_str, buf, count))
1289                 return -EFAULT;
1290
1291         outlen_str[7] = 0;
1292
1293         err = sscanf(outlen_str, "%d", &outlen);
1294         if (err < 0)
1295                 return err;
1296
1297         ptr = kzalloc(outlen, GFP_KERNEL);
1298         if (!ptr)
1299                 return -ENOMEM;
1300
1301         dbg->out_msg = ptr;
1302         dbg->outlen = outlen;
1303
1304         *pos = count;
1305
1306         return count;
1307 }
1308
1309 static const struct file_operations olfops = {
1310         .owner  = THIS_MODULE,
1311         .open   = simple_open,
1312         .write  = outlen_write,
1313         .read   = outlen_read,
1314 };
1315
1316 static void set_wqname(struct mlx5_core_dev *dev)
1317 {
1318         struct mlx5_cmd *cmd = &dev->cmd;
1319
1320         snprintf(cmd->wq_name, sizeof(cmd->wq_name), "mlx5_cmd_%s",
1321                  dev_name(&dev->pdev->dev));
1322 }
1323
1324 static void clean_debug_files(struct mlx5_core_dev *dev)
1325 {
1326         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1327
1328         if (!mlx5_debugfs_root)
1329                 return;
1330
1331         mlx5_cmdif_debugfs_cleanup(dev);
1332         debugfs_remove_recursive(dbg->dbg_root);
1333 }
1334
1335 static int create_debugfs_files(struct mlx5_core_dev *dev)
1336 {
1337         struct mlx5_cmd_debug *dbg = &dev->cmd.dbg;
1338         int err = -ENOMEM;
1339
1340         if (!mlx5_debugfs_root)
1341                 return 0;
1342
1343         dbg->dbg_root = debugfs_create_dir("cmd", dev->priv.dbg_root);
1344         if (!dbg->dbg_root)
1345                 return err;
1346
1347         dbg->dbg_in = debugfs_create_file("in", 0400, dbg->dbg_root,
1348                                           dev, &dfops);
1349         if (!dbg->dbg_in)
1350                 goto err_dbg;
1351
1352         dbg->dbg_out = debugfs_create_file("out", 0200, dbg->dbg_root,
1353                                            dev, &dfops);
1354         if (!dbg->dbg_out)
1355                 goto err_dbg;
1356
1357         dbg->dbg_outlen = debugfs_create_file("out_len", 0600, dbg->dbg_root,
1358                                               dev, &olfops);
1359         if (!dbg->dbg_outlen)
1360                 goto err_dbg;
1361
1362         dbg->dbg_status = debugfs_create_u8("status", 0600, dbg->dbg_root,
1363                                             &dbg->status);
1364         if (!dbg->dbg_status)
1365                 goto err_dbg;
1366
1367         dbg->dbg_run = debugfs_create_file("run", 0200, dbg->dbg_root, dev, &fops);
1368         if (!dbg->dbg_run)
1369                 goto err_dbg;
1370
1371         mlx5_cmdif_debugfs_init(dev);
1372
1373         return 0;
1374
1375 err_dbg:
1376         clean_debug_files(dev);
1377         return err;
1378 }
1379
1380 static void mlx5_cmd_change_mod(struct mlx5_core_dev *dev, int mode)
1381 {
1382         struct mlx5_cmd *cmd = &dev->cmd;
1383         int i;
1384
1385         for (i = 0; i < cmd->max_reg_cmds; i++)
1386                 down(&cmd->sem);
1387         down(&cmd->pages_sem);
1388
1389         cmd->mode = mode;
1390
1391         up(&cmd->pages_sem);
1392         for (i = 0; i < cmd->max_reg_cmds; i++)
1393                 up(&cmd->sem);
1394 }
1395
1396 void mlx5_cmd_use_events(struct mlx5_core_dev *dev)
1397 {
1398         mlx5_cmd_change_mod(dev, CMD_MODE_EVENTS);
1399 }
1400
1401 void mlx5_cmd_use_polling(struct mlx5_core_dev *dev)
1402 {
1403         mlx5_cmd_change_mod(dev, CMD_MODE_POLLING);
1404 }
1405
1406 static void free_msg(struct mlx5_core_dev *dev, struct mlx5_cmd_msg *msg)
1407 {
1408         unsigned long flags;
1409
1410         if (msg->parent) {
1411                 spin_lock_irqsave(&msg->parent->lock, flags);
1412                 list_add_tail(&msg->list, &msg->parent->head);
1413                 spin_unlock_irqrestore(&msg->parent->lock, flags);
1414         } else {
1415                 mlx5_free_cmd_msg(dev, msg);
1416         }
1417 }
1418
1419 void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec, bool forced)
1420 {
1421         struct mlx5_cmd *cmd = &dev->cmd;
1422         struct mlx5_cmd_work_ent *ent;
1423         mlx5_cmd_cbk_t callback;
1424         void *context;
1425         int err;
1426         int i;
1427         s64 ds;
1428         struct mlx5_cmd_stats *stats;
1429         unsigned long flags;
1430         unsigned long vector;
1431
1432         /* there can be at most 32 command queues */
1433         vector = vec & 0xffffffff;
1434         for (i = 0; i < (1 << cmd->log_sz); i++) {
1435                 if (test_bit(i, &vector)) {
1436                         struct semaphore *sem;
1437
1438                         ent = cmd->ent_arr[i];
1439
1440                         /* if we already completed the command, ignore it */
1441                         if (!test_and_clear_bit(MLX5_CMD_ENT_STATE_PENDING_COMP,
1442                                                 &ent->state)) {
1443                                 /* only real completion can free the cmd slot */
1444                                 if (!forced) {
1445                                         mlx5_core_err(dev, "Command completion arrived after timeout (entry idx = %d).\n",
1446                                                       ent->idx);
1447                                         free_ent(cmd, ent->idx);
1448                                         free_cmd(ent);
1449                                 }
1450                                 continue;
1451                         }
1452
1453                         if (ent->callback)
1454                                 cancel_delayed_work(&ent->cb_timeout_work);
1455                         if (ent->page_queue)
1456                                 sem = &cmd->pages_sem;
1457                         else
1458                                 sem = &cmd->sem;
1459                         ent->ts2 = ktime_get_ns();
1460                         memcpy(ent->out->first.data, ent->lay->out, sizeof(ent->lay->out));
1461                         dump_command(dev, ent, 0);
1462                         if (!ent->ret) {
1463                                 if (!cmd->checksum_disabled)
1464                                         ent->ret = verify_signature(ent);
1465                                 else
1466                                         ent->ret = 0;
1467                                 if (vec & MLX5_TRIGGERED_CMD_COMP)
1468                                         ent->status = MLX5_DRIVER_STATUS_ABORTED;
1469                                 else
1470                                         ent->status = ent->lay->status_own >> 1;
1471
1472                                 mlx5_core_dbg(dev, "command completed. ret 0x%x, delivery status %s(0x%x)\n",
1473                                               ent->ret, deliv_status_to_str(ent->status), ent->status);
1474                         }
1475
1476                         /* only real completion will free the entry slot */
1477                         if (!forced)
1478                                 free_ent(cmd, ent->idx);
1479
1480                         if (ent->callback) {
1481                                 ds = ent->ts2 - ent->ts1;
1482                                 if (ent->op < ARRAY_SIZE(cmd->stats)) {
1483                                         stats = &cmd->stats[ent->op];
1484                                         spin_lock_irqsave(&stats->lock, flags);
1485                                         stats->sum += ds;
1486                                         ++stats->n;
1487                                         spin_unlock_irqrestore(&stats->lock, flags);
1488                                 }
1489
1490                                 callback = ent->callback;
1491                                 context = ent->context;
1492                                 err = ent->ret;
1493                                 if (!err) {
1494                                         err = mlx5_copy_from_msg(ent->uout,
1495                                                                  ent->out,
1496                                                                  ent->uout_size);
1497
1498                                         err = err ? err : mlx5_cmd_check(dev,
1499                                                                         ent->in->first.data,
1500                                                                         ent->uout);
1501                                 }
1502
1503                                 mlx5_free_cmd_msg(dev, ent->out);
1504                                 free_msg(dev, ent->in);
1505
1506                                 err = err ? err : ent->status;
1507                                 if (!forced)
1508                                         free_cmd(ent);
1509                                 callback(err, context);
1510                         } else {
1511                                 complete(&ent->done);
1512                         }
1513                         up(sem);
1514                 }
1515         }
1516 }
1517 EXPORT_SYMBOL(mlx5_cmd_comp_handler);
1518
1519 static int status_to_err(u8 status)
1520 {
1521         return status ? -1 : 0; /* TBD more meaningful codes */
1522 }
1523
1524 static struct mlx5_cmd_msg *alloc_msg(struct mlx5_core_dev *dev, int in_size,
1525                                       gfp_t gfp)
1526 {
1527         struct mlx5_cmd_msg *msg = ERR_PTR(-ENOMEM);
1528         struct cmd_msg_cache *ch = NULL;
1529         struct mlx5_cmd *cmd = &dev->cmd;
1530         int i;
1531
1532         if (in_size <= 16)
1533                 goto cache_miss;
1534
1535         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1536                 ch = &cmd->cache[i];
1537                 if (in_size > ch->max_inbox_size)
1538                         continue;
1539                 spin_lock_irq(&ch->lock);
1540                 if (list_empty(&ch->head)) {
1541                         spin_unlock_irq(&ch->lock);
1542                         continue;
1543                 }
1544                 msg = list_entry(ch->head.next, typeof(*msg), list);
1545                 /* For cached lists, we must explicitly state what is
1546                  * the real size
1547                  */
1548                 msg->len = in_size;
1549                 list_del(&msg->list);
1550                 spin_unlock_irq(&ch->lock);
1551                 break;
1552         }
1553
1554         if (!IS_ERR(msg))
1555                 return msg;
1556
1557 cache_miss:
1558         msg = mlx5_alloc_cmd_msg(dev, gfp, in_size, 0);
1559         return msg;
1560 }
1561
1562 static int is_manage_pages(void *in)
1563 {
1564         return MLX5_GET(mbox_in, in, opcode) == MLX5_CMD_OP_MANAGE_PAGES;
1565 }
1566
1567 static int cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1568                     int out_size, mlx5_cmd_cbk_t callback, void *context,
1569                     bool force_polling)
1570 {
1571         struct mlx5_cmd_msg *inb;
1572         struct mlx5_cmd_msg *outb;
1573         int pages_queue;
1574         gfp_t gfp;
1575         int err;
1576         u8 status = 0;
1577         u32 drv_synd;
1578         u8 token;
1579
1580         if (pci_channel_offline(dev->pdev) ||
1581             dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1582                 u16 opcode = MLX5_GET(mbox_in, in, opcode);
1583
1584                 err = mlx5_internal_err_ret_value(dev, opcode, &drv_synd, &status);
1585                 MLX5_SET(mbox_out, out, status, status);
1586                 MLX5_SET(mbox_out, out, syndrome, drv_synd);
1587                 return err;
1588         }
1589
1590         pages_queue = is_manage_pages(in);
1591         gfp = callback ? GFP_ATOMIC : GFP_KERNEL;
1592
1593         inb = alloc_msg(dev, in_size, gfp);
1594         if (IS_ERR(inb)) {
1595                 err = PTR_ERR(inb);
1596                 return err;
1597         }
1598
1599         token = alloc_token(&dev->cmd);
1600
1601         err = mlx5_copy_to_msg(inb, in, in_size, token);
1602         if (err) {
1603                 mlx5_core_warn(dev, "err %d\n", err);
1604                 goto out_in;
1605         }
1606
1607         outb = mlx5_alloc_cmd_msg(dev, gfp, out_size, token);
1608         if (IS_ERR(outb)) {
1609                 err = PTR_ERR(outb);
1610                 goto out_in;
1611         }
1612
1613         err = mlx5_cmd_invoke(dev, inb, outb, out, out_size, callback, context,
1614                               pages_queue, &status, token, force_polling);
1615         if (err)
1616                 goto out_out;
1617
1618         mlx5_core_dbg(dev, "err %d, status %d\n", err, status);
1619         if (status) {
1620                 err = status_to_err(status);
1621                 goto out_out;
1622         }
1623
1624         if (!callback)
1625                 err = mlx5_copy_from_msg(out, outb, out_size);
1626
1627 out_out:
1628         if (!callback)
1629                 mlx5_free_cmd_msg(dev, outb);
1630
1631 out_in:
1632         if (!callback)
1633                 free_msg(dev, inb);
1634         return err;
1635 }
1636
1637 int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
1638                   int out_size)
1639 {
1640         int err;
1641
1642         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, false);
1643         return err ? : mlx5_cmd_check(dev, in, out);
1644 }
1645 EXPORT_SYMBOL(mlx5_cmd_exec);
1646
1647 int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size,
1648                      void *out, int out_size, mlx5_cmd_cbk_t callback,
1649                      void *context)
1650 {
1651         return cmd_exec(dev, in, in_size, out, out_size, callback, context,
1652                         false);
1653 }
1654 EXPORT_SYMBOL(mlx5_cmd_exec_cb);
1655
1656 int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
1657                           void *out, int out_size)
1658 {
1659         int err;
1660
1661         err = cmd_exec(dev, in, in_size, out, out_size, NULL, NULL, true);
1662
1663         return err ? : mlx5_cmd_check(dev, in, out);
1664 }
1665 EXPORT_SYMBOL(mlx5_cmd_exec_polling);
1666
1667 static void destroy_msg_cache(struct mlx5_core_dev *dev)
1668 {
1669         struct cmd_msg_cache *ch;
1670         struct mlx5_cmd_msg *msg;
1671         struct mlx5_cmd_msg *n;
1672         int i;
1673
1674         for (i = 0; i < MLX5_NUM_COMMAND_CACHES; i++) {
1675                 ch = &dev->cmd.cache[i];
1676                 list_for_each_entry_safe(msg, n, &ch->head, list) {
1677                         list_del(&msg->list);
1678                         mlx5_free_cmd_msg(dev, msg);
1679                 }
1680         }
1681 }
1682
1683 static unsigned cmd_cache_num_ent[MLX5_NUM_COMMAND_CACHES] = {
1684         512, 32, 16, 8, 2
1685 };
1686
1687 static unsigned cmd_cache_ent_size[MLX5_NUM_COMMAND_CACHES] = {
1688         16 + MLX5_CMD_DATA_BLOCK_SIZE,
1689         16 + MLX5_CMD_DATA_BLOCK_SIZE * 2,
1690         16 + MLX5_CMD_DATA_BLOCK_SIZE * 16,
1691         16 + MLX5_CMD_DATA_BLOCK_SIZE * 256,
1692         16 + MLX5_CMD_DATA_BLOCK_SIZE * 512,
1693 };
1694
1695 static void create_msg_cache(struct mlx5_core_dev *dev)
1696 {
1697         struct mlx5_cmd *cmd = &dev->cmd;
1698         struct cmd_msg_cache *ch;
1699         struct mlx5_cmd_msg *msg;
1700         int i;
1701         int k;
1702
1703         /* Initialize and fill the caches with initial entries */
1704         for (k = 0; k < MLX5_NUM_COMMAND_CACHES; k++) {
1705                 ch = &cmd->cache[k];
1706                 spin_lock_init(&ch->lock);
1707                 INIT_LIST_HEAD(&ch->head);
1708                 ch->num_ent = cmd_cache_num_ent[k];
1709                 ch->max_inbox_size = cmd_cache_ent_size[k];
1710                 for (i = 0; i < ch->num_ent; i++) {
1711                         msg = mlx5_alloc_cmd_msg(dev, GFP_KERNEL | __GFP_NOWARN,
1712                                                  ch->max_inbox_size, 0);
1713                         if (IS_ERR(msg))
1714                                 break;
1715                         msg->parent = ch;
1716                         list_add_tail(&msg->list, &ch->head);
1717                 }
1718         }
1719 }
1720
1721 static int alloc_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1722 {
1723         struct device *ddev = &dev->pdev->dev;
1724
1725         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE,
1726                                                  &cmd->alloc_dma, GFP_KERNEL);
1727         if (!cmd->cmd_alloc_buf)
1728                 return -ENOMEM;
1729
1730         /* make sure it is aligned to 4K */
1731         if (!((uintptr_t)cmd->cmd_alloc_buf & (MLX5_ADAPTER_PAGE_SIZE - 1))) {
1732                 cmd->cmd_buf = cmd->cmd_alloc_buf;
1733                 cmd->dma = cmd->alloc_dma;
1734                 cmd->alloc_size = MLX5_ADAPTER_PAGE_SIZE;
1735                 return 0;
1736         }
1737
1738         dma_free_coherent(ddev, MLX5_ADAPTER_PAGE_SIZE, cmd->cmd_alloc_buf,
1739                           cmd->alloc_dma);
1740         cmd->cmd_alloc_buf = dma_zalloc_coherent(ddev,
1741                                                  2 * MLX5_ADAPTER_PAGE_SIZE - 1,
1742                                                  &cmd->alloc_dma, GFP_KERNEL);
1743         if (!cmd->cmd_alloc_buf)
1744                 return -ENOMEM;
1745
1746         cmd->cmd_buf = PTR_ALIGN(cmd->cmd_alloc_buf, MLX5_ADAPTER_PAGE_SIZE);
1747         cmd->dma = ALIGN(cmd->alloc_dma, MLX5_ADAPTER_PAGE_SIZE);
1748         cmd->alloc_size = 2 * MLX5_ADAPTER_PAGE_SIZE - 1;
1749         return 0;
1750 }
1751
1752 static void free_cmd_page(struct mlx5_core_dev *dev, struct mlx5_cmd *cmd)
1753 {
1754         struct device *ddev = &dev->pdev->dev;
1755
1756         dma_free_coherent(ddev, cmd->alloc_size, cmd->cmd_alloc_buf,
1757                           cmd->alloc_dma);
1758 }
1759
1760 int mlx5_cmd_init(struct mlx5_core_dev *dev)
1761 {
1762         int size = sizeof(struct mlx5_cmd_prot_block);
1763         int align = roundup_pow_of_two(size);
1764         struct mlx5_cmd *cmd = &dev->cmd;
1765         u32 cmd_h, cmd_l;
1766         u16 cmd_if_rev;
1767         int err;
1768         int i;
1769
1770         memset(cmd, 0, sizeof(*cmd));
1771         cmd_if_rev = cmdif_rev(dev);
1772         if (cmd_if_rev != CMD_IF_REV) {
1773                 dev_err(&dev->pdev->dev,
1774                         "Driver cmdif rev(%d) differs from firmware's(%d)\n",
1775                         CMD_IF_REV, cmd_if_rev);
1776                 return -EINVAL;
1777         }
1778
1779         cmd->pool = pci_pool_create("mlx5_cmd", dev->pdev, size, align, 0);
1780         if (!cmd->pool)
1781                 return -ENOMEM;
1782
1783         err = alloc_cmd_page(dev, cmd);
1784         if (err)
1785                 goto err_free_pool;
1786
1787         cmd_l = ioread32be(&dev->iseg->cmdq_addr_l_sz) & 0xff;
1788         cmd->log_sz = cmd_l >> 4 & 0xf;
1789         cmd->log_stride = cmd_l & 0xf;
1790         if (1 << cmd->log_sz > MLX5_MAX_COMMANDS) {
1791                 dev_err(&dev->pdev->dev, "firmware reports too many outstanding commands %d\n",
1792                         1 << cmd->log_sz);
1793                 err = -EINVAL;
1794                 goto err_free_page;
1795         }
1796
1797         if (cmd->log_sz + cmd->log_stride > MLX5_ADAPTER_PAGE_SHIFT) {
1798                 dev_err(&dev->pdev->dev, "command queue size overflow\n");
1799                 err = -EINVAL;
1800                 goto err_free_page;
1801         }
1802
1803         cmd->checksum_disabled = 1;
1804         cmd->max_reg_cmds = (1 << cmd->log_sz) - 1;
1805         cmd->bitmask = (1 << cmd->max_reg_cmds) - 1;
1806
1807         cmd->cmdif_rev = ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16;
1808         if (cmd->cmdif_rev > CMD_IF_REV) {
1809                 dev_err(&dev->pdev->dev, "driver does not support command interface version. driver %d, firmware %d\n",
1810                         CMD_IF_REV, cmd->cmdif_rev);
1811                 err = -EOPNOTSUPP;
1812                 goto err_free_page;
1813         }
1814
1815         spin_lock_init(&cmd->alloc_lock);
1816         spin_lock_init(&cmd->token_lock);
1817         for (i = 0; i < ARRAY_SIZE(cmd->stats); i++)
1818                 spin_lock_init(&cmd->stats[i].lock);
1819
1820         sema_init(&cmd->sem, cmd->max_reg_cmds);
1821         sema_init(&cmd->pages_sem, 1);
1822
1823         cmd_h = (u32)((u64)(cmd->dma) >> 32);
1824         cmd_l = (u32)(cmd->dma);
1825         if (cmd_l & 0xfff) {
1826                 dev_err(&dev->pdev->dev, "invalid command queue address\n");
1827                 err = -ENOMEM;
1828                 goto err_free_page;
1829         }
1830
1831         iowrite32be(cmd_h, &dev->iseg->cmdq_addr_h);
1832         iowrite32be(cmd_l, &dev->iseg->cmdq_addr_l_sz);
1833
1834         /* Make sure firmware sees the complete address before we proceed */
1835         wmb();
1836
1837         mlx5_core_dbg(dev, "descriptor at dma 0x%llx\n", (unsigned long long)(cmd->dma));
1838
1839         cmd->mode = CMD_MODE_POLLING;
1840
1841         create_msg_cache(dev);
1842
1843         set_wqname(dev);
1844         cmd->wq = create_singlethread_workqueue(cmd->wq_name);
1845         if (!cmd->wq) {
1846                 dev_err(&dev->pdev->dev, "failed to create command workqueue\n");
1847                 err = -ENOMEM;
1848                 goto err_cache;
1849         }
1850
1851         err = create_debugfs_files(dev);
1852         if (err) {
1853                 err = -ENOMEM;
1854                 goto err_wq;
1855         }
1856
1857         return 0;
1858
1859 err_wq:
1860         destroy_workqueue(cmd->wq);
1861
1862 err_cache:
1863         destroy_msg_cache(dev);
1864
1865 err_free_page:
1866         free_cmd_page(dev, cmd);
1867
1868 err_free_pool:
1869         pci_pool_destroy(cmd->pool);
1870
1871         return err;
1872 }
1873 EXPORT_SYMBOL(mlx5_cmd_init);
1874
1875 void mlx5_cmd_cleanup(struct mlx5_core_dev *dev)
1876 {
1877         struct mlx5_cmd *cmd = &dev->cmd;
1878
1879         clean_debug_files(dev);
1880         destroy_workqueue(cmd->wq);
1881         destroy_msg_cache(dev);
1882         free_cmd_page(dev, cmd);
1883         pci_pool_destroy(cmd->pool);
1884 }
1885 EXPORT_SYMBOL(mlx5_cmd_cleanup);