drivers/net/ethernet/microchip/enc28j60.c

   1 /*
   2  * Microchip ENC28J60 ethernet driver (MAC + PHY)
   3  *
   4  * Copyright (C) 2007 Eurek srl
   5  * Author: Claudio Lanconelli <lanconelli.claudio@eptar.com>
   6  * based on enc28j60.c written by David Anders for 2.4 kernel version
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * $Id: enc28j60.c,v 1.22 2007/12/20 10:47:01 claudio Exp $
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/types.h>
  19 #include <linux/fcntl.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/string.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/netdevice.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/ethtool.h>
  27 #include <linux/tcp.h>
  28 #include <linux/skbuff.h>
  29 #include <linux/delay.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/of_net.h>
  32
  33 #include "enc28j60_hw.h"
  34
  35 #define DRV_NAME        "enc28j60"
  36 #define DRV_VERSION     "1.02"
  37
  38 #define SPI_OPLEN       1
  39
  40 #define ENC28J60_MSG_DEFAULT    \
  41         (NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN | NETIF_MSG_LINK)
  42
  43 /* Buffer size required for the largest SPI transfer (i.e., reading a
  44  * frame). */
  45 #define SPI_TRANSFER_BUF_LEN    (4 + MAX_FRAMELEN)
  46
  47 #define TX_TIMEOUT      (4 * HZ)
  48
  49 /* Max TX retries in case of collision as suggested by errata datasheet */
  50 #define MAX_TX_RETRYCOUNT       16
  51
  52 enum {
  53         RXFILTER_NORMAL,
  54         RXFILTER_MULTI,
  55         RXFILTER_PROMISC
  56 };
  57
  58 /* Driver local data */
  59 struct enc28j60_net {
  60         struct net_device *netdev;
  61         struct spi_device *spi;
  62         struct mutex lock;
  63         struct sk_buff *tx_skb;
  64         struct work_struct tx_work;
  65         struct work_struct irq_work;
  66         struct work_struct setrx_work;
  67         struct work_struct restart_work;
  68         u8 bank;                /* current register bank selected */
  69         u16 next_pk_ptr;        /* next packet pointer within FIFO */
  70         u16 max_pk_counter;     /* statistics: max packet counter */
  71         u16 tx_retry_count;
  72         bool hw_enable;
  73         bool full_duplex;
  74         int rxfilter;
  75         u32 msg_enable;
  76         u8 spi_transfer_buf[SPI_TRANSFER_BUF_LEN];
  77 };
  78
  79 /* use ethtool to change the level for any given device */
  80 static struct {
  81         u32 msg_enable;
  82 } debug = { -1 };
  83
  84 /*
  85  * SPI read buffer
  86  * wait for the SPI transfer and copy received data to destination
  87  */
  88 static int
  89 spi_read_buf(struct enc28j60_net *priv, int len, u8 *data)
  90 {
  91         u8 *rx_buf = priv->spi_transfer_buf + 4;
  92         u8 *tx_buf = priv->spi_transfer_buf;
  93         struct spi_transfer tx = {
  94                 .tx_buf = tx_buf,
  95                 .len = SPI_OPLEN,
  96         };
  97         struct spi_transfer rx = {
  98                 .rx_buf = rx_buf,
  99                 .len = len,
 100         };
 101         struct spi_message msg;
 102         int ret;
 103
 104         tx_buf[0] = ENC28J60_READ_BUF_MEM;
 105
 106         spi_message_init(&msg);
 107         spi_message_add_tail(&tx, &msg);
 108         spi_message_add_tail(&rx, &msg);
 109
 110         ret = spi_sync(priv->spi, &msg);
 111         if (ret == 0) {
 112                 memcpy(data, rx_buf, len);
 113                 ret = msg.status;
 114         }
 115         if (ret && netif_msg_drv(priv))
 116                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 117                         __func__, ret);
 118
 119         return ret;
 120 }
 121
 122 /*
 123  * SPI write buffer
 124  */
 125 static int spi_write_buf(struct enc28j60_net *priv, int len,
 126                          const u8 *data)
 127 {
 128         int ret;
 129
 130         if (len > SPI_TRANSFER_BUF_LEN - 1 || len <= 0)
 131                 ret = -EINVAL;
 132         else {
 133                 priv->spi_transfer_buf[0] = ENC28J60_WRITE_BUF_MEM;
 134                 memcpy(&priv->spi_transfer_buf[1], data, len);
 135                 ret = spi_write(priv->spi, priv->spi_transfer_buf, len + 1);
 136                 if (ret && netif_msg_drv(priv))
 137                         printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 138                                 __func__, ret);
 139         }
 140         return ret;
 141 }
 142
 143 /*
 144  * basic SPI read operation
 145  */
 146 static u8 spi_read_op(struct enc28j60_net *priv, u8 op,
 147                            u8 addr)
 148 {
 149         u8 tx_buf[2];
 150         u8 rx_buf[4];
 151         u8 val = 0;
 152         int ret;
 153         int slen = SPI_OPLEN;
 154
 155         /* do dummy read if needed */
 156         if (addr & SPRD_MASK)
 157                 slen++;
 158
 159         tx_buf[0] = op | (addr & ADDR_MASK);
 160         ret = spi_write_then_read(priv->spi, tx_buf, 1, rx_buf, slen);
 161         if (ret)
 162                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 163                         __func__, ret);
 164         else
 165                 val = rx_buf[slen - 1];
 166
 167         return val;
 168 }
 169
 170 /*
 171  * basic SPI write operation
 172  */
 173 static int spi_write_op(struct enc28j60_net *priv, u8 op,
 174                         u8 addr, u8 val)
 175 {
 176         int ret;
 177
 178         priv->spi_transfer_buf[0] = op | (addr & ADDR_MASK);
 179         priv->spi_transfer_buf[1] = val;
 180         ret = spi_write(priv->spi, priv->spi_transfer_buf, 2);
 181         if (ret && netif_msg_drv(priv))
 182                 printk(KERN_DEBUG DRV_NAME ": %s() failed: ret = %d\n",
 183                         __func__, ret);
 184         return ret;
 185 }
 186
 187 static void enc28j60_soft_reset(struct enc28j60_net *priv)
 188 {
 189         if (netif_msg_hw(priv))
 190                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
 191
 192         spi_write_op(priv, ENC28J60_SOFT_RESET, 0, ENC28J60_SOFT_RESET);
 193         /* Errata workaround #1, CLKRDY check is unreliable,
 194          * delay at least 1 mS instead */
 195         udelay(2000);
 196 }
 197
 198 /*
 199  * select the current register bank if necessary
 200  */
 201 static void enc28j60_set_bank(struct enc28j60_net *priv, u8 addr)
 202 {
 203         u8 b = (addr & BANK_MASK) >> 5;
 204
 205         /* These registers (EIE, EIR, ESTAT, ECON2, ECON1)
 206          * are present in all banks, no need to switch bank
 207          */
 208         if (addr >= EIE && addr <= ECON1)
 209                 return;
 210
 211         /* Clear or set each bank selection bit as needed */
 212         if ((b & ECON1_BSEL0) != (priv->bank & ECON1_BSEL0)) {
 213                 if (b & ECON1_BSEL0)
 214                         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
 215                                         ECON1_BSEL0);
 216                 else
 217                         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
 218                                         ECON1_BSEL0);
 219         }
 220         if ((b & ECON1_BSEL1) != (priv->bank & ECON1_BSEL1)) {
 221                 if (b & ECON1_BSEL1)
 222                         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, ECON1,
 223                                         ECON1_BSEL1);
 224                 else
 225                         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, ECON1,
 226                                         ECON1_BSEL1);
 227         }
 228         priv->bank = b;
 229 }
 230
 231 /*
 232  * Register access routines through the SPI bus.
 233  * Every register access comes in two flavours:
 234  * - nolock_xxx: caller needs to invoke mutex_lock, usually to access
 235  *   atomically more than one register
 236  * - locked_xxx: caller doesn't need to invoke mutex_lock, single access
 237  *
 238  * Some registers can be accessed through the bit field clear and
 239  * bit field set to avoid a read modify write cycle.
 240  */
 241
 242 /*
 243  * Register bit field Set
 244  */
 245 static void nolock_reg_bfset(struct enc28j60_net *priv,
 246                                       u8 addr, u8 mask)
 247 {
 248         enc28j60_set_bank(priv, addr);
 249         spi_write_op(priv, ENC28J60_BIT_FIELD_SET, addr, mask);
 250 }
 251
 252 static void locked_reg_bfset(struct enc28j60_net *priv,
 253                                       u8 addr, u8 mask)
 254 {
 255         mutex_lock(&priv->lock);
 256         nolock_reg_bfset(priv, addr, mask);
 257         mutex_unlock(&priv->lock);
 258 }
 259
 260 /*
 261  * Register bit field Clear
 262  */
 263 static void nolock_reg_bfclr(struct enc28j60_net *priv,
 264                                       u8 addr, u8 mask)
 265 {
 266         enc28j60_set_bank(priv, addr);
 267         spi_write_op(priv, ENC28J60_BIT_FIELD_CLR, addr, mask);
 268 }
 269
 270 static void locked_reg_bfclr(struct enc28j60_net *priv,
 271                                       u8 addr, u8 mask)
 272 {
 273         mutex_lock(&priv->lock);
 274         nolock_reg_bfclr(priv, addr, mask);
 275         mutex_unlock(&priv->lock);
 276 }
 277
 278 /*
 279  * Register byte read
 280  */
 281 static int nolock_regb_read(struct enc28j60_net *priv,
 282                                      u8 address)
 283 {
 284         enc28j60_set_bank(priv, address);
 285         return spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
 286 }
 287
 288 static int locked_regb_read(struct enc28j60_net *priv,
 289                                      u8 address)
 290 {
 291         int ret;
 292
 293         mutex_lock(&priv->lock);
 294         ret = nolock_regb_read(priv, address);
 295         mutex_unlock(&priv->lock);
 296
 297         return ret;
 298 }
 299
 300 /*
 301  * Register word read
 302  */
 303 static int nolock_regw_read(struct enc28j60_net *priv,
 304                                      u8 address)
 305 {
 306         int rl, rh;
 307
 308         enc28j60_set_bank(priv, address);
 309         rl = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address);
 310         rh = spi_read_op(priv, ENC28J60_READ_CTRL_REG, address + 1);
 311
 312         return (rh << 8) | rl;
 313 }
 314
 315 static int locked_regw_read(struct enc28j60_net *priv,
 316                                      u8 address)
 317 {
 318         int ret;
 319
 320         mutex_lock(&priv->lock);
 321         ret = nolock_regw_read(priv, address);
 322         mutex_unlock(&priv->lock);
 323
 324         return ret;
 325 }
 326
 327 /*
 328  * Register byte write
 329  */
 330 static void nolock_regb_write(struct enc28j60_net *priv,
 331                                        u8 address, u8 data)
 332 {
 333         enc28j60_set_bank(priv, address);
 334         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, data);
 335 }
 336
 337 static void locked_regb_write(struct enc28j60_net *priv,
 338                                        u8 address, u8 data)
 339 {
 340         mutex_lock(&priv->lock);
 341         nolock_regb_write(priv, address, data);
 342         mutex_unlock(&priv->lock);
 343 }
 344
 345 /*
 346  * Register word write
 347  */
 348 static void nolock_regw_write(struct enc28j60_net *priv,
 349                                        u8 address, u16 data)
 350 {
 351         enc28j60_set_bank(priv, address);
 352         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address, (u8) data);
 353         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, address + 1,
 354                      (u8) (data >> 8));
 355 }
 356
 357 static void locked_regw_write(struct enc28j60_net *priv,
 358                                        u8 address, u16 data)
 359 {
 360         mutex_lock(&priv->lock);
 361         nolock_regw_write(priv, address, data);
 362         mutex_unlock(&priv->lock);
 363 }
 364
 365 /*
 366  * Buffer memory read
 367  * Select the starting address and execute a SPI buffer read
 368  */
 369 static void enc28j60_mem_read(struct enc28j60_net *priv,
 370                                      u16 addr, int len, u8 *data)
 371 {
 372         mutex_lock(&priv->lock);
 373         nolock_regw_write(priv, ERDPTL, addr);
 374 #ifdef CONFIG_ENC28J60_WRITEVERIFY
 375         if (netif_msg_drv(priv)) {
 376                 u16 reg;
 377                 reg = nolock_regw_read(priv, ERDPTL);
 378                 if (reg != addr)
 379                         printk(KERN_DEBUG DRV_NAME ": %s() error writing ERDPT "
 380                                 "(0x%04x - 0x%04x)\n", __func__, reg, addr);
 381         }
 382 #endif
 383         spi_read_buf(priv, len, data);
 384         mutex_unlock(&priv->lock);
 385 }
 386
 387 /*
 388  * Write packet to enc28j60 TX buffer memory
 389  */
 390 static void
 391 enc28j60_packet_write(struct enc28j60_net *priv, int len, const u8 *data)
 392 {
 393         mutex_lock(&priv->lock);
 394         /* Set the write pointer to start of transmit buffer area */
 395         nolock_regw_write(priv, EWRPTL, TXSTART_INIT);
 396 #ifdef CONFIG_ENC28J60_WRITEVERIFY
 397         if (netif_msg_drv(priv)) {
 398                 u16 reg;
 399                 reg = nolock_regw_read(priv, EWRPTL);
 400                 if (reg != TXSTART_INIT)
 401                         printk(KERN_DEBUG DRV_NAME
 402                                 ": %s() ERWPT:0x%04x != 0x%04x\n",
 403                                 __func__, reg, TXSTART_INIT);
 404         }
 405 #endif
 406         /* Set the TXND pointer to correspond to the packet size given */
 407         nolock_regw_write(priv, ETXNDL, TXSTART_INIT + len);
 408         /* write per-packet control byte */
 409         spi_write_op(priv, ENC28J60_WRITE_BUF_MEM, 0, 0x00);
 410         if (netif_msg_hw(priv))
 411                 printk(KERN_DEBUG DRV_NAME
 412                         ": %s() after control byte ERWPT:0x%04x\n",
 413                         __func__, nolock_regw_read(priv, EWRPTL));
 414         /* copy the packet into the transmit buffer */
 415         spi_write_buf(priv, len, data);
 416         if (netif_msg_hw(priv))
 417                 printk(KERN_DEBUG DRV_NAME
 418                          ": %s() after write packet ERWPT:0x%04x, len=%d\n",
 419                          __func__, nolock_regw_read(priv, EWRPTL), len);
 420         mutex_unlock(&priv->lock);
 421 }
 422
 423 static unsigned long msec20_to_jiffies;
 424
 425 static int poll_ready(struct enc28j60_net *priv, u8 reg, u8 mask, u8 val)
 426 {
 427         unsigned long timeout = jiffies + msec20_to_jiffies;
 428
 429         /* 20 msec timeout read */
 430         while ((nolock_regb_read(priv, reg) & mask) != val) {
 431                 if (time_after(jiffies, timeout)) {
 432                         if (netif_msg_drv(priv))
 433                                 dev_dbg(&priv->spi->dev,
 434                                         "reg %02x ready timeout!\n", reg);
 435                         return -ETIMEDOUT;
 436                 }
 437                 cpu_relax();
 438         }
 439         return 0;
 440 }
 441
 442 /*
 443  * Wait until the PHY operation is complete.
 444  */
 445 static int wait_phy_ready(struct enc28j60_net *priv)
 446 {
 447         return poll_ready(priv, MISTAT, MISTAT_BUSY, 0) ? 0 : 1;
 448 }
 449
 450 /*
 451  * PHY register read
 452  * PHY registers are not accessed directly, but through the MII
 453  */
 454 static u16 enc28j60_phy_read(struct enc28j60_net *priv, u8 address)
 455 {
 456         u16 ret;
 457
 458         mutex_lock(&priv->lock);
 459         /* set the PHY register address */
 460         nolock_regb_write(priv, MIREGADR, address);
 461         /* start the register read operation */
 462         nolock_regb_write(priv, MICMD, MICMD_MIIRD);
 463         /* wait until the PHY read completes */
 464         wait_phy_ready(priv);
 465         /* quit reading */
 466         nolock_regb_write(priv, MICMD, 0x00);
 467         /* return the data */
 468         ret  = nolock_regw_read(priv, MIRDL);
 469         mutex_unlock(&priv->lock);
 470
 471         return ret;
 472 }
 473
 474 static int enc28j60_phy_write(struct enc28j60_net *priv, u8 address, u16 data)
 475 {
 476         int ret;
 477
 478         mutex_lock(&priv->lock);
 479         /* set the PHY register address */
 480         nolock_regb_write(priv, MIREGADR, address);
 481         /* write the PHY data */
 482         nolock_regw_write(priv, MIWRL, data);
 483         /* wait until the PHY write completes and return */
 484         ret = wait_phy_ready(priv);
 485         mutex_unlock(&priv->lock);
 486
 487         return ret;
 488 }
 489
 490 /*
 491  * Program the hardware MAC address from dev->dev_addr.
 492  */
 493 static int enc28j60_set_hw_macaddr(struct net_device *ndev)
 494 {
 495         int ret;
 496         struct enc28j60_net *priv = netdev_priv(ndev);
 497
 498         mutex_lock(&priv->lock);
 499         if (!priv->hw_enable) {
 500                 if (netif_msg_drv(priv))
 501                         printk(KERN_INFO DRV_NAME
 502                                 ": %s: Setting MAC address to %pM\n",
 503                                 ndev->name, ndev->dev_addr);
 504                 /* NOTE: MAC address in ENC28J60 is byte-backward */
 505                 nolock_regb_write(priv, MAADR5, ndev->dev_addr[0]);
 506                 nolock_regb_write(priv, MAADR4, ndev->dev_addr[1]);
 507                 nolock_regb_write(priv, MAADR3, ndev->dev_addr[2]);
 508                 nolock_regb_write(priv, MAADR2, ndev->dev_addr[3]);
 509                 nolock_regb_write(priv, MAADR1, ndev->dev_addr[4]);
 510                 nolock_regb_write(priv, MAADR0, ndev->dev_addr[5]);
 511                 ret = 0;
 512         } else {
 513                 if (netif_msg_drv(priv))
 514                         printk(KERN_DEBUG DRV_NAME
 515                                 ": %s() Hardware must be disabled to set "
 516                                 "Mac address\n", __func__);
 517                 ret = -EBUSY;
 518         }
 519         mutex_unlock(&priv->lock);
 520         return ret;
 521 }
 522
 523 /*
 524  * Store the new hardware address in dev->dev_addr, and update the MAC.
 525  */
 526 static int enc28j60_set_mac_address(struct net_device *dev, void *addr)
 527 {
 528         struct sockaddr *address = addr;
 529
 530         if (netif_running(dev))
 531                 return -EBUSY;
 532         if (!is_valid_ether_addr(address->sa_data))
 533                 return -EADDRNOTAVAIL;
 534
 535         memcpy(dev->dev_addr, address->sa_data, dev->addr_len);
 536         return enc28j60_set_hw_macaddr(dev);
 537 }
 538
 539 /*
 540  * Debug routine to dump useful register contents
 541  */
 542 static void enc28j60_dump_regs(struct enc28j60_net *priv, const char *msg)
 543 {
 544         mutex_lock(&priv->lock);
 545         printk(KERN_DEBUG DRV_NAME " %s\n"
 546                 "HwRevID: 0x%02x\n"
 547                 "Cntrl: ECON1 ECON2 ESTAT  EIR  EIE\n"
 548                 "       0x%02x  0x%02x  0x%02x  0x%02x  0x%02x\n"
 549                 "MAC  : MACON1 MACON3 MACON4\n"
 550                 "       0x%02x   0x%02x   0x%02x\n"
 551                 "Rx   : ERXST  ERXND  ERXWRPT ERXRDPT ERXFCON EPKTCNT MAMXFL\n"
 552                 "       0x%04x 0x%04x 0x%04x  0x%04x  "
 553                 "0x%02x    0x%02x    0x%04x\n"
 554                 "Tx   : ETXST  ETXND  MACLCON1 MACLCON2 MAPHSUP\n"
 555                 "       0x%04x 0x%04x 0x%02x     0x%02x     0x%02x\n",
 556                 msg, nolock_regb_read(priv, EREVID),
 557                 nolock_regb_read(priv, ECON1), nolock_regb_read(priv, ECON2),
 558                 nolock_regb_read(priv, ESTAT), nolock_regb_read(priv, EIR),
 559                 nolock_regb_read(priv, EIE), nolock_regb_read(priv, MACON1),
 560                 nolock_regb_read(priv, MACON3), nolock_regb_read(priv, MACON4),
 561                 nolock_regw_read(priv, ERXSTL), nolock_regw_read(priv, ERXNDL),
 562                 nolock_regw_read(priv, ERXWRPTL),
 563                 nolock_regw_read(priv, ERXRDPTL),
 564                 nolock_regb_read(priv, ERXFCON),
 565                 nolock_regb_read(priv, EPKTCNT),
 566                 nolock_regw_read(priv, MAMXFLL), nolock_regw_read(priv, ETXSTL),
 567                 nolock_regw_read(priv, ETXNDL),
 568                 nolock_regb_read(priv, MACLCON1),
 569                 nolock_regb_read(priv, MACLCON2),
 570                 nolock_regb_read(priv, MAPHSUP));
 571         mutex_unlock(&priv->lock);
 572 }
 573
 574 /*
 575  * ERXRDPT need to be set always at odd addresses, refer to errata datasheet
 576  */
 577 static u16 erxrdpt_workaround(u16 next_packet_ptr, u16 start, u16 end)
 578 {
 579         u16 erxrdpt;
 580
 581         if ((next_packet_ptr - 1 < start) || (next_packet_ptr - 1 > end))
 582                 erxrdpt = end;
 583         else
 584                 erxrdpt = next_packet_ptr - 1;
 585
 586         return erxrdpt;
 587 }
 588
 589 /*
 590  * Calculate wrap around when reading beyond the end of the RX buffer
 591  */
 592 static u16 rx_packet_start(u16 ptr)
 593 {
 594         if (ptr + RSV_SIZE > RXEND_INIT)
 595                 return (ptr + RSV_SIZE) - (RXEND_INIT - RXSTART_INIT + 1);
 596         else
 597                 return ptr + RSV_SIZE;
 598 }
 599
 600 static void nolock_rxfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
 601 {
 602         u16 erxrdpt;
 603
 604         if (start > 0x1FFF || end > 0x1FFF || start > end) {
 605                 if (netif_msg_drv(priv))
 606                         printk(KERN_ERR DRV_NAME ": %s(%d, %d) RXFIFO "
 607                                 "bad parameters!\n", __func__, start, end);
 608                 return;
 609         }
 610         /* set receive buffer start + end */
 611         priv->next_pk_ptr = start;
 612         nolock_regw_write(priv, ERXSTL, start);
 613         erxrdpt = erxrdpt_workaround(priv->next_pk_ptr, start, end);
 614         nolock_regw_write(priv, ERXRDPTL, erxrdpt);
 615         nolock_regw_write(priv, ERXNDL, end);
 616 }
 617
 618 static void nolock_txfifo_init(struct enc28j60_net *priv, u16 start, u16 end)
 619 {
 620         if (start > 0x1FFF || end > 0x1FFF || start > end) {
 621                 if (netif_msg_drv(priv))
 622                         printk(KERN_ERR DRV_NAME ": %s(%d, %d) TXFIFO "
 623                                 "bad parameters!\n", __func__, start, end);
 624                 return;
 625         }
 626         /* set transmit buffer start + end */
 627         nolock_regw_write(priv, ETXSTL, start);
 628         nolock_regw_write(priv, ETXNDL, end);
 629 }
 630
 631 /*
 632  * Low power mode shrinks power consumption about 100x, so we'd like
 633  * the chip to be in that mode whenever it's inactive.  (However, we
 634  * can't stay in lowpower mode during suspend with WOL active.)
 635  */
 636 static void enc28j60_lowpower(struct enc28j60_net *priv, bool is_low)
 637 {
 638         if (netif_msg_drv(priv))
 639                 dev_dbg(&priv->spi->dev, "%s power...\n",
 640                                 is_low ? "low" : "high");
 641
 642         mutex_lock(&priv->lock);
 643         if (is_low) {
 644                 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 645                 poll_ready(priv, ESTAT, ESTAT_RXBUSY, 0);
 646                 poll_ready(priv, ECON1, ECON1_TXRTS, 0);
 647                 /* ECON2_VRPS was set during initialization */
 648                 nolock_reg_bfset(priv, ECON2, ECON2_PWRSV);
 649         } else {
 650                 nolock_reg_bfclr(priv, ECON2, ECON2_PWRSV);
 651                 poll_ready(priv, ESTAT, ESTAT_CLKRDY, ESTAT_CLKRDY);
 652                 /* caller sets ECON1_RXEN */
 653         }
 654         mutex_unlock(&priv->lock);
 655 }
 656
 657 static int enc28j60_hw_init(struct enc28j60_net *priv)
 658 {
 659         u8 reg;
 660
 661         if (netif_msg_drv(priv))
 662                 printk(KERN_DEBUG DRV_NAME ": %s() - %s\n", __func__,
 663                         priv->full_duplex ? "FullDuplex" : "HalfDuplex");
 664
 665         mutex_lock(&priv->lock);
 666         /* first reset the chip */
 667         enc28j60_soft_reset(priv);
 668         /* Clear ECON1 */
 669         spi_write_op(priv, ENC28J60_WRITE_CTRL_REG, ECON1, 0x00);
 670         priv->bank = 0;
 671         priv->hw_enable = false;
 672         priv->tx_retry_count = 0;
 673         priv->max_pk_counter = 0;
 674         priv->rxfilter = RXFILTER_NORMAL;
 675         /* enable address auto increment and voltage regulator powersave */
 676         nolock_regb_write(priv, ECON2, ECON2_AUTOINC | ECON2_VRPS);
 677
 678         nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
 679         nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
 680         mutex_unlock(&priv->lock);
 681
 682         /*
 683          * Check the RevID.
 684          * If it's 0x00 or 0xFF probably the enc28j60 is not mounted or
 685          * damaged
 686          */
 687         reg = locked_regb_read(priv, EREVID);
 688         if (netif_msg_drv(priv))
 689                 printk(KERN_INFO DRV_NAME ": chip RevID: 0x%02x\n", reg);
 690         if (reg == 0x00 || reg == 0xff) {
 691                 if (netif_msg_drv(priv))
 692                         printk(KERN_DEBUG DRV_NAME ": %s() Invalid RevId %d\n",
 693                                 __func__, reg);
 694                 return 0;
 695         }
 696
 697         /* default filter mode: (unicast OR broadcast) AND crc valid */
 698         locked_regb_write(priv, ERXFCON,
 699                             ERXFCON_UCEN | ERXFCON_CRCEN | ERXFCON_BCEN);
 700
 701         /* enable MAC receive */
 702         locked_regb_write(priv, MACON1,
 703                             MACON1_MARXEN | MACON1_TXPAUS | MACON1_RXPAUS);
 704         /* enable automatic padding and CRC operations */
 705         if (priv->full_duplex) {
 706                 locked_regb_write(priv, MACON3,
 707                                     MACON3_PADCFG0 | MACON3_TXCRCEN |
 708                                     MACON3_FRMLNEN | MACON3_FULDPX);
 709                 /* set inter-frame gap (non-back-to-back) */
 710                 locked_regb_write(priv, MAIPGL, 0x12);
 711                 /* set inter-frame gap (back-to-back) */
 712                 locked_regb_write(priv, MABBIPG, 0x15);
 713         } else {
 714                 locked_regb_write(priv, MACON3,
 715                                     MACON3_PADCFG0 | MACON3_TXCRCEN |
 716                                     MACON3_FRMLNEN);
 717                 locked_regb_write(priv, MACON4, 1 << 6);        /* DEFER bit */
 718                 /* set inter-frame gap (non-back-to-back) */
 719                 locked_regw_write(priv, MAIPGL, 0x0C12);
 720                 /* set inter-frame gap (back-to-back) */
 721                 locked_regb_write(priv, MABBIPG, 0x12);
 722         }
 723         /*
 724          * MACLCON1 (default)
 725          * MACLCON2 (default)
 726          * Set the maximum packet size which the controller will accept
 727          */
 728         locked_regw_write(priv, MAMXFLL, MAX_FRAMELEN);
 729
 730         /* Configure LEDs */
 731         if (!enc28j60_phy_write(priv, PHLCON, ENC28J60_LAMPS_MODE))
 732                 return 0;
 733
 734         if (priv->full_duplex) {
 735                 if (!enc28j60_phy_write(priv, PHCON1, PHCON1_PDPXMD))
 736                         return 0;
 737                 if (!enc28j60_phy_write(priv, PHCON2, 0x00))
 738                         return 0;
 739         } else {
 740                 if (!enc28j60_phy_write(priv, PHCON1, 0x00))
 741                         return 0;
 742                 if (!enc28j60_phy_write(priv, PHCON2, PHCON2_HDLDIS))
 743                         return 0;
 744         }
 745         if (netif_msg_hw(priv))
 746                 enc28j60_dump_regs(priv, "Hw initialized.");
 747
 748         return 1;
 749 }
 750
 751 static void enc28j60_hw_enable(struct enc28j60_net *priv)
 752 {
 753         /* enable interrupts */
 754         if (netif_msg_hw(priv))
 755                 printk(KERN_DEBUG DRV_NAME ": %s() enabling interrupts.\n",
 756                         __func__);
 757
 758         enc28j60_phy_write(priv, PHIE, PHIE_PGEIE | PHIE_PLNKIE);
 759
 760         mutex_lock(&priv->lock);
 761         nolock_reg_bfclr(priv, EIR, EIR_DMAIF | EIR_LINKIF |
 762                          EIR_TXIF | EIR_TXERIF | EIR_RXERIF | EIR_PKTIF);
 763         nolock_regb_write(priv, EIE, EIE_INTIE | EIE_PKTIE | EIE_LINKIE |
 764                           EIE_TXIE | EIE_TXERIE | EIE_RXERIE);
 765
 766         /* enable receive logic */
 767         nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
 768         priv->hw_enable = true;
 769         mutex_unlock(&priv->lock);
 770 }
 771
 772 static void enc28j60_hw_disable(struct enc28j60_net *priv)
 773 {
 774         mutex_lock(&priv->lock);
 775         /* disable interrutps and packet reception */
 776         nolock_regb_write(priv, EIE, 0x00);
 777         nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 778         priv->hw_enable = false;
 779         mutex_unlock(&priv->lock);
 780 }
 781
 782 static int
 783 enc28j60_setlink(struct net_device *ndev, u8 autoneg, u16 speed, u8 duplex)
 784 {
 785         struct enc28j60_net *priv = netdev_priv(ndev);
 786         int ret = 0;
 787
 788         if (!priv->hw_enable) {
 789                 /* link is in low power mode now; duplex setting
 790                  * will take effect on next enc28j60_hw_init().
 791                  */
 792                 if (autoneg == AUTONEG_DISABLE && speed == SPEED_10)
 793                         priv->full_duplex = (duplex == DUPLEX_FULL);
 794                 else {
 795                         if (netif_msg_link(priv))
 796                                 dev_warn(&ndev->dev,
 797                                         "unsupported link setting\n");
 798                         ret = -EOPNOTSUPP;
 799                 }
 800         } else {
 801                 if (netif_msg_link(priv))
 802                         dev_warn(&ndev->dev, "Warning: hw must be disabled "
 803                                 "to set link mode\n");
 804                 ret = -EBUSY;
 805         }
 806         return ret;
 807 }
 808
 809 /*
 810  * Read the Transmit Status Vector
 811  */
 812 static void enc28j60_read_tsv(struct enc28j60_net *priv, u8 tsv[TSV_SIZE])
 813 {
 814         int endptr;
 815
 816         endptr = locked_regw_read(priv, ETXNDL);
 817         if (netif_msg_hw(priv))
 818                 printk(KERN_DEBUG DRV_NAME ": reading TSV at addr:0x%04x\n",
 819                          endptr + 1);
 820         enc28j60_mem_read(priv, endptr + 1, TSV_SIZE, tsv);
 821 }
 822
 823 static void enc28j60_dump_tsv(struct enc28j60_net *priv, const char *msg,
 824                                 u8 tsv[TSV_SIZE])
 825 {
 826         u16 tmp1, tmp2;
 827
 828         printk(KERN_DEBUG DRV_NAME ": %s - TSV:\n", msg);
 829         tmp1 = tsv[1];
 830         tmp1 <<= 8;
 831         tmp1 |= tsv[0];
 832
 833         tmp2 = tsv[5];
 834         tmp2 <<= 8;
 835         tmp2 |= tsv[4];
 836
 837         printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, CollisionCount: %d,"
 838                 " TotByteOnWire: %d\n", tmp1, tsv[2] & 0x0f, tmp2);
 839         printk(KERN_DEBUG DRV_NAME ": TxDone: %d, CRCErr:%d, LenChkErr: %d,"
 840                 " LenOutOfRange: %d\n", TSV_GETBIT(tsv, TSV_TXDONE),
 841                 TSV_GETBIT(tsv, TSV_TXCRCERROR),
 842                 TSV_GETBIT(tsv, TSV_TXLENCHKERROR),
 843                 TSV_GETBIT(tsv, TSV_TXLENOUTOFRANGE));
 844         printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
 845                 "PacketDefer: %d, ExDefer: %d\n",
 846                 TSV_GETBIT(tsv, TSV_TXMULTICAST),
 847                 TSV_GETBIT(tsv, TSV_TXBROADCAST),
 848                 TSV_GETBIT(tsv, TSV_TXPACKETDEFER),
 849                 TSV_GETBIT(tsv, TSV_TXEXDEFER));
 850         printk(KERN_DEBUG DRV_NAME ": ExCollision: %d, LateCollision: %d, "
 851                  "Giant: %d, Underrun: %d\n",
 852                  TSV_GETBIT(tsv, TSV_TXEXCOLLISION),
 853                  TSV_GETBIT(tsv, TSV_TXLATECOLLISION),
 854                  TSV_GETBIT(tsv, TSV_TXGIANT), TSV_GETBIT(tsv, TSV_TXUNDERRUN));
 855         printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d, "
 856                  "BackPressApp: %d, VLanTagFrame: %d\n",
 857                  TSV_GETBIT(tsv, TSV_TXCONTROLFRAME),
 858                  TSV_GETBIT(tsv, TSV_TXPAUSEFRAME),
 859                  TSV_GETBIT(tsv, TSV_BACKPRESSUREAPP),
 860                  TSV_GETBIT(tsv, TSV_TXVLANTAGFRAME));
 861 }
 862
 863 /*
 864  * Receive Status vector
 865  */
 866 static void enc28j60_dump_rsv(struct enc28j60_net *priv, const char *msg,
 867                               u16 pk_ptr, int len, u16 sts)
 868 {
 869         printk(KERN_DEBUG DRV_NAME ": %s - NextPk: 0x%04x - RSV:\n",
 870                 msg, pk_ptr);
 871         printk(KERN_DEBUG DRV_NAME ": ByteCount: %d, DribbleNibble: %d\n", len,
 872                  RSV_GETBIT(sts, RSV_DRIBBLENIBBLE));
 873         printk(KERN_DEBUG DRV_NAME ": RxOK: %d, CRCErr:%d, LenChkErr: %d,"
 874                  " LenOutOfRange: %d\n", RSV_GETBIT(sts, RSV_RXOK),
 875                  RSV_GETBIT(sts, RSV_CRCERROR),
 876                  RSV_GETBIT(sts, RSV_LENCHECKERR),
 877                  RSV_GETBIT(sts, RSV_LENOUTOFRANGE));
 878         printk(KERN_DEBUG DRV_NAME ": Multicast: %d, Broadcast: %d, "
 879                  "LongDropEvent: %d, CarrierEvent: %d\n",
 880                  RSV_GETBIT(sts, RSV_RXMULTICAST),
 881                  RSV_GETBIT(sts, RSV_RXBROADCAST),
 882                  RSV_GETBIT(sts, RSV_RXLONGEVDROPEV),
 883                  RSV_GETBIT(sts, RSV_CARRIEREV));
 884         printk(KERN_DEBUG DRV_NAME ": ControlFrame: %d, PauseFrame: %d,"
 885                  " UnknownOp: %d, VLanTagFrame: %d\n",
 886                  RSV_GETBIT(sts, RSV_RXCONTROLFRAME),
 887                  RSV_GETBIT(sts, RSV_RXPAUSEFRAME),
 888                  RSV_GETBIT(sts, RSV_RXUNKNOWNOPCODE),
 889                  RSV_GETBIT(sts, RSV_RXTYPEVLAN));
 890 }
 891
 892 static void dump_packet(const char *msg, int len, const char *data)
 893 {
 894         printk(KERN_DEBUG DRV_NAME ": %s - packet len:%d\n", msg, len);
 895         print_hex_dump(KERN_DEBUG, "pk data: ", DUMP_PREFIX_OFFSET, 16, 1,
 896                         data, len, true);
 897 }
 898
 899 /*
 900  * Hardware receive function.
 901  * Read the buffer memory, update the FIFO pointer to free the buffer,
 902  * check the status vector and decrement the packet counter.
 903  */
 904 static void enc28j60_hw_rx(struct net_device *ndev)
 905 {
 906         struct enc28j60_net *priv = netdev_priv(ndev);
 907         struct sk_buff *skb = NULL;
 908         u16 erxrdpt, next_packet, rxstat;
 909         u8 rsv[RSV_SIZE];
 910         int len;
 911
 912         if (netif_msg_rx_status(priv))
 913                 printk(KERN_DEBUG DRV_NAME ": RX pk_addr:0x%04x\n",
 914                         priv->next_pk_ptr);
 915
 916         if (unlikely(priv->next_pk_ptr > RXEND_INIT)) {
 917                 if (netif_msg_rx_err(priv))
 918                         dev_err(&ndev->dev,
 919                                 "%s() Invalid packet address!! 0x%04x\n",
 920                                 __func__, priv->next_pk_ptr);
 921                 /* packet address corrupted: reset RX logic */
 922                 mutex_lock(&priv->lock);
 923                 nolock_reg_bfclr(priv, ECON1, ECON1_RXEN);
 924                 nolock_reg_bfset(priv, ECON1, ECON1_RXRST);
 925                 nolock_reg_bfclr(priv, ECON1, ECON1_RXRST);
 926                 nolock_rxfifo_init(priv, RXSTART_INIT, RXEND_INIT);
 927                 nolock_reg_bfclr(priv, EIR, EIR_RXERIF);
 928                 nolock_reg_bfset(priv, ECON1, ECON1_RXEN);
 929                 mutex_unlock(&priv->lock);
 930                 ndev->stats.rx_errors++;
 931                 return;
 932         }
 933         /* Read next packet pointer and rx status vector */
 934         enc28j60_mem_read(priv, priv->next_pk_ptr, sizeof(rsv), rsv);
 935
 936         next_packet = rsv[1];
 937         next_packet <<= 8;
 938         next_packet |= rsv[0];
 939
 940         len = rsv[3];
 941         len <<= 8;
 942         len |= rsv[2];
 943
 944         rxstat = rsv[5];
 945         rxstat <<= 8;
 946         rxstat |= rsv[4];
 947
 948         if (netif_msg_rx_status(priv))
 949                 enc28j60_dump_rsv(priv, __func__, next_packet, len, rxstat);
 950
 951         if (!RSV_GETBIT(rxstat, RSV_RXOK) || len > MAX_FRAMELEN) {
 952                 if (netif_msg_rx_err(priv))
 953                         dev_err(&ndev->dev, "Rx Error (%04x)\n", rxstat);
 954                 ndev->stats.rx_errors++;
 955                 if (RSV_GETBIT(rxstat, RSV_CRCERROR))
 956                         ndev->stats.rx_crc_errors++;
 957                 if (RSV_GETBIT(rxstat, RSV_LENCHECKERR))
 958                         ndev->stats.rx_frame_errors++;
 959                 if (len > MAX_FRAMELEN)
 960                         ndev->stats.rx_over_errors++;
 961         } else {
 962                 skb = netdev_alloc_skb(ndev, len + NET_IP_ALIGN);
 963                 if (!skb) {
 964                         if (netif_msg_rx_err(priv))
 965                                 dev_err(&ndev->dev,
 966                                         "out of memory for Rx'd frame\n");
 967                         ndev->stats.rx_dropped++;
 968                 } else {
 969                         skb_reserve(skb, NET_IP_ALIGN);
 970                         /* copy the packet from the receive buffer */
 971                         enc28j60_mem_read(priv,
 972                                 rx_packet_start(priv->next_pk_ptr),
 973                                 len, skb_put(skb, len));
 974                         if (netif_msg_pktdata(priv))
 975                                 dump_packet(__func__, skb->len, skb->data);
 976                         skb->protocol = eth_type_trans(skb, ndev);
 977                         /* update statistics */
 978                         ndev->stats.rx_packets++;
 979                         ndev->stats.rx_bytes += len;
 980                         netif_rx_ni(skb);
 981                 }
 982         }
 983         /*
 984          * Move the RX read pointer to the start of the next
 985          * received packet.
 986          * This frees the memory we just read out
 987          */
 988         erxrdpt = erxrdpt_workaround(next_packet, RXSTART_INIT, RXEND_INIT);
 989         if (netif_msg_hw(priv))
 990                 printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT:0x%04x\n",
 991                         __func__, erxrdpt);
 992
 993         mutex_lock(&priv->lock);
 994         nolock_regw_write(priv, ERXRDPTL, erxrdpt);
 995 #ifdef CONFIG_ENC28J60_WRITEVERIFY
 996         if (netif_msg_drv(priv)) {
 997                 u16 reg;
 998                 reg = nolock_regw_read(priv, ERXRDPTL);
 999                 if (reg != erxrdpt)
1000                         printk(KERN_DEBUG DRV_NAME ": %s() ERXRDPT verify "
1001                                 "error (0x%04x - 0x%04x)\n", __func__,
1002                                 reg, erxrdpt);
1003         }
1004 #endif
1005         priv->next_pk_ptr = next_packet;
1006         /* we are done with this packet, decrement the packet counter */
1007         nolock_reg_bfset(priv, ECON2, ECON2_PKTDEC);
1008         mutex_unlock(&priv->lock);
1009 }
1010
1011 /*
1012  * Calculate free space in RxFIFO
1013  */
1014 static int enc28j60_get_free_rxfifo(struct enc28j60_net *priv)
1015 {
1016         int epkcnt, erxst, erxnd, erxwr, erxrd;
1017         int free_space;
1018
1019         mutex_lock(&priv->lock);
1020         epkcnt = nolock_regb_read(priv, EPKTCNT);
1021         if (epkcnt >= 255)
1022                 free_space = -1;
1023         else {
1024                 erxst = nolock_regw_read(priv, ERXSTL);
1025                 erxnd = nolock_regw_read(priv, ERXNDL);
1026                 erxwr = nolock_regw_read(priv, ERXWRPTL);
1027                 erxrd = nolock_regw_read(priv, ERXRDPTL);
1028
1029                 if (erxwr > erxrd)
1030                         free_space = (erxnd - erxst) - (erxwr - erxrd);
1031                 else if (erxwr == erxrd)
1032                         free_space = (erxnd - erxst);
1033                 else
1034                         free_space = erxrd - erxwr - 1;
1035         }
1036         mutex_unlock(&priv->lock);
1037         if (netif_msg_rx_status(priv))
1038                 printk(KERN_DEBUG DRV_NAME ": %s() free_space = %d\n",
1039                         __func__, free_space);
1040         return free_space;
1041 }
1042
1043 /*
1044  * Access the PHY to determine link status
1045  */
1046 static void enc28j60_check_link_status(struct net_device *ndev)
1047 {
1048         struct enc28j60_net *priv = netdev_priv(ndev);
1049         u16 reg;
1050         int duplex;
1051
1052         reg = enc28j60_phy_read(priv, PHSTAT2);
1053         if (netif_msg_hw(priv))
1054                 printk(KERN_DEBUG DRV_NAME ": %s() PHSTAT1: %04x, "
1055                         "PHSTAT2: %04x\n", __func__,
1056                         enc28j60_phy_read(priv, PHSTAT1), reg);
1057         duplex = reg & PHSTAT2_DPXSTAT;
1058
1059         if (reg & PHSTAT2_LSTAT) {
1060                 netif_carrier_on(ndev);
1061                 if (netif_msg_ifup(priv))
1062                         dev_info(&ndev->dev, "link up - %s\n",
1063                                 duplex ? "Full duplex" : "Half duplex");
1064         } else {
1065                 if (netif_msg_ifdown(priv))
1066                         dev_info(&ndev->dev, "link down\n");
1067                 netif_carrier_off(ndev);
1068         }
1069 }
1070
1071 static void enc28j60_tx_clear(struct net_device *ndev, bool err)
1072 {
1073         struct enc28j60_net *priv = netdev_priv(ndev);
1074
1075         if (err)
1076                 ndev->stats.tx_errors++;
1077         else
1078                 ndev->stats.tx_packets++;
1079
1080         if (priv->tx_skb) {
1081                 if (!err)
1082                         ndev->stats.tx_bytes += priv->tx_skb->len;
1083                 dev_kfree_skb(priv->tx_skb);
1084                 priv->tx_skb = NULL;
1085         }
1086         locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1087         netif_wake_queue(ndev);
1088 }
1089
1090 /*
1091  * RX handler
1092  * ignore PKTIF because is unreliable! (look at the errata datasheet)
1093  * check EPKTCNT is the suggested workaround.
1094  * We don't need to clear interrupt flag, automatically done when
1095  * enc28j60_hw_rx() decrements the packet counter.
1096  * Returns how many packet processed.
1097  */
1098 static int enc28j60_rx_interrupt(struct net_device *ndev)
1099 {
1100         struct enc28j60_net *priv = netdev_priv(ndev);
1101         int pk_counter, ret;
1102
1103         pk_counter = locked_regb_read(priv, EPKTCNT);
1104         if (pk_counter && netif_msg_intr(priv))
1105                 printk(KERN_DEBUG DRV_NAME ": intRX, pk_cnt: %d\n", pk_counter);
1106         if (pk_counter > priv->max_pk_counter) {
1107                 /* update statistics */
1108                 priv->max_pk_counter = pk_counter;
1109                 if (netif_msg_rx_status(priv) && priv->max_pk_counter > 1)
1110                         printk(KERN_DEBUG DRV_NAME ": RX max_pk_cnt: %d\n",
1111                                 priv->max_pk_counter);
1112         }
1113         ret = pk_counter;
1114         while (pk_counter-- > 0)
1115                 enc28j60_hw_rx(ndev);
1116
1117         return ret;
1118 }
1119
1120 static void enc28j60_irq_work_handler(struct work_struct *work)
1121 {
1122         struct enc28j60_net *priv =
1123                 container_of(work, struct enc28j60_net, irq_work);
1124         struct net_device *ndev = priv->netdev;
1125         int intflags, loop;
1126
1127         if (netif_msg_intr(priv))
1128                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1129         /* disable further interrupts */
1130         locked_reg_bfclr(priv, EIE, EIE_INTIE);
1131
1132         do {
1133                 loop = 0;
1134                 intflags = locked_regb_read(priv, EIR);
1135                 /* DMA interrupt handler (not currently used) */
1136                 if ((intflags & EIR_DMAIF) != 0) {
1137                         loop++;
1138                         if (netif_msg_intr(priv))
1139                                 printk(KERN_DEBUG DRV_NAME
1140                                         ": intDMA(%d)\n", loop);
1141                         locked_reg_bfclr(priv, EIR, EIR_DMAIF);
1142                 }
1143                 /* LINK changed handler */
1144                 if ((intflags & EIR_LINKIF) != 0) {
1145                         loop++;
1146                         if (netif_msg_intr(priv))
1147                                 printk(KERN_DEBUG DRV_NAME
1148                                         ": intLINK(%d)\n", loop);
1149                         enc28j60_check_link_status(ndev);
1150                         /* read PHIR to clear the flag */
1151                         enc28j60_phy_read(priv, PHIR);
1152                 }
1153                 /* TX complete handler */
1154                 if (((intflags & EIR_TXIF) != 0) &&
1155                     ((intflags & EIR_TXERIF) == 0)) {
1156                         bool err = false;
1157                         loop++;
1158                         if (netif_msg_intr(priv))
1159                                 printk(KERN_DEBUG DRV_NAME
1160                                         ": intTX(%d)\n", loop);
1161                         priv->tx_retry_count = 0;
1162                         if (locked_regb_read(priv, ESTAT) & ESTAT_TXABRT) {
1163                                 if (netif_msg_tx_err(priv))
1164                                         dev_err(&ndev->dev,
1165                                                 "Tx Error (aborted)\n");
1166                                 err = true;
1167                         }
1168                         if (netif_msg_tx_done(priv)) {
1169                                 u8 tsv[TSV_SIZE];
1170                                 enc28j60_read_tsv(priv, tsv);
1171                                 enc28j60_dump_tsv(priv, "Tx Done", tsv);
1172                         }
1173                         enc28j60_tx_clear(ndev, err);
1174                         locked_reg_bfclr(priv, EIR, EIR_TXIF);
1175                 }
1176                 /* TX Error handler */
1177                 if ((intflags & EIR_TXERIF) != 0) {
1178                         u8 tsv[TSV_SIZE];
1179
1180                         loop++;
1181                         if (netif_msg_intr(priv))
1182                                 printk(KERN_DEBUG DRV_NAME
1183                                         ": intTXErr(%d)\n", loop);
1184                         locked_reg_bfclr(priv, ECON1, ECON1_TXRTS);
1185                         enc28j60_read_tsv(priv, tsv);
1186                         if (netif_msg_tx_err(priv))
1187                                 enc28j60_dump_tsv(priv, "Tx Error", tsv);
1188                         /* Reset TX logic */
1189                         mutex_lock(&priv->lock);
1190                         nolock_reg_bfset(priv, ECON1, ECON1_TXRST);
1191                         nolock_reg_bfclr(priv, ECON1, ECON1_TXRST);
1192                         nolock_txfifo_init(priv, TXSTART_INIT, TXEND_INIT);
1193                         mutex_unlock(&priv->lock);
1194                         /* Transmit Late collision check for retransmit */
1195                         if (TSV_GETBIT(tsv, TSV_TXLATECOLLISION)) {
1196                                 if (netif_msg_tx_err(priv))
1197                                         printk(KERN_DEBUG DRV_NAME
1198                                                 ": LateCollision TXErr (%d)\n",
1199                                                 priv->tx_retry_count);
1200                                 if (priv->tx_retry_count++ < MAX_TX_RETRYCOUNT)
1201                                         locked_reg_bfset(priv, ECON1,
1202                                                            ECON1_TXRTS);
1203                                 else
1204                                         enc28j60_tx_clear(ndev, true);
1205                         } else
1206                                 enc28j60_tx_clear(ndev, true);
1207                         locked_reg_bfclr(priv, EIR, EIR_TXERIF | EIR_TXIF);
1208                 }
1209                 /* RX Error handler */
1210                 if ((intflags & EIR_RXERIF) != 0) {
1211                         loop++;
1212                         if (netif_msg_intr(priv))
1213                                 printk(KERN_DEBUG DRV_NAME
1214                                         ": intRXErr(%d)\n", loop);
1215                         /* Check free FIFO space to flag RX overrun */
1216                         if (enc28j60_get_free_rxfifo(priv) <= 0) {
1217                                 if (netif_msg_rx_err(priv))
1218                                         printk(KERN_DEBUG DRV_NAME
1219                                                 ": RX Overrun\n");
1220                                 ndev->stats.rx_dropped++;
1221                         }
1222                         locked_reg_bfclr(priv, EIR, EIR_RXERIF);
1223                 }
1224                 /* RX handler */
1225                 if (enc28j60_rx_interrupt(ndev))
1226                         loop++;
1227         } while (loop);
1228
1229         /* re-enable interrupts */
1230         locked_reg_bfset(priv, EIE, EIE_INTIE);
1231         if (netif_msg_intr(priv))
1232                 printk(KERN_DEBUG DRV_NAME ": %s() exit\n", __func__);
1233 }
1234
1235 /*
1236  * Hardware transmit function.
1237  * Fill the buffer memory and send the contents of the transmit buffer
1238  * onto the network
1239  */
1240 static void enc28j60_hw_tx(struct enc28j60_net *priv)
1241 {
1242         BUG_ON(!priv->tx_skb);
1243
1244         if (netif_msg_tx_queued(priv))
1245                 printk(KERN_DEBUG DRV_NAME
1246                         ": Tx Packet Len:%d\n", priv->tx_skb->len);
1247
1248         if (netif_msg_pktdata(priv))
1249                 dump_packet(__func__,
1250                             priv->tx_skb->len, priv->tx_skb->data);
1251         enc28j60_packet_write(priv, priv->tx_skb->len, priv->tx_skb->data);
1252
1253 #ifdef CONFIG_ENC28J60_WRITEVERIFY
1254         /* readback and verify written data */
1255         if (netif_msg_drv(priv)) {
1256                 int test_len, k;
1257                 u8 test_buf[64]; /* limit the test to the first 64 bytes */
1258                 int okflag;
1259
1260                 test_len = priv->tx_skb->len;
1261                 if (test_len > sizeof(test_buf))
1262                         test_len = sizeof(test_buf);
1263
1264                 /* + 1 to skip control byte */
1265                 enc28j60_mem_read(priv, TXSTART_INIT + 1, test_len, test_buf);
1266                 okflag = 1;
1267                 for (k = 0; k < test_len; k++) {
1268                         if (priv->tx_skb->data[k] != test_buf[k]) {
1269                                 printk(KERN_DEBUG DRV_NAME
1270                                          ": Error, %d location differ: "
1271                                          "0x%02x-0x%02x\n", k,
1272                                          priv->tx_skb->data[k], test_buf[k]);
1273                                 okflag = 0;
1274                         }
1275                 }
1276                 if (!okflag)
1277                         printk(KERN_DEBUG DRV_NAME ": Tx write buffer, "
1278                                 "verify ERROR!\n");
1279         }
1280 #endif
1281         /* set TX request flag */
1282         locked_reg_bfset(priv, ECON1, ECON1_TXRTS);
1283 }
1284
1285 static netdev_tx_t enc28j60_send_packet(struct sk_buff *skb,
1286                                         struct net_device *dev)
1287 {
1288         struct enc28j60_net *priv = netdev_priv(dev);
1289
1290         if (netif_msg_tx_queued(priv))
1291                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1292
1293         /* If some error occurs while trying to transmit this
1294          * packet, you should return '1' from this function.
1295          * In such a case you _may not_ do anything to the
1296          * SKB, it is still owned by the network queueing
1297          * layer when an error is returned.  This means you
1298          * may not modify any SKB fields, you may not free
1299          * the SKB, etc.
1300          */
1301         netif_stop_queue(dev);
1302
1303         /* Remember the skb for deferred processing */
1304         priv->tx_skb = skb;
1305         schedule_work(&priv->tx_work);
1306
1307         return NETDEV_TX_OK;
1308 }
1309
1310 static void enc28j60_tx_work_handler(struct work_struct *work)
1311 {
1312         struct enc28j60_net *priv =
1313                 container_of(work, struct enc28j60_net, tx_work);
1314
1315         /* actual delivery of data */
1316         enc28j60_hw_tx(priv);
1317 }
1318
1319 static irqreturn_t enc28j60_irq(int irq, void *dev_id)
1320 {
1321         struct enc28j60_net *priv = dev_id;
1322
1323         /*
1324          * Can't do anything in interrupt context because we need to
1325          * block (spi_sync() is blocking) so fire of the interrupt
1326          * handling workqueue.
1327          * Remember that we access enc28j60 registers through SPI bus
1328          * via spi_sync() call.
1329          */
1330         schedule_work(&priv->irq_work);
1331
1332         return IRQ_HANDLED;
1333 }
1334
1335 static void enc28j60_tx_timeout(struct net_device *ndev)
1336 {
1337         struct enc28j60_net *priv = netdev_priv(ndev);
1338
1339         if (netif_msg_timer(priv))
1340                 dev_err(&ndev->dev, DRV_NAME " tx timeout\n");
1341
1342         ndev->stats.tx_errors++;
1343         /* can't restart safely under softirq */
1344         schedule_work(&priv->restart_work);
1345 }
1346
1347 /*
1348  * Open/initialize the board. This is called (in the current kernel)
1349  * sometime after booting when the 'ifconfig' program is run.
1350  *
1351  * This routine should set everything up anew at each open, even
1352  * registers that "should" only need to be set once at boot, so that
1353  * there is non-reboot way to recover if something goes wrong.
1354  */
1355 static int enc28j60_net_open(struct net_device *dev)
1356 {
1357         struct enc28j60_net *priv = netdev_priv(dev);
1358
1359         if (netif_msg_drv(priv))
1360                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1361
1362         if (!is_valid_ether_addr(dev->dev_addr)) {
1363                 if (netif_msg_ifup(priv))
1364                         dev_err(&dev->dev, "invalid MAC address %pM\n",
1365                                 dev->dev_addr);
1366                 return -EADDRNOTAVAIL;
1367         }
1368         /* Reset the hardware here (and take it out of low power mode) */
1369         enc28j60_lowpower(priv, false);
1370         enc28j60_hw_disable(priv);
1371         if (!enc28j60_hw_init(priv)) {
1372                 if (netif_msg_ifup(priv))
1373                         dev_err(&dev->dev, "hw_reset() failed\n");
1374                 return -EINVAL;
1375         }
1376         /* Update the MAC address (in case user has changed it) */
1377         enc28j60_set_hw_macaddr(dev);
1378         /* Enable interrupts */
1379         enc28j60_hw_enable(priv);
1380         /* check link status */
1381         enc28j60_check_link_status(dev);
1382         /* We are now ready to accept transmit requests from
1383          * the queueing layer of the networking.
1384          */
1385         netif_start_queue(dev);
1386
1387         return 0;
1388 }
1389
1390 /* The inverse routine to net_open(). */
1391 static int enc28j60_net_close(struct net_device *dev)
1392 {
1393         struct enc28j60_net *priv = netdev_priv(dev);
1394
1395         if (netif_msg_drv(priv))
1396                 printk(KERN_DEBUG DRV_NAME ": %s() enter\n", __func__);
1397
1398         enc28j60_hw_disable(priv);
1399         enc28j60_lowpower(priv, true);
1400         netif_stop_queue(dev);
1401
1402         return 0;
1403 }
1404
1405 /*
1406  * Set or clear the multicast filter for this adapter
1407  * num_addrs == -1      Promiscuous mode, receive all packets
1408  * num_addrs == 0       Normal mode, filter out multicast packets
1409  * num_addrs > 0        Multicast mode, receive normal and MC packets
1410  */
1411 static void enc28j60_set_multicast_list(struct net_device *dev)
1412 {
1413         struct enc28j60_net *priv = netdev_priv(dev);
1414         int oldfilter = priv->rxfilter;
1415
1416         if (dev->flags & IFF_PROMISC) {
1417                 if (netif_msg_link(priv))
1418                         dev_info(&dev->dev, "promiscuous mode\n");
1419                 priv->rxfilter = RXFILTER_PROMISC;
1420         } else if ((dev->flags & IFF_ALLMULTI) || !netdev_mc_empty(dev)) {
1421                 if (netif_msg_link(priv))
1422                         dev_info(&dev->dev, "%smulticast mode\n",
1423                                 (dev->flags & IFF_ALLMULTI) ? "all-" : "");
1424                 priv->rxfilter = RXFILTER_MULTI;
1425         } else {
1426                 if (netif_msg_link(priv))
1427                         dev_info(&dev->dev, "normal mode\n");
1428                 priv->rxfilter = RXFILTER_NORMAL;
1429         }
1430
1431         if (oldfilter != priv->rxfilter)
1432                 schedule_work(&priv->setrx_work);
1433 }
1434
1435 static void enc28j60_setrx_work_handler(struct work_struct *work)
1436 {
1437         struct enc28j60_net *priv =
1438                 container_of(work, struct enc28j60_net, setrx_work);
1439
1440         if (priv->rxfilter == RXFILTER_PROMISC) {
1441                 if (netif_msg_drv(priv))
1442                         printk(KERN_DEBUG DRV_NAME ": promiscuous mode\n");
1443                 locked_regb_write(priv, ERXFCON, 0x00);
1444         } else if (priv->rxfilter == RXFILTER_MULTI) {
1445                 if (netif_msg_drv(priv))
1446                         printk(KERN_DEBUG DRV_NAME ": multicast mode\n");
1447                 locked_regb_write(priv, ERXFCON,
1448                                         ERXFCON_UCEN | ERXFCON_CRCEN |
1449                                         ERXFCON_BCEN | ERXFCON_MCEN);
1450         } else {
1451                 if (netif_msg_drv(priv))
1452                         printk(KERN_DEBUG DRV_NAME ": normal mode\n");
1453                 locked_regb_write(priv, ERXFCON,
1454                                         ERXFCON_UCEN | ERXFCON_CRCEN |
1455                                         ERXFCON_BCEN);
1456         }
1457 }
1458
1459 static void enc28j60_restart_work_handler(struct work_struct *work)
1460 {
1461         struct enc28j60_net *priv =
1462                         container_of(work, struct enc28j60_net, restart_work);
1463         struct net_device *ndev = priv->netdev;
1464         int ret;
1465
1466         rtnl_lock();
1467         if (netif_running(ndev)) {
1468                 enc28j60_net_close(ndev);
1469                 ret = enc28j60_net_open(ndev);
1470                 if (unlikely(ret)) {
1471                         dev_info(&ndev->dev, " could not restart %d\n", ret);
1472                         dev_close(ndev);
1473                 }
1474         }
1475         rtnl_unlock();
1476 }
1477
1478 /* ......................... ETHTOOL SUPPORT ........................... */
1479
1480 static void
1481 enc28j60_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1482 {
1483         strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1484         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1485         strlcpy(info->bus_info,
1486                 dev_name(dev->dev.parent), sizeof(info->bus_info));
1487 }
1488
1489 static int
1490 enc28j60_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1491 {
1492         struct enc28j60_net *priv = netdev_priv(dev);
1493
1494         cmd->transceiver = XCVR_INTERNAL;
1495         cmd->supported  = SUPPORTED_10baseT_Half
1496                         | SUPPORTED_10baseT_Full
1497                         | SUPPORTED_TP;
1498         ethtool_cmd_speed_set(cmd,  SPEED_10);
1499         cmd->duplex     = priv->full_duplex ? DUPLEX_FULL : DUPLEX_HALF;
1500         cmd->port       = PORT_TP;
1501         cmd->autoneg    = AUTONEG_DISABLE;
1502
1503         return 0;
1504 }
1505
1506 static int
1507 enc28j60_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1508 {
1509         return enc28j60_setlink(dev, cmd->autoneg,
1510                                 ethtool_cmd_speed(cmd), cmd->duplex);
1511 }
1512
1513 static u32 enc28j60_get_msglevel(struct net_device *dev)
1514 {
1515         struct enc28j60_net *priv = netdev_priv(dev);
1516         return priv->msg_enable;
1517 }
1518
1519 static void enc28j60_set_msglevel(struct net_device *dev, u32 val)
1520 {
1521         struct enc28j60_net *priv = netdev_priv(dev);
1522         priv->msg_enable = val;
1523 }
1524
1525 static const struct ethtool_ops enc28j60_ethtool_ops = {
1526         .get_settings   = enc28j60_get_settings,
1527         .set_settings   = enc28j60_set_settings,
1528         .get_drvinfo    = enc28j60_get_drvinfo,
1529         .get_msglevel   = enc28j60_get_msglevel,
1530         .set_msglevel   = enc28j60_set_msglevel,
1531 };
1532
1533 static int enc28j60_chipset_init(struct net_device *dev)
1534 {
1535         struct enc28j60_net *priv = netdev_priv(dev);
1536
1537         return enc28j60_hw_init(priv);
1538 }
1539
1540 static const struct net_device_ops enc28j60_netdev_ops = {
1541         .ndo_open               = enc28j60_net_open,
1542         .ndo_stop               = enc28j60_net_close,
1543         .ndo_start_xmit         = enc28j60_send_packet,
1544         .ndo_set_rx_mode        = enc28j60_set_multicast_list,
1545         .ndo_set_mac_address    = enc28j60_set_mac_address,
1546         .ndo_tx_timeout         = enc28j60_tx_timeout,
1547         .ndo_change_mtu         = eth_change_mtu,
1548         .ndo_validate_addr      = eth_validate_addr,
1549 };
1550
1551 static int enc28j60_probe(struct spi_device *spi)
1552 {
1553         struct net_device *dev;
1554         struct enc28j60_net *priv;
1555         const void *macaddr;
1556         int ret = 0;
1557
1558         if (netif_msg_drv(&debug))
1559                 dev_info(&spi->dev, DRV_NAME " Ethernet driver %s loaded\n",
1560                         DRV_VERSION);
1561
1562         dev = alloc_etherdev(sizeof(struct enc28j60_net));
1563         if (!dev) {
1564                 ret = -ENOMEM;
1565                 goto error_alloc;
1566         }
1567         priv = netdev_priv(dev);
1568
1569         priv->netdev = dev;     /* priv to netdev reference */
1570         priv->spi = spi;        /* priv to spi reference */
1571         priv->msg_enable = netif_msg_init(debug.msg_enable,
1572                                                 ENC28J60_MSG_DEFAULT);
1573         mutex_init(&priv->lock);
1574         INIT_WORK(&priv->tx_work, enc28j60_tx_work_handler);
1575         INIT_WORK(&priv->setrx_work, enc28j60_setrx_work_handler);
1576         INIT_WORK(&priv->irq_work, enc28j60_irq_work_handler);
1577         INIT_WORK(&priv->restart_work, enc28j60_restart_work_handler);
1578         spi_set_drvdata(spi, priv);     /* spi to priv reference */
1579         SET_NETDEV_DEV(dev, &spi->dev);
1580
1581         if (!enc28j60_chipset_init(dev)) {
1582                 if (netif_msg_probe(priv))
1583                         dev_info(&spi->dev, DRV_NAME " chip not found\n");
1584                 ret = -EIO;
1585                 goto error_irq;
1586         }
1587
1588         macaddr = of_get_mac_address(spi->dev.of_node);
1589         if (macaddr)
1590                 ether_addr_copy(dev->dev_addr, macaddr);
1591         else
1592                 eth_hw_addr_random(dev);
1593         enc28j60_set_hw_macaddr(dev);
1594
1595         /* Board setup must set the relevant edge trigger type;
1596          * level triggers won't currently work.
1597          */
1598         ret = request_irq(spi->irq, enc28j60_irq, 0, DRV_NAME, priv);
1599         if (ret < 0) {
1600                 if (netif_msg_probe(priv))
1601                         dev_err(&spi->dev, DRV_NAME ": request irq %d failed "
1602                                 "(ret = %d)\n", spi->irq, ret);
1603                 goto error_irq;
1604         }
1605
1606         dev->if_port = IF_PORT_10BASET;
1607         dev->irq = spi->irq;
1608         dev->netdev_ops = &enc28j60_netdev_ops;
1609         dev->watchdog_timeo = TX_TIMEOUT;
1610         dev->ethtool_ops = &enc28j60_ethtool_ops;
1611
1612         enc28j60_lowpower(priv, true);
1613
1614         ret = register_netdev(dev);
1615         if (ret) {
1616                 if (netif_msg_probe(priv))
1617                         dev_err(&spi->dev, "register netdev " DRV_NAME
1618                                 " failed (ret = %d)\n", ret);
1619                 goto error_register;
1620         }
1621         dev_info(&dev->dev, DRV_NAME " driver registered\n");
1622
1623         return 0;
1624
1625 error_register:
1626         free_irq(spi->irq, priv);
1627 error_irq:
1628         free_netdev(dev);
1629 error_alloc:
1630         return ret;
1631 }
1632
1633 static int enc28j60_remove(struct spi_device *spi)
1634 {
1635         struct enc28j60_net *priv = spi_get_drvdata(spi);
1636
1637         if (netif_msg_drv(priv))
1638                 printk(KERN_DEBUG DRV_NAME ": remove\n");
1639
1640         unregister_netdev(priv->netdev);
1641         free_irq(spi->irq, priv);
1642         free_netdev(priv->netdev);
1643
1644         return 0;
1645 }
1646
1647 static const struct of_device_id enc28j60_dt_ids[] = {
1648         { .compatible = "microchip,enc28j60" },
1649         { /* sentinel */ }
1650 };
1651 MODULE_DEVICE_TABLE(of, enc28j60_dt_ids);
1652
1653 static struct spi_driver enc28j60_driver = {
1654         .driver = {
1655                 .name = DRV_NAME,
1656                 .of_match_table = enc28j60_dt_ids,
1657          },
1658         .probe = enc28j60_probe,
1659         .remove = enc28j60_remove,
1660 };
1661
1662 static int __init enc28j60_init(void)
1663 {
1664         msec20_to_jiffies = msecs_to_jiffies(20);
1665
1666         return spi_register_driver(&enc28j60_driver);
1667 }
1668
1669 module_init(enc28j60_init);
1670
1671 static void __exit enc28j60_exit(void)
1672 {
1673         spi_unregister_driver(&enc28j60_driver);
1674 }
1675
1676 module_exit(enc28j60_exit);
1677
1678 MODULE_DESCRIPTION(DRV_NAME " ethernet driver");
1679 MODULE_AUTHOR("Claudio Lanconelli <lanconelli.claudio@eptar.com>");
1680 MODULE_LICENSE("GPL");
1681 module_param_named(debug, debug.msg_enable, int, 0);
1682 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., ffff=all)");
1683 MODULE_ALIAS("spi:" DRV_NAME);