drivers/net/ethernet/ti/cpsw.c

   1 /*
   2  * Texas Instruments Ethernet Switch Driver
   3  *
   4  * Copyright (C) 2012 Texas Instruments
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation version 2.
   9  *
  10  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  11  * kind, whether express or implied; without even the implied warranty
  12  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/io.h>
  18 #include <linux/clk.h>
  19 #include <linux/timer.h>
  20 #include <linux/module.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/irqreturn.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/if_ether.h>
  25 #include <linux/etherdevice.h>
  26 #include <linux/netdevice.h>
  27 #include <linux/net_tstamp.h>
  28 #include <linux/phy.h>
  29 #include <linux/workqueue.h>
  30 #include <linux/delay.h>
  31 #include <linux/pm_runtime.h>
  32 #include <linux/gpio.h>
  33 #include <linux/of.h>
  34 #include <linux/of_mdio.h>
  35 #include <linux/of_net.h>
  36 #include <linux/of_device.h>
  37 #include <linux/if_vlan.h>
  38
  39 #include <linux/pinctrl/consumer.h>
  40
  41 #include "cpsw.h"
  42 #include "cpsw_ale.h"
  43 #include "cpts.h"
  44 #include "davinci_cpdma.h"
  45
  46 #define CPSW_DEBUG      (NETIF_MSG_HW           | NETIF_MSG_WOL         | \
  47                          NETIF_MSG_DRV          | NETIF_MSG_LINK        | \
  48                          NETIF_MSG_IFUP         | NETIF_MSG_INTR        | \
  49                          NETIF_MSG_PROBE        | NETIF_MSG_TIMER       | \
  50                          NETIF_MSG_IFDOWN       | NETIF_MSG_RX_ERR      | \
  51                          NETIF_MSG_TX_ERR       | NETIF_MSG_TX_DONE     | \
  52                          NETIF_MSG_PKTDATA      | NETIF_MSG_TX_QUEUED   | \
  53                          NETIF_MSG_RX_STATUS)
  54
  55 #define cpsw_info(priv, type, format, ...)              \
  56 do {                                                            \
  57         if (netif_msg_##type(priv) && net_ratelimit())          \
  58                 dev_info(priv->dev, format, ## __VA_ARGS__);    \
  59 } while (0)
  60
  61 #define cpsw_err(priv, type, format, ...)               \
  62 do {                                                            \
  63         if (netif_msg_##type(priv) && net_ratelimit())          \
  64                 dev_err(priv->dev, format, ## __VA_ARGS__);     \
  65 } while (0)
  66
  67 #define cpsw_dbg(priv, type, format, ...)               \
  68 do {                                                            \
  69         if (netif_msg_##type(priv) && net_ratelimit())          \
  70                 dev_dbg(priv->dev, format, ## __VA_ARGS__);     \
  71 } while (0)
  72
  73 #define cpsw_notice(priv, type, format, ...)            \
  74 do {                                                            \
  75         if (netif_msg_##type(priv) && net_ratelimit())          \
  76                 dev_notice(priv->dev, format, ## __VA_ARGS__);  \
  77 } while (0)
  78
  79 #define ALE_ALL_PORTS           0x7
  80
  81 #define CPSW_MAJOR_VERSION(reg)         (reg >> 8 & 0x7)
  82 #define CPSW_MINOR_VERSION(reg)         (reg & 0xff)
  83 #define CPSW_RTL_VERSION(reg)           ((reg >> 11) & 0x1f)
  84
  85 #define CPSW_VERSION_1          0x19010a
  86 #define CPSW_VERSION_2          0x19010c
  87 #define CPSW_VERSION_3          0x19010f
  88 #define CPSW_VERSION_4          0x190112
  89
  90 #define HOST_PORT_NUM           0
  91 #define SLIVER_SIZE             0x40
  92
  93 #define CPSW1_HOST_PORT_OFFSET  0x028
  94 #define CPSW1_SLAVE_OFFSET      0x050
  95 #define CPSW1_SLAVE_SIZE        0x040
  96 #define CPSW1_CPDMA_OFFSET      0x100
  97 #define CPSW1_STATERAM_OFFSET   0x200
  98 #define CPSW1_HW_STATS          0x400
  99 #define CPSW1_CPTS_OFFSET       0x500
 100 #define CPSW1_ALE_OFFSET        0x600
 101 #define CPSW1_SLIVER_OFFSET     0x700
 102
 103 #define CPSW2_HOST_PORT_OFFSET  0x108
 104 #define CPSW2_SLAVE_OFFSET      0x200
 105 #define CPSW2_SLAVE_SIZE        0x100
 106 #define CPSW2_CPDMA_OFFSET      0x800
 107 #define CPSW2_HW_STATS          0x900
 108 #define CPSW2_STATERAM_OFFSET   0xa00
 109 #define CPSW2_CPTS_OFFSET       0xc00
 110 #define CPSW2_ALE_OFFSET        0xd00
 111 #define CPSW2_SLIVER_OFFSET     0xd80
 112 #define CPSW2_BD_OFFSET         0x2000
 113
 114 #define CPDMA_RXTHRESH          0x0c0
 115 #define CPDMA_RXFREE            0x0e0
 116 #define CPDMA_TXHDP             0x00
 117 #define CPDMA_RXHDP             0x20
 118 #define CPDMA_TXCP              0x40
 119 #define CPDMA_RXCP              0x60
 120
 121 #define CPSW_POLL_WEIGHT        64
 122 #define CPSW_MIN_PACKET_SIZE    60
 123 #define CPSW_MAX_PACKET_SIZE    (1500 + 14 + 4 + 4)
 124
 125 #define RX_PRIORITY_MAPPING     0x76543210
 126 #define TX_PRIORITY_MAPPING     0x33221100
 127 #define CPDMA_TX_PRIORITY_MAP   0x01234567
 128
 129 #define CPSW_VLAN_AWARE         BIT(1)
 130 #define CPSW_ALE_VLAN_AWARE     1
 131
 132 #define CPSW_FIFO_NORMAL_MODE           (0 << 16)
 133 #define CPSW_FIFO_DUAL_MAC_MODE         (1 << 16)
 134 #define CPSW_FIFO_RATE_LIMIT_MODE       (2 << 16)
 135
 136 #define CPSW_INTPACEEN          (0x3f << 16)
 137 #define CPSW_INTPRESCALE_MASK   (0x7FF << 0)
 138 #define CPSW_CMINTMAX_CNT       63
 139 #define CPSW_CMINTMIN_CNT       2
 140 #define CPSW_CMINTMAX_INTVL     (1000 / CPSW_CMINTMIN_CNT)
 141 #define CPSW_CMINTMIN_INTVL     ((1000 / CPSW_CMINTMAX_CNT) + 1)
 142
 143 #define cpsw_slave_index(cpsw, priv)                            \
 144                 ((cpsw->data.dual_emac) ? priv->emac_port :     \
 145                 cpsw->data.active_slave)
 146 #define IRQ_NUM                 2
 147 #define CPSW_MAX_QUEUES         8
 148 #define CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT 256
 149
 150 static int debug_level;
 151 module_param(debug_level, int, 0);
 152 MODULE_PARM_DESC(debug_level, "cpsw debug level (NETIF_MSG bits)");
 153
 154 static int ale_ageout = 10;
 155 module_param(ale_ageout, int, 0);
 156 MODULE_PARM_DESC(ale_ageout, "cpsw ale ageout interval (seconds)");
 157
 158 static int rx_packet_max = CPSW_MAX_PACKET_SIZE;
 159 module_param(rx_packet_max, int, 0);
 160 MODULE_PARM_DESC(rx_packet_max, "maximum receive packet size (bytes)");
 161
 162 static int descs_pool_size = CPSW_CPDMA_DESCS_POOL_SIZE_DEFAULT;
 163 module_param(descs_pool_size, int, 0444);
 164 MODULE_PARM_DESC(descs_pool_size, "Number of CPDMA CPPI descriptors in pool");
 165
 166 struct cpsw_wr_regs {
 167         u32     id_ver;
 168         u32     soft_reset;
 169         u32     control;
 170         u32     int_control;
 171         u32     rx_thresh_en;
 172         u32     rx_en;
 173         u32     tx_en;
 174         u32     misc_en;
 175         u32     mem_allign1[8];
 176         u32     rx_thresh_stat;
 177         u32     rx_stat;
 178         u32     tx_stat;
 179         u32     misc_stat;
 180         u32     mem_allign2[8];
 181         u32     rx_imax;
 182         u32     tx_imax;
 183
 184 };
 185
 186 struct cpsw_ss_regs {
 187         u32     id_ver;
 188         u32     control;
 189         u32     soft_reset;
 190         u32     stat_port_en;
 191         u32     ptype;
 192         u32     soft_idle;
 193         u32     thru_rate;
 194         u32     gap_thresh;
 195         u32     tx_start_wds;
 196         u32     flow_control;
 197         u32     vlan_ltype;
 198         u32     ts_ltype;
 199         u32     dlr_ltype;
 200 };
 201
 202 /* CPSW_PORT_V1 */
 203 #define CPSW1_MAX_BLKS      0x00 /* Maximum FIFO Blocks */
 204 #define CPSW1_BLK_CNT       0x04 /* FIFO Block Usage Count (Read Only) */
 205 #define CPSW1_TX_IN_CTL     0x08 /* Transmit FIFO Control */
 206 #define CPSW1_PORT_VLAN     0x0c /* VLAN Register */
 207 #define CPSW1_TX_PRI_MAP    0x10 /* Tx Header Priority to Switch Pri Mapping */
 208 #define CPSW1_TS_CTL        0x14 /* Time Sync Control */
 209 #define CPSW1_TS_SEQ_LTYPE  0x18 /* Time Sync Sequence ID Offset and Msg Type */
 210 #define CPSW1_TS_VLAN       0x1c /* Time Sync VLAN1 and VLAN2 */
 211
 212 /* CPSW_PORT_V2 */
 213 #define CPSW2_CONTROL       0x00 /* Control Register */
 214 #define CPSW2_MAX_BLKS      0x08 /* Maximum FIFO Blocks */
 215 #define CPSW2_BLK_CNT       0x0c /* FIFO Block Usage Count (Read Only) */
 216 #define CPSW2_TX_IN_CTL     0x10 /* Transmit FIFO Control */
 217 #define CPSW2_PORT_VLAN     0x14 /* VLAN Register */
 218 #define CPSW2_TX_PRI_MAP    0x18 /* Tx Header Priority to Switch Pri Mapping */
 219 #define CPSW2_TS_SEQ_MTYPE  0x1c /* Time Sync Sequence ID Offset and Msg Type */
 220
 221 /* CPSW_PORT_V1 and V2 */
 222 #define SA_LO               0x20 /* CPGMAC_SL Source Address Low */
 223 #define SA_HI               0x24 /* CPGMAC_SL Source Address High */
 224 #define SEND_PERCENT        0x28 /* Transmit Queue Send Percentages */
 225
 226 /* CPSW_PORT_V2 only */
 227 #define RX_DSCP_PRI_MAP0    0x30 /* Rx DSCP Priority to Rx Packet Mapping */
 228 #define RX_DSCP_PRI_MAP1    0x34 /* Rx DSCP Priority to Rx Packet Mapping */
 229 #define RX_DSCP_PRI_MAP2    0x38 /* Rx DSCP Priority to Rx Packet Mapping */
 230 #define RX_DSCP_PRI_MAP3    0x3c /* Rx DSCP Priority to Rx Packet Mapping */
 231 #define RX_DSCP_PRI_MAP4    0x40 /* Rx DSCP Priority to Rx Packet Mapping */
 232 #define RX_DSCP_PRI_MAP5    0x44 /* Rx DSCP Priority to Rx Packet Mapping */
 233 #define RX_DSCP_PRI_MAP6    0x48 /* Rx DSCP Priority to Rx Packet Mapping */
 234 #define RX_DSCP_PRI_MAP7    0x4c /* Rx DSCP Priority to Rx Packet Mapping */
 235
 236 /* Bit definitions for the CPSW2_CONTROL register */
 237 #define PASS_PRI_TAGGED     (1<<24) /* Pass Priority Tagged */
 238 #define VLAN_LTYPE2_EN      (1<<21) /* VLAN LTYPE 2 enable */
 239 #define VLAN_LTYPE1_EN      (1<<20) /* VLAN LTYPE 1 enable */
 240 #define DSCP_PRI_EN         (1<<16) /* DSCP Priority Enable */
 241 #define TS_320              (1<<14) /* Time Sync Dest Port 320 enable */
 242 #define TS_319              (1<<13) /* Time Sync Dest Port 319 enable */
 243 #define TS_132              (1<<12) /* Time Sync Dest IP Addr 132 enable */
 244 #define TS_131              (1<<11) /* Time Sync Dest IP Addr 131 enable */
 245 #define TS_130              (1<<10) /* Time Sync Dest IP Addr 130 enable */
 246 #define TS_129              (1<<9)  /* Time Sync Dest IP Addr 129 enable */
 247 #define TS_TTL_NONZERO      (1<<8)  /* Time Sync Time To Live Non-zero enable */
 248 #define TS_ANNEX_F_EN       (1<<6)  /* Time Sync Annex F enable */
 249 #define TS_ANNEX_D_EN       (1<<4)  /* Time Sync Annex D enable */
 250 #define TS_LTYPE2_EN        (1<<3)  /* Time Sync LTYPE 2 enable */
 251 #define TS_LTYPE1_EN        (1<<2)  /* Time Sync LTYPE 1 enable */
 252 #define TS_TX_EN            (1<<1)  /* Time Sync Transmit Enable */
 253 #define TS_RX_EN            (1<<0)  /* Time Sync Receive Enable */
 254
 255 #define CTRL_V2_TS_BITS \
 256         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 257          TS_TTL_NONZERO  | TS_ANNEX_D_EN | TS_LTYPE1_EN)
 258
 259 #define CTRL_V2_ALL_TS_MASK (CTRL_V2_TS_BITS | TS_TX_EN | TS_RX_EN)
 260 #define CTRL_V2_TX_TS_BITS  (CTRL_V2_TS_BITS | TS_TX_EN)
 261 #define CTRL_V2_RX_TS_BITS  (CTRL_V2_TS_BITS | TS_RX_EN)
 262
 263
 264 #define CTRL_V3_TS_BITS \
 265         (TS_320 | TS_319 | TS_132 | TS_131 | TS_130 | TS_129 |\
 266          TS_TTL_NONZERO | TS_ANNEX_F_EN | TS_ANNEX_D_EN |\
 267          TS_LTYPE1_EN)
 268
 269 #define CTRL_V3_ALL_TS_MASK (CTRL_V3_TS_BITS | TS_TX_EN | TS_RX_EN)
 270 #define CTRL_V3_TX_TS_BITS  (CTRL_V3_TS_BITS | TS_TX_EN)
 271 #define CTRL_V3_RX_TS_BITS  (CTRL_V3_TS_BITS | TS_RX_EN)
 272
 273 /* Bit definitions for the CPSW2_TS_SEQ_MTYPE register */
 274 #define TS_SEQ_ID_OFFSET_SHIFT   (16)    /* Time Sync Sequence ID Offset */
 275 #define TS_SEQ_ID_OFFSET_MASK    (0x3f)
 276 #define TS_MSG_TYPE_EN_SHIFT     (0)     /* Time Sync Message Type Enable */
 277 #define TS_MSG_TYPE_EN_MASK      (0xffff)
 278
 279 /* The PTP event messages - Sync, Delay_Req, Pdelay_Req, and Pdelay_Resp. */
 280 #define EVENT_MSG_BITS ((1<<0) | (1<<1) | (1<<2) | (1<<3))
 281
 282 /* Bit definitions for the CPSW1_TS_CTL register */
 283 #define CPSW_V1_TS_RX_EN                BIT(0)
 284 #define CPSW_V1_TS_TX_EN                BIT(4)
 285 #define CPSW_V1_MSG_TYPE_OFS            16
 286
 287 /* Bit definitions for the CPSW1_TS_SEQ_LTYPE register */
 288 #define CPSW_V1_SEQ_ID_OFS_SHIFT        16
 289
 290 #define CPSW_MAX_BLKS_TX                15
 291 #define CPSW_MAX_BLKS_TX_SHIFT          4
 292 #define CPSW_MAX_BLKS_RX                5
 293
 294 struct cpsw_host_regs {
 295         u32     max_blks;
 296         u32     blk_cnt;
 297         u32     tx_in_ctl;
 298         u32     port_vlan;
 299         u32     tx_pri_map;
 300         u32     cpdma_tx_pri_map;
 301         u32     cpdma_rx_chan_map;
 302 };
 303
 304 struct cpsw_sliver_regs {
 305         u32     id_ver;
 306         u32     mac_control;
 307         u32     mac_status;
 308         u32     soft_reset;
 309         u32     rx_maxlen;
 310         u32     __reserved_0;
 311         u32     rx_pause;
 312         u32     tx_pause;
 313         u32     __reserved_1;
 314         u32     rx_pri_map;
 315 };
 316
 317 struct cpsw_hw_stats {
 318         u32     rxgoodframes;
 319         u32     rxbroadcastframes;
 320         u32     rxmulticastframes;
 321         u32     rxpauseframes;
 322         u32     rxcrcerrors;
 323         u32     rxaligncodeerrors;
 324         u32     rxoversizedframes;
 325         u32     rxjabberframes;
 326         u32     rxundersizedframes;
 327         u32     rxfragments;
 328         u32     __pad_0[2];
 329         u32     rxoctets;
 330         u32     txgoodframes;
 331         u32     txbroadcastframes;
 332         u32     txmulticastframes;
 333         u32     txpauseframes;
 334         u32     txdeferredframes;
 335         u32     txcollisionframes;
 336         u32     txsinglecollframes;
 337         u32     txmultcollframes;
 338         u32     txexcessivecollisions;
 339         u32     txlatecollisions;
 340         u32     txunderrun;
 341         u32     txcarriersenseerrors;
 342         u32     txoctets;
 343         u32     octetframes64;
 344         u32     octetframes65t127;
 345         u32     octetframes128t255;
 346         u32     octetframes256t511;
 347         u32     octetframes512t1023;
 348         u32     octetframes1024tup;
 349         u32     netoctets;
 350         u32     rxsofoverruns;
 351         u32     rxmofoverruns;
 352         u32     rxdmaoverruns;
 353 };
 354
 355 struct cpsw_slave {
 356         void __iomem                    *regs;
 357         struct cpsw_sliver_regs __iomem *sliver;
 358         int                             slave_num;
 359         u32                             mac_control;
 360         struct cpsw_slave_data          *data;
 361         struct phy_device               *phy;
 362         struct net_device               *ndev;
 363         u32                             port_vlan;
 364 };
 365
 366 static inline u32 slave_read(struct cpsw_slave *slave, u32 offset)
 367 {
 368         return __raw_readl(slave->regs + offset);
 369 }
 370
 371 static inline void slave_write(struct cpsw_slave *slave, u32 val, u32 offset)
 372 {
 373         __raw_writel(val, slave->regs + offset);
 374 }
 375
 376 struct cpsw_vector {
 377         struct cpdma_chan *ch;
 378         int budget;
 379 };
 380
 381 struct cpsw_common {
 382         struct device                   *dev;
 383         struct cpsw_platform_data       data;
 384         struct napi_struct              napi_rx;
 385         struct napi_struct              napi_tx;
 386         struct cpsw_ss_regs __iomem     *regs;
 387         struct cpsw_wr_regs __iomem     *wr_regs;
 388         u8 __iomem                      *hw_stats;
 389         struct cpsw_host_regs __iomem   *host_port_regs;
 390         u32                             version;
 391         u32                             coal_intvl;
 392         u32                             bus_freq_mhz;
 393         int                             rx_packet_max;
 394         struct cpsw_slave               *slaves;
 395         struct cpdma_ctlr               *dma;
 396         struct cpsw_vector              txv[CPSW_MAX_QUEUES];
 397         struct cpsw_vector              rxv[CPSW_MAX_QUEUES];
 398         struct cpsw_ale                 *ale;
 399         bool                            quirk_irq;
 400         bool                            rx_irq_disabled;
 401         bool                            tx_irq_disabled;
 402         u32 irqs_table[IRQ_NUM];
 403         struct cpts                     *cpts;
 404         int                             rx_ch_num, tx_ch_num;
 405         int                             speed;
 406         int                             usage_count;
 407 };
 408
 409 struct cpsw_priv {
 410         struct net_device               *ndev;
 411         struct device                   *dev;
 412         u32                             msg_enable;
 413         u8                              mac_addr[ETH_ALEN];
 414         bool                            rx_pause;
 415         bool                            tx_pause;
 416         u32 emac_port;
 417         struct cpsw_common *cpsw;
 418 };
 419
 420 struct cpsw_stats {
 421         char stat_string[ETH_GSTRING_LEN];
 422         int type;
 423         int sizeof_stat;
 424         int stat_offset;
 425 };
 426
 427 enum {
 428         CPSW_STATS,
 429         CPDMA_RX_STATS,
 430         CPDMA_TX_STATS,
 431 };
 432
 433 #define CPSW_STAT(m)            CPSW_STATS,                             \
 434                                 sizeof(((struct cpsw_hw_stats *)0)->m), \
 435                                 offsetof(struct cpsw_hw_stats, m)
 436 #define CPDMA_RX_STAT(m)        CPDMA_RX_STATS,                            \
 437                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 438                                 offsetof(struct cpdma_chan_stats, m)
 439 #define CPDMA_TX_STAT(m)        CPDMA_TX_STATS,                            \
 440                                 sizeof(((struct cpdma_chan_stats *)0)->m), \
 441                                 offsetof(struct cpdma_chan_stats, m)
 442
 443 static const struct cpsw_stats cpsw_gstrings_stats[] = {
 444         { "Good Rx Frames", CPSW_STAT(rxgoodframes) },
 445         { "Broadcast Rx Frames", CPSW_STAT(rxbroadcastframes) },
 446         { "Multicast Rx Frames", CPSW_STAT(rxmulticastframes) },
 447         { "Pause Rx Frames", CPSW_STAT(rxpauseframes) },
 448         { "Rx CRC Errors", CPSW_STAT(rxcrcerrors) },
 449         { "Rx Align/Code Errors", CPSW_STAT(rxaligncodeerrors) },
 450         { "Oversize Rx Frames", CPSW_STAT(rxoversizedframes) },
 451         { "Rx Jabbers", CPSW_STAT(rxjabberframes) },
 452         { "Undersize (Short) Rx Frames", CPSW_STAT(rxundersizedframes) },
 453         { "Rx Fragments", CPSW_STAT(rxfragments) },
 454         { "Rx Octets", CPSW_STAT(rxoctets) },
 455         { "Good Tx Frames", CPSW_STAT(txgoodframes) },
 456         { "Broadcast Tx Frames", CPSW_STAT(txbroadcastframes) },
 457         { "Multicast Tx Frames", CPSW_STAT(txmulticastframes) },
 458         { "Pause Tx Frames", CPSW_STAT(txpauseframes) },
 459         { "Deferred Tx Frames", CPSW_STAT(txdeferredframes) },
 460         { "Collisions", CPSW_STAT(txcollisionframes) },
 461         { "Single Collision Tx Frames", CPSW_STAT(txsinglecollframes) },
 462         { "Multiple Collision Tx Frames", CPSW_STAT(txmultcollframes) },
 463         { "Excessive Collisions", CPSW_STAT(txexcessivecollisions) },
 464         { "Late Collisions", CPSW_STAT(txlatecollisions) },
 465         { "Tx Underrun", CPSW_STAT(txunderrun) },
 466         { "Carrier Sense Errors", CPSW_STAT(txcarriersenseerrors) },
 467         { "Tx Octets", CPSW_STAT(txoctets) },
 468         { "Rx + Tx 64 Octet Frames", CPSW_STAT(octetframes64) },
 469         { "Rx + Tx 65-127 Octet Frames", CPSW_STAT(octetframes65t127) },
 470         { "Rx + Tx 128-255 Octet Frames", CPSW_STAT(octetframes128t255) },
 471         { "Rx + Tx 256-511 Octet Frames", CPSW_STAT(octetframes256t511) },
 472         { "Rx + Tx 512-1023 Octet Frames", CPSW_STAT(octetframes512t1023) },
 473         { "Rx + Tx 1024-Up Octet Frames", CPSW_STAT(octetframes1024tup) },
 474         { "Net Octets", CPSW_STAT(netoctets) },
 475         { "Rx Start of Frame Overruns", CPSW_STAT(rxsofoverruns) },
 476         { "Rx Middle of Frame Overruns", CPSW_STAT(rxmofoverruns) },
 477         { "Rx DMA Overruns", CPSW_STAT(rxdmaoverruns) },
 478 };
 479
 480 static const struct cpsw_stats cpsw_gstrings_ch_stats[] = {
 481         { "head_enqueue", CPDMA_RX_STAT(head_enqueue) },
 482         { "tail_enqueue", CPDMA_RX_STAT(tail_enqueue) },
 483         { "pad_enqueue", CPDMA_RX_STAT(pad_enqueue) },
 484         { "misqueued", CPDMA_RX_STAT(misqueued) },
 485         { "desc_alloc_fail", CPDMA_RX_STAT(desc_alloc_fail) },
 486         { "pad_alloc_fail", CPDMA_RX_STAT(pad_alloc_fail) },
 487         { "runt_receive_buf", CPDMA_RX_STAT(runt_receive_buff) },
 488         { "runt_transmit_buf", CPDMA_RX_STAT(runt_transmit_buff) },
 489         { "empty_dequeue", CPDMA_RX_STAT(empty_dequeue) },
 490         { "busy_dequeue", CPDMA_RX_STAT(busy_dequeue) },
 491         { "good_dequeue", CPDMA_RX_STAT(good_dequeue) },
 492         { "requeue", CPDMA_RX_STAT(requeue) },
 493         { "teardown_dequeue", CPDMA_RX_STAT(teardown_dequeue) },
 494 };
 495
 496 #define CPSW_STATS_COMMON_LEN   ARRAY_SIZE(cpsw_gstrings_stats)
 497 #define CPSW_STATS_CH_LEN       ARRAY_SIZE(cpsw_gstrings_ch_stats)
 498
 499 #define ndev_to_cpsw(ndev) (((struct cpsw_priv *)netdev_priv(ndev))->cpsw)
 500 #define napi_to_cpsw(napi)      container_of(napi, struct cpsw_common, napi)
 501 #define for_each_slave(priv, func, arg...)                              \
 502         do {                                                            \
 503                 struct cpsw_slave *slave;                               \
 504                 struct cpsw_common *cpsw = (priv)->cpsw;                \
 505                 int n;                                                  \
 506                 if (cpsw->data.dual_emac)                               \
 507                         (func)((cpsw)->slaves + priv->emac_port, ##arg);\
 508                 else                                                    \
 509                         for (n = cpsw->data.slaves,                     \
 510                                         slave = cpsw->slaves;           \
 511                                         n; n--)                         \
 512                                 (func)(slave++, ##arg);                 \
 513         } while (0)
 514
 515 #define cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb)         \
 516         do {                                                            \
 517                 if (!cpsw->data.dual_emac)                              \
 518                         break;                                          \
 519                 if (CPDMA_RX_SOURCE_PORT(status) == 1) {                \
 520                         ndev = cpsw->slaves[0].ndev;                    \
 521                         skb->dev = ndev;                                \
 522                 } else if (CPDMA_RX_SOURCE_PORT(status) == 2) {         \
 523                         ndev = cpsw->slaves[1].ndev;                    \
 524                         skb->dev = ndev;                                \
 525                 }                                                       \
 526         } while (0)
 527 #define cpsw_add_mcast(cpsw, priv, addr)                                \
 528         do {                                                            \
 529                 if (cpsw->data.dual_emac) {                             \
 530                         struct cpsw_slave *slave = cpsw->slaves +       \
 531                                                 priv->emac_port;        \
 532                         int slave_port = cpsw_get_slave_port(           \
 533                                                 slave->slave_num);      \
 534                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 535                                 1 << slave_port | ALE_PORT_HOST,        \
 536                                 ALE_VLAN, slave->port_vlan, 0);         \
 537                 } else {                                                \
 538                         cpsw_ale_add_mcast(cpsw->ale, addr,             \
 539                                 ALE_ALL_PORTS,                          \
 540                                 0, 0, 0);                               \
 541                 }                                                       \
 542         } while (0)
 543
 544 static inline int cpsw_get_slave_port(u32 slave_num)
 545 {
 546         return slave_num + 1;
 547 }
 548
 549 static void cpsw_set_promiscious(struct net_device *ndev, bool enable)
 550 {
 551         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
 552         struct cpsw_ale *ale = cpsw->ale;
 553         int i;
 554
 555         if (cpsw->data.dual_emac) {
 556                 bool flag = false;
 557
 558                 /* Enabling promiscuous mode for one interface will be
 559                  * common for both the interface as the interface shares
 560                  * the same hardware resource.
 561                  */
 562                 for (i = 0; i < cpsw->data.slaves; i++)
 563                         if (cpsw->slaves[i].ndev->flags & IFF_PROMISC)
 564                                 flag = true;
 565
 566                 if (!enable && flag) {
 567                         enable = true;
 568                         dev_err(&ndev->dev, "promiscuity not disabled as the other interface is still in promiscuity mode\n");
 569                 }
 570
 571                 if (enable) {
 572                         /* Enable Bypass */
 573                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 1);
 574
 575                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 576                 } else {
 577                         /* Disable Bypass */
 578                         cpsw_ale_control_set(ale, 0, ALE_BYPASS, 0);
 579                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 580                 }
 581         } else {
 582                 if (enable) {
 583                         unsigned long timeout = jiffies + HZ;
 584
 585                         /* Disable Learn for all ports (host is port 0 and slaves are port 1 and up */
 586                         for (i = 0; i <= cpsw->data.slaves; i++) {
 587                                 cpsw_ale_control_set(ale, i,
 588                                                      ALE_PORT_NOLEARN, 1);
 589                                 cpsw_ale_control_set(ale, i,
 590                                                      ALE_PORT_NO_SA_UPDATE, 1);
 591                         }
 592
 593                         /* Clear All Untouched entries */
 594                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 595                         do {
 596                                 cpu_relax();
 597                                 if (cpsw_ale_control_get(ale, 0, ALE_AGEOUT))
 598                                         break;
 599                         } while (time_after(timeout, jiffies));
 600                         cpsw_ale_control_set(ale, 0, ALE_AGEOUT, 1);
 601
 602                         /* Clear all mcast from ALE */
 603                         cpsw_ale_flush_multicast(ale, ALE_ALL_PORTS, -1);
 604
 605                         /* Flood All Unicast Packets to Host port */
 606                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 1);
 607                         dev_dbg(&ndev->dev, "promiscuity enabled\n");
 608                 } else {
 609                         /* Don't Flood All Unicast Packets to Host port */
 610                         cpsw_ale_control_set(ale, 0, ALE_P0_UNI_FLOOD, 0);
 611
 612                         /* Enable Learn for all ports (host is port 0 and slaves are port 1 and up */
 613                         for (i = 0; i <= cpsw->data.slaves; i++) {
 614                                 cpsw_ale_control_set(ale, i,
 615                                                      ALE_PORT_NOLEARN, 0);
 616                                 cpsw_ale_control_set(ale, i,
 617                                                      ALE_PORT_NO_SA_UPDATE, 0);
 618                         }
 619                         dev_dbg(&ndev->dev, "promiscuity disabled\n");
 620                 }
 621         }
 622 }
 623
 624 static void cpsw_ndo_set_rx_mode(struct net_device *ndev)
 625 {
 626         struct cpsw_priv *priv = netdev_priv(ndev);
 627         struct cpsw_common *cpsw = priv->cpsw;
 628         int vid;
 629
 630         if (cpsw->data.dual_emac)
 631                 vid = cpsw->slaves[priv->emac_port].port_vlan;
 632         else
 633                 vid = cpsw->data.default_vlan;
 634
 635         if (ndev->flags & IFF_PROMISC) {
 636                 /* Enable promiscuous mode */
 637                 cpsw_set_promiscious(ndev, true);
 638                 cpsw_ale_set_allmulti(cpsw->ale, IFF_ALLMULTI);
 639                 return;
 640         } else {
 641                 /* Disable promiscuous mode */
 642                 cpsw_set_promiscious(ndev, false);
 643         }
 644
 645         /* Restore allmulti on vlans if necessary */
 646         cpsw_ale_set_allmulti(cpsw->ale, priv->ndev->flags & IFF_ALLMULTI);
 647
 648         /* Clear all mcast from ALE */
 649         cpsw_ale_flush_multicast(cpsw->ale, ALE_ALL_PORTS, vid);
 650
 651         if (!netdev_mc_empty(ndev)) {
 652                 struct netdev_hw_addr *ha;
 653
 654                 /* program multicast address list into ALE register */
 655                 netdev_for_each_mc_addr(ha, ndev) {
 656                         cpsw_add_mcast(cpsw, priv, (u8 *)ha->addr);
 657                 }
 658         }
 659 }
 660
 661 static void cpsw_intr_enable(struct cpsw_common *cpsw)
 662 {
 663         __raw_writel(0xFF, &cpsw->wr_regs->tx_en);
 664         __raw_writel(0xFF, &cpsw->wr_regs->rx_en);
 665
 666         cpdma_ctlr_int_ctrl(cpsw->dma, true);
 667         return;
 668 }
 669
 670 static void cpsw_intr_disable(struct cpsw_common *cpsw)
 671 {
 672         __raw_writel(0, &cpsw->wr_regs->tx_en);
 673         __raw_writel(0, &cpsw->wr_regs->rx_en);
 674
 675         cpdma_ctlr_int_ctrl(cpsw->dma, false);
 676         return;
 677 }
 678
 679 static void cpsw_tx_handler(void *token, int len, int status)
 680 {
 681         struct netdev_queue     *txq;
 682         struct sk_buff          *skb = token;
 683         struct net_device       *ndev = skb->dev;
 684         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 685
 686         /* Check whether the queue is stopped due to stalled tx dma, if the
 687          * queue is stopped then start the queue as we have free desc for tx
 688          */
 689         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
 690         if (unlikely(netif_tx_queue_stopped(txq)))
 691                 netif_tx_wake_queue(txq);
 692
 693         cpts_tx_timestamp(cpsw->cpts, skb);
 694         ndev->stats.tx_packets++;
 695         ndev->stats.tx_bytes += len;
 696         dev_kfree_skb_any(skb);
 697 }
 698
 699 static void cpsw_rx_handler(void *token, int len, int status)
 700 {
 701         struct cpdma_chan       *ch;
 702         struct sk_buff          *skb = token;
 703         struct sk_buff          *new_skb;
 704         struct net_device       *ndev = skb->dev;
 705         int                     ret = 0;
 706         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
 707
 708         cpsw_dual_emac_src_port_detect(cpsw, status, ndev, skb);
 709
 710         if (unlikely(status < 0) || unlikely(!netif_running(ndev))) {
 711                 /* In dual emac mode check for all interfaces */
 712                 if (cpsw->data.dual_emac && cpsw->usage_count &&
 713                     (status >= 0)) {
 714                         /* The packet received is for the interface which
 715                          * is already down and the other interface is up
 716                          * and running, instead of freeing which results
 717                          * in reducing of the number of rx descriptor in
 718                          * DMA engine, requeue skb back to cpdma.
 719                          */
 720                         new_skb = skb;
 721                         goto requeue;
 722                 }
 723
 724                 /* the interface is going down, skbs are purged */
 725                 dev_kfree_skb_any(skb);
 726                 return;
 727         }
 728
 729         new_skb = netdev_alloc_skb_ip_align(ndev, cpsw->rx_packet_max);
 730         if (new_skb) {
 731                 skb_copy_queue_mapping(new_skb, skb);
 732                 skb_put(skb, len);
 733                 cpts_rx_timestamp(cpsw->cpts, skb);
 734                 skb->protocol = eth_type_trans(skb, ndev);
 735                 netif_receive_skb(skb);
 736                 ndev->stats.rx_bytes += len;
 737                 ndev->stats.rx_packets++;
 738                 kmemleak_not_leak(new_skb);
 739         } else {
 740                 ndev->stats.rx_dropped++;
 741                 new_skb = skb;
 742         }
 743
 744 requeue:
 745         if (netif_dormant(ndev)) {
 746                 dev_kfree_skb_any(new_skb);
 747                 return;
 748         }
 749
 750         ch = cpsw->rxv[skb_get_queue_mapping(new_skb)].ch;
 751         ret = cpdma_chan_submit(ch, new_skb, new_skb->data,
 752                                 skb_tailroom(new_skb), 0);
 753         if (WARN_ON(ret < 0))
 754                 dev_kfree_skb_any(new_skb);
 755 }
 756
 757 static void cpsw_split_res(struct net_device *ndev)
 758 {
 759         struct cpsw_priv *priv = netdev_priv(ndev);
 760         u32 consumed_rate = 0, bigest_rate = 0;
 761         struct cpsw_common *cpsw = priv->cpsw;
 762         struct cpsw_vector *txv = cpsw->txv;
 763         int i, ch_weight, rlim_ch_num = 0;
 764         int budget, bigest_rate_ch = 0;
 765         u32 ch_rate, max_rate;
 766         int ch_budget = 0;
 767
 768         for (i = 0; i < cpsw->tx_ch_num; i++) {
 769                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 770                 if (!ch_rate)
 771                         continue;
 772
 773                 rlim_ch_num++;
 774                 consumed_rate += ch_rate;
 775         }
 776
 777         if (cpsw->tx_ch_num == rlim_ch_num) {
 778                 max_rate = consumed_rate;
 779         } else if (!rlim_ch_num) {
 780                 ch_budget = CPSW_POLL_WEIGHT / cpsw->tx_ch_num;
 781                 bigest_rate = 0;
 782                 max_rate = consumed_rate;
 783         } else {
 784                 max_rate = cpsw->speed * 1000;
 785
 786                 /* if max_rate is less then expected due to reduced link speed,
 787                  * split proportionally according next potential max speed
 788                  */
 789                 if (max_rate < consumed_rate)
 790                         max_rate *= 10;
 791
 792                 if (max_rate < consumed_rate)
 793                         max_rate *= 10;
 794
 795                 ch_budget = (consumed_rate * CPSW_POLL_WEIGHT) / max_rate;
 796                 ch_budget = (CPSW_POLL_WEIGHT - ch_budget) /
 797                             (cpsw->tx_ch_num - rlim_ch_num);
 798                 bigest_rate = (max_rate - consumed_rate) /
 799                               (cpsw->tx_ch_num - rlim_ch_num);
 800         }
 801
 802         /* split tx weight/budget */
 803         budget = CPSW_POLL_WEIGHT;
 804         for (i = 0; i < cpsw->tx_ch_num; i++) {
 805                 ch_rate = cpdma_chan_get_rate(txv[i].ch);
 806                 if (ch_rate) {
 807                         txv[i].budget = (ch_rate * CPSW_POLL_WEIGHT) / max_rate;
 808                         if (!txv[i].budget)
 809                                 txv[i].budget++;
 810                         if (ch_rate > bigest_rate) {
 811                                 bigest_rate_ch = i;
 812                                 bigest_rate = ch_rate;
 813                         }
 814
 815                         ch_weight = (ch_rate * 100) / max_rate;
 816                         if (!ch_weight)
 817                                 ch_weight++;
 818                         cpdma_chan_set_weight(cpsw->txv[i].ch, ch_weight);
 819                 } else {
 820                         txv[i].budget = ch_budget;
 821                         if (!bigest_rate_ch)
 822                                 bigest_rate_ch = i;
 823                         cpdma_chan_set_weight(cpsw->txv[i].ch, 0);
 824                 }
 825
 826                 budget -= txv[i].budget;
 827         }
 828
 829         if (budget)
 830                 txv[bigest_rate_ch].budget += budget;
 831
 832         /* split rx budget */
 833         budget = CPSW_POLL_WEIGHT;
 834         ch_budget = budget / cpsw->rx_ch_num;
 835         for (i = 0; i < cpsw->rx_ch_num; i++) {
 836                 cpsw->rxv[i].budget = ch_budget;
 837                 budget -= ch_budget;
 838         }
 839
 840         if (budget)
 841                 cpsw->rxv[0].budget += budget;
 842 }
 843
 844 static irqreturn_t cpsw_tx_interrupt(int irq, void *dev_id)
 845 {
 846         struct cpsw_common *cpsw = dev_id;
 847
 848         writel(0, &cpsw->wr_regs->tx_en);
 849         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_TX);
 850
 851         if (cpsw->quirk_irq) {
 852                 disable_irq_nosync(cpsw->irqs_table[1]);
 853                 cpsw->tx_irq_disabled = true;
 854         }
 855
 856         napi_schedule(&cpsw->napi_tx);
 857         return IRQ_HANDLED;
 858 }
 859
 860 static irqreturn_t cpsw_rx_interrupt(int irq, void *dev_id)
 861 {
 862         struct cpsw_common *cpsw = dev_id;
 863
 864         cpdma_ctlr_eoi(cpsw->dma, CPDMA_EOI_RX);
 865         writel(0, &cpsw->wr_regs->rx_en);
 866
 867         if (cpsw->quirk_irq) {
 868                 disable_irq_nosync(cpsw->irqs_table[0]);
 869                 cpsw->rx_irq_disabled = true;
 870         }
 871
 872         napi_schedule(&cpsw->napi_rx);
 873         return IRQ_HANDLED;
 874 }
 875
 876 static int cpsw_tx_poll(struct napi_struct *napi_tx, int budget)
 877 {
 878         u32                     ch_map;
 879         int                     num_tx, cur_budget, ch;
 880         struct cpsw_common      *cpsw = napi_to_cpsw(napi_tx);
 881         struct cpsw_vector      *txv;
 882
 883         /* process every unprocessed channel */
 884         ch_map = cpdma_ctrl_txchs_state(cpsw->dma);
 885         for (ch = 0, num_tx = 0; ch_map; ch_map >>= 1, ch++) {
 886                 if (!(ch_map & 0x01))
 887                         continue;
 888
 889                 txv = &cpsw->txv[ch];
 890                 if (unlikely(txv->budget > budget - num_tx))
 891                         cur_budget = budget - num_tx;
 892                 else
 893                         cur_budget = txv->budget;
 894
 895                 num_tx += cpdma_chan_process(txv->ch, cur_budget);
 896                 if (num_tx >= budget)
 897                         break;
 898         }
 899
 900         if (num_tx < budget) {
 901                 napi_complete(napi_tx);
 902                 writel(0xff, &cpsw->wr_regs->tx_en);
 903                 if (cpsw->quirk_irq && cpsw->tx_irq_disabled) {
 904                         cpsw->tx_irq_disabled = false;
 905                         enable_irq(cpsw->irqs_table[1]);
 906                 }
 907         }
 908
 909         return num_tx;
 910 }
 911
 912 static int cpsw_rx_poll(struct napi_struct *napi_rx, int budget)
 913 {
 914         u32                     ch_map;
 915         int                     num_rx, cur_budget, ch;
 916         struct cpsw_common      *cpsw = napi_to_cpsw(napi_rx);
 917         struct cpsw_vector      *rxv;
 918
 919         /* process every unprocessed channel */
 920         ch_map = cpdma_ctrl_rxchs_state(cpsw->dma);
 921         for (ch = 0, num_rx = 0; ch_map; ch_map >>= 1, ch++) {
 922                 if (!(ch_map & 0x01))
 923                         continue;
 924
 925                 rxv = &cpsw->rxv[ch];
 926                 if (unlikely(rxv->budget > budget - num_rx))
 927                         cur_budget = budget - num_rx;
 928                 else
 929                         cur_budget = rxv->budget;
 930
 931                 num_rx += cpdma_chan_process(rxv->ch, cur_budget);
 932                 if (num_rx >= budget)
 933                         break;
 934         }
 935
 936         if (num_rx < budget) {
 937                 napi_complete_done(napi_rx, num_rx);
 938                 writel(0xff, &cpsw->wr_regs->rx_en);
 939                 if (cpsw->quirk_irq && cpsw->rx_irq_disabled) {
 940                         cpsw->rx_irq_disabled = false;
 941                         enable_irq(cpsw->irqs_table[0]);
 942                 }
 943         }
 944
 945         return num_rx;
 946 }
 947
 948 static inline void soft_reset(const char *module, void __iomem *reg)
 949 {
 950         unsigned long timeout = jiffies + HZ;
 951
 952         __raw_writel(1, reg);
 953         do {
 954                 cpu_relax();
 955         } while ((__raw_readl(reg) & 1) && time_after(timeout, jiffies));
 956
 957         WARN(__raw_readl(reg) & 1, "failed to soft-reset %s\n", module);
 958 }
 959
 960 #define mac_hi(mac)     (((mac)[0] << 0) | ((mac)[1] << 8) |    \
 961                          ((mac)[2] << 16) | ((mac)[3] << 24))
 962 #define mac_lo(mac)     (((mac)[4] << 0) | ((mac)[5] << 8))
 963
 964 static void cpsw_set_slave_mac(struct cpsw_slave *slave,
 965                                struct cpsw_priv *priv)
 966 {
 967         slave_write(slave, mac_hi(priv->mac_addr), SA_HI);
 968         slave_write(slave, mac_lo(priv->mac_addr), SA_LO);
 969 }
 970
 971 static void _cpsw_adjust_link(struct cpsw_slave *slave,
 972                               struct cpsw_priv *priv, bool *link)
 973 {
 974         struct phy_device       *phy = slave->phy;
 975         u32                     mac_control = 0;
 976         u32                     slave_port;
 977         struct cpsw_common *cpsw = priv->cpsw;
 978
 979         if (!phy)
 980                 return;
 981
 982         slave_port = cpsw_get_slave_port(slave->slave_num);
 983
 984         if (phy->link) {
 985                 mac_control = cpsw->data.mac_control;
 986
 987                 /* enable forwarding */
 988                 cpsw_ale_control_set(cpsw->ale, slave_port,
 989                                      ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
 990
 991                 if (phy->speed == 1000)
 992                         mac_control |= BIT(7);  /* GIGABITEN    */
 993                 if (phy->duplex)
 994                         mac_control |= BIT(0);  /* FULLDUPLEXEN */
 995
 996                 /* set speed_in input in case RMII mode is used in 100Mbps */
 997                 if (phy->speed == 100)
 998                         mac_control |= BIT(15);
 999                 else if (phy->speed == 10)
1000                         mac_control |= BIT(18); /* In Band mode */
1001
1002                 if (priv->rx_pause)
1003                         mac_control |= BIT(3);
1004
1005                 if (priv->tx_pause)
1006                         mac_control |= BIT(4);
1007
1008                 *link = true;
1009         } else {
1010                 mac_control = 0;
1011                 /* disable forwarding */
1012                 cpsw_ale_control_set(cpsw->ale, slave_port,
1013                                      ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1014         }
1015
1016         if (mac_control != slave->mac_control) {
1017                 phy_print_status(phy);
1018                 __raw_writel(mac_control, &slave->sliver->mac_control);
1019         }
1020
1021         slave->mac_control = mac_control;
1022 }
1023
1024 static int cpsw_get_common_speed(struct cpsw_common *cpsw)
1025 {
1026         int i, speed;
1027
1028         for (i = 0, speed = 0; i < cpsw->data.slaves; i++)
1029                 if (cpsw->slaves[i].phy && cpsw->slaves[i].phy->link)
1030                         speed += cpsw->slaves[i].phy->speed;
1031
1032         return speed;
1033 }
1034
1035 static int cpsw_need_resplit(struct cpsw_common *cpsw)
1036 {
1037         int i, rlim_ch_num;
1038         int speed, ch_rate;
1039
1040         /* re-split resources only in case speed was changed */
1041         speed = cpsw_get_common_speed(cpsw);
1042         if (speed == cpsw->speed || !speed)
1043                 return 0;
1044
1045         cpsw->speed = speed;
1046
1047         for (i = 0, rlim_ch_num = 0; i < cpsw->tx_ch_num; i++) {
1048                 ch_rate = cpdma_chan_get_rate(cpsw->txv[i].ch);
1049                 if (!ch_rate)
1050                         break;
1051
1052                 rlim_ch_num++;
1053         }
1054
1055         /* cases not dependent on speed */
1056         if (!rlim_ch_num || rlim_ch_num == cpsw->tx_ch_num)
1057                 return 0;
1058
1059         return 1;
1060 }
1061
1062 static void cpsw_adjust_link(struct net_device *ndev)
1063 {
1064         struct cpsw_priv        *priv = netdev_priv(ndev);
1065         struct cpsw_common      *cpsw = priv->cpsw;
1066         bool                    link = false;
1067
1068         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
1069
1070         if (link) {
1071                 if (cpsw_need_resplit(cpsw))
1072                         cpsw_split_res(ndev);
1073
1074                 netif_carrier_on(ndev);
1075                 if (netif_running(ndev))
1076                         netif_tx_wake_all_queues(ndev);
1077         } else {
1078                 netif_carrier_off(ndev);
1079                 netif_tx_stop_all_queues(ndev);
1080         }
1081 }
1082
1083 static int cpsw_get_coalesce(struct net_device *ndev,
1084                                 struct ethtool_coalesce *coal)
1085 {
1086         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1087
1088         coal->rx_coalesce_usecs = cpsw->coal_intvl;
1089         return 0;
1090 }
1091
1092 static int cpsw_set_coalesce(struct net_device *ndev,
1093                                 struct ethtool_coalesce *coal)
1094 {
1095         struct cpsw_priv *priv = netdev_priv(ndev);
1096         u32 int_ctrl;
1097         u32 num_interrupts = 0;
1098         u32 prescale = 0;
1099         u32 addnl_dvdr = 1;
1100         u32 coal_intvl = 0;
1101         struct cpsw_common *cpsw = priv->cpsw;
1102
1103         coal_intvl = coal->rx_coalesce_usecs;
1104
1105         int_ctrl =  readl(&cpsw->wr_regs->int_control);
1106         prescale = cpsw->bus_freq_mhz * 4;
1107
1108         if (!coal->rx_coalesce_usecs) {
1109                 int_ctrl &= ~(CPSW_INTPRESCALE_MASK | CPSW_INTPACEEN);
1110                 goto update_return;
1111         }
1112
1113         if (coal_intvl < CPSW_CMINTMIN_INTVL)
1114                 coal_intvl = CPSW_CMINTMIN_INTVL;
1115
1116         if (coal_intvl > CPSW_CMINTMAX_INTVL) {
1117                 /* Interrupt pacer works with 4us Pulse, we can
1118                  * throttle further by dilating the 4us pulse.
1119                  */
1120                 addnl_dvdr = CPSW_INTPRESCALE_MASK / prescale;
1121
1122                 if (addnl_dvdr > 1) {
1123                         prescale *= addnl_dvdr;
1124                         if (coal_intvl > (CPSW_CMINTMAX_INTVL * addnl_dvdr))
1125                                 coal_intvl = (CPSW_CMINTMAX_INTVL
1126                                                 * addnl_dvdr);
1127                 } else {
1128                         addnl_dvdr = 1;
1129                         coal_intvl = CPSW_CMINTMAX_INTVL;
1130                 }
1131         }
1132
1133         num_interrupts = (1000 * addnl_dvdr) / coal_intvl;
1134         writel(num_interrupts, &cpsw->wr_regs->rx_imax);
1135         writel(num_interrupts, &cpsw->wr_regs->tx_imax);
1136
1137         int_ctrl |= CPSW_INTPACEEN;
1138         int_ctrl &= (~CPSW_INTPRESCALE_MASK);
1139         int_ctrl |= (prescale & CPSW_INTPRESCALE_MASK);
1140
1141 update_return:
1142         writel(int_ctrl, &cpsw->wr_regs->int_control);
1143
1144         cpsw_notice(priv, timer, "Set coalesce to %d usecs.\n", coal_intvl);
1145         cpsw->coal_intvl = coal_intvl;
1146
1147         return 0;
1148 }
1149
1150 static int cpsw_get_sset_count(struct net_device *ndev, int sset)
1151 {
1152         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1153
1154         switch (sset) {
1155         case ETH_SS_STATS:
1156                 return (CPSW_STATS_COMMON_LEN +
1157                        (cpsw->rx_ch_num + cpsw->tx_ch_num) *
1158                        CPSW_STATS_CH_LEN);
1159         default:
1160                 return -EOPNOTSUPP;
1161         }
1162 }
1163
1164 static void cpsw_add_ch_strings(u8 **p, int ch_num, int rx_dir)
1165 {
1166         int ch_stats_len;
1167         int line;
1168         int i;
1169
1170         ch_stats_len = CPSW_STATS_CH_LEN * ch_num;
1171         for (i = 0; i < ch_stats_len; i++) {
1172                 line = i % CPSW_STATS_CH_LEN;
1173                 snprintf(*p, ETH_GSTRING_LEN,
1174                          "%s DMA chan %d: %s", rx_dir ? "Rx" : "Tx",
1175                          i / CPSW_STATS_CH_LEN,
1176                          cpsw_gstrings_ch_stats[line].stat_string);
1177                 *p += ETH_GSTRING_LEN;
1178         }
1179 }
1180
1181 static void cpsw_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1182 {
1183         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1184         u8 *p = data;
1185         int i;
1186
1187         switch (stringset) {
1188         case ETH_SS_STATS:
1189                 for (i = 0; i < CPSW_STATS_COMMON_LEN; i++) {
1190                         memcpy(p, cpsw_gstrings_stats[i].stat_string,
1191                                ETH_GSTRING_LEN);
1192                         p += ETH_GSTRING_LEN;
1193                 }
1194
1195                 cpsw_add_ch_strings(&p, cpsw->rx_ch_num, 1);
1196                 cpsw_add_ch_strings(&p, cpsw->tx_ch_num, 0);
1197                 break;
1198         }
1199 }
1200
1201 static void cpsw_get_ethtool_stats(struct net_device *ndev,
1202                                     struct ethtool_stats *stats, u64 *data)
1203 {
1204         u8 *p;
1205         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1206         struct cpdma_chan_stats ch_stats;
1207         int i, l, ch;
1208
1209         /* Collect Davinci CPDMA stats for Rx and Tx Channel */
1210         for (l = 0; l < CPSW_STATS_COMMON_LEN; l++)
1211                 data[l] = readl(cpsw->hw_stats +
1212                                 cpsw_gstrings_stats[l].stat_offset);
1213
1214         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1215                 cpdma_chan_get_stats(cpsw->rxv[ch].ch, &ch_stats);
1216                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1217                         p = (u8 *)&ch_stats +
1218                                 cpsw_gstrings_ch_stats[i].stat_offset;
1219                         data[l] = *(u32 *)p;
1220                 }
1221         }
1222
1223         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1224                 cpdma_chan_get_stats(cpsw->txv[ch].ch, &ch_stats);
1225                 for (i = 0; i < CPSW_STATS_CH_LEN; i++, l++) {
1226                         p = (u8 *)&ch_stats +
1227                                 cpsw_gstrings_ch_stats[i].stat_offset;
1228                         data[l] = *(u32 *)p;
1229                 }
1230         }
1231 }
1232
1233 static inline int cpsw_tx_packet_submit(struct cpsw_priv *priv,
1234                                         struct sk_buff *skb,
1235                                         struct cpdma_chan *txch)
1236 {
1237         struct cpsw_common *cpsw = priv->cpsw;
1238
1239         skb_tx_timestamp(skb);
1240         return cpdma_chan_submit(txch, skb, skb->data, skb->len,
1241                                  priv->emac_port + cpsw->data.dual_emac);
1242 }
1243
1244 static inline void cpsw_add_dual_emac_def_ale_entries(
1245                 struct cpsw_priv *priv, struct cpsw_slave *slave,
1246                 u32 slave_port)
1247 {
1248         struct cpsw_common *cpsw = priv->cpsw;
1249         u32 port_mask = 1 << slave_port | ALE_PORT_HOST;
1250
1251         if (cpsw->version == CPSW_VERSION_1)
1252                 slave_write(slave, slave->port_vlan, CPSW1_PORT_VLAN);
1253         else
1254                 slave_write(slave, slave->port_vlan, CPSW2_PORT_VLAN);
1255         cpsw_ale_add_vlan(cpsw->ale, slave->port_vlan, port_mask,
1256                           port_mask, port_mask, 0);
1257         cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1258                            port_mask, ALE_VLAN, slave->port_vlan, 0);
1259         cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1260                            HOST_PORT_NUM, ALE_VLAN |
1261                            ALE_SECURE, slave->port_vlan);
1262 }
1263
1264 static void soft_reset_slave(struct cpsw_slave *slave)
1265 {
1266         char name[32];
1267
1268         snprintf(name, sizeof(name), "slave-%d", slave->slave_num);
1269         soft_reset(name, &slave->sliver->soft_reset);
1270 }
1271
1272 static void cpsw_slave_open(struct cpsw_slave *slave, struct cpsw_priv *priv)
1273 {
1274         u32 slave_port;
1275         struct phy_device *phy;
1276         struct cpsw_common *cpsw = priv->cpsw;
1277
1278         soft_reset_slave(slave);
1279
1280         /* setup priority mapping */
1281         __raw_writel(RX_PRIORITY_MAPPING, &slave->sliver->rx_pri_map);
1282
1283         switch (cpsw->version) {
1284         case CPSW_VERSION_1:
1285                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW1_TX_PRI_MAP);
1286                 /* Increase RX FIFO size to 5 for supporting fullduplex
1287                  * flow control mode
1288                  */
1289                 slave_write(slave,
1290                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1291                             CPSW_MAX_BLKS_RX, CPSW1_MAX_BLKS);
1292                 break;
1293         case CPSW_VERSION_2:
1294         case CPSW_VERSION_3:
1295         case CPSW_VERSION_4:
1296                 slave_write(slave, TX_PRIORITY_MAPPING, CPSW2_TX_PRI_MAP);
1297                 /* Increase RX FIFO size to 5 for supporting fullduplex
1298                  * flow control mode
1299                  */
1300                 slave_write(slave,
1301                             (CPSW_MAX_BLKS_TX << CPSW_MAX_BLKS_TX_SHIFT) |
1302                             CPSW_MAX_BLKS_RX, CPSW2_MAX_BLKS);
1303                 break;
1304         }
1305
1306         /* setup max packet size, and mac address */
1307         __raw_writel(cpsw->rx_packet_max, &slave->sliver->rx_maxlen);
1308         cpsw_set_slave_mac(slave, priv);
1309
1310         slave->mac_control = 0; /* no link yet */
1311
1312         slave_port = cpsw_get_slave_port(slave->slave_num);
1313
1314         if (cpsw->data.dual_emac)
1315                 cpsw_add_dual_emac_def_ale_entries(priv, slave, slave_port);
1316         else
1317                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1318                                    1 << slave_port, 0, 0, ALE_MCAST_FWD_2);
1319
1320         if (slave->data->phy_node) {
1321                 phy = of_phy_connect(priv->ndev, slave->data->phy_node,
1322                                  &cpsw_adjust_link, 0, slave->data->phy_if);
1323                 if (!phy) {
1324                         dev_err(priv->dev, "phy \"%s\" not found on slave %d\n",
1325                                 slave->data->phy_node->full_name,
1326                                 slave->slave_num);
1327                         return;
1328                 }
1329         } else {
1330                 phy = phy_connect(priv->ndev, slave->data->phy_id,
1331                                  &cpsw_adjust_link, slave->data->phy_if);
1332                 if (IS_ERR(phy)) {
1333                         dev_err(priv->dev,
1334                                 "phy \"%s\" not found on slave %d, err %ld\n",
1335                                 slave->data->phy_id, slave->slave_num,
1336                                 PTR_ERR(phy));
1337                         return;
1338                 }
1339         }
1340
1341         slave->phy = phy;
1342
1343         phy_attached_info(slave->phy);
1344
1345         phy_start(slave->phy);
1346
1347         /* Configure GMII_SEL register */
1348         cpsw_phy_sel(cpsw->dev, slave->phy->interface, slave->slave_num);
1349 }
1350
1351 static inline void cpsw_add_default_vlan(struct cpsw_priv *priv)
1352 {
1353         struct cpsw_common *cpsw = priv->cpsw;
1354         const int vlan = cpsw->data.default_vlan;
1355         u32 reg;
1356         int i;
1357         int unreg_mcast_mask;
1358
1359         reg = (cpsw->version == CPSW_VERSION_1) ? CPSW1_PORT_VLAN :
1360                CPSW2_PORT_VLAN;
1361
1362         writel(vlan, &cpsw->host_port_regs->port_vlan);
1363
1364         for (i = 0; i < cpsw->data.slaves; i++)
1365                 slave_write(cpsw->slaves + i, vlan, reg);
1366
1367         if (priv->ndev->flags & IFF_ALLMULTI)
1368                 unreg_mcast_mask = ALE_ALL_PORTS;
1369         else
1370                 unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1371
1372         cpsw_ale_add_vlan(cpsw->ale, vlan, ALE_ALL_PORTS,
1373                           ALE_ALL_PORTS, ALE_ALL_PORTS,
1374                           unreg_mcast_mask);
1375 }
1376
1377 static void cpsw_init_host_port(struct cpsw_priv *priv)
1378 {
1379         u32 fifo_mode;
1380         u32 control_reg;
1381         struct cpsw_common *cpsw = priv->cpsw;
1382
1383         /* soft reset the controller and initialize ale */
1384         soft_reset("cpsw", &cpsw->regs->soft_reset);
1385         cpsw_ale_start(cpsw->ale);
1386
1387         /* switch to vlan unaware mode */
1388         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM, ALE_VLAN_AWARE,
1389                              CPSW_ALE_VLAN_AWARE);
1390         control_reg = readl(&cpsw->regs->control);
1391         control_reg |= CPSW_VLAN_AWARE;
1392         writel(control_reg, &cpsw->regs->control);
1393         fifo_mode = (cpsw->data.dual_emac) ? CPSW_FIFO_DUAL_MAC_MODE :
1394                      CPSW_FIFO_NORMAL_MODE;
1395         writel(fifo_mode, &cpsw->host_port_regs->tx_in_ctl);
1396
1397         /* setup host port priority mapping */
1398         __raw_writel(CPDMA_TX_PRIORITY_MAP,
1399                      &cpsw->host_port_regs->cpdma_tx_pri_map);
1400         __raw_writel(0, &cpsw->host_port_regs->cpdma_rx_chan_map);
1401
1402         cpsw_ale_control_set(cpsw->ale, HOST_PORT_NUM,
1403                              ALE_PORT_STATE, ALE_PORT_STATE_FORWARD);
1404
1405         if (!cpsw->data.dual_emac) {
1406                 cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1407                                    0, 0);
1408                 cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1409                                    ALE_PORT_HOST, 0, 0, ALE_MCAST_FWD_2);
1410         }
1411 }
1412
1413 static int cpsw_fill_rx_channels(struct cpsw_priv *priv)
1414 {
1415         struct cpsw_common *cpsw = priv->cpsw;
1416         struct sk_buff *skb;
1417         int ch_buf_num;
1418         int ch, i, ret;
1419
1420         for (ch = 0; ch < cpsw->rx_ch_num; ch++) {
1421                 ch_buf_num = cpdma_chan_get_rx_buf_num(cpsw->rxv[ch].ch);
1422                 for (i = 0; i < ch_buf_num; i++) {
1423                         skb = __netdev_alloc_skb_ip_align(priv->ndev,
1424                                                           cpsw->rx_packet_max,
1425                                                           GFP_KERNEL);
1426                         if (!skb) {
1427                                 cpsw_err(priv, ifup, "cannot allocate skb\n");
1428                                 return -ENOMEM;
1429                         }
1430
1431                         skb_set_queue_mapping(skb, ch);
1432                         ret = cpdma_chan_submit(cpsw->rxv[ch].ch, skb,
1433                                                 skb->data, skb_tailroom(skb),
1434                                                 0);
1435                         if (ret < 0) {
1436                                 cpsw_err(priv, ifup,
1437                                          "cannot submit skb to channel %d rx, error %d\n",
1438                                          ch, ret);
1439                                 kfree_skb(skb);
1440                                 return ret;
1441                         }
1442                         kmemleak_not_leak(skb);
1443                 }
1444
1445                 cpsw_info(priv, ifup, "ch %d rx, submitted %d descriptors\n",
1446                           ch, ch_buf_num);
1447         }
1448
1449         return 0;
1450 }
1451
1452 static void cpsw_slave_stop(struct cpsw_slave *slave, struct cpsw_common *cpsw)
1453 {
1454         u32 slave_port;
1455
1456         slave_port = cpsw_get_slave_port(slave->slave_num);
1457
1458         if (!slave->phy)
1459                 return;
1460         phy_stop(slave->phy);
1461         phy_disconnect(slave->phy);
1462         slave->phy = NULL;
1463         cpsw_ale_control_set(cpsw->ale, slave_port,
1464                              ALE_PORT_STATE, ALE_PORT_STATE_DISABLE);
1465         soft_reset_slave(slave);
1466 }
1467
1468 static int cpsw_ndo_open(struct net_device *ndev)
1469 {
1470         struct cpsw_priv *priv = netdev_priv(ndev);
1471         struct cpsw_common *cpsw = priv->cpsw;
1472         int ret;
1473         u32 reg;
1474
1475         ret = pm_runtime_get_sync(cpsw->dev);
1476         if (ret < 0) {
1477                 pm_runtime_put_noidle(cpsw->dev);
1478                 return ret;
1479         }
1480
1481         netif_carrier_off(ndev);
1482
1483         /* Notify the stack of the actual queue counts. */
1484         ret = netif_set_real_num_tx_queues(ndev, cpsw->tx_ch_num);
1485         if (ret) {
1486                 dev_err(priv->dev, "cannot set real number of tx queues\n");
1487                 goto err_cleanup;
1488         }
1489
1490         ret = netif_set_real_num_rx_queues(ndev, cpsw->rx_ch_num);
1491         if (ret) {
1492                 dev_err(priv->dev, "cannot set real number of rx queues\n");
1493                 goto err_cleanup;
1494         }
1495
1496         reg = cpsw->version;
1497
1498         dev_info(priv->dev, "initializing cpsw version %d.%d (%d)\n",
1499                  CPSW_MAJOR_VERSION(reg), CPSW_MINOR_VERSION(reg),
1500                  CPSW_RTL_VERSION(reg));
1501
1502         /* Initialize host and slave ports */
1503         if (!cpsw->usage_count)
1504                 cpsw_init_host_port(priv);
1505         for_each_slave(priv, cpsw_slave_open, priv);
1506
1507         /* Add default VLAN */
1508         if (!cpsw->data.dual_emac)
1509                 cpsw_add_default_vlan(priv);
1510         else
1511                 cpsw_ale_add_vlan(cpsw->ale, cpsw->data.default_vlan,
1512                                   ALE_ALL_PORTS, ALE_ALL_PORTS, 0, 0);
1513
1514         /* initialize shared resources for every ndev */
1515         if (!cpsw->usage_count) {
1516                 /* disable priority elevation */
1517                 __raw_writel(0, &cpsw->regs->ptype);
1518
1519                 /* enable statistics collection only on all ports */
1520                 __raw_writel(0x7, &cpsw->regs->stat_port_en);
1521
1522                 /* Enable internal fifo flow control */
1523                 writel(0x7, &cpsw->regs->flow_control);
1524
1525                 napi_enable(&cpsw->napi_rx);
1526                 napi_enable(&cpsw->napi_tx);
1527
1528                 if (cpsw->tx_irq_disabled) {
1529                         cpsw->tx_irq_disabled = false;
1530                         enable_irq(cpsw->irqs_table[1]);
1531                 }
1532
1533                 if (cpsw->rx_irq_disabled) {
1534                         cpsw->rx_irq_disabled = false;
1535                         enable_irq(cpsw->irqs_table[0]);
1536                 }
1537
1538                 ret = cpsw_fill_rx_channels(priv);
1539                 if (ret < 0)
1540                         goto err_cleanup;
1541
1542                 if (cpts_register(cpsw->cpts))
1543                         dev_err(priv->dev, "error registering cpts device\n");
1544
1545         }
1546
1547         /* Enable Interrupt pacing if configured */
1548         if (cpsw->coal_intvl != 0) {
1549                 struct ethtool_coalesce coal;
1550
1551                 coal.rx_coalesce_usecs = cpsw->coal_intvl;
1552                 cpsw_set_coalesce(ndev, &coal);
1553         }
1554
1555         cpdma_ctlr_start(cpsw->dma);
1556         cpsw_intr_enable(cpsw);
1557         cpsw->usage_count++;
1558
1559         return 0;
1560
1561 err_cleanup:
1562         cpdma_ctlr_stop(cpsw->dma);
1563         for_each_slave(priv, cpsw_slave_stop, cpsw);
1564         pm_runtime_put_sync(cpsw->dev);
1565         netif_carrier_off(priv->ndev);
1566         return ret;
1567 }
1568
1569 static int cpsw_ndo_stop(struct net_device *ndev)
1570 {
1571         struct cpsw_priv *priv = netdev_priv(ndev);
1572         struct cpsw_common *cpsw = priv->cpsw;
1573
1574         cpsw_info(priv, ifdown, "shutting down cpsw device\n");
1575         netif_tx_stop_all_queues(priv->ndev);
1576         netif_carrier_off(priv->ndev);
1577
1578         if (cpsw->usage_count <= 1) {
1579                 napi_disable(&cpsw->napi_rx);
1580                 napi_disable(&cpsw->napi_tx);
1581                 cpts_unregister(cpsw->cpts);
1582                 cpsw_intr_disable(cpsw);
1583                 cpdma_ctlr_stop(cpsw->dma);
1584                 cpsw_ale_stop(cpsw->ale);
1585         }
1586         for_each_slave(priv, cpsw_slave_stop, cpsw);
1587
1588         if (cpsw_need_resplit(cpsw))
1589                 cpsw_split_res(ndev);
1590
1591         cpsw->usage_count--;
1592         pm_runtime_put_sync(cpsw->dev);
1593         return 0;
1594 }
1595
1596 static netdev_tx_t cpsw_ndo_start_xmit(struct sk_buff *skb,
1597                                        struct net_device *ndev)
1598 {
1599         struct cpsw_priv *priv = netdev_priv(ndev);
1600         struct cpsw_common *cpsw = priv->cpsw;
1601         struct cpts *cpts = cpsw->cpts;
1602         struct netdev_queue *txq;
1603         struct cpdma_chan *txch;
1604         int ret, q_idx;
1605
1606         if (skb_padto(skb, CPSW_MIN_PACKET_SIZE)) {
1607                 cpsw_err(priv, tx_err, "packet pad failed\n");
1608                 ndev->stats.tx_dropped++;
1609                 return NET_XMIT_DROP;
1610         }
1611
1612         if (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP &&
1613             cpts_is_tx_enabled(cpts) && cpts_can_timestamp(cpts, skb))
1614                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1615
1616         q_idx = skb_get_queue_mapping(skb);
1617         if (q_idx >= cpsw->tx_ch_num)
1618                 q_idx = q_idx % cpsw->tx_ch_num;
1619
1620         txch = cpsw->txv[q_idx].ch;
1621         ret = cpsw_tx_packet_submit(priv, skb, txch);
1622         if (unlikely(ret != 0)) {
1623                 cpsw_err(priv, tx_err, "desc submit failed\n");
1624                 goto fail;
1625         }
1626
1627         /* If there is no more tx desc left free then we need to
1628          * tell the kernel to stop sending us tx frames.
1629          */
1630         if (unlikely(!cpdma_check_free_tx_desc(txch))) {
1631                 txq = netdev_get_tx_queue(ndev, q_idx);
1632                 netif_tx_stop_queue(txq);
1633         }
1634
1635         return NETDEV_TX_OK;
1636 fail:
1637         ndev->stats.tx_dropped++;
1638         txq = netdev_get_tx_queue(ndev, skb_get_queue_mapping(skb));
1639         netif_tx_stop_queue(txq);
1640         return NETDEV_TX_BUSY;
1641 }
1642
1643 #if IS_ENABLED(CONFIG_TI_CPTS)
1644
1645 static void cpsw_hwtstamp_v1(struct cpsw_common *cpsw)
1646 {
1647         struct cpsw_slave *slave = &cpsw->slaves[cpsw->data.active_slave];
1648         u32 ts_en, seq_id;
1649
1650         if (!cpts_is_tx_enabled(cpsw->cpts) &&
1651             !cpts_is_rx_enabled(cpsw->cpts)) {
1652                 slave_write(slave, 0, CPSW1_TS_CTL);
1653                 return;
1654         }
1655
1656         seq_id = (30 << CPSW_V1_SEQ_ID_OFS_SHIFT) | ETH_P_1588;
1657         ts_en = EVENT_MSG_BITS << CPSW_V1_MSG_TYPE_OFS;
1658
1659         if (cpts_is_tx_enabled(cpsw->cpts))
1660                 ts_en |= CPSW_V1_TS_TX_EN;
1661
1662         if (cpts_is_rx_enabled(cpsw->cpts))
1663                 ts_en |= CPSW_V1_TS_RX_EN;
1664
1665         slave_write(slave, ts_en, CPSW1_TS_CTL);
1666         slave_write(slave, seq_id, CPSW1_TS_SEQ_LTYPE);
1667 }
1668
1669 static void cpsw_hwtstamp_v2(struct cpsw_priv *priv)
1670 {
1671         struct cpsw_slave *slave;
1672         struct cpsw_common *cpsw = priv->cpsw;
1673         u32 ctrl, mtype;
1674
1675         slave = &cpsw->slaves[cpsw_slave_index(cpsw, priv)];
1676
1677         ctrl = slave_read(slave, CPSW2_CONTROL);
1678         switch (cpsw->version) {
1679         case CPSW_VERSION_2:
1680                 ctrl &= ~CTRL_V2_ALL_TS_MASK;
1681
1682                 if (cpts_is_tx_enabled(cpsw->cpts))
1683                         ctrl |= CTRL_V2_TX_TS_BITS;
1684
1685                 if (cpts_is_rx_enabled(cpsw->cpts))
1686                         ctrl |= CTRL_V2_RX_TS_BITS;
1687                 break;
1688         case CPSW_VERSION_3:
1689         default:
1690                 ctrl &= ~CTRL_V3_ALL_TS_MASK;
1691
1692                 if (cpts_is_tx_enabled(cpsw->cpts))
1693                         ctrl |= CTRL_V3_TX_TS_BITS;
1694
1695                 if (cpts_is_rx_enabled(cpsw->cpts))
1696                         ctrl |= CTRL_V3_RX_TS_BITS;
1697                 break;
1698         }
1699
1700         mtype = (30 << TS_SEQ_ID_OFFSET_SHIFT) | EVENT_MSG_BITS;
1701
1702         slave_write(slave, mtype, CPSW2_TS_SEQ_MTYPE);
1703         slave_write(slave, ctrl, CPSW2_CONTROL);
1704         __raw_writel(ETH_P_1588, &cpsw->regs->ts_ltype);
1705 }
1706
1707 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1708 {
1709         struct cpsw_priv *priv = netdev_priv(dev);
1710         struct hwtstamp_config cfg;
1711         struct cpsw_common *cpsw = priv->cpsw;
1712         struct cpts *cpts = cpsw->cpts;
1713
1714         if (cpsw->version != CPSW_VERSION_1 &&
1715             cpsw->version != CPSW_VERSION_2 &&
1716             cpsw->version != CPSW_VERSION_3)
1717                 return -EOPNOTSUPP;
1718
1719         if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
1720                 return -EFAULT;
1721
1722         /* reserved for future extensions */
1723         if (cfg.flags)
1724                 return -EINVAL;
1725
1726         if (cfg.tx_type != HWTSTAMP_TX_OFF && cfg.tx_type != HWTSTAMP_TX_ON)
1727                 return -ERANGE;
1728
1729         switch (cfg.rx_filter) {
1730         case HWTSTAMP_FILTER_NONE:
1731                 cpts_rx_enable(cpts, 0);
1732                 break;
1733         case HWTSTAMP_FILTER_ALL:
1734         case HWTSTAMP_FILTER_NTP_ALL:
1735                 return -ERANGE;
1736         case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
1737         case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
1738         case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
1739                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V1_L4_EVENT);
1740                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
1741                 break;
1742         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
1743         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
1744         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
1745         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1746         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
1747         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
1748         case HWTSTAMP_FILTER_PTP_V2_EVENT:
1749         case HWTSTAMP_FILTER_PTP_V2_SYNC:
1750         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
1751                 cpts_rx_enable(cpts, HWTSTAMP_FILTER_PTP_V2_EVENT);
1752                 cfg.rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
1753                 break;
1754         default:
1755                 return -ERANGE;
1756         }
1757
1758         cpts_tx_enable(cpts, cfg.tx_type == HWTSTAMP_TX_ON);
1759
1760         switch (cpsw->version) {
1761         case CPSW_VERSION_1:
1762                 cpsw_hwtstamp_v1(cpsw);
1763                 break;
1764         case CPSW_VERSION_2:
1765         case CPSW_VERSION_3:
1766                 cpsw_hwtstamp_v2(priv);
1767                 break;
1768         default:
1769                 WARN_ON(1);
1770         }
1771
1772         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1773 }
1774
1775 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1776 {
1777         struct cpsw_common *cpsw = ndev_to_cpsw(dev);
1778         struct cpts *cpts = cpsw->cpts;
1779         struct hwtstamp_config cfg;
1780
1781         if (cpsw->version != CPSW_VERSION_1 &&
1782             cpsw->version != CPSW_VERSION_2 &&
1783             cpsw->version != CPSW_VERSION_3)
1784                 return -EOPNOTSUPP;
1785
1786         cfg.flags = 0;
1787         cfg.tx_type = cpts_is_tx_enabled(cpts) ?
1788                       HWTSTAMP_TX_ON : HWTSTAMP_TX_OFF;
1789         cfg.rx_filter = (cpts_is_rx_enabled(cpts) ?
1790                          cpts->rx_enable : HWTSTAMP_FILTER_NONE);
1791
1792         return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
1793 }
1794 #else
1795 static int cpsw_hwtstamp_get(struct net_device *dev, struct ifreq *ifr)
1796 {
1797         return -EOPNOTSUPP;
1798 }
1799
1800 static int cpsw_hwtstamp_set(struct net_device *dev, struct ifreq *ifr)
1801 {
1802         return -EOPNOTSUPP;
1803 }
1804 #endif /*CONFIG_TI_CPTS*/
1805
1806 static int cpsw_ndo_ioctl(struct net_device *dev, struct ifreq *req, int cmd)
1807 {
1808         struct cpsw_priv *priv = netdev_priv(dev);
1809         struct cpsw_common *cpsw = priv->cpsw;
1810         int slave_no = cpsw_slave_index(cpsw, priv);
1811
1812         if (!netif_running(dev))
1813                 return -EINVAL;
1814
1815         switch (cmd) {
1816         case SIOCSHWTSTAMP:
1817                 return cpsw_hwtstamp_set(dev, req);
1818         case SIOCGHWTSTAMP:
1819                 return cpsw_hwtstamp_get(dev, req);
1820         }
1821
1822         if (!cpsw->slaves[slave_no].phy)
1823                 return -EOPNOTSUPP;
1824         return phy_mii_ioctl(cpsw->slaves[slave_no].phy, req, cmd);
1825 }
1826
1827 static void cpsw_ndo_tx_timeout(struct net_device *ndev)
1828 {
1829         struct cpsw_priv *priv = netdev_priv(ndev);
1830         struct cpsw_common *cpsw = priv->cpsw;
1831         int ch;
1832
1833         cpsw_err(priv, tx_err, "transmit timeout, restarting dma\n");
1834         ndev->stats.tx_errors++;
1835         cpsw_intr_disable(cpsw);
1836         for (ch = 0; ch < cpsw->tx_ch_num; ch++) {
1837                 cpdma_chan_stop(cpsw->txv[ch].ch);
1838                 cpdma_chan_start(cpsw->txv[ch].ch);
1839         }
1840
1841         cpsw_intr_enable(cpsw);
1842         netif_trans_update(ndev);
1843         netif_tx_wake_all_queues(ndev);
1844 }
1845
1846 static int cpsw_ndo_set_mac_address(struct net_device *ndev, void *p)
1847 {
1848         struct cpsw_priv *priv = netdev_priv(ndev);
1849         struct sockaddr *addr = (struct sockaddr *)p;
1850         struct cpsw_common *cpsw = priv->cpsw;
1851         int flags = 0;
1852         u16 vid = 0;
1853         int ret;
1854
1855         if (!is_valid_ether_addr(addr->sa_data))
1856                 return -EADDRNOTAVAIL;
1857
1858         ret = pm_runtime_get_sync(cpsw->dev);
1859         if (ret < 0) {
1860                 pm_runtime_put_noidle(cpsw->dev);
1861                 return ret;
1862         }
1863
1864         if (cpsw->data.dual_emac) {
1865                 vid = cpsw->slaves[priv->emac_port].port_vlan;
1866                 flags = ALE_VLAN;
1867         }
1868
1869         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr, HOST_PORT_NUM,
1870                            flags, vid);
1871         cpsw_ale_add_ucast(cpsw->ale, addr->sa_data, HOST_PORT_NUM,
1872                            flags, vid);
1873
1874         memcpy(priv->mac_addr, addr->sa_data, ETH_ALEN);
1875         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
1876         for_each_slave(priv, cpsw_set_slave_mac, priv);
1877
1878         pm_runtime_put(cpsw->dev);
1879
1880         return 0;
1881 }
1882
1883 #ifdef CONFIG_NET_POLL_CONTROLLER
1884 static void cpsw_ndo_poll_controller(struct net_device *ndev)
1885 {
1886         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
1887
1888         cpsw_intr_disable(cpsw);
1889         cpsw_rx_interrupt(cpsw->irqs_table[0], cpsw);
1890         cpsw_tx_interrupt(cpsw->irqs_table[1], cpsw);
1891         cpsw_intr_enable(cpsw);
1892 }
1893 #endif
1894
1895 static inline int cpsw_add_vlan_ale_entry(struct cpsw_priv *priv,
1896                                 unsigned short vid)
1897 {
1898         int ret;
1899         int unreg_mcast_mask = 0;
1900         u32 port_mask;
1901         struct cpsw_common *cpsw = priv->cpsw;
1902
1903         if (cpsw->data.dual_emac) {
1904                 port_mask = (1 << (priv->emac_port + 1)) | ALE_PORT_HOST;
1905
1906                 if (priv->ndev->flags & IFF_ALLMULTI)
1907                         unreg_mcast_mask = port_mask;
1908         } else {
1909                 port_mask = ALE_ALL_PORTS;
1910
1911                 if (priv->ndev->flags & IFF_ALLMULTI)
1912                         unreg_mcast_mask = ALE_ALL_PORTS;
1913                 else
1914                         unreg_mcast_mask = ALE_PORT_1 | ALE_PORT_2;
1915         }
1916
1917         ret = cpsw_ale_add_vlan(cpsw->ale, vid, port_mask, 0, port_mask,
1918                                 unreg_mcast_mask);
1919         if (ret != 0)
1920                 return ret;
1921
1922         ret = cpsw_ale_add_ucast(cpsw->ale, priv->mac_addr,
1923                                  HOST_PORT_NUM, ALE_VLAN, vid);
1924         if (ret != 0)
1925                 goto clean_vid;
1926
1927         ret = cpsw_ale_add_mcast(cpsw->ale, priv->ndev->broadcast,
1928                                  port_mask, ALE_VLAN, vid, 0);
1929         if (ret != 0)
1930                 goto clean_vlan_ucast;
1931         return 0;
1932
1933 clean_vlan_ucast:
1934         cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
1935                            HOST_PORT_NUM, ALE_VLAN, vid);
1936 clean_vid:
1937         cpsw_ale_del_vlan(cpsw->ale, vid, 0);
1938         return ret;
1939 }
1940
1941 static int cpsw_ndo_vlan_rx_add_vid(struct net_device *ndev,
1942                                     __be16 proto, u16 vid)
1943 {
1944         struct cpsw_priv *priv = netdev_priv(ndev);
1945         struct cpsw_common *cpsw = priv->cpsw;
1946         int ret;
1947
1948         if (vid == cpsw->data.default_vlan)
1949                 return 0;
1950
1951         ret = pm_runtime_get_sync(cpsw->dev);
1952         if (ret < 0) {
1953                 pm_runtime_put_noidle(cpsw->dev);
1954                 return ret;
1955         }
1956
1957         if (cpsw->data.dual_emac) {
1958                 /* In dual EMAC, reserved VLAN id should not be used for
1959                  * creating VLAN interfaces as this can break the dual
1960                  * EMAC port separation
1961                  */
1962                 int i;
1963
1964                 for (i = 0; i < cpsw->data.slaves; i++) {
1965                         if (vid == cpsw->slaves[i].port_vlan)
1966                                 return -EINVAL;
1967                 }
1968         }
1969
1970         dev_info(priv->dev, "Adding vlanid %d to vlan filter\n", vid);
1971         ret = cpsw_add_vlan_ale_entry(priv, vid);
1972
1973         pm_runtime_put(cpsw->dev);
1974         return ret;
1975 }
1976
1977 static int cpsw_ndo_vlan_rx_kill_vid(struct net_device *ndev,
1978                                      __be16 proto, u16 vid)
1979 {
1980         struct cpsw_priv *priv = netdev_priv(ndev);
1981         struct cpsw_common *cpsw = priv->cpsw;
1982         int ret;
1983
1984         if (vid == cpsw->data.default_vlan)
1985                 return 0;
1986
1987         ret = pm_runtime_get_sync(cpsw->dev);
1988         if (ret < 0) {
1989                 pm_runtime_put_noidle(cpsw->dev);
1990                 return ret;
1991         }
1992
1993         if (cpsw->data.dual_emac) {
1994                 int i;
1995
1996                 for (i = 0; i < cpsw->data.slaves; i++) {
1997                         if (vid == cpsw->slaves[i].port_vlan)
1998                                 return -EINVAL;
1999                 }
2000         }
2001
2002         dev_info(priv->dev, "removing vlanid %d from vlan filter\n", vid);
2003         ret = cpsw_ale_del_vlan(cpsw->ale, vid, 0);
2004         if (ret != 0)
2005                 return ret;
2006
2007         ret = cpsw_ale_del_ucast(cpsw->ale, priv->mac_addr,
2008                                  HOST_PORT_NUM, ALE_VLAN, vid);
2009         if (ret != 0)
2010                 return ret;
2011
2012         ret = cpsw_ale_del_mcast(cpsw->ale, priv->ndev->broadcast,
2013                                  0, ALE_VLAN, vid);
2014         pm_runtime_put(cpsw->dev);
2015         return ret;
2016 }
2017
2018 static int cpsw_ndo_set_tx_maxrate(struct net_device *ndev, int queue, u32 rate)
2019 {
2020         struct cpsw_priv *priv = netdev_priv(ndev);
2021         struct cpsw_common *cpsw = priv->cpsw;
2022         struct cpsw_slave *slave;
2023         u32 min_rate;
2024         u32 ch_rate;
2025         int i, ret;
2026
2027         ch_rate = netdev_get_tx_queue(ndev, queue)->tx_maxrate;
2028         if (ch_rate == rate)
2029                 return 0;
2030
2031         ch_rate = rate * 1000;
2032         min_rate = cpdma_chan_get_min_rate(cpsw->dma);
2033         if ((ch_rate < min_rate && ch_rate)) {
2034                 dev_err(priv->dev, "The channel rate cannot be less than %dMbps",
2035                         min_rate);
2036                 return -EINVAL;
2037         }
2038
2039         if (rate > cpsw->speed) {
2040                 dev_err(priv->dev, "The channel rate cannot be more than 2Gbps");
2041                 return -EINVAL;
2042         }
2043
2044         ret = pm_runtime_get_sync(cpsw->dev);
2045         if (ret < 0) {
2046                 pm_runtime_put_noidle(cpsw->dev);
2047                 return ret;
2048         }
2049
2050         ret = cpdma_chan_set_rate(cpsw->txv[queue].ch, ch_rate);
2051         pm_runtime_put(cpsw->dev);
2052
2053         if (ret)
2054                 return ret;
2055
2056         /* update rates for slaves tx queues */
2057         for (i = 0; i < cpsw->data.slaves; i++) {
2058                 slave = &cpsw->slaves[i];
2059                 if (!slave->ndev)
2060                         continue;
2061
2062                 netdev_get_tx_queue(slave->ndev, queue)->tx_maxrate = rate;
2063         }
2064
2065         cpsw_split_res(ndev);
2066         return ret;
2067 }
2068
2069 static const struct net_device_ops cpsw_netdev_ops = {
2070         .ndo_open               = cpsw_ndo_open,
2071         .ndo_stop               = cpsw_ndo_stop,
2072         .ndo_start_xmit         = cpsw_ndo_start_xmit,
2073         .ndo_set_mac_address    = cpsw_ndo_set_mac_address,
2074         .ndo_do_ioctl           = cpsw_ndo_ioctl,
2075         .ndo_validate_addr      = eth_validate_addr,
2076         .ndo_tx_timeout         = cpsw_ndo_tx_timeout,
2077         .ndo_set_rx_mode        = cpsw_ndo_set_rx_mode,
2078         .ndo_set_tx_maxrate     = cpsw_ndo_set_tx_maxrate,
2079 #ifdef CONFIG_NET_POLL_CONTROLLER
2080         .ndo_poll_controller    = cpsw_ndo_poll_controller,
2081 #endif
2082         .ndo_vlan_rx_add_vid    = cpsw_ndo_vlan_rx_add_vid,
2083         .ndo_vlan_rx_kill_vid   = cpsw_ndo_vlan_rx_kill_vid,
2084 };
2085
2086 static int cpsw_get_regs_len(struct net_device *ndev)
2087 {
2088         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2089
2090         return cpsw->data.ale_entries * ALE_ENTRY_WORDS * sizeof(u32);
2091 }
2092
2093 static void cpsw_get_regs(struct net_device *ndev,
2094                           struct ethtool_regs *regs, void *p)
2095 {
2096         u32 *reg = p;
2097         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2098
2099         /* update CPSW IP version */
2100         regs->version = cpsw->version;
2101
2102         cpsw_ale_dump(cpsw->ale, reg);
2103 }
2104
2105 static void cpsw_get_drvinfo(struct net_device *ndev,
2106                              struct ethtool_drvinfo *info)
2107 {
2108         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2109         struct platform_device  *pdev = to_platform_device(cpsw->dev);
2110
2111         strlcpy(info->driver, "cpsw", sizeof(info->driver));
2112         strlcpy(info->version, "1.0", sizeof(info->version));
2113         strlcpy(info->bus_info, pdev->name, sizeof(info->bus_info));
2114 }
2115
2116 static u32 cpsw_get_msglevel(struct net_device *ndev)
2117 {
2118         struct cpsw_priv *priv = netdev_priv(ndev);
2119         return priv->msg_enable;
2120 }
2121
2122 static void cpsw_set_msglevel(struct net_device *ndev, u32 value)
2123 {
2124         struct cpsw_priv *priv = netdev_priv(ndev);
2125         priv->msg_enable = value;
2126 }
2127
2128 #if IS_ENABLED(CONFIG_TI_CPTS)
2129 static int cpsw_get_ts_info(struct net_device *ndev,
2130                             struct ethtool_ts_info *info)
2131 {
2132         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2133
2134         info->so_timestamping =
2135                 SOF_TIMESTAMPING_TX_HARDWARE |
2136                 SOF_TIMESTAMPING_TX_SOFTWARE |
2137                 SOF_TIMESTAMPING_RX_HARDWARE |
2138                 SOF_TIMESTAMPING_RX_SOFTWARE |
2139                 SOF_TIMESTAMPING_SOFTWARE |
2140                 SOF_TIMESTAMPING_RAW_HARDWARE;
2141         info->phc_index = cpsw->cpts->phc_index;
2142         info->tx_types =
2143                 (1 << HWTSTAMP_TX_OFF) |
2144                 (1 << HWTSTAMP_TX_ON);
2145         info->rx_filters =
2146                 (1 << HWTSTAMP_FILTER_NONE) |
2147                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2148                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2149         return 0;
2150 }
2151 #else
2152 static int cpsw_get_ts_info(struct net_device *ndev,
2153                             struct ethtool_ts_info *info)
2154 {
2155         info->so_timestamping =
2156                 SOF_TIMESTAMPING_TX_SOFTWARE |
2157                 SOF_TIMESTAMPING_RX_SOFTWARE |
2158                 SOF_TIMESTAMPING_SOFTWARE;
2159         info->phc_index = -1;
2160         info->tx_types = 0;
2161         info->rx_filters = 0;
2162         return 0;
2163 }
2164 #endif
2165
2166 static int cpsw_get_link_ksettings(struct net_device *ndev,
2167                                    struct ethtool_link_ksettings *ecmd)
2168 {
2169         struct cpsw_priv *priv = netdev_priv(ndev);
2170         struct cpsw_common *cpsw = priv->cpsw;
2171         int slave_no = cpsw_slave_index(cpsw, priv);
2172
2173         if (!cpsw->slaves[slave_no].phy)
2174                 return -EOPNOTSUPP;
2175
2176         phy_ethtool_ksettings_get(cpsw->slaves[slave_no].phy, ecmd);
2177         return 0;
2178 }
2179
2180 static int cpsw_set_link_ksettings(struct net_device *ndev,
2181                                    const struct ethtool_link_ksettings *ecmd)
2182 {
2183         struct cpsw_priv *priv = netdev_priv(ndev);
2184         struct cpsw_common *cpsw = priv->cpsw;
2185         int slave_no = cpsw_slave_index(cpsw, priv);
2186
2187         if (cpsw->slaves[slave_no].phy)
2188                 return phy_ethtool_ksettings_set(cpsw->slaves[slave_no].phy,
2189                                                  ecmd);
2190         else
2191                 return -EOPNOTSUPP;
2192 }
2193
2194 static void cpsw_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2195 {
2196         struct cpsw_priv *priv = netdev_priv(ndev);
2197         struct cpsw_common *cpsw = priv->cpsw;
2198         int slave_no = cpsw_slave_index(cpsw, priv);
2199
2200         wol->supported = 0;
2201         wol->wolopts = 0;
2202
2203         if (cpsw->slaves[slave_no].phy)
2204                 phy_ethtool_get_wol(cpsw->slaves[slave_no].phy, wol);
2205 }
2206
2207 static int cpsw_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2208 {
2209         struct cpsw_priv *priv = netdev_priv(ndev);
2210         struct cpsw_common *cpsw = priv->cpsw;
2211         int slave_no = cpsw_slave_index(cpsw, priv);
2212
2213         if (cpsw->slaves[slave_no].phy)
2214                 return phy_ethtool_set_wol(cpsw->slaves[slave_no].phy, wol);
2215         else
2216                 return -EOPNOTSUPP;
2217 }
2218
2219 static void cpsw_get_pauseparam(struct net_device *ndev,
2220                                 struct ethtool_pauseparam *pause)
2221 {
2222         struct cpsw_priv *priv = netdev_priv(ndev);
2223
2224         pause->autoneg = AUTONEG_DISABLE;
2225         pause->rx_pause = priv->rx_pause ? true : false;
2226         pause->tx_pause = priv->tx_pause ? true : false;
2227 }
2228
2229 static int cpsw_set_pauseparam(struct net_device *ndev,
2230                                struct ethtool_pauseparam *pause)
2231 {
2232         struct cpsw_priv *priv = netdev_priv(ndev);
2233         bool link;
2234
2235         priv->rx_pause = pause->rx_pause ? true : false;
2236         priv->tx_pause = pause->tx_pause ? true : false;
2237
2238         for_each_slave(priv, _cpsw_adjust_link, priv, &link);
2239         return 0;
2240 }
2241
2242 static int cpsw_ethtool_op_begin(struct net_device *ndev)
2243 {
2244         struct cpsw_priv *priv = netdev_priv(ndev);
2245         struct cpsw_common *cpsw = priv->cpsw;
2246         int ret;
2247
2248         ret = pm_runtime_get_sync(cpsw->dev);
2249         if (ret < 0) {
2250                 cpsw_err(priv, drv, "ethtool begin failed %d\n", ret);
2251                 pm_runtime_put_noidle(cpsw->dev);
2252         }
2253
2254         return ret;
2255 }
2256
2257 static void cpsw_ethtool_op_complete(struct net_device *ndev)
2258 {
2259         struct cpsw_priv *priv = netdev_priv(ndev);
2260         int ret;
2261
2262         ret = pm_runtime_put(priv->cpsw->dev);
2263         if (ret < 0)
2264                 cpsw_err(priv, drv, "ethtool complete failed %d\n", ret);
2265 }
2266
2267 static void cpsw_get_channels(struct net_device *ndev,
2268                               struct ethtool_channels *ch)
2269 {
2270         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2271
2272         ch->max_combined = 0;
2273         ch->max_rx = CPSW_MAX_QUEUES;
2274         ch->max_tx = CPSW_MAX_QUEUES;
2275         ch->max_other = 0;
2276         ch->other_count = 0;
2277         ch->rx_count = cpsw->rx_ch_num;
2278         ch->tx_count = cpsw->tx_ch_num;
2279         ch->combined_count = 0;
2280 }
2281
2282 static int cpsw_check_ch_settings(struct cpsw_common *cpsw,
2283                                   struct ethtool_channels *ch)
2284 {
2285         if (ch->combined_count)
2286                 return -EINVAL;
2287
2288         /* verify we have at least one channel in each direction */
2289         if (!ch->rx_count || !ch->tx_count)
2290                 return -EINVAL;
2291
2292         if (ch->rx_count > cpsw->data.channels ||
2293             ch->tx_count > cpsw->data.channels)
2294                 return -EINVAL;
2295
2296         return 0;
2297 }
2298
2299 static int cpsw_update_channels_res(struct cpsw_priv *priv, int ch_num, int rx)
2300 {
2301         int (*poll)(struct napi_struct *, int);
2302         struct cpsw_common *cpsw = priv->cpsw;
2303         void (*handler)(void *, int, int);
2304         struct netdev_queue *queue;
2305         struct cpsw_vector *vec;
2306         int ret, *ch;
2307
2308         if (rx) {
2309                 ch = &cpsw->rx_ch_num;
2310                 vec = cpsw->rxv;
2311                 handler = cpsw_rx_handler;
2312                 poll = cpsw_rx_poll;
2313         } else {
2314                 ch = &cpsw->tx_ch_num;
2315                 vec = cpsw->txv;
2316                 handler = cpsw_tx_handler;
2317                 poll = cpsw_tx_poll;
2318         }
2319
2320         while (*ch < ch_num) {
2321                 vec[*ch].ch = cpdma_chan_create(cpsw->dma, *ch, handler, rx);
2322                 queue = netdev_get_tx_queue(priv->ndev, *ch);
2323                 queue->tx_maxrate = 0;
2324
2325                 if (IS_ERR(vec[*ch].ch))
2326                         return PTR_ERR(vec[*ch].ch);
2327
2328                 if (!vec[*ch].ch)
2329                         return -EINVAL;
2330
2331                 cpsw_info(priv, ifup, "created new %d %s channel\n", *ch,
2332                           (rx ? "rx" : "tx"));
2333                 (*ch)++;
2334         }
2335
2336         while (*ch > ch_num) {
2337                 (*ch)--;
2338
2339                 ret = cpdma_chan_destroy(vec[*ch].ch);
2340                 if (ret)
2341                         return ret;
2342
2343                 cpsw_info(priv, ifup, "destroyed %d %s channel\n", *ch,
2344                           (rx ? "rx" : "tx"));
2345         }
2346
2347         return 0;
2348 }
2349
2350 static int cpsw_update_channels(struct cpsw_priv *priv,
2351                                 struct ethtool_channels *ch)
2352 {
2353         int ret;
2354
2355         ret = cpsw_update_channels_res(priv, ch->rx_count, 1);
2356         if (ret)
2357                 return ret;
2358
2359         ret = cpsw_update_channels_res(priv, ch->tx_count, 0);
2360         if (ret)
2361                 return ret;
2362
2363         return 0;
2364 }
2365
2366 static void cpsw_suspend_data_pass(struct net_device *ndev)
2367 {
2368         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2369         struct cpsw_slave *slave;
2370         int i;
2371
2372         /* Disable NAPI scheduling */
2373         cpsw_intr_disable(cpsw);
2374
2375         /* Stop all transmit queues for every network device.
2376          * Disable re-using rx descriptors with dormant_on.
2377          */
2378         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2379                 if (!(slave->ndev && netif_running(slave->ndev)))
2380                         continue;
2381
2382                 netif_tx_stop_all_queues(slave->ndev);
2383                 netif_dormant_on(slave->ndev);
2384         }
2385
2386         /* Handle rest of tx packets and stop cpdma channels */
2387         cpdma_ctlr_stop(cpsw->dma);
2388 }
2389
2390 static int cpsw_resume_data_pass(struct net_device *ndev)
2391 {
2392         struct cpsw_priv *priv = netdev_priv(ndev);
2393         struct cpsw_common *cpsw = priv->cpsw;
2394         struct cpsw_slave *slave;
2395         int i, ret;
2396
2397         /* Allow rx packets handling */
2398         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2399                 if (slave->ndev && netif_running(slave->ndev))
2400                         netif_dormant_off(slave->ndev);
2401
2402         /* After this receive is started */
2403         if (cpsw->usage_count) {
2404                 ret = cpsw_fill_rx_channels(priv);
2405                 if (ret)
2406                         return ret;
2407
2408                 cpdma_ctlr_start(cpsw->dma);
2409                 cpsw_intr_enable(cpsw);
2410         }
2411
2412         /* Resume transmit for every affected interface */
2413         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++)
2414                 if (slave->ndev && netif_running(slave->ndev))
2415                         netif_tx_start_all_queues(slave->ndev);
2416
2417         return 0;
2418 }
2419
2420 static int cpsw_set_channels(struct net_device *ndev,
2421                              struct ethtool_channels *chs)
2422 {
2423         struct cpsw_priv *priv = netdev_priv(ndev);
2424         struct cpsw_common *cpsw = priv->cpsw;
2425         struct cpsw_slave *slave;
2426         int i, ret;
2427
2428         ret = cpsw_check_ch_settings(cpsw, chs);
2429         if (ret < 0)
2430                 return ret;
2431
2432         cpsw_suspend_data_pass(ndev);
2433         ret = cpsw_update_channels(priv, chs);
2434         if (ret)
2435                 goto err;
2436
2437         for (i = cpsw->data.slaves, slave = cpsw->slaves; i; i--, slave++) {
2438                 if (!(slave->ndev && netif_running(slave->ndev)))
2439                         continue;
2440
2441                 /* Inform stack about new count of queues */
2442                 ret = netif_set_real_num_tx_queues(slave->ndev,
2443                                                    cpsw->tx_ch_num);
2444                 if (ret) {
2445                         dev_err(priv->dev, "cannot set real number of tx queues\n");
2446                         goto err;
2447                 }
2448
2449                 ret = netif_set_real_num_rx_queues(slave->ndev,
2450                                                    cpsw->rx_ch_num);
2451                 if (ret) {
2452                         dev_err(priv->dev, "cannot set real number of rx queues\n");
2453                         goto err;
2454                 }
2455         }
2456
2457         if (cpsw->usage_count)
2458                 cpsw_split_res(ndev);
2459
2460         ret = cpsw_resume_data_pass(ndev);
2461         if (!ret)
2462                 return 0;
2463 err:
2464         dev_err(priv->dev, "cannot update channels number, closing device\n");
2465         dev_close(ndev);
2466         return ret;
2467 }
2468
2469 static int cpsw_get_eee(struct net_device *ndev, struct ethtool_eee *edata)
2470 {
2471         struct cpsw_priv *priv = netdev_priv(ndev);
2472         struct cpsw_common *cpsw = priv->cpsw;
2473         int slave_no = cpsw_slave_index(cpsw, priv);
2474
2475         if (cpsw->slaves[slave_no].phy)
2476                 return phy_ethtool_get_eee(cpsw->slaves[slave_no].phy, edata);
2477         else
2478                 return -EOPNOTSUPP;
2479 }
2480
2481 static int cpsw_set_eee(struct net_device *ndev, struct ethtool_eee *edata)
2482 {
2483         struct cpsw_priv *priv = netdev_priv(ndev);
2484         struct cpsw_common *cpsw = priv->cpsw;
2485         int slave_no = cpsw_slave_index(cpsw, priv);
2486
2487         if (cpsw->slaves[slave_no].phy)
2488                 return phy_ethtool_set_eee(cpsw->slaves[slave_no].phy, edata);
2489         else
2490                 return -EOPNOTSUPP;
2491 }
2492
2493 static int cpsw_nway_reset(struct net_device *ndev)
2494 {
2495         struct cpsw_priv *priv = netdev_priv(ndev);
2496         struct cpsw_common *cpsw = priv->cpsw;
2497         int slave_no = cpsw_slave_index(cpsw, priv);
2498
2499         if (cpsw->slaves[slave_no].phy)
2500                 return genphy_restart_aneg(cpsw->slaves[slave_no].phy);
2501         else
2502                 return -EOPNOTSUPP;
2503 }
2504
2505 static void cpsw_get_ringparam(struct net_device *ndev,
2506                                struct ethtool_ringparam *ering)
2507 {
2508         struct cpsw_priv *priv = netdev_priv(ndev);
2509         struct cpsw_common *cpsw = priv->cpsw;
2510
2511         /* not supported */
2512         ering->tx_max_pending = 0;
2513         ering->tx_pending = cpdma_get_num_tx_descs(cpsw->dma);
2514         ering->rx_max_pending = descs_pool_size - CPSW_MAX_QUEUES;
2515         ering->rx_pending = cpdma_get_num_rx_descs(cpsw->dma);
2516 }
2517
2518 static int cpsw_set_ringparam(struct net_device *ndev,
2519                               struct ethtool_ringparam *ering)
2520 {
2521         struct cpsw_priv *priv = netdev_priv(ndev);
2522         struct cpsw_common *cpsw = priv->cpsw;
2523         int ret;
2524
2525         /* ignore ering->tx_pending - only rx_pending adjustment is supported */
2526
2527         if (ering->rx_mini_pending || ering->rx_jumbo_pending ||
2528             ering->rx_pending < CPSW_MAX_QUEUES ||
2529             ering->rx_pending > (descs_pool_size - CPSW_MAX_QUEUES))
2530                 return -EINVAL;
2531
2532         if (ering->rx_pending == cpdma_get_num_rx_descs(cpsw->dma))
2533                 return 0;
2534
2535         cpsw_suspend_data_pass(ndev);
2536
2537         cpdma_set_num_rx_descs(cpsw->dma, ering->rx_pending);
2538
2539         if (cpsw->usage_count)
2540                 cpdma_chan_split_pool(cpsw->dma);
2541
2542         ret = cpsw_resume_data_pass(ndev);
2543         if (!ret)
2544                 return 0;
2545
2546         dev_err(&ndev->dev, "cannot set ring params, closing device\n");
2547         dev_close(ndev);
2548         return ret;
2549 }
2550
2551 static const struct ethtool_ops cpsw_ethtool_ops = {
2552         .get_drvinfo    = cpsw_get_drvinfo,
2553         .get_msglevel   = cpsw_get_msglevel,
2554         .set_msglevel   = cpsw_set_msglevel,
2555         .get_link       = ethtool_op_get_link,
2556         .get_ts_info    = cpsw_get_ts_info,
2557         .get_coalesce   = cpsw_get_coalesce,
2558         .set_coalesce   = cpsw_set_coalesce,
2559         .get_sset_count         = cpsw_get_sset_count,
2560         .get_strings            = cpsw_get_strings,
2561         .get_ethtool_stats      = cpsw_get_ethtool_stats,
2562         .get_pauseparam         = cpsw_get_pauseparam,
2563         .set_pauseparam         = cpsw_set_pauseparam,
2564         .get_wol        = cpsw_get_wol,
2565         .set_wol        = cpsw_set_wol,
2566         .get_regs_len   = cpsw_get_regs_len,
2567         .get_regs       = cpsw_get_regs,
2568         .begin          = cpsw_ethtool_op_begin,
2569         .complete       = cpsw_ethtool_op_complete,
2570         .get_channels   = cpsw_get_channels,
2571         .set_channels   = cpsw_set_channels,
2572         .get_link_ksettings     = cpsw_get_link_ksettings,
2573         .set_link_ksettings     = cpsw_set_link_ksettings,
2574         .get_eee        = cpsw_get_eee,
2575         .set_eee        = cpsw_set_eee,
2576         .nway_reset     = cpsw_nway_reset,
2577         .get_ringparam = cpsw_get_ringparam,
2578         .set_ringparam = cpsw_set_ringparam,
2579 };
2580
2581 static void cpsw_slave_init(struct cpsw_slave *slave, struct cpsw_common *cpsw,
2582                             u32 slave_reg_ofs, u32 sliver_reg_ofs)
2583 {
2584         void __iomem            *regs = cpsw->regs;
2585         int                     slave_num = slave->slave_num;
2586         struct cpsw_slave_data  *data = cpsw->data.slave_data + slave_num;
2587
2588         slave->data     = data;
2589         slave->regs     = regs + slave_reg_ofs;
2590         slave->sliver   = regs + sliver_reg_ofs;
2591         slave->port_vlan = data->dual_emac_res_vlan;
2592 }
2593
2594 static int cpsw_probe_dt(struct cpsw_platform_data *data,
2595                          struct platform_device *pdev)
2596 {
2597         struct device_node *node = pdev->dev.of_node;
2598         struct device_node *slave_node;
2599         int i = 0, ret;
2600         u32 prop;
2601
2602         if (!node)
2603                 return -EINVAL;
2604
2605         if (of_property_read_u32(node, "slaves", &prop)) {
2606                 dev_err(&pdev->dev, "Missing slaves property in the DT.\n");
2607                 return -EINVAL;
2608         }
2609         data->slaves = prop;
2610
2611         if (of_property_read_u32(node, "active_slave", &prop)) {
2612                 dev_err(&pdev->dev, "Missing active_slave property in the DT.\n");
2613                 return -EINVAL;
2614         }
2615         data->active_slave = prop;
2616
2617         data->slave_data = devm_kzalloc(&pdev->dev, data->slaves
2618                                         * sizeof(struct cpsw_slave_data),
2619                                         GFP_KERNEL);
2620         if (!data->slave_data)
2621                 return -ENOMEM;
2622
2623         if (of_property_read_u32(node, "cpdma_channels", &prop)) {
2624                 dev_err(&pdev->dev, "Missing cpdma_channels property in the DT.\n");
2625                 return -EINVAL;
2626         }
2627         data->channels = prop;
2628
2629         if (of_property_read_u32(node, "ale_entries", &prop)) {
2630                 dev_err(&pdev->dev, "Missing ale_entries property in the DT.\n");
2631                 return -EINVAL;
2632         }
2633         data->ale_entries = prop;
2634
2635         if (of_property_read_u32(node, "bd_ram_size", &prop)) {
2636                 dev_err(&pdev->dev, "Missing bd_ram_size property in the DT.\n");
2637                 return -EINVAL;
2638         }
2639         data->bd_ram_size = prop;
2640
2641         if (of_property_read_u32(node, "mac_control", &prop)) {
2642                 dev_err(&pdev->dev, "Missing mac_control property in the DT.\n");
2643                 return -EINVAL;
2644         }
2645         data->mac_control = prop;
2646
2647         if (of_property_read_bool(node, "dual_emac"))
2648                 data->dual_emac = 1;
2649
2650         /*
2651          * Populate all the child nodes here...
2652          */
2653         ret = of_platform_populate(node, NULL, NULL, &pdev->dev);
2654         /* We do not want to force this, as in some cases may not have child */
2655         if (ret)
2656                 dev_warn(&pdev->dev, "Doesn't have any child node\n");
2657
2658         for_each_available_child_of_node(node, slave_node) {
2659                 struct cpsw_slave_data *slave_data = data->slave_data + i;
2660                 const void *mac_addr = NULL;
2661                 int lenp;
2662                 const __be32 *parp;
2663
2664                 /* This is no slave child node, continue */
2665                 if (strcmp(slave_node->name, "slave"))
2666                         continue;
2667
2668                 slave_data->phy_node = of_parse_phandle(slave_node,
2669                                                         "phy-handle", 0);
2670                 parp = of_get_property(slave_node, "phy_id", &lenp);
2671                 if (slave_data->phy_node) {
2672                         dev_dbg(&pdev->dev,
2673                                 "slave[%d] using phy-handle=\"%s\"\n",
2674                                 i, slave_data->phy_node->full_name);
2675                 } else if (of_phy_is_fixed_link(slave_node)) {
2676                         /* In the case of a fixed PHY, the DT node associated
2677                          * to the PHY is the Ethernet MAC DT node.
2678                          */
2679                         ret = of_phy_register_fixed_link(slave_node);
2680                         if (ret) {
2681                                 if (ret != -EPROBE_DEFER)
2682                                         dev_err(&pdev->dev, "failed to register fixed-link phy: %d\n", ret);
2683                                 return ret;
2684                         }
2685                         slave_data->phy_node = of_node_get(slave_node);
2686                 } else if (parp) {
2687                         u32 phyid;
2688                         struct device_node *mdio_node;
2689                         struct platform_device *mdio;
2690
2691                         if (lenp != (sizeof(__be32) * 2)) {
2692                                 dev_err(&pdev->dev, "Invalid slave[%d] phy_id property\n", i);
2693                                 goto no_phy_slave;
2694                         }
2695                         mdio_node = of_find_node_by_phandle(be32_to_cpup(parp));
2696                         phyid = be32_to_cpup(parp+1);
2697                         mdio = of_find_device_by_node(mdio_node);
2698                         of_node_put(mdio_node);
2699                         if (!mdio) {
2700                                 dev_err(&pdev->dev, "Missing mdio platform device\n");
2701                                 return -EINVAL;
2702                         }
2703                         snprintf(slave_data->phy_id, sizeof(slave_data->phy_id),
2704                                  PHY_ID_FMT, mdio->name, phyid);
2705                         put_device(&mdio->dev);
2706                 } else {
2707                         dev_err(&pdev->dev,
2708                                 "No slave[%d] phy_id, phy-handle, or fixed-link property\n",
2709                                 i);
2710                         goto no_phy_slave;
2711                 }
2712                 slave_data->phy_if = of_get_phy_mode(slave_node);
2713                 if (slave_data->phy_if < 0) {
2714                         dev_err(&pdev->dev, "Missing or malformed slave[%d] phy-mode property\n",
2715                                 i);
2716                         return slave_data->phy_if;
2717                 }
2718
2719 no_phy_slave:
2720                 mac_addr = of_get_mac_address(slave_node);
2721                 if (mac_addr) {
2722                         memcpy(slave_data->mac_addr, mac_addr, ETH_ALEN);
2723                 } else {
2724                         ret = ti_cm_get_macid(&pdev->dev, i,
2725                                               slave_data->mac_addr);
2726                         if (ret)
2727                                 return ret;
2728                 }
2729                 if (data->dual_emac) {
2730                         if (of_property_read_u32(slave_node, "dual_emac_res_vlan",
2731                                                  &prop)) {
2732                                 dev_err(&pdev->dev, "Missing dual_emac_res_vlan in DT.\n");
2733                                 slave_data->dual_emac_res_vlan = i+1;
2734                                 dev_err(&pdev->dev, "Using %d as Reserved VLAN for %d slave\n",
2735                                         slave_data->dual_emac_res_vlan, i);
2736                         } else {
2737                                 slave_data->dual_emac_res_vlan = prop;
2738                         }
2739                 }
2740
2741                 i++;
2742                 if (i == data->slaves)
2743                         break;
2744         }
2745
2746         return 0;
2747 }
2748
2749 static void cpsw_remove_dt(struct platform_device *pdev)
2750 {
2751         struct net_device *ndev = platform_get_drvdata(pdev);
2752         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
2753         struct cpsw_platform_data *data = &cpsw->data;
2754         struct device_node *node = pdev->dev.of_node;
2755         struct device_node *slave_node;
2756         int i = 0;
2757
2758         for_each_available_child_of_node(node, slave_node) {
2759                 struct cpsw_slave_data *slave_data = &data->slave_data[i];
2760
2761                 if (strcmp(slave_node->name, "slave"))
2762                         continue;
2763
2764                 if (of_phy_is_fixed_link(slave_node))
2765                         of_phy_deregister_fixed_link(slave_node);
2766
2767                 of_node_put(slave_data->phy_node);
2768
2769                 i++;
2770                 if (i == data->slaves)
2771                         break;
2772         }
2773
2774         of_platform_depopulate(&pdev->dev);
2775 }
2776
2777 static int cpsw_probe_dual_emac(struct cpsw_priv *priv)
2778 {
2779         struct cpsw_common              *cpsw = priv->cpsw;
2780         struct cpsw_platform_data       *data = &cpsw->data;
2781         struct net_device               *ndev;
2782         struct cpsw_priv                *priv_sl2;
2783         int ret = 0;
2784
2785         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2786         if (!ndev) {
2787                 dev_err(cpsw->dev, "cpsw: error allocating net_device\n");
2788                 return -ENOMEM;
2789         }
2790
2791         priv_sl2 = netdev_priv(ndev);
2792         priv_sl2->cpsw = cpsw;
2793         priv_sl2->ndev = ndev;
2794         priv_sl2->dev  = &ndev->dev;
2795         priv_sl2->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2796
2797         if (is_valid_ether_addr(data->slave_data[1].mac_addr)) {
2798                 memcpy(priv_sl2->mac_addr, data->slave_data[1].mac_addr,
2799                         ETH_ALEN);
2800                 dev_info(cpsw->dev, "cpsw: Detected MACID = %pM\n",
2801                          priv_sl2->mac_addr);
2802         } else {
2803                 random_ether_addr(priv_sl2->mac_addr);
2804                 dev_info(cpsw->dev, "cpsw: Random MACID = %pM\n",
2805                          priv_sl2->mac_addr);
2806         }
2807         memcpy(ndev->dev_addr, priv_sl2->mac_addr, ETH_ALEN);
2808
2809         priv_sl2->emac_port = 1;
2810         cpsw->slaves[1].ndev = ndev;
2811         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
2812
2813         ndev->netdev_ops = &cpsw_netdev_ops;
2814         ndev->ethtool_ops = &cpsw_ethtool_ops;
2815
2816         /* register the network device */
2817         SET_NETDEV_DEV(ndev, cpsw->dev);
2818         ret = register_netdev(ndev);
2819         if (ret) {
2820                 dev_err(cpsw->dev, "cpsw: error registering net device\n");
2821                 free_netdev(ndev);
2822                 ret = -ENODEV;
2823         }
2824
2825         return ret;
2826 }
2827
2828 #define CPSW_QUIRK_IRQ          BIT(0)
2829
2830 static struct platform_device_id cpsw_devtype[] = {
2831         {
2832                 /* keep it for existing comaptibles */
2833                 .name = "cpsw",
2834                 .driver_data = CPSW_QUIRK_IRQ,
2835         }, {
2836                 .name = "am335x-cpsw",
2837                 .driver_data = CPSW_QUIRK_IRQ,
2838         }, {
2839                 .name = "am4372-cpsw",
2840                 .driver_data = 0,
2841         }, {
2842                 .name = "dra7-cpsw",
2843                 .driver_data = 0,
2844         }, {
2845                 /* sentinel */
2846         }
2847 };
2848 MODULE_DEVICE_TABLE(platform, cpsw_devtype);
2849
2850 enum ti_cpsw_type {
2851         CPSW = 0,
2852         AM335X_CPSW,
2853         AM4372_CPSW,
2854         DRA7_CPSW,
2855 };
2856
2857 static const struct of_device_id cpsw_of_mtable[] = {
2858         { .compatible = "ti,cpsw", .data = &cpsw_devtype[CPSW], },
2859         { .compatible = "ti,am335x-cpsw", .data = &cpsw_devtype[AM335X_CPSW], },
2860         { .compatible = "ti,am4372-cpsw", .data = &cpsw_devtype[AM4372_CPSW], },
2861         { .compatible = "ti,dra7-cpsw", .data = &cpsw_devtype[DRA7_CPSW], },
2862         { /* sentinel */ },
2863 };
2864 MODULE_DEVICE_TABLE(of, cpsw_of_mtable);
2865
2866 static int cpsw_probe(struct platform_device *pdev)
2867 {
2868         struct clk                      *clk;
2869         struct cpsw_platform_data       *data;
2870         struct net_device               *ndev;
2871         struct cpsw_priv                *priv;
2872         struct cpdma_params             dma_params;
2873         struct cpsw_ale_params          ale_params;
2874         void __iomem                    *ss_regs;
2875         void __iomem                    *cpts_regs;
2876         struct resource                 *res, *ss_res;
2877         const struct of_device_id       *of_id;
2878         struct gpio_descs               *mode;
2879         u32 slave_offset, sliver_offset, slave_size;
2880         struct cpsw_common              *cpsw;
2881         int ret = 0, i;
2882         int irq;
2883
2884         cpsw = devm_kzalloc(&pdev->dev, sizeof(struct cpsw_common), GFP_KERNEL);
2885         if (!cpsw)
2886                 return -ENOMEM;
2887
2888         cpsw->dev = &pdev->dev;
2889
2890         ndev = alloc_etherdev_mq(sizeof(struct cpsw_priv), CPSW_MAX_QUEUES);
2891         if (!ndev) {
2892                 dev_err(&pdev->dev, "error allocating net_device\n");
2893                 return -ENOMEM;
2894         }
2895
2896         platform_set_drvdata(pdev, ndev);
2897         priv = netdev_priv(ndev);
2898         priv->cpsw = cpsw;
2899         priv->ndev = ndev;
2900         priv->dev  = &ndev->dev;
2901         priv->msg_enable = netif_msg_init(debug_level, CPSW_DEBUG);
2902         cpsw->rx_packet_max = max(rx_packet_max, 128);
2903
2904         mode = devm_gpiod_get_array_optional(&pdev->dev, "mode", GPIOD_OUT_LOW);
2905         if (IS_ERR(mode)) {
2906                 ret = PTR_ERR(mode);
2907                 dev_err(&pdev->dev, "gpio request failed, ret %d\n", ret);
2908                 goto clean_ndev_ret;
2909         }
2910
2911         /*
2912          * This may be required here for child devices.
2913          */
2914         pm_runtime_enable(&pdev->dev);
2915
2916         /* Select default pin state */
2917         pinctrl_pm_select_default_state(&pdev->dev);
2918
2919         /* Need to enable clocks with runtime PM api to access module
2920          * registers
2921          */
2922         ret = pm_runtime_get_sync(&pdev->dev);
2923         if (ret < 0) {
2924                 pm_runtime_put_noidle(&pdev->dev);
2925                 goto clean_runtime_disable_ret;
2926         }
2927
2928         ret = cpsw_probe_dt(&cpsw->data, pdev);
2929         if (ret)
2930                 goto clean_dt_ret;
2931
2932         data = &cpsw->data;
2933         cpsw->rx_ch_num = 1;
2934         cpsw->tx_ch_num = 1;
2935
2936         if (is_valid_ether_addr(data->slave_data[0].mac_addr)) {
2937                 memcpy(priv->mac_addr, data->slave_data[0].mac_addr, ETH_ALEN);
2938                 dev_info(&pdev->dev, "Detected MACID = %pM\n", priv->mac_addr);
2939         } else {
2940                 eth_random_addr(priv->mac_addr);
2941                 dev_info(&pdev->dev, "Random MACID = %pM\n", priv->mac_addr);
2942         }
2943
2944         memcpy(ndev->dev_addr, priv->mac_addr, ETH_ALEN);
2945
2946         cpsw->slaves = devm_kzalloc(&pdev->dev,
2947                                     sizeof(struct cpsw_slave) * data->slaves,
2948                                     GFP_KERNEL);
2949         if (!cpsw->slaves) {
2950                 ret = -ENOMEM;
2951                 goto clean_dt_ret;
2952         }
2953         for (i = 0; i < data->slaves; i++)
2954                 cpsw->slaves[i].slave_num = i;
2955
2956         cpsw->slaves[0].ndev = ndev;
2957         priv->emac_port = 0;
2958
2959         clk = devm_clk_get(&pdev->dev, "fck");
2960         if (IS_ERR(clk)) {
2961                 dev_err(priv->dev, "fck is not found\n");
2962                 ret = -ENODEV;
2963                 goto clean_dt_ret;
2964         }
2965         cpsw->bus_freq_mhz = clk_get_rate(clk) / 1000000;
2966
2967         ss_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2968         ss_regs = devm_ioremap_resource(&pdev->dev, ss_res);
2969         if (IS_ERR(ss_regs)) {
2970                 ret = PTR_ERR(ss_regs);
2971                 goto clean_dt_ret;
2972         }
2973         cpsw->regs = ss_regs;
2974
2975         cpsw->version = readl(&cpsw->regs->id_ver);
2976
2977         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2978         cpsw->wr_regs = devm_ioremap_resource(&pdev->dev, res);
2979         if (IS_ERR(cpsw->wr_regs)) {
2980                 ret = PTR_ERR(cpsw->wr_regs);
2981                 goto clean_dt_ret;
2982         }
2983
2984         memset(&dma_params, 0, sizeof(dma_params));
2985         memset(&ale_params, 0, sizeof(ale_params));
2986
2987         switch (cpsw->version) {
2988         case CPSW_VERSION_1:
2989                 cpsw->host_port_regs = ss_regs + CPSW1_HOST_PORT_OFFSET;
2990                 cpts_regs               = ss_regs + CPSW1_CPTS_OFFSET;
2991                 cpsw->hw_stats       = ss_regs + CPSW1_HW_STATS;
2992                 dma_params.dmaregs   = ss_regs + CPSW1_CPDMA_OFFSET;
2993                 dma_params.txhdp     = ss_regs + CPSW1_STATERAM_OFFSET;
2994                 ale_params.ale_regs  = ss_regs + CPSW1_ALE_OFFSET;
2995                 slave_offset         = CPSW1_SLAVE_OFFSET;
2996                 slave_size           = CPSW1_SLAVE_SIZE;
2997                 sliver_offset        = CPSW1_SLIVER_OFFSET;
2998                 dma_params.desc_mem_phys = 0;
2999                 break;
3000         case CPSW_VERSION_2:
3001         case CPSW_VERSION_3:
3002         case CPSW_VERSION_4:
3003                 cpsw->host_port_regs = ss_regs + CPSW2_HOST_PORT_OFFSET;
3004                 cpts_regs               = ss_regs + CPSW2_CPTS_OFFSET;
3005                 cpsw->hw_stats       = ss_regs + CPSW2_HW_STATS;
3006                 dma_params.dmaregs   = ss_regs + CPSW2_CPDMA_OFFSET;
3007                 dma_params.txhdp     = ss_regs + CPSW2_STATERAM_OFFSET;
3008                 ale_params.ale_regs  = ss_regs + CPSW2_ALE_OFFSET;
3009                 slave_offset         = CPSW2_SLAVE_OFFSET;
3010                 slave_size           = CPSW2_SLAVE_SIZE;
3011                 sliver_offset        = CPSW2_SLIVER_OFFSET;
3012                 dma_params.desc_mem_phys =
3013                         (u32 __force) ss_res->start + CPSW2_BD_OFFSET;
3014                 break;
3015         default:
3016                 dev_err(priv->dev, "unknown version 0x%08x\n", cpsw->version);
3017                 ret = -ENODEV;
3018                 goto clean_dt_ret;
3019         }
3020         for (i = 0; i < cpsw->data.slaves; i++) {
3021                 struct cpsw_slave *slave = &cpsw->slaves[i];
3022
3023                 cpsw_slave_init(slave, cpsw, slave_offset, sliver_offset);
3024                 slave_offset  += slave_size;
3025                 sliver_offset += SLIVER_SIZE;
3026         }
3027
3028         dma_params.dev          = &pdev->dev;
3029         dma_params.rxthresh     = dma_params.dmaregs + CPDMA_RXTHRESH;
3030         dma_params.rxfree       = dma_params.dmaregs + CPDMA_RXFREE;
3031         dma_params.rxhdp        = dma_params.txhdp + CPDMA_RXHDP;
3032         dma_params.txcp         = dma_params.txhdp + CPDMA_TXCP;
3033         dma_params.rxcp         = dma_params.txhdp + CPDMA_RXCP;
3034
3035         dma_params.num_chan             = data->channels;
3036         dma_params.has_soft_reset       = true;
3037         dma_params.min_packet_size      = CPSW_MIN_PACKET_SIZE;
3038         dma_params.desc_mem_size        = data->bd_ram_size;
3039         dma_params.desc_align           = 16;
3040         dma_params.has_ext_regs         = true;
3041         dma_params.desc_hw_addr         = dma_params.desc_mem_phys;
3042         dma_params.bus_freq_mhz         = cpsw->bus_freq_mhz;
3043         dma_params.descs_pool_size      = descs_pool_size;
3044
3045         cpsw->dma = cpdma_ctlr_create(&dma_params);
3046         if (!cpsw->dma) {
3047                 dev_err(priv->dev, "error initializing dma\n");
3048                 ret = -ENOMEM;
3049                 goto clean_dt_ret;
3050         }
3051
3052         cpsw->txv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_tx_handler, 0);
3053         cpsw->rxv[0].ch = cpdma_chan_create(cpsw->dma, 0, cpsw_rx_handler, 1);
3054         if (WARN_ON(!cpsw->rxv[0].ch || !cpsw->txv[0].ch)) {
3055                 dev_err(priv->dev, "error initializing dma channels\n");
3056                 ret = -ENOMEM;
3057                 goto clean_dma_ret;
3058         }
3059
3060         ale_params.dev                  = &pdev->dev;
3061         ale_params.ale_ageout           = ale_ageout;
3062         ale_params.ale_entries          = data->ale_entries;
3063         ale_params.ale_ports            = data->slaves;
3064
3065         cpsw->ale = cpsw_ale_create(&ale_params);
3066         if (!cpsw->ale) {
3067                 dev_err(priv->dev, "error initializing ale engine\n");
3068                 ret = -ENODEV;
3069                 goto clean_dma_ret;
3070         }
3071
3072         cpsw->cpts = cpts_create(cpsw->dev, cpts_regs, cpsw->dev->of_node);
3073         if (IS_ERR(cpsw->cpts)) {
3074                 ret = PTR_ERR(cpsw->cpts);
3075                 goto clean_ale_ret;
3076         }
3077
3078         ndev->irq = platform_get_irq(pdev, 1);
3079         if (ndev->irq < 0) {
3080                 dev_err(priv->dev, "error getting irq resource\n");
3081                 ret = ndev->irq;
3082                 goto clean_ale_ret;
3083         }
3084
3085         of_id = of_match_device(cpsw_of_mtable, &pdev->dev);
3086         if (of_id) {
3087                 pdev->id_entry = of_id->data;
3088                 if (pdev->id_entry->driver_data)
3089                         cpsw->quirk_irq = true;
3090         }
3091
3092         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3093
3094         ndev->netdev_ops = &cpsw_netdev_ops;
3095         ndev->ethtool_ops = &cpsw_ethtool_ops;
3096         netif_napi_add(ndev, &cpsw->napi_rx, cpsw_rx_poll, CPSW_POLL_WEIGHT);
3097         netif_tx_napi_add(ndev, &cpsw->napi_tx, cpsw_tx_poll, CPSW_POLL_WEIGHT);
3098         cpsw_split_res(ndev);
3099
3100         /* register the network device */
3101         SET_NETDEV_DEV(ndev, &pdev->dev);
3102         ret = register_netdev(ndev);
3103         if (ret) {
3104                 dev_err(priv->dev, "error registering net device\n");
3105                 ret = -ENODEV;
3106                 goto clean_ale_ret;
3107         }
3108
3109         if (cpsw->data.dual_emac) {
3110                 ret = cpsw_probe_dual_emac(priv);
3111                 if (ret) {
3112                         cpsw_err(priv, probe, "error probe slave 2 emac interface\n");
3113                         goto clean_unregister_netdev_ret;
3114                 }
3115         }
3116
3117         /* Grab RX and TX IRQs. Note that we also have RX_THRESHOLD and
3118          * MISC IRQs which are always kept disabled with this driver so
3119          * we will not request them.
3120          *
3121          * If anyone wants to implement support for those, make sure to
3122          * first request and append them to irqs_table array.
3123          */
3124
3125         /* RX IRQ */
3126         irq = platform_get_irq(pdev, 1);
3127         if (irq < 0) {
3128                 ret = irq;
3129                 goto clean_ale_ret;
3130         }
3131
3132         cpsw->irqs_table[0] = irq;
3133         ret = devm_request_irq(&pdev->dev, irq, cpsw_rx_interrupt,
3134                                0, dev_name(&pdev->dev), cpsw);
3135         if (ret < 0) {
3136                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3137                 goto clean_ale_ret;
3138         }
3139
3140         /* TX IRQ */
3141         irq = platform_get_irq(pdev, 2);
3142         if (irq < 0) {
3143                 ret = irq;
3144                 goto clean_ale_ret;
3145         }
3146
3147         cpsw->irqs_table[1] = irq;
3148         ret = devm_request_irq(&pdev->dev, irq, cpsw_tx_interrupt,
3149                                0, dev_name(&pdev->dev), cpsw);
3150         if (ret < 0) {
3151                 dev_err(priv->dev, "error attaching irq (%d)\n", ret);
3152                 goto clean_ale_ret;
3153         }
3154
3155         cpsw_notice(priv, probe,
3156                     "initialized device (regs %pa, irq %d, pool size %d)\n",
3157                     &ss_res->start, ndev->irq, dma_params.descs_pool_size);
3158
3159         pm_runtime_put(&pdev->dev);
3160
3161         return 0;
3162
3163 clean_unregister_netdev_ret:
3164         unregister_netdev(ndev);
3165 clean_ale_ret:
3166         cpsw_ale_destroy(cpsw->ale);
3167 clean_dma_ret:
3168         cpdma_ctlr_destroy(cpsw->dma);
3169 clean_dt_ret:
3170         cpsw_remove_dt(pdev);
3171         pm_runtime_put_sync(&pdev->dev);
3172 clean_runtime_disable_ret:
3173         pm_runtime_disable(&pdev->dev);
3174 clean_ndev_ret:
3175         free_netdev(priv->ndev);
3176         return ret;
3177 }
3178
3179 static int cpsw_remove(struct platform_device *pdev)
3180 {
3181         struct net_device *ndev = platform_get_drvdata(pdev);
3182         struct cpsw_common *cpsw = ndev_to_cpsw(ndev);
3183         int ret;
3184
3185         ret = pm_runtime_get_sync(&pdev->dev);
3186         if (ret < 0) {
3187                 pm_runtime_put_noidle(&pdev->dev);
3188                 return ret;
3189         }
3190
3191         if (cpsw->data.dual_emac)
3192                 unregister_netdev(cpsw->slaves[1].ndev);
3193         unregister_netdev(ndev);
3194
3195         cpts_release(cpsw->cpts);
3196         cpsw_ale_destroy(cpsw->ale);
3197         cpdma_ctlr_destroy(cpsw->dma);
3198         cpsw_remove_dt(pdev);
3199         pm_runtime_put_sync(&pdev->dev);
3200         pm_runtime_disable(&pdev->dev);
3201         if (cpsw->data.dual_emac)
3202                 free_netdev(cpsw->slaves[1].ndev);
3203         free_netdev(ndev);
3204         return 0;
3205 }
3206
3207 #ifdef CONFIG_PM_SLEEP
3208 static int cpsw_suspend(struct device *dev)
3209 {
3210         struct platform_device  *pdev = to_platform_device(dev);
3211         struct net_device       *ndev = platform_get_drvdata(pdev);
3212         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3213
3214         if (cpsw->data.dual_emac) {
3215                 int i;
3216
3217                 for (i = 0; i < cpsw->data.slaves; i++) {
3218                         if (netif_running(cpsw->slaves[i].ndev))
3219                                 cpsw_ndo_stop(cpsw->slaves[i].ndev);
3220                 }
3221         } else {
3222                 if (netif_running(ndev))
3223                         cpsw_ndo_stop(ndev);
3224         }
3225
3226         /* Select sleep pin state */
3227         pinctrl_pm_select_sleep_state(dev);
3228
3229         return 0;
3230 }
3231
3232 static int cpsw_resume(struct device *dev)
3233 {
3234         struct platform_device  *pdev = to_platform_device(dev);
3235         struct net_device       *ndev = platform_get_drvdata(pdev);
3236         struct cpsw_common      *cpsw = ndev_to_cpsw(ndev);
3237
3238         /* Select default pin state */
3239         pinctrl_pm_select_default_state(dev);
3240
3241         /* shut up ASSERT_RTNL() warning in netif_set_real_num_tx/rx_queues */
3242         rtnl_lock();
3243         if (cpsw->data.dual_emac) {
3244                 int i;
3245
3246                 for (i = 0; i < cpsw->data.slaves; i++) {
3247                         if (netif_running(cpsw->slaves[i].ndev))
3248                                 cpsw_ndo_open(cpsw->slaves[i].ndev);
3249                 }
3250         } else {
3251                 if (netif_running(ndev))
3252                         cpsw_ndo_open(ndev);
3253         }
3254         rtnl_unlock();
3255
3256         return 0;
3257 }
3258 #endif
3259
3260 static SIMPLE_DEV_PM_OPS(cpsw_pm_ops, cpsw_suspend, cpsw_resume);
3261
3262 static struct platform_driver cpsw_driver = {
3263         .driver = {
3264                 .name    = "cpsw",
3265                 .pm      = &cpsw_pm_ops,
3266                 .of_match_table = cpsw_of_mtable,
3267         },
3268         .probe = cpsw_probe,
3269         .remove = cpsw_remove,
3270 };
3271
3272 module_platform_driver(cpsw_driver);
3273
3274 MODULE_LICENSE("GPL");
3275 MODULE_AUTHOR("Cyril Chemparathy <cyril@ti.com>");
3276 MODULE_AUTHOR("Mugunthan V N <mugunthanvnm@ti.com>");
3277 MODULE_DESCRIPTION("TI CPSW Ethernet driver");