drivers/net/ethernet/toshiba/tc35815.c

   1 /*
   2  * tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
   3  *
   4  * Based on skelton.c by Donald Becker.
   5  *
   6  * This driver is a replacement of older and less maintained version.
   7  * This is a header of the older version:
   8  *      -----<snip>-----
   9  *      Copyright 2001 MontaVista Software Inc.
  10  *      Author: MontaVista Software, Inc.
  11  *              ahennessy@mvista.com
  12  *      Copyright (C) 2000-2001 Toshiba Corporation
  13  *      static const char *version =
  14  *              "tc35815.c:v0.00 26/07/2000 by Toshiba Corporation\n";
  15  *      -----<snip>-----
  16  *
  17  * This file is subject to the terms and conditions of the GNU General Public
  18  * License.  See the file "COPYING" in the main directory of this archive
  19  * for more details.
  20  *
  21  * (C) Copyright TOSHIBA CORPORATION 2004-2005
  22  * All Rights Reserved.
  23  */
  24
  25 #define DRV_VERSION     "1.39"
  26 static const char version[] = "tc35815.c:v" DRV_VERSION "\n";
  27 #define MODNAME                 "tc35815"
  28
  29 #include <linux/module.h>
  30 #include <linux/kernel.h>
  31 #include <linux/types.h>
  32 #include <linux/fcntl.h>
  33 #include <linux/interrupt.h>
  34 #include <linux/ioport.h>
  35 #include <linux/in.h>
  36 #include <linux/if_vlan.h>
  37 #include <linux/slab.h>
  38 #include <linux/string.h>
  39 #include <linux/spinlock.h>
  40 #include <linux/errno.h>
  41 #include <linux/netdevice.h>
  42 #include <linux/etherdevice.h>
  43 #include <linux/skbuff.h>
  44 #include <linux/delay.h>
  45 #include <linux/pci.h>
  46 #include <linux/phy.h>
  47 #include <linux/workqueue.h>
  48 #include <linux/platform_device.h>
  49 #include <linux/prefetch.h>
  50 #include <asm/io.h>
  51 #include <asm/byteorder.h>
  52
  53 enum tc35815_chiptype {
  54         TC35815CF = 0,
  55         TC35815_NWU,
  56         TC35815_TX4939,
  57 };
  58
  59 /* indexed by tc35815_chiptype, above */
  60 static const struct {
  61         const char *name;
  62 } chip_info[] = {
  63         { "TOSHIBA TC35815CF 10/100BaseTX" },
  64         { "TOSHIBA TC35815 with Wake on LAN" },
  65         { "TOSHIBA TC35815/TX4939" },
  66 };
  67
  68 static const struct pci_device_id tc35815_pci_tbl[] = {
  69         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF), .driver_data = TC35815CF },
  70         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_NWU), .driver_data = TC35815_NWU },
  71         {PCI_DEVICE(PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815_TX4939), .driver_data = TC35815_TX4939 },
  72         {0,}
  73 };
  74 MODULE_DEVICE_TABLE(pci, tc35815_pci_tbl);
  75
  76 /* see MODULE_PARM_DESC */
  77 static struct tc35815_options {
  78         int speed;
  79         int duplex;
  80 } options;
  81
  82 /*
  83  * Registers
  84  */
  85 struct tc35815_regs {
  86         __u32 DMA_Ctl;          /* 0x00 */
  87         __u32 TxFrmPtr;
  88         __u32 TxThrsh;
  89         __u32 TxPollCtr;
  90         __u32 BLFrmPtr;
  91         __u32 RxFragSize;
  92         __u32 Int_En;
  93         __u32 FDA_Bas;
  94         __u32 FDA_Lim;          /* 0x20 */
  95         __u32 Int_Src;
  96         __u32 unused0[2];
  97         __u32 PauseCnt;
  98         __u32 RemPauCnt;
  99         __u32 TxCtlFrmStat;
 100         __u32 unused1;
 101         __u32 MAC_Ctl;          /* 0x40 */
 102         __u32 CAM_Ctl;
 103         __u32 Tx_Ctl;
 104         __u32 Tx_Stat;
 105         __u32 Rx_Ctl;
 106         __u32 Rx_Stat;
 107         __u32 MD_Data;
 108         __u32 MD_CA;
 109         __u32 CAM_Adr;          /* 0x60 */
 110         __u32 CAM_Data;
 111         __u32 CAM_Ena;
 112         __u32 PROM_Ctl;
 113         __u32 PROM_Data;
 114         __u32 Algn_Cnt;
 115         __u32 CRC_Cnt;
 116         __u32 Miss_Cnt;
 117 };
 118
 119 /*
 120  * Bit assignments
 121  */
 122 /* DMA_Ctl bit assign ------------------------------------------------------- */
 123 #define DMA_RxAlign            0x00c00000 /* 1:Reception Alignment           */
 124 #define DMA_RxAlign_1          0x00400000
 125 #define DMA_RxAlign_2          0x00800000
 126 #define DMA_RxAlign_3          0x00c00000
 127 #define DMA_M66EnStat          0x00080000 /* 1:66MHz Enable State            */
 128 #define DMA_IntMask            0x00040000 /* 1:Interrupt mask                */
 129 #define DMA_SWIntReq           0x00020000 /* 1:Software Interrupt request    */
 130 #define DMA_TxWakeUp           0x00010000 /* 1:Transmit Wake Up              */
 131 #define DMA_RxBigE             0x00008000 /* 1:Receive Big Endian            */
 132 #define DMA_TxBigE             0x00004000 /* 1:Transmit Big Endian           */
 133 #define DMA_TestMode           0x00002000 /* 1:Test Mode                     */
 134 #define DMA_PowrMgmnt          0x00001000 /* 1:Power Management              */
 135 #define DMA_DmBurst_Mask       0x000001fc /* DMA Burst size                  */
 136
 137 /* RxFragSize bit assign ---------------------------------------------------- */
 138 #define RxFrag_EnPack          0x00008000 /* 1:Enable Packing                */
 139 #define RxFrag_MinFragMask     0x00000ffc /* Minimum Fragment                */
 140
 141 /* MAC_Ctl bit assign ------------------------------------------------------- */
 142 #define MAC_Link10             0x00008000 /* 1:Link Status 10Mbits           */
 143 #define MAC_EnMissRoll         0x00002000 /* 1:Enable Missed Roll            */
 144 #define MAC_MissRoll           0x00000400 /* 1:Missed Roll                   */
 145 #define MAC_Loop10             0x00000080 /* 1:Loop 10 Mbps                  */
 146 #define MAC_Conn_Auto          0x00000000 /*00:Connection mode (Automatic)   */
 147 #define MAC_Conn_10M           0x00000020 /*01:                (10Mbps endec)*/
 148 #define MAC_Conn_Mll           0x00000040 /*10:                (Mll clock)   */
 149 #define MAC_MacLoop            0x00000010 /* 1:MAC Loopback                  */
 150 #define MAC_FullDup            0x00000008 /* 1:Full Duplex 0:Half Duplex     */
 151 #define MAC_Reset              0x00000004 /* 1:Software Reset                */
 152 #define MAC_HaltImm            0x00000002 /* 1:Halt Immediate                */
 153 #define MAC_HaltReq            0x00000001 /* 1:Halt request                  */
 154
 155 /* PROM_Ctl bit assign ------------------------------------------------------ */
 156 #define PROM_Busy              0x00008000 /* 1:Busy (Start Operation)        */
 157 #define PROM_Read              0x00004000 /*10:Read operation                */
 158 #define PROM_Write             0x00002000 /*01:Write operation               */
 159 #define PROM_Erase             0x00006000 /*11:Erase operation               */
 160                                           /*00:Enable or Disable Writting,   */
 161                                           /*      as specified in PROM_Addr. */
 162 #define PROM_Addr_Ena          0x00000030 /*11xxxx:PROM Write enable         */
 163                                           /*00xxxx:           disable        */
 164
 165 /* CAM_Ctl bit assign ------------------------------------------------------- */
 166 #define CAM_CompEn             0x00000010 /* 1:CAM Compare Enable            */
 167 #define CAM_NegCAM             0x00000008 /* 1:Reject packets CAM recognizes,*/
 168                                           /*                    accept other */
 169 #define CAM_BroadAcc           0x00000004 /* 1:Broadcast assept              */
 170 #define CAM_GroupAcc           0x00000002 /* 1:Multicast assept              */
 171 #define CAM_StationAcc         0x00000001 /* 1:unicast accept                */
 172
 173 /* CAM_Ena bit assign ------------------------------------------------------- */
 174 #define CAM_ENTRY_MAX                  21   /* CAM Data entry max count      */
 175 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits)  */
 176 #define CAM_Ena_Bit(index)      (1 << (index))
 177 #define CAM_ENTRY_DESTINATION   0
 178 #define CAM_ENTRY_SOURCE        1
 179 #define CAM_ENTRY_MACCTL        20
 180
 181 /* Tx_Ctl bit assign -------------------------------------------------------- */
 182 #define Tx_En                  0x00000001 /* 1:Transmit enable               */
 183 #define Tx_TxHalt              0x00000002 /* 1:Transmit Halt Request         */
 184 #define Tx_NoPad               0x00000004 /* 1:Suppress Padding              */
 185 #define Tx_NoCRC               0x00000008 /* 1:Suppress Padding              */
 186 #define Tx_FBack               0x00000010 /* 1:Fast Back-off                 */
 187 #define Tx_EnUnder             0x00000100 /* 1:Enable Underrun               */
 188 #define Tx_EnExDefer           0x00000200 /* 1:Enable Excessive Deferral     */
 189 #define Tx_EnLCarr             0x00000400 /* 1:Enable Lost Carrier           */
 190 #define Tx_EnExColl            0x00000800 /* 1:Enable Excessive Collision    */
 191 #define Tx_EnLateColl          0x00001000 /* 1:Enable Late Collision         */
 192 #define Tx_EnTxPar             0x00002000 /* 1:Enable Transmit Parity        */
 193 #define Tx_EnComp              0x00004000 /* 1:Enable Completion             */
 194
 195 /* Tx_Stat bit assign ------------------------------------------------------- */
 196 #define Tx_TxColl_MASK         0x0000000F /* Tx Collision Count              */
 197 #define Tx_ExColl              0x00000010 /* Excessive Collision             */
 198 #define Tx_TXDefer             0x00000020 /* Transmit Defered                */
 199 #define Tx_Paused              0x00000040 /* Transmit Paused                 */
 200 #define Tx_IntTx               0x00000080 /* Interrupt on Tx                 */
 201 #define Tx_Under               0x00000100 /* Underrun                        */
 202 #define Tx_Defer               0x00000200 /* Deferral                        */
 203 #define Tx_NCarr               0x00000400 /* No Carrier                      */
 204 #define Tx_10Stat              0x00000800 /* 10Mbps Status                   */
 205 #define Tx_LateColl            0x00001000 /* Late Collision                  */
 206 #define Tx_TxPar               0x00002000 /* Tx Parity Error                 */
 207 #define Tx_Comp                0x00004000 /* Completion                      */
 208 #define Tx_Halted              0x00008000 /* Tx Halted                       */
 209 #define Tx_SQErr               0x00010000 /* Signal Quality Error(SQE)       */
 210
 211 /* Rx_Ctl bit assign -------------------------------------------------------- */
 212 #define Rx_EnGood              0x00004000 /* 1:Enable Good                   */
 213 #define Rx_EnRxPar             0x00002000 /* 1:Enable Receive Parity         */
 214 #define Rx_EnLongErr           0x00000800 /* 1:Enable Long Error             */
 215 #define Rx_EnOver              0x00000400 /* 1:Enable OverFlow               */
 216 #define Rx_EnCRCErr            0x00000200 /* 1:Enable CRC Error              */
 217 #define Rx_EnAlign             0x00000100 /* 1:Enable Alignment              */
 218 #define Rx_IgnoreCRC           0x00000040 /* 1:Ignore CRC Value              */
 219 #define Rx_StripCRC            0x00000010 /* 1:Strip CRC Value               */
 220 #define Rx_ShortEn             0x00000008 /* 1:Short Enable                  */
 221 #define Rx_LongEn              0x00000004 /* 1:Long Enable                   */
 222 #define Rx_RxHalt              0x00000002 /* 1:Receive Halt Request          */
 223 #define Rx_RxEn                0x00000001 /* 1:Receive Intrrupt Enable       */
 224
 225 /* Rx_Stat bit assign ------------------------------------------------------- */
 226 #define Rx_Halted              0x00008000 /* Rx Halted                       */
 227 #define Rx_Good                0x00004000 /* Rx Good                         */
 228 #define Rx_RxPar               0x00002000 /* Rx Parity Error                 */
 229 #define Rx_TypePkt             0x00001000 /* Rx Type Packet                  */
 230 #define Rx_LongErr             0x00000800 /* Rx Long Error                   */
 231 #define Rx_Over                0x00000400 /* Rx Overflow                     */
 232 #define Rx_CRCErr              0x00000200 /* Rx CRC Error                    */
 233 #define Rx_Align               0x00000100 /* Rx Alignment Error              */
 234 #define Rx_10Stat              0x00000080 /* Rx 10Mbps Status                */
 235 #define Rx_IntRx               0x00000040 /* Rx Interrupt                    */
 236 #define Rx_CtlRecd             0x00000020 /* Rx Control Receive              */
 237 #define Rx_InLenErr            0x00000010 /* Rx In Range Frame Length Error  */
 238
 239 #define Rx_Stat_Mask           0x0000FFF0 /* Rx All Status Mask              */
 240
 241 /* Int_En bit assign -------------------------------------------------------- */
 242 #define Int_NRAbtEn            0x00000800 /* 1:Non-recoverable Abort Enable  */
 243 #define Int_TxCtlCmpEn         0x00000400 /* 1:Transmit Ctl Complete Enable  */
 244 #define Int_DmParErrEn         0x00000200 /* 1:DMA Parity Error Enable       */
 245 #define Int_DParDEn            0x00000100 /* 1:Data Parity Error Enable      */
 246 #define Int_EarNotEn           0x00000080 /* 1:Early Notify Enable           */
 247 #define Int_DParErrEn          0x00000040 /* 1:Detected Parity Error Enable  */
 248 #define Int_SSysErrEn          0x00000020 /* 1:Signalled System Error Enable */
 249 #define Int_RMasAbtEn          0x00000010 /* 1:Received Master Abort Enable  */
 250 #define Int_RTargAbtEn         0x00000008 /* 1:Received Target Abort Enable  */
 251 #define Int_STargAbtEn         0x00000004 /* 1:Signalled Target Abort Enable */
 252 #define Int_BLExEn             0x00000002 /* 1:Buffer List Exhausted Enable  */
 253 #define Int_FDAExEn            0x00000001 /* 1:Free Descriptor Area          */
 254                                           /*               Exhausted Enable  */
 255
 256 /* Int_Src bit assign ------------------------------------------------------- */
 257 #define Int_NRabt              0x00004000 /* 1:Non Recoverable error         */
 258 #define Int_DmParErrStat       0x00002000 /* 1:DMA Parity Error & Clear      */
 259 #define Int_BLEx               0x00001000 /* 1:Buffer List Empty & Clear     */
 260 #define Int_FDAEx              0x00000800 /* 1:FDA Empty & Clear             */
 261 #define Int_IntNRAbt           0x00000400 /* 1:Non Recoverable Abort         */
 262 #define Int_IntCmp             0x00000200 /* 1:MAC control packet complete   */
 263 #define Int_IntExBD            0x00000100 /* 1:Interrupt Extra BD & Clear    */
 264 #define Int_DmParErr           0x00000080 /* 1:DMA Parity Error & Clear      */
 265 #define Int_IntEarNot          0x00000040 /* 1:Receive Data write & Clear    */
 266 #define Int_SWInt              0x00000020 /* 1:Software request & Clear      */
 267 #define Int_IntBLEx            0x00000010 /* 1:Buffer List Empty & Clear     */
 268 #define Int_IntFDAEx           0x00000008 /* 1:FDA Empty & Clear             */
 269 #define Int_IntPCI             0x00000004 /* 1:PCI controller & Clear        */
 270 #define Int_IntMacRx           0x00000002 /* 1:Rx controller & Clear         */
 271 #define Int_IntMacTx           0x00000001 /* 1:Tx controller & Clear         */
 272
 273 /* MD_CA bit assign --------------------------------------------------------- */
 274 #define MD_CA_PreSup           0x00001000 /* 1:Preamble Suppress                     */
 275 #define MD_CA_Busy             0x00000800 /* 1:Busy (Start Operation)        */
 276 #define MD_CA_Wr               0x00000400 /* 1:Write 0:Read                  */
 277
 278
 279 /*
 280  * Descriptors
 281  */
 282
 283 /* Frame descriptor */
 284 struct FDesc {
 285         volatile __u32 FDNext;
 286         volatile __u32 FDSystem;
 287         volatile __u32 FDStat;
 288         volatile __u32 FDCtl;
 289 };
 290
 291 /* Buffer descriptor */
 292 struct BDesc {
 293         volatile __u32 BuffData;
 294         volatile __u32 BDCtl;
 295 };
 296
 297 #define FD_ALIGN        16
 298
 299 /* Frame Descriptor bit assign ---------------------------------------------- */
 300 #define FD_FDLength_MASK       0x0000FFFF /* Length MASK                     */
 301 #define FD_BDCnt_MASK          0x001F0000 /* BD count MASK in FD             */
 302 #define FD_FrmOpt_MASK         0x7C000000 /* Frame option MASK               */
 303 #define FD_FrmOpt_BigEndian    0x40000000 /* Tx/Rx */
 304 #define FD_FrmOpt_IntTx        0x20000000 /* Tx only */
 305 #define FD_FrmOpt_NoCRC        0x10000000 /* Tx only */
 306 #define FD_FrmOpt_NoPadding    0x08000000 /* Tx only */
 307 #define FD_FrmOpt_Packing      0x04000000 /* Rx only */
 308 #define FD_CownsFD             0x80000000 /* FD Controller owner bit         */
 309 #define FD_Next_EOL            0x00000001 /* FD EOL indicator                */
 310 #define FD_BDCnt_SHIFT         16
 311
 312 /* Buffer Descriptor bit assign --------------------------------------------- */
 313 #define BD_BuffLength_MASK     0x0000FFFF /* Receive Data Size               */
 314 #define BD_RxBDID_MASK         0x00FF0000 /* BD ID Number MASK               */
 315 #define BD_RxBDSeqN_MASK       0x7F000000 /* Rx BD Sequence Number           */
 316 #define BD_CownsBD             0x80000000 /* BD Controller owner bit         */
 317 #define BD_RxBDID_SHIFT        16
 318 #define BD_RxBDSeqN_SHIFT      24
 319
 320
 321 /* Some useful constants. */
 322
 323 #define TX_CTL_CMD      (Tx_EnTxPar | Tx_EnLateColl | \
 324         Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
 325         Tx_En)  /* maybe  0x7b01 */
 326 /* Do not use Rx_StripCRC -- it causes trouble on BLEx/FDAEx condition */
 327 #define RX_CTL_CMD      (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
 328         | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
 329 #define INT_EN_CMD  (Int_NRAbtEn | \
 330         Int_DmParErrEn | Int_DParDEn | Int_DParErrEn | \
 331         Int_SSysErrEn  | Int_RMasAbtEn | Int_RTargAbtEn | \
 332         Int_STargAbtEn | \
 333         Int_BLExEn  | Int_FDAExEn) /* maybe 0xb7f*/
 334 #define DMA_CTL_CMD     DMA_BURST_SIZE
 335 #define HAVE_DMA_RXALIGN(lp)    likely((lp)->chiptype != TC35815CF)
 336
 337 /* Tuning parameters */
 338 #define DMA_BURST_SIZE  32
 339 #define TX_THRESHOLD    1024
 340 /* used threshold with packet max byte for low pci transfer ability.*/
 341 #define TX_THRESHOLD_MAX 1536
 342 /* setting threshold max value when overrun error occurred this count. */
 343 #define TX_THRESHOLD_KEEP_LIMIT 10
 344
 345 /* 16 + RX_BUF_NUM * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*FD_PAGE_NUM */
 346 #define FD_PAGE_NUM 4
 347 #define RX_BUF_NUM      128     /* < 256 */
 348 #define RX_FD_NUM       256     /* >= 32 */
 349 #define TX_FD_NUM       128
 350 #if RX_CTL_CMD & Rx_LongEn
 351 #define RX_BUF_SIZE     PAGE_SIZE
 352 #elif RX_CTL_CMD & Rx_StripCRC
 353 #define RX_BUF_SIZE     \
 354         L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + NET_IP_ALIGN)
 355 #else
 356 #define RX_BUF_SIZE     \
 357         L1_CACHE_ALIGN(ETH_FRAME_LEN + VLAN_HLEN + ETH_FCS_LEN + NET_IP_ALIGN)
 358 #endif
 359 #define RX_FD_RESERVE   (2 / 2) /* max 2 BD per RxFD */
 360 #define NAPI_WEIGHT     16
 361
 362 struct TxFD {
 363         struct FDesc fd;
 364         struct BDesc bd;
 365         struct BDesc unused;
 366 };
 367
 368 struct RxFD {
 369         struct FDesc fd;
 370         struct BDesc bd[0];     /* variable length */
 371 };
 372
 373 struct FrFD {
 374         struct FDesc fd;
 375         struct BDesc bd[RX_BUF_NUM];
 376 };
 377
 378
 379 #define tc_readl(addr)  ioread32(addr)
 380 #define tc_writel(d, addr)      iowrite32(d, addr)
 381
 382 #define TC35815_TX_TIMEOUT  msecs_to_jiffies(400)
 383
 384 /* Information that need to be kept for each controller. */
 385 struct tc35815_local {
 386         struct pci_dev *pci_dev;
 387
 388         struct net_device *dev;
 389         struct napi_struct napi;
 390
 391         /* statistics */
 392         struct {
 393                 int max_tx_qlen;
 394                 int tx_ints;
 395                 int rx_ints;
 396                 int tx_underrun;
 397         } lstats;
 398
 399         /* Tx control lock.  This protects the transmit buffer ring
 400          * state along with the "tx full" state of the driver.  This
 401          * means all netif_queue flow control actions are protected
 402          * by this lock as well.
 403          */
 404         spinlock_t lock;
 405         spinlock_t rx_lock;
 406
 407         struct mii_bus *mii_bus;
 408         int duplex;
 409         int speed;
 410         int link;
 411         struct work_struct restart_work;
 412
 413         /*
 414          * Transmitting: Batch Mode.
 415          *      1 BD in 1 TxFD.
 416          * Receiving: Non-Packing Mode.
 417          *      1 circular FD for Free Buffer List.
 418          *      RX_BUF_NUM BD in Free Buffer FD.
 419          *      One Free Buffer BD has ETH_FRAME_LEN data buffer.
 420          */
 421         void *fd_buf;   /* for TxFD, RxFD, FrFD */
 422         dma_addr_t fd_buf_dma;
 423         struct TxFD *tfd_base;
 424         unsigned int tfd_start;
 425         unsigned int tfd_end;
 426         struct RxFD *rfd_base;
 427         struct RxFD *rfd_limit;
 428         struct RxFD *rfd_cur;
 429         struct FrFD *fbl_ptr;
 430         unsigned int fbl_count;
 431         struct {
 432                 struct sk_buff *skb;
 433                 dma_addr_t skb_dma;
 434         } tx_skbs[TX_FD_NUM], rx_skbs[RX_BUF_NUM];
 435         u32 msg_enable;
 436         enum tc35815_chiptype chiptype;
 437 };
 438
 439 static inline dma_addr_t fd_virt_to_bus(struct tc35815_local *lp, void *virt)
 440 {
 441         return lp->fd_buf_dma + ((u8 *)virt - (u8 *)lp->fd_buf);
 442 }
 443 #ifdef DEBUG
 444 static inline void *fd_bus_to_virt(struct tc35815_local *lp, dma_addr_t bus)
 445 {
 446         return (void *)((u8 *)lp->fd_buf + (bus - lp->fd_buf_dma));
 447 }
 448 #endif
 449 static struct sk_buff *alloc_rxbuf_skb(struct net_device *dev,
 450                                        struct pci_dev *hwdev,
 451                                        dma_addr_t *dma_handle)
 452 {
 453         struct sk_buff *skb;
 454         skb = netdev_alloc_skb(dev, RX_BUF_SIZE);
 455         if (!skb)
 456                 return NULL;
 457         *dma_handle = pci_map_single(hwdev, skb->data, RX_BUF_SIZE,
 458                                      PCI_DMA_FROMDEVICE);
 459         if (pci_dma_mapping_error(hwdev, *dma_handle)) {
 460                 dev_kfree_skb_any(skb);
 461                 return NULL;
 462         }
 463         skb_reserve(skb, 2);    /* make IP header 4byte aligned */
 464         return skb;
 465 }
 466
 467 static void free_rxbuf_skb(struct pci_dev *hwdev, struct sk_buff *skb, dma_addr_t dma_handle)
 468 {
 469         pci_unmap_single(hwdev, dma_handle, RX_BUF_SIZE,
 470                          PCI_DMA_FROMDEVICE);
 471         dev_kfree_skb_any(skb);
 472 }
 473
 474 /* Index to functions, as function prototypes. */
 475
 476 static int      tc35815_open(struct net_device *dev);
 477 static int      tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
 478 static irqreturn_t      tc35815_interrupt(int irq, void *dev_id);
 479 static int      tc35815_rx(struct net_device *dev, int limit);
 480 static int      tc35815_poll(struct napi_struct *napi, int budget);
 481 static void     tc35815_txdone(struct net_device *dev);
 482 static int      tc35815_close(struct net_device *dev);
 483 static struct   net_device_stats *tc35815_get_stats(struct net_device *dev);
 484 static void     tc35815_set_multicast_list(struct net_device *dev);
 485 static void     tc35815_tx_timeout(struct net_device *dev);
 486 static int      tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 487 #ifdef CONFIG_NET_POLL_CONTROLLER
 488 static void     tc35815_poll_controller(struct net_device *dev);
 489 #endif
 490 static const struct ethtool_ops tc35815_ethtool_ops;
 491
 492 /* Example routines you must write ;->. */
 493 static void     tc35815_chip_reset(struct net_device *dev);
 494 static void     tc35815_chip_init(struct net_device *dev);
 495
 496 #ifdef DEBUG
 497 static void     panic_queues(struct net_device *dev);
 498 #endif
 499
 500 static void tc35815_restart_work(struct work_struct *work);
 501
 502 static int tc_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
 503 {
 504         struct net_device *dev = bus->priv;
 505         struct tc35815_regs __iomem *tr =
 506                 (struct tc35815_regs __iomem *)dev->base_addr;
 507         unsigned long timeout = jiffies + HZ;
 508
 509         tc_writel(MD_CA_Busy | (mii_id << 5) | (regnum & 0x1f), &tr->MD_CA);
 510         udelay(12); /* it takes 32 x 400ns at least */
 511         while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
 512                 if (time_after(jiffies, timeout))
 513                         return -EIO;
 514                 cpu_relax();
 515         }
 516         return tc_readl(&tr->MD_Data) & 0xffff;
 517 }
 518
 519 static int tc_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 val)
 520 {
 521         struct net_device *dev = bus->priv;
 522         struct tc35815_regs __iomem *tr =
 523                 (struct tc35815_regs __iomem *)dev->base_addr;
 524         unsigned long timeout = jiffies + HZ;
 525
 526         tc_writel(val, &tr->MD_Data);
 527         tc_writel(MD_CA_Busy | MD_CA_Wr | (mii_id << 5) | (regnum & 0x1f),
 528                   &tr->MD_CA);
 529         udelay(12); /* it takes 32 x 400ns at least */
 530         while (tc_readl(&tr->MD_CA) & MD_CA_Busy) {
 531                 if (time_after(jiffies, timeout))
 532                         return -EIO;
 533                 cpu_relax();
 534         }
 535         return 0;
 536 }
 537
 538 static void tc_handle_link_change(struct net_device *dev)
 539 {
 540         struct tc35815_local *lp = netdev_priv(dev);
 541         struct phy_device *phydev = dev->phydev;
 542         unsigned long flags;
 543         int status_change = 0;
 544
 545         spin_lock_irqsave(&lp->lock, flags);
 546         if (phydev->link &&
 547             (lp->speed != phydev->speed || lp->duplex != phydev->duplex)) {
 548                 struct tc35815_regs __iomem *tr =
 549                         (struct tc35815_regs __iomem *)dev->base_addr;
 550                 u32 reg;
 551
 552                 reg = tc_readl(&tr->MAC_Ctl);
 553                 reg |= MAC_HaltReq;
 554                 tc_writel(reg, &tr->MAC_Ctl);
 555                 if (phydev->duplex == DUPLEX_FULL)
 556                         reg |= MAC_FullDup;
 557                 else
 558                         reg &= ~MAC_FullDup;
 559                 tc_writel(reg, &tr->MAC_Ctl);
 560                 reg &= ~MAC_HaltReq;
 561                 tc_writel(reg, &tr->MAC_Ctl);
 562
 563                 /*
 564                  * TX4939 PCFG.SPEEDn bit will be changed on
 565                  * NETDEV_CHANGE event.
 566                  */
 567                 /*
 568                  * WORKAROUND: enable LostCrS only if half duplex
 569                  * operation.
 570                  * (TX4939 does not have EnLCarr)
 571                  */
 572                 if (phydev->duplex == DUPLEX_HALF &&
 573                     lp->chiptype != TC35815_TX4939)
 574                         tc_writel(tc_readl(&tr->Tx_Ctl) | Tx_EnLCarr,
 575                                   &tr->Tx_Ctl);
 576
 577                 lp->speed = phydev->speed;
 578                 lp->duplex = phydev->duplex;
 579                 status_change = 1;
 580         }
 581
 582         if (phydev->link != lp->link) {
 583                 if (phydev->link) {
 584                         /* delayed promiscuous enabling */
 585                         if (dev->flags & IFF_PROMISC)
 586                                 tc35815_set_multicast_list(dev);
 587                 } else {
 588                         lp->speed = 0;
 589                         lp->duplex = -1;
 590                 }
 591                 lp->link = phydev->link;
 592
 593                 status_change = 1;
 594         }
 595         spin_unlock_irqrestore(&lp->lock, flags);
 596
 597         if (status_change && netif_msg_link(lp)) {
 598                 phy_print_status(phydev);
 599                 pr_debug("%s: MII BMCR %04x BMSR %04x LPA %04x\n",
 600                          dev->name,
 601                          phy_read(phydev, MII_BMCR),
 602                          phy_read(phydev, MII_BMSR),
 603                          phy_read(phydev, MII_LPA));
 604         }
 605 }
 606
 607 static int tc_mii_probe(struct net_device *dev)
 608 {
 609         struct tc35815_local *lp = netdev_priv(dev);
 610         struct phy_device *phydev;
 611         u32 dropmask;
 612
 613         phydev = phy_find_first(lp->mii_bus);
 614         if (!phydev) {
 615                 printk(KERN_ERR "%s: no PHY found\n", dev->name);
 616                 return -ENODEV;
 617         }
 618
 619         /* attach the mac to the phy */
 620         phydev = phy_connect(dev, phydev_name(phydev),
 621                              &tc_handle_link_change,
 622                              lp->chiptype == TC35815_TX4939 ? PHY_INTERFACE_MODE_RMII : PHY_INTERFACE_MODE_MII);
 623         if (IS_ERR(phydev)) {
 624                 printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
 625                 return PTR_ERR(phydev);
 626         }
 627
 628         phy_attached_info(phydev);
 629
 630         /* mask with MAC supported features */
 631         phydev->supported &= PHY_BASIC_FEATURES;
 632         dropmask = 0;
 633         if (options.speed == 10)
 634                 dropmask |= SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full;
 635         else if (options.speed == 100)
 636                 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full;
 637         if (options.duplex == 1)
 638                 dropmask |= SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full;
 639         else if (options.duplex == 2)
 640                 dropmask |= SUPPORTED_10baseT_Half | SUPPORTED_100baseT_Half;
 641         phydev->supported &= ~dropmask;
 642         phydev->advertising = phydev->supported;
 643
 644         lp->link = 0;
 645         lp->speed = 0;
 646         lp->duplex = -1;
 647
 648         return 0;
 649 }
 650
 651 static int tc_mii_init(struct net_device *dev)
 652 {
 653         struct tc35815_local *lp = netdev_priv(dev);
 654         int err;
 655
 656         lp->mii_bus = mdiobus_alloc();
 657         if (lp->mii_bus == NULL) {
 658                 err = -ENOMEM;
 659                 goto err_out;
 660         }
 661
 662         lp->mii_bus->name = "tc35815_mii_bus";
 663         lp->mii_bus->read = tc_mdio_read;
 664         lp->mii_bus->write = tc_mdio_write;
 665         snprintf(lp->mii_bus->id, MII_BUS_ID_SIZE, "%x",
 666                  (lp->pci_dev->bus->number << 8) | lp->pci_dev->devfn);
 667         lp->mii_bus->priv = dev;
 668         lp->mii_bus->parent = &lp->pci_dev->dev;
 669         err = mdiobus_register(lp->mii_bus);
 670         if (err)
 671                 goto err_out_free_mii_bus;
 672         err = tc_mii_probe(dev);
 673         if (err)
 674                 goto err_out_unregister_bus;
 675         return 0;
 676
 677 err_out_unregister_bus:
 678         mdiobus_unregister(lp->mii_bus);
 679 err_out_free_mii_bus:
 680         mdiobus_free(lp->mii_bus);
 681 err_out:
 682         return err;
 683 }
 684
 685 #ifdef CONFIG_CPU_TX49XX
 686 /*
 687  * Find a platform_device providing a MAC address.  The platform code
 688  * should provide a "tc35815-mac" device with a MAC address in its
 689  * platform_data.
 690  */
 691 static int tc35815_mac_match(struct device *dev, void *data)
 692 {
 693         struct platform_device *plat_dev = to_platform_device(dev);
 694         struct pci_dev *pci_dev = data;
 695         unsigned int id = pci_dev->irq;
 696         return !strcmp(plat_dev->name, "tc35815-mac") && plat_dev->id == id;
 697 }
 698
 699 static int tc35815_read_plat_dev_addr(struct net_device *dev)
 700 {
 701         struct tc35815_local *lp = netdev_priv(dev);
 702         struct device *pd = bus_find_device(&platform_bus_type, NULL,
 703                                             lp->pci_dev, tc35815_mac_match);
 704         if (pd) {
 705                 if (pd->platform_data)
 706                         memcpy(dev->dev_addr, pd->platform_data, ETH_ALEN);
 707                 put_device(pd);
 708                 return is_valid_ether_addr(dev->dev_addr) ? 0 : -ENODEV;
 709         }
 710         return -ENODEV;
 711 }
 712 #else
 713 static int tc35815_read_plat_dev_addr(struct net_device *dev)
 714 {
 715         return -ENODEV;
 716 }
 717 #endif
 718
 719 static int tc35815_init_dev_addr(struct net_device *dev)
 720 {
 721         struct tc35815_regs __iomem *tr =
 722                 (struct tc35815_regs __iomem *)dev->base_addr;
 723         int i;
 724
 725         while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
 726                 ;
 727         for (i = 0; i < 6; i += 2) {
 728                 unsigned short data;
 729                 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
 730                 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
 731                         ;
 732                 data = tc_readl(&tr->PROM_Data);
 733                 dev->dev_addr[i] = data & 0xff;
 734                 dev->dev_addr[i+1] = data >> 8;
 735         }
 736         if (!is_valid_ether_addr(dev->dev_addr))
 737                 return tc35815_read_plat_dev_addr(dev);
 738         return 0;
 739 }
 740
 741 static const struct net_device_ops tc35815_netdev_ops = {
 742         .ndo_open               = tc35815_open,
 743         .ndo_stop               = tc35815_close,
 744         .ndo_start_xmit         = tc35815_send_packet,
 745         .ndo_get_stats          = tc35815_get_stats,
 746         .ndo_set_rx_mode        = tc35815_set_multicast_list,
 747         .ndo_tx_timeout         = tc35815_tx_timeout,
 748         .ndo_do_ioctl           = tc35815_ioctl,
 749         .ndo_validate_addr      = eth_validate_addr,
 750         .ndo_set_mac_address    = eth_mac_addr,
 751 #ifdef CONFIG_NET_POLL_CONTROLLER
 752         .ndo_poll_controller    = tc35815_poll_controller,
 753 #endif
 754 };
 755
 756 static int tc35815_init_one(struct pci_dev *pdev,
 757                             const struct pci_device_id *ent)
 758 {
 759         void __iomem *ioaddr = NULL;
 760         struct net_device *dev;
 761         struct tc35815_local *lp;
 762         int rc;
 763
 764         static int printed_version;
 765         if (!printed_version++) {
 766                 printk(version);
 767                 dev_printk(KERN_DEBUG, &pdev->dev,
 768                            "speed:%d duplex:%d\n",
 769                            options.speed, options.duplex);
 770         }
 771
 772         if (!pdev->irq) {
 773                 dev_warn(&pdev->dev, "no IRQ assigned.\n");
 774                 return -ENODEV;
 775         }
 776
 777         /* dev zeroed in alloc_etherdev */
 778         dev = alloc_etherdev(sizeof(*lp));
 779         if (dev == NULL)
 780                 return -ENOMEM;
 781
 782         SET_NETDEV_DEV(dev, &pdev->dev);
 783         lp = netdev_priv(dev);
 784         lp->dev = dev;
 785
 786         /* enable device (incl. PCI PM wakeup), and bus-mastering */
 787         rc = pcim_enable_device(pdev);
 788         if (rc)
 789                 goto err_out;
 790         rc = pcim_iomap_regions(pdev, 1 << 1, MODNAME);
 791         if (rc)
 792                 goto err_out;
 793         pci_set_master(pdev);
 794         ioaddr = pcim_iomap_table(pdev)[1];
 795
 796         /* Initialize the device structure. */
 797         dev->netdev_ops = &tc35815_netdev_ops;
 798         dev->ethtool_ops = &tc35815_ethtool_ops;
 799         dev->watchdog_timeo = TC35815_TX_TIMEOUT;
 800         netif_napi_add(dev, &lp->napi, tc35815_poll, NAPI_WEIGHT);
 801
 802         dev->irq = pdev->irq;
 803         dev->base_addr = (unsigned long)ioaddr;
 804
 805         INIT_WORK(&lp->restart_work, tc35815_restart_work);
 806         spin_lock_init(&lp->lock);
 807         spin_lock_init(&lp->rx_lock);
 808         lp->pci_dev = pdev;
 809         lp->chiptype = ent->driver_data;
 810
 811         lp->msg_enable = NETIF_MSG_TX_ERR | NETIF_MSG_HW | NETIF_MSG_DRV | NETIF_MSG_LINK;
 812         pci_set_drvdata(pdev, dev);
 813
 814         /* Soft reset the chip. */
 815         tc35815_chip_reset(dev);
 816
 817         /* Retrieve the ethernet address. */
 818         if (tc35815_init_dev_addr(dev)) {
 819                 dev_warn(&pdev->dev, "not valid ether addr\n");
 820                 eth_hw_addr_random(dev);
 821         }
 822
 823         rc = register_netdev(dev);
 824         if (rc)
 825                 goto err_out;
 826
 827         printk(KERN_INFO "%s: %s at 0x%lx, %pM, IRQ %d\n",
 828                 dev->name,
 829                 chip_info[ent->driver_data].name,
 830                 dev->base_addr,
 831                 dev->dev_addr,
 832                 dev->irq);
 833
 834         rc = tc_mii_init(dev);
 835         if (rc)
 836                 goto err_out_unregister;
 837
 838         return 0;
 839
 840 err_out_unregister:
 841         unregister_netdev(dev);
 842 err_out:
 843         free_netdev(dev);
 844         return rc;
 845 }
 846
 847
 848 static void tc35815_remove_one(struct pci_dev *pdev)
 849 {
 850         struct net_device *dev = pci_get_drvdata(pdev);
 851         struct tc35815_local *lp = netdev_priv(dev);
 852
 853         phy_disconnect(dev->phydev);
 854         mdiobus_unregister(lp->mii_bus);
 855         mdiobus_free(lp->mii_bus);
 856         unregister_netdev(dev);
 857         free_netdev(dev);
 858 }
 859
 860 static int
 861 tc35815_init_queues(struct net_device *dev)
 862 {
 863         struct tc35815_local *lp = netdev_priv(dev);
 864         int i;
 865         unsigned long fd_addr;
 866
 867         if (!lp->fd_buf) {
 868                 BUG_ON(sizeof(struct FDesc) +
 869                        sizeof(struct BDesc) * RX_BUF_NUM +
 870                        sizeof(struct FDesc) * RX_FD_NUM +
 871                        sizeof(struct TxFD) * TX_FD_NUM >
 872                        PAGE_SIZE * FD_PAGE_NUM);
 873
 874                 lp->fd_buf = pci_alloc_consistent(lp->pci_dev,
 875                                                   PAGE_SIZE * FD_PAGE_NUM,
 876                                                   &lp->fd_buf_dma);
 877                 if (!lp->fd_buf)
 878                         return -ENOMEM;
 879                 for (i = 0; i < RX_BUF_NUM; i++) {
 880                         lp->rx_skbs[i].skb =
 881                                 alloc_rxbuf_skb(dev, lp->pci_dev,
 882                                                 &lp->rx_skbs[i].skb_dma);
 883                         if (!lp->rx_skbs[i].skb) {
 884                                 while (--i >= 0) {
 885                                         free_rxbuf_skb(lp->pci_dev,
 886                                                        lp->rx_skbs[i].skb,
 887                                                        lp->rx_skbs[i].skb_dma);
 888                                         lp->rx_skbs[i].skb = NULL;
 889                                 }
 890                                 pci_free_consistent(lp->pci_dev,
 891                                                     PAGE_SIZE * FD_PAGE_NUM,
 892                                                     lp->fd_buf,
 893                                                     lp->fd_buf_dma);
 894                                 lp->fd_buf = NULL;
 895                                 return -ENOMEM;
 896                         }
 897                 }
 898                 printk(KERN_DEBUG "%s: FD buf %p DataBuf",
 899                        dev->name, lp->fd_buf);
 900                 printk("\n");
 901         } else {
 902                 for (i = 0; i < FD_PAGE_NUM; i++)
 903                         clear_page((void *)((unsigned long)lp->fd_buf +
 904                                             i * PAGE_SIZE));
 905         }
 906         fd_addr = (unsigned long)lp->fd_buf;
 907
 908         /* Free Descriptors (for Receive) */
 909         lp->rfd_base = (struct RxFD *)fd_addr;
 910         fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
 911         for (i = 0; i < RX_FD_NUM; i++)
 912                 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
 913         lp->rfd_cur = lp->rfd_base;
 914         lp->rfd_limit = (struct RxFD *)fd_addr - (RX_FD_RESERVE + 1);
 915
 916         /* Transmit Descriptors */
 917         lp->tfd_base = (struct TxFD *)fd_addr;
 918         fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
 919         for (i = 0; i < TX_FD_NUM; i++) {
 920                 lp->tfd_base[i].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[i+1]));
 921                 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
 922                 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
 923         }
 924         lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, &lp->tfd_base[0]));
 925         lp->tfd_start = 0;
 926         lp->tfd_end = 0;
 927
 928         /* Buffer List (for Receive) */
 929         lp->fbl_ptr = (struct FrFD *)fd_addr;
 930         lp->fbl_ptr->fd.FDNext = cpu_to_le32(fd_virt_to_bus(lp, lp->fbl_ptr));
 931         lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_NUM | FD_CownsFD);
 932         /*
 933          * move all allocated skbs to head of rx_skbs[] array.
 934          * fbl_count mighe not be RX_BUF_NUM if alloc_rxbuf_skb() in
 935          * tc35815_rx() had failed.
 936          */
 937         lp->fbl_count = 0;
 938         for (i = 0; i < RX_BUF_NUM; i++) {
 939                 if (lp->rx_skbs[i].skb) {
 940                         if (i != lp->fbl_count) {
 941                                 lp->rx_skbs[lp->fbl_count].skb =
 942                                         lp->rx_skbs[i].skb;
 943                                 lp->rx_skbs[lp->fbl_count].skb_dma =
 944                                         lp->rx_skbs[i].skb_dma;
 945                         }
 946                         lp->fbl_count++;
 947                 }
 948         }
 949         for (i = 0; i < RX_BUF_NUM; i++) {
 950                 if (i >= lp->fbl_count) {
 951                         lp->fbl_ptr->bd[i].BuffData = 0;
 952                         lp->fbl_ptr->bd[i].BDCtl = 0;
 953                         continue;
 954                 }
 955                 lp->fbl_ptr->bd[i].BuffData =
 956                         cpu_to_le32(lp->rx_skbs[i].skb_dma);
 957                 /* BDID is index of FrFD.bd[] */
 958                 lp->fbl_ptr->bd[i].BDCtl =
 959                         cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) |
 960                                     RX_BUF_SIZE);
 961         }
 962
 963         printk(KERN_DEBUG "%s: TxFD %p RxFD %p FrFD %p\n",
 964                dev->name, lp->tfd_base, lp->rfd_base, lp->fbl_ptr);
 965         return 0;
 966 }
 967
 968 static void
 969 tc35815_clear_queues(struct net_device *dev)
 970 {
 971         struct tc35815_local *lp = netdev_priv(dev);
 972         int i;
 973
 974         for (i = 0; i < TX_FD_NUM; i++) {
 975                 u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
 976                 struct sk_buff *skb =
 977                         fdsystem != 0xffffffff ?
 978                         lp->tx_skbs[fdsystem].skb : NULL;
 979 #ifdef DEBUG
 980                 if (lp->tx_skbs[i].skb != skb) {
 981                         printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
 982                         panic_queues(dev);
 983                 }
 984 #else
 985                 BUG_ON(lp->tx_skbs[i].skb != skb);
 986 #endif
 987                 if (skb) {
 988                         pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
 989                         lp->tx_skbs[i].skb = NULL;
 990                         lp->tx_skbs[i].skb_dma = 0;
 991                         dev_kfree_skb_any(skb);
 992                 }
 993                 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
 994         }
 995
 996         tc35815_init_queues(dev);
 997 }
 998
 999 static void
1000 tc35815_free_queues(struct net_device *dev)
1001 {
1002         struct tc35815_local *lp = netdev_priv(dev);
1003         int i;
1004
1005         if (lp->tfd_base) {
1006                 for (i = 0; i < TX_FD_NUM; i++) {
1007                         u32 fdsystem = le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
1008                         struct sk_buff *skb =
1009                                 fdsystem != 0xffffffff ?
1010                                 lp->tx_skbs[fdsystem].skb : NULL;
1011 #ifdef DEBUG
1012                         if (lp->tx_skbs[i].skb != skb) {
1013                                 printk("%s: tx_skbs mismatch(%d).\n", dev->name, i);
1014                                 panic_queues(dev);
1015                         }
1016 #else
1017                         BUG_ON(lp->tx_skbs[i].skb != skb);
1018 #endif
1019                         if (skb) {
1020                                 pci_unmap_single(lp->pci_dev, lp->tx_skbs[i].skb_dma, skb->len, PCI_DMA_TODEVICE);
1021                                 dev_kfree_skb(skb);
1022                                 lp->tx_skbs[i].skb = NULL;
1023                                 lp->tx_skbs[i].skb_dma = 0;
1024                         }
1025                         lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0xffffffff);
1026                 }
1027         }
1028
1029         lp->rfd_base = NULL;
1030         lp->rfd_limit = NULL;
1031         lp->rfd_cur = NULL;
1032         lp->fbl_ptr = NULL;
1033
1034         for (i = 0; i < RX_BUF_NUM; i++) {
1035                 if (lp->rx_skbs[i].skb) {
1036                         free_rxbuf_skb(lp->pci_dev, lp->rx_skbs[i].skb,
1037                                        lp->rx_skbs[i].skb_dma);
1038                         lp->rx_skbs[i].skb = NULL;
1039                 }
1040         }
1041         if (lp->fd_buf) {
1042                 pci_free_consistent(lp->pci_dev, PAGE_SIZE * FD_PAGE_NUM,
1043                                     lp->fd_buf, lp->fd_buf_dma);
1044                 lp->fd_buf = NULL;
1045         }
1046 }
1047
1048 static void
1049 dump_txfd(struct TxFD *fd)
1050 {
1051         printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
1052                le32_to_cpu(fd->fd.FDNext),
1053                le32_to_cpu(fd->fd.FDSystem),
1054                le32_to_cpu(fd->fd.FDStat),
1055                le32_to_cpu(fd->fd.FDCtl));
1056         printk("BD: ");
1057         printk(" %08x %08x",
1058                le32_to_cpu(fd->bd.BuffData),
1059                le32_to_cpu(fd->bd.BDCtl));
1060         printk("\n");
1061 }
1062
1063 static int
1064 dump_rxfd(struct RxFD *fd)
1065 {
1066         int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1067         if (bd_count > 8)
1068                 bd_count = 8;
1069         printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
1070                le32_to_cpu(fd->fd.FDNext),
1071                le32_to_cpu(fd->fd.FDSystem),
1072                le32_to_cpu(fd->fd.FDStat),
1073                le32_to_cpu(fd->fd.FDCtl));
1074         if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
1075                 return 0;
1076         printk("BD: ");
1077         for (i = 0; i < bd_count; i++)
1078                 printk(" %08x %08x",
1079                        le32_to_cpu(fd->bd[i].BuffData),
1080                        le32_to_cpu(fd->bd[i].BDCtl));
1081         printk("\n");
1082         return bd_count;
1083 }
1084
1085 #ifdef DEBUG
1086 static void
1087 dump_frfd(struct FrFD *fd)
1088 {
1089         int i;
1090         printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
1091                le32_to_cpu(fd->fd.FDNext),
1092                le32_to_cpu(fd->fd.FDSystem),
1093                le32_to_cpu(fd->fd.FDStat),
1094                le32_to_cpu(fd->fd.FDCtl));
1095         printk("BD: ");
1096         for (i = 0; i < RX_BUF_NUM; i++)
1097                 printk(" %08x %08x",
1098                        le32_to_cpu(fd->bd[i].BuffData),
1099                        le32_to_cpu(fd->bd[i].BDCtl));
1100         printk("\n");
1101 }
1102
1103 static void
1104 panic_queues(struct net_device *dev)
1105 {
1106         struct tc35815_local *lp = netdev_priv(dev);
1107         int i;
1108
1109         printk("TxFD base %p, start %u, end %u\n",
1110                lp->tfd_base, lp->tfd_start, lp->tfd_end);
1111         printk("RxFD base %p limit %p cur %p\n",
1112                lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
1113         printk("FrFD %p\n", lp->fbl_ptr);
1114         for (i = 0; i < TX_FD_NUM; i++)
1115                 dump_txfd(&lp->tfd_base[i]);
1116         for (i = 0; i < RX_FD_NUM; i++) {
1117                 int bd_count = dump_rxfd(&lp->rfd_base[i]);
1118                 i += (bd_count + 1) / 2;        /* skip BDs */
1119         }
1120         dump_frfd(lp->fbl_ptr);
1121         panic("%s: Illegal queue state.", dev->name);
1122 }
1123 #endif
1124
1125 static void print_eth(const u8 *add)
1126 {
1127         printk(KERN_DEBUG "print_eth(%p)\n", add);
1128         printk(KERN_DEBUG " %pM => %pM : %02x%02x\n",
1129                 add + 6, add, add[12], add[13]);
1130 }
1131
1132 static int tc35815_tx_full(struct net_device *dev)
1133 {
1134         struct tc35815_local *lp = netdev_priv(dev);
1135         return (lp->tfd_start + 1) % TX_FD_NUM == lp->tfd_end;
1136 }
1137
1138 static void tc35815_restart(struct net_device *dev)
1139 {
1140         struct tc35815_local *lp = netdev_priv(dev);
1141         int ret;
1142
1143         if (dev->phydev) {
1144                 ret = phy_init_hw(dev->phydev);
1145                 if (ret)
1146                         printk(KERN_ERR "%s: PHY init failed.\n", dev->name);
1147         }
1148
1149         spin_lock_bh(&lp->rx_lock);
1150         spin_lock_irq(&lp->lock);
1151         tc35815_chip_reset(dev);
1152         tc35815_clear_queues(dev);
1153         tc35815_chip_init(dev);
1154         /* Reconfigure CAM again since tc35815_chip_init() initialize it. */
1155         tc35815_set_multicast_list(dev);
1156         spin_unlock_irq(&lp->lock);
1157         spin_unlock_bh(&lp->rx_lock);
1158
1159         netif_wake_queue(dev);
1160 }
1161
1162 static void tc35815_restart_work(struct work_struct *work)
1163 {
1164         struct tc35815_local *lp =
1165                 container_of(work, struct tc35815_local, restart_work);
1166         struct net_device *dev = lp->dev;
1167
1168         tc35815_restart(dev);
1169 }
1170
1171 static void tc35815_schedule_restart(struct net_device *dev)
1172 {
1173         struct tc35815_local *lp = netdev_priv(dev);
1174         struct tc35815_regs __iomem *tr =
1175                 (struct tc35815_regs __iomem *)dev->base_addr;
1176         unsigned long flags;
1177
1178         /* disable interrupts */
1179         spin_lock_irqsave(&lp->lock, flags);
1180         tc_writel(0, &tr->Int_En);
1181         tc_writel(tc_readl(&tr->DMA_Ctl) | DMA_IntMask, &tr->DMA_Ctl);
1182         schedule_work(&lp->restart_work);
1183         spin_unlock_irqrestore(&lp->lock, flags);
1184 }
1185
1186 static void tc35815_tx_timeout(struct net_device *dev)
1187 {
1188         struct tc35815_regs __iomem *tr =
1189                 (struct tc35815_regs __iomem *)dev->base_addr;
1190
1191         printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
1192                dev->name, tc_readl(&tr->Tx_Stat));
1193
1194         /* Try to restart the adaptor. */
1195         tc35815_schedule_restart(dev);
1196         dev->stats.tx_errors++;
1197 }
1198
1199 /*
1200  * Open/initialize the controller. This is called (in the current kernel)
1201  * sometime after booting when the 'ifconfig' program is run.
1202  *
1203  * This routine should set everything up anew at each open, even
1204  * registers that "should" only need to be set once at boot, so that
1205  * there is non-reboot way to recover if something goes wrong.
1206  */
1207 static int
1208 tc35815_open(struct net_device *dev)
1209 {
1210         struct tc35815_local *lp = netdev_priv(dev);
1211
1212         /*
1213          * This is used if the interrupt line can turned off (shared).
1214          * See 3c503.c for an example of selecting the IRQ at config-time.
1215          */
1216         if (request_irq(dev->irq, tc35815_interrupt, IRQF_SHARED,
1217                         dev->name, dev))
1218                 return -EAGAIN;
1219
1220         tc35815_chip_reset(dev);
1221
1222         if (tc35815_init_queues(dev) != 0) {
1223                 free_irq(dev->irq, dev);
1224                 return -EAGAIN;
1225         }
1226
1227         napi_enable(&lp->napi);
1228
1229         /* Reset the hardware here. Don't forget to set the station address. */
1230         spin_lock_irq(&lp->lock);
1231         tc35815_chip_init(dev);
1232         spin_unlock_irq(&lp->lock);
1233
1234         netif_carrier_off(dev);
1235         /* schedule a link state check */
1236         phy_start(dev->phydev);
1237
1238         /* We are now ready to accept transmit requeusts from
1239          * the queueing layer of the networking.
1240          */
1241         netif_start_queue(dev);
1242
1243         return 0;
1244 }
1245
1246 /* This will only be invoked if your driver is _not_ in XOFF state.
1247  * What this means is that you need not check it, and that this
1248  * invariant will hold if you make sure that the netif_*_queue()
1249  * calls are done at the proper times.
1250  */
1251 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
1252 {
1253         struct tc35815_local *lp = netdev_priv(dev);
1254         struct TxFD *txfd;
1255         unsigned long flags;
1256
1257         /* If some error occurs while trying to transmit this
1258          * packet, you should return '1' from this function.
1259          * In such a case you _may not_ do anything to the
1260          * SKB, it is still owned by the network queueing
1261          * layer when an error is returned.  This means you
1262          * may not modify any SKB fields, you may not free
1263          * the SKB, etc.
1264          */
1265
1266         /* This is the most common case for modern hardware.
1267          * The spinlock protects this code from the TX complete
1268          * hardware interrupt handler.  Queue flow control is
1269          * thus managed under this lock as well.
1270          */
1271         spin_lock_irqsave(&lp->lock, flags);
1272
1273         /* failsafe... (handle txdone now if half of FDs are used) */
1274         if ((lp->tfd_start + TX_FD_NUM - lp->tfd_end) % TX_FD_NUM >
1275             TX_FD_NUM / 2)
1276                 tc35815_txdone(dev);
1277
1278         if (netif_msg_pktdata(lp))
1279                 print_eth(skb->data);
1280 #ifdef DEBUG
1281         if (lp->tx_skbs[lp->tfd_start].skb) {
1282                 printk("%s: tx_skbs conflict.\n", dev->name);
1283                 panic_queues(dev);
1284         }
1285 #else
1286         BUG_ON(lp->tx_skbs[lp->tfd_start].skb);
1287 #endif
1288         lp->tx_skbs[lp->tfd_start].skb = skb;
1289         lp->tx_skbs[lp->tfd_start].skb_dma = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1290
1291         /*add to ring */
1292         txfd = &lp->tfd_base[lp->tfd_start];
1293         txfd->bd.BuffData = cpu_to_le32(lp->tx_skbs[lp->tfd_start].skb_dma);
1294         txfd->bd.BDCtl = cpu_to_le32(skb->len);
1295         txfd->fd.FDSystem = cpu_to_le32(lp->tfd_start);
1296         txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
1297
1298         if (lp->tfd_start == lp->tfd_end) {
1299                 struct tc35815_regs __iomem *tr =
1300                         (struct tc35815_regs __iomem *)dev->base_addr;
1301                 /* Start DMA Transmitter. */
1302                 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1303                 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1304                 if (netif_msg_tx_queued(lp)) {
1305                         printk("%s: starting TxFD.\n", dev->name);
1306                         dump_txfd(txfd);
1307                 }
1308                 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1309         } else {
1310                 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1311                 if (netif_msg_tx_queued(lp)) {
1312                         printk("%s: queueing TxFD.\n", dev->name);
1313                         dump_txfd(txfd);
1314                 }
1315         }
1316         lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1317
1318         /* If we just used up the very last entry in the
1319          * TX ring on this device, tell the queueing
1320          * layer to send no more.
1321          */
1322         if (tc35815_tx_full(dev)) {
1323                 if (netif_msg_tx_queued(lp))
1324                         printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1325                 netif_stop_queue(dev);
1326         }
1327
1328         /* When the TX completion hw interrupt arrives, this
1329          * is when the transmit statistics are updated.
1330          */
1331
1332         spin_unlock_irqrestore(&lp->lock, flags);
1333         return NETDEV_TX_OK;
1334 }
1335
1336 #define FATAL_ERROR_INT \
1337         (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1338 static void tc35815_fatal_error_interrupt(struct net_device *dev, u32 status)
1339 {
1340         static int count;
1341         printk(KERN_WARNING "%s: Fatal Error Interrupt (%#x):",
1342                dev->name, status);
1343         if (status & Int_IntPCI)
1344                 printk(" IntPCI");
1345         if (status & Int_DmParErr)
1346                 printk(" DmParErr");
1347         if (status & Int_IntNRAbt)
1348                 printk(" IntNRAbt");
1349         printk("\n");
1350         if (count++ > 100)
1351                 panic("%s: Too many fatal errors.", dev->name);
1352         printk(KERN_WARNING "%s: Resetting ...\n", dev->name);
1353         /* Try to restart the adaptor. */
1354         tc35815_schedule_restart(dev);
1355 }
1356
1357 static int tc35815_do_interrupt(struct net_device *dev, u32 status, int limit)
1358 {
1359         struct tc35815_local *lp = netdev_priv(dev);
1360         int ret = -1;
1361
1362         /* Fatal errors... */
1363         if (status & FATAL_ERROR_INT) {
1364                 tc35815_fatal_error_interrupt(dev, status);
1365                 return 0;
1366         }
1367         /* recoverable errors */
1368         if (status & Int_IntFDAEx) {
1369                 if (netif_msg_rx_err(lp))
1370                         dev_warn(&dev->dev,
1371                                  "Free Descriptor Area Exhausted (%#x).\n",
1372                                  status);
1373                 dev->stats.rx_dropped++;
1374                 ret = 0;
1375         }
1376         if (status & Int_IntBLEx) {
1377                 if (netif_msg_rx_err(lp))
1378                         dev_warn(&dev->dev,
1379                                  "Buffer List Exhausted (%#x).\n",
1380                                  status);
1381                 dev->stats.rx_dropped++;
1382                 ret = 0;
1383         }
1384         if (status & Int_IntExBD) {
1385                 if (netif_msg_rx_err(lp))
1386                         dev_warn(&dev->dev,
1387                                  "Excessive Buffer Descriptors (%#x).\n",
1388                                  status);
1389                 dev->stats.rx_length_errors++;
1390                 ret = 0;
1391         }
1392
1393         /* normal notification */
1394         if (status & Int_IntMacRx) {
1395                 /* Got a packet(s). */
1396                 ret = tc35815_rx(dev, limit);
1397                 lp->lstats.rx_ints++;
1398         }
1399         if (status & Int_IntMacTx) {
1400                 /* Transmit complete. */
1401                 lp->lstats.tx_ints++;
1402                 spin_lock_irq(&lp->lock);
1403                 tc35815_txdone(dev);
1404                 spin_unlock_irq(&lp->lock);
1405                 if (ret < 0)
1406                         ret = 0;
1407         }
1408         return ret;
1409 }
1410
1411 /*
1412  * The typical workload of the driver:
1413  * Handle the network interface interrupts.
1414  */
1415 static irqreturn_t tc35815_interrupt(int irq, void *dev_id)
1416 {
1417         struct net_device *dev = dev_id;
1418         struct tc35815_local *lp = netdev_priv(dev);
1419         struct tc35815_regs __iomem *tr =
1420                 (struct tc35815_regs __iomem *)dev->base_addr;
1421         u32 dmactl = tc_readl(&tr->DMA_Ctl);
1422
1423         if (!(dmactl & DMA_IntMask)) {
1424                 /* disable interrupts */
1425                 tc_writel(dmactl | DMA_IntMask, &tr->DMA_Ctl);
1426                 if (napi_schedule_prep(&lp->napi))
1427                         __napi_schedule(&lp->napi);
1428                 else {
1429                         printk(KERN_ERR "%s: interrupt taken in poll\n",
1430                                dev->name);
1431                         BUG();
1432                 }
1433                 (void)tc_readl(&tr->Int_Src);   /* flush */
1434                 return IRQ_HANDLED;
1435         }
1436         return IRQ_NONE;
1437 }
1438
1439 #ifdef CONFIG_NET_POLL_CONTROLLER
1440 static void tc35815_poll_controller(struct net_device *dev)
1441 {
1442         disable_irq(dev->irq);
1443         tc35815_interrupt(dev->irq, dev);
1444         enable_irq(dev->irq);
1445 }
1446 #endif
1447
1448 /* We have a good packet(s), get it/them out of the buffers. */
1449 static int
1450 tc35815_rx(struct net_device *dev, int limit)
1451 {
1452         struct tc35815_local *lp = netdev_priv(dev);
1453         unsigned int fdctl;
1454         int i;
1455         int received = 0;
1456
1457         while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1458                 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1459                 int pkt_len = fdctl & FD_FDLength_MASK;
1460                 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1461 #ifdef DEBUG
1462                 struct RxFD *next_rfd;
1463 #endif
1464 #if (RX_CTL_CMD & Rx_StripCRC) == 0
1465                 pkt_len -= ETH_FCS_LEN;
1466 #endif
1467
1468                 if (netif_msg_rx_status(lp))
1469                         dump_rxfd(lp->rfd_cur);
1470                 if (status & Rx_Good) {
1471                         struct sk_buff *skb;
1472                         unsigned char *data;
1473                         int cur_bd;
1474
1475                         if (--limit < 0)
1476                                 break;
1477                         BUG_ON(bd_count > 1);
1478                         cur_bd = (le32_to_cpu(lp->rfd_cur->bd[0].BDCtl)
1479                                   & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1480 #ifdef DEBUG
1481                         if (cur_bd >= RX_BUF_NUM) {
1482                                 printk("%s: invalid BDID.\n", dev->name);
1483                                 panic_queues(dev);
1484                         }
1485                         BUG_ON(lp->rx_skbs[cur_bd].skb_dma !=
1486                                (le32_to_cpu(lp->rfd_cur->bd[0].BuffData) & ~3));
1487                         if (!lp->rx_skbs[cur_bd].skb) {
1488                                 printk("%s: NULL skb.\n", dev->name);
1489                                 panic_queues(dev);
1490                         }
1491 #else
1492                         BUG_ON(cur_bd >= RX_BUF_NUM);
1493 #endif
1494                         skb = lp->rx_skbs[cur_bd].skb;
1495                         prefetch(skb->data);
1496                         lp->rx_skbs[cur_bd].skb = NULL;
1497                         pci_unmap_single(lp->pci_dev,
1498                                          lp->rx_skbs[cur_bd].skb_dma,
1499                                          RX_BUF_SIZE, PCI_DMA_FROMDEVICE);
1500                         if (!HAVE_DMA_RXALIGN(lp) && NET_IP_ALIGN)
1501                                 memmove(skb->data, skb->data - NET_IP_ALIGN,
1502                                         pkt_len);
1503                         data = skb_put(skb, pkt_len);
1504                         if (netif_msg_pktdata(lp))
1505                                 print_eth(data);
1506                         skb->protocol = eth_type_trans(skb, dev);
1507                         netif_receive_skb(skb);
1508                         received++;
1509                         dev->stats.rx_packets++;
1510                         dev->stats.rx_bytes += pkt_len;
1511                 } else {
1512                         dev->stats.rx_errors++;
1513                         if (netif_msg_rx_err(lp))
1514                                 dev_info(&dev->dev, "Rx error (status %x)\n",
1515                                          status & Rx_Stat_Mask);
1516                         /* WORKAROUND: LongErr and CRCErr means Overflow. */
1517                         if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1518                                 status &= ~(Rx_LongErr|Rx_CRCErr);
1519                                 status |= Rx_Over;
1520                         }
1521                         if (status & Rx_LongErr)
1522                                 dev->stats.rx_length_errors++;
1523                         if (status & Rx_Over)
1524                                 dev->stats.rx_fifo_errors++;
1525                         if (status & Rx_CRCErr)
1526                                 dev->stats.rx_crc_errors++;
1527                         if (status & Rx_Align)
1528                                 dev->stats.rx_frame_errors++;
1529                 }
1530
1531                 if (bd_count > 0) {
1532                         /* put Free Buffer back to controller */
1533                         int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1534                         unsigned char id =
1535                                 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1536 #ifdef DEBUG
1537                         if (id >= RX_BUF_NUM) {
1538                                 printk("%s: invalid BDID.\n", dev->name);
1539                                 panic_queues(dev);
1540                         }
1541 #else
1542                         BUG_ON(id >= RX_BUF_NUM);
1543 #endif
1544                         /* free old buffers */
1545                         lp->fbl_count--;
1546                         while (lp->fbl_count < RX_BUF_NUM)
1547                         {
1548                                 unsigned char curid =
1549                                         (id + 1 + lp->fbl_count) % RX_BUF_NUM;
1550                                 struct BDesc *bd = &lp->fbl_ptr->bd[curid];
1551 #ifdef DEBUG
1552                                 bdctl = le32_to_cpu(bd->BDCtl);
1553                                 if (bdctl & BD_CownsBD) {
1554                                         printk("%s: Freeing invalid BD.\n",
1555                                                dev->name);
1556                                         panic_queues(dev);
1557                                 }
1558 #endif
1559                                 /* pass BD to controller */
1560                                 if (!lp->rx_skbs[curid].skb) {
1561                                         lp->rx_skbs[curid].skb =
1562                                                 alloc_rxbuf_skb(dev,
1563                                                                 lp->pci_dev,
1564                                                                 &lp->rx_skbs[curid].skb_dma);
1565                                         if (!lp->rx_skbs[curid].skb)
1566                                                 break; /* try on next reception */
1567                                         bd->BuffData = cpu_to_le32(lp->rx_skbs[curid].skb_dma);
1568                                 }
1569                                 /* Note: BDLength was modified by chip. */
1570                                 bd->BDCtl = cpu_to_le32(BD_CownsBD |
1571                                                         (curid << BD_RxBDID_SHIFT) |
1572                                                         RX_BUF_SIZE);
1573                                 lp->fbl_count++;
1574                         }
1575                 }
1576
1577                 /* put RxFD back to controller */
1578 #ifdef DEBUG
1579                 next_rfd = fd_bus_to_virt(lp,
1580                                           le32_to_cpu(lp->rfd_cur->fd.FDNext));
1581                 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1582                         printk("%s: RxFD FDNext invalid.\n", dev->name);
1583                         panic_queues(dev);
1584                 }
1585 #endif
1586                 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1587                         /* pass FD to controller */
1588 #ifdef DEBUG
1589                         lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead);
1590 #else
1591                         lp->rfd_cur->fd.FDNext = cpu_to_le32(FD_Next_EOL);
1592 #endif
1593                         lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1594                         lp->rfd_cur++;
1595                 }
1596                 if (lp->rfd_cur > lp->rfd_limit)
1597                         lp->rfd_cur = lp->rfd_base;
1598 #ifdef DEBUG
1599                 if (lp->rfd_cur != next_rfd)
1600                         printk("rfd_cur = %p, next_rfd %p\n",
1601                                lp->rfd_cur, next_rfd);
1602 #endif
1603         }
1604
1605         return received;
1606 }
1607
1608 static int tc35815_poll(struct napi_struct *napi, int budget)
1609 {
1610         struct tc35815_local *lp = container_of(napi, struct tc35815_local, napi);
1611         struct net_device *dev = lp->dev;
1612         struct tc35815_regs __iomem *tr =
1613                 (struct tc35815_regs __iomem *)dev->base_addr;
1614         int received = 0, handled;
1615         u32 status;
1616
1617         if (budget <= 0)
1618                 return received;
1619
1620         spin_lock(&lp->rx_lock);
1621         status = tc_readl(&tr->Int_Src);
1622         do {
1623                 /* BLEx, FDAEx will be cleared later */
1624                 tc_writel(status & ~(Int_BLEx | Int_FDAEx),
1625                           &tr->Int_Src);        /* write to clear */
1626
1627                 handled = tc35815_do_interrupt(dev, status, budget - received);
1628                 if (status & (Int_BLEx | Int_FDAEx))
1629                         tc_writel(status & (Int_BLEx | Int_FDAEx),
1630                                   &tr->Int_Src);
1631                 if (handled >= 0) {
1632                         received += handled;
1633                         if (received >= budget)
1634                                 break;
1635                 }
1636                 status = tc_readl(&tr->Int_Src);
1637         } while (status);
1638         spin_unlock(&lp->rx_lock);
1639
1640         if (received < budget) {
1641                 napi_complete_done(napi, received);
1642                 /* enable interrupts */
1643                 tc_writel(tc_readl(&tr->DMA_Ctl) & ~DMA_IntMask, &tr->DMA_Ctl);
1644         }
1645         return received;
1646 }
1647
1648 #define TX_STA_ERR      (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1649
1650 static void
1651 tc35815_check_tx_stat(struct net_device *dev, int status)
1652 {
1653         struct tc35815_local *lp = netdev_priv(dev);
1654         const char *msg = NULL;
1655
1656         /* count collisions */
1657         if (status & Tx_ExColl)
1658                 dev->stats.collisions += 16;
1659         if (status & Tx_TxColl_MASK)
1660                 dev->stats.collisions += status & Tx_TxColl_MASK;
1661
1662         /* TX4939 does not have NCarr */
1663         if (lp->chiptype == TC35815_TX4939)
1664                 status &= ~Tx_NCarr;
1665         /* WORKAROUND: ignore LostCrS in full duplex operation */
1666         if (!lp->link || lp->duplex == DUPLEX_FULL)
1667                 status &= ~Tx_NCarr;
1668
1669         if (!(status & TX_STA_ERR)) {
1670                 /* no error. */
1671                 dev->stats.tx_packets++;
1672                 return;
1673         }
1674
1675         dev->stats.tx_errors++;
1676         if (status & Tx_ExColl) {
1677                 dev->stats.tx_aborted_errors++;
1678                 msg = "Excessive Collision.";
1679         }
1680         if (status & Tx_Under) {
1681                 dev->stats.tx_fifo_errors++;
1682                 msg = "Tx FIFO Underrun.";
1683                 if (lp->lstats.tx_underrun < TX_THRESHOLD_KEEP_LIMIT) {
1684                         lp->lstats.tx_underrun++;
1685                         if (lp->lstats.tx_underrun >= TX_THRESHOLD_KEEP_LIMIT) {
1686                                 struct tc35815_regs __iomem *tr =
1687                                         (struct tc35815_regs __iomem *)dev->base_addr;
1688                                 tc_writel(TX_THRESHOLD_MAX, &tr->TxThrsh);
1689                                 msg = "Tx FIFO Underrun.Change Tx threshold to max.";
1690                         }
1691                 }
1692         }
1693         if (status & Tx_Defer) {
1694                 dev->stats.tx_fifo_errors++;
1695                 msg = "Excessive Deferral.";
1696         }
1697         if (status & Tx_NCarr) {
1698                 dev->stats.tx_carrier_errors++;
1699                 msg = "Lost Carrier Sense.";
1700         }
1701         if (status & Tx_LateColl) {
1702                 dev->stats.tx_aborted_errors++;
1703                 msg = "Late Collision.";
1704         }
1705         if (status & Tx_TxPar) {
1706                 dev->stats.tx_fifo_errors++;
1707                 msg = "Transmit Parity Error.";
1708         }
1709         if (status & Tx_SQErr) {
1710                 dev->stats.tx_heartbeat_errors++;
1711                 msg = "Signal Quality Error.";
1712         }
1713         if (msg && netif_msg_tx_err(lp))
1714                 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1715 }
1716
1717 /* This handles TX complete events posted by the device
1718  * via interrupts.
1719  */
1720 static void
1721 tc35815_txdone(struct net_device *dev)
1722 {
1723         struct tc35815_local *lp = netdev_priv(dev);
1724         struct TxFD *txfd;
1725         unsigned int fdctl;
1726
1727         txfd = &lp->tfd_base[lp->tfd_end];
1728         while (lp->tfd_start != lp->tfd_end &&
1729                !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1730                 int status = le32_to_cpu(txfd->fd.FDStat);
1731                 struct sk_buff *skb;
1732                 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1733                 u32 fdsystem = le32_to_cpu(txfd->fd.FDSystem);
1734
1735                 if (netif_msg_tx_done(lp)) {
1736                         printk("%s: complete TxFD.\n", dev->name);
1737                         dump_txfd(txfd);
1738                 }
1739                 tc35815_check_tx_stat(dev, status);
1740
1741                 skb = fdsystem != 0xffffffff ?
1742                         lp->tx_skbs[fdsystem].skb : NULL;
1743 #ifdef DEBUG
1744                 if (lp->tx_skbs[lp->tfd_end].skb != skb) {
1745                         printk("%s: tx_skbs mismatch.\n", dev->name);
1746                         panic_queues(dev);
1747                 }
1748 #else
1749                 BUG_ON(lp->tx_skbs[lp->tfd_end].skb != skb);
1750 #endif
1751                 if (skb) {
1752                         dev->stats.tx_bytes += skb->len;
1753                         pci_unmap_single(lp->pci_dev, lp->tx_skbs[lp->tfd_end].skb_dma, skb->len, PCI_DMA_TODEVICE);
1754                         lp->tx_skbs[lp->tfd_end].skb = NULL;
1755                         lp->tx_skbs[lp->tfd_end].skb_dma = 0;
1756                         dev_kfree_skb_any(skb);
1757                 }
1758                 txfd->fd.FDSystem = cpu_to_le32(0xffffffff);
1759
1760                 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1761                 txfd = &lp->tfd_base[lp->tfd_end];
1762 #ifdef DEBUG
1763                 if ((fdnext & ~FD_Next_EOL) != fd_virt_to_bus(lp, txfd)) {
1764                         printk("%s: TxFD FDNext invalid.\n", dev->name);
1765                         panic_queues(dev);
1766                 }
1767 #endif
1768                 if (fdnext & FD_Next_EOL) {
1769                         /* DMA Transmitter has been stopping... */
1770                         if (lp->tfd_end != lp->tfd_start) {
1771                                 struct tc35815_regs __iomem *tr =
1772                                         (struct tc35815_regs __iomem *)dev->base_addr;
1773                                 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1774                                 struct TxFD *txhead = &lp->tfd_base[head];
1775                                 int qlen = (lp->tfd_start + TX_FD_NUM
1776                                             - lp->tfd_end) % TX_FD_NUM;
1777
1778 #ifdef DEBUG
1779                                 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1780                                         printk("%s: TxFD FDCtl invalid.\n", dev->name);
1781                                         panic_queues(dev);
1782                                 }
1783 #endif
1784                                 /* log max queue length */
1785                                 if (lp->lstats.max_tx_qlen < qlen)
1786                                         lp->lstats.max_tx_qlen = qlen;
1787
1788
1789                                 /* start DMA Transmitter again */
1790                                 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1791                                 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1792                                 if (netif_msg_tx_queued(lp)) {
1793                                         printk("%s: start TxFD on queue.\n",
1794                                                dev->name);
1795                                         dump_txfd(txfd);
1796                                 }
1797                                 tc_writel(fd_virt_to_bus(lp, txfd), &tr->TxFrmPtr);
1798                         }
1799                         break;
1800                 }
1801         }
1802
1803         /* If we had stopped the queue due to a "tx full"
1804          * condition, and space has now been made available,
1805          * wake up the queue.
1806          */
1807         if (netif_queue_stopped(dev) && !tc35815_tx_full(dev))
1808                 netif_wake_queue(dev);
1809 }
1810
1811 /* The inverse routine to tc35815_open(). */
1812 static int
1813 tc35815_close(struct net_device *dev)
1814 {
1815         struct tc35815_local *lp = netdev_priv(dev);
1816
1817         netif_stop_queue(dev);
1818         napi_disable(&lp->napi);
1819         if (dev->phydev)
1820                 phy_stop(dev->phydev);
1821         cancel_work_sync(&lp->restart_work);
1822
1823         /* Flush the Tx and disable Rx here. */
1824         tc35815_chip_reset(dev);
1825         free_irq(dev->irq, dev);
1826
1827         tc35815_free_queues(dev);
1828
1829         return 0;
1830
1831 }
1832
1833 /*
1834  * Get the current statistics.
1835  * This may be called with the card open or closed.
1836  */
1837 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1838 {
1839         struct tc35815_regs __iomem *tr =
1840                 (struct tc35815_regs __iomem *)dev->base_addr;
1841         if (netif_running(dev))
1842                 /* Update the statistics from the device registers. */
1843                 dev->stats.rx_missed_errors += tc_readl(&tr->Miss_Cnt);
1844
1845         return &dev->stats;
1846 }
1847
1848 static void tc35815_set_cam_entry(struct net_device *dev, int index, unsigned char *addr)
1849 {
1850         struct tc35815_local *lp = netdev_priv(dev);
1851         struct tc35815_regs __iomem *tr =
1852                 (struct tc35815_regs __iomem *)dev->base_addr;
1853         int cam_index = index * 6;
1854         u32 cam_data;
1855         u32 saved_addr;
1856
1857         saved_addr = tc_readl(&tr->CAM_Adr);
1858
1859         if (netif_msg_hw(lp))
1860                 printk(KERN_DEBUG "%s: CAM %d: %pM\n",
1861                         dev->name, index, addr);
1862         if (index & 1) {
1863                 /* read modify write */
1864                 tc_writel(cam_index - 2, &tr->CAM_Adr);
1865                 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1866                 cam_data |= addr[0] << 8 | addr[1];
1867                 tc_writel(cam_data, &tr->CAM_Data);
1868                 /* write whole word */
1869                 tc_writel(cam_index + 2, &tr->CAM_Adr);
1870                 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1871                 tc_writel(cam_data, &tr->CAM_Data);
1872         } else {
1873                 /* write whole word */
1874                 tc_writel(cam_index, &tr->CAM_Adr);
1875                 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1876                 tc_writel(cam_data, &tr->CAM_Data);
1877                 /* read modify write */
1878                 tc_writel(cam_index + 4, &tr->CAM_Adr);
1879                 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1880                 cam_data |= addr[4] << 24 | (addr[5] << 16);
1881                 tc_writel(cam_data, &tr->CAM_Data);
1882         }
1883
1884         tc_writel(saved_addr, &tr->CAM_Adr);
1885 }
1886
1887
1888 /*
1889  * Set or clear the multicast filter for this adaptor.
1890  * num_addrs == -1      Promiscuous mode, receive all packets
1891  * num_addrs == 0       Normal mode, clear multicast list
1892  * num_addrs > 0        Multicast mode, receive normal and MC packets,
1893  *                      and do best-effort filtering.
1894  */
1895 static void
1896 tc35815_set_multicast_list(struct net_device *dev)
1897 {
1898         struct tc35815_regs __iomem *tr =
1899                 (struct tc35815_regs __iomem *)dev->base_addr;
1900
1901         if (dev->flags & IFF_PROMISC) {
1902                 /* With some (all?) 100MHalf HUB, controller will hang
1903                  * if we enabled promiscuous mode before linkup... */
1904                 struct tc35815_local *lp = netdev_priv(dev);
1905
1906                 if (!lp->link)
1907                         return;
1908                 /* Enable promiscuous mode */
1909                 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1910         } else if ((dev->flags & IFF_ALLMULTI) ||
1911                   netdev_mc_count(dev) > CAM_ENTRY_MAX - 3) {
1912                 /* CAM 0, 1, 20 are reserved. */
1913                 /* Disable promiscuous mode, use normal mode. */
1914                 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1915         } else if (!netdev_mc_empty(dev)) {
1916                 struct netdev_hw_addr *ha;
1917                 int i;
1918                 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1919
1920                 tc_writel(0, &tr->CAM_Ctl);
1921                 /* Walk the address list, and load the filter */
1922                 i = 0;
1923                 netdev_for_each_mc_addr(ha, dev) {
1924                         /* entry 0,1 is reserved. */
1925                         tc35815_set_cam_entry(dev, i + 2, ha->addr);
1926                         ena_bits |= CAM_Ena_Bit(i + 2);
1927                         i++;
1928                 }
1929                 tc_writel(ena_bits, &tr->CAM_Ena);
1930                 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1931         } else {
1932                 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1933                 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1934         }
1935 }
1936
1937 static void tc35815_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1938 {
1939         struct tc35815_local *lp = netdev_priv(dev);
1940
1941         strlcpy(info->driver, MODNAME, sizeof(info->driver));
1942         strlcpy(info->version, DRV_VERSION, sizeof(info->version));
1943         strlcpy(info->bus_info, pci_name(lp->pci_dev), sizeof(info->bus_info));
1944 }
1945
1946 static u32 tc35815_get_msglevel(struct net_device *dev)
1947 {
1948         struct tc35815_local *lp = netdev_priv(dev);
1949         return lp->msg_enable;
1950 }
1951
1952 static void tc35815_set_msglevel(struct net_device *dev, u32 datum)
1953 {
1954         struct tc35815_local *lp = netdev_priv(dev);
1955         lp->msg_enable = datum;
1956 }
1957
1958 static int tc35815_get_sset_count(struct net_device *dev, int sset)
1959 {
1960         struct tc35815_local *lp = netdev_priv(dev);
1961
1962         switch (sset) {
1963         case ETH_SS_STATS:
1964                 return sizeof(lp->lstats) / sizeof(int);
1965         default:
1966                 return -EOPNOTSUPP;
1967         }
1968 }
1969
1970 static void tc35815_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
1971 {
1972         struct tc35815_local *lp = netdev_priv(dev);
1973         data[0] = lp->lstats.max_tx_qlen;
1974         data[1] = lp->lstats.tx_ints;
1975         data[2] = lp->lstats.rx_ints;
1976         data[3] = lp->lstats.tx_underrun;
1977 }
1978
1979 static struct {
1980         const char str[ETH_GSTRING_LEN];
1981 } ethtool_stats_keys[] = {
1982         { "max_tx_qlen" },
1983         { "tx_ints" },
1984         { "rx_ints" },
1985         { "tx_underrun" },
1986 };
1987
1988 static void tc35815_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1989 {
1990         memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
1991 }
1992
1993 static const struct ethtool_ops tc35815_ethtool_ops = {
1994         .get_drvinfo            = tc35815_get_drvinfo,
1995         .get_link               = ethtool_op_get_link,
1996         .get_msglevel           = tc35815_get_msglevel,
1997         .set_msglevel           = tc35815_set_msglevel,
1998         .get_strings            = tc35815_get_strings,
1999         .get_sset_count         = tc35815_get_sset_count,
2000         .get_ethtool_stats      = tc35815_get_ethtool_stats,
2001         .get_link_ksettings = phy_ethtool_get_link_ksettings,
2002         .set_link_ksettings = phy_ethtool_set_link_ksettings,
2003 };
2004
2005 static int tc35815_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2006 {
2007         if (!netif_running(dev))
2008                 return -EINVAL;
2009         if (!dev->phydev)
2010                 return -ENODEV;
2011         return phy_mii_ioctl(dev->phydev, rq, cmd);
2012 }
2013
2014 static void tc35815_chip_reset(struct net_device *dev)
2015 {
2016         struct tc35815_regs __iomem *tr =
2017                 (struct tc35815_regs __iomem *)dev->base_addr;
2018         int i;
2019         /* reset the controller */
2020         tc_writel(MAC_Reset, &tr->MAC_Ctl);
2021         udelay(4); /* 3200ns */
2022         i = 0;
2023         while (tc_readl(&tr->MAC_Ctl) & MAC_Reset) {
2024                 if (i++ > 100) {
2025                         printk(KERN_ERR "%s: MAC reset failed.\n", dev->name);
2026                         break;
2027                 }
2028                 mdelay(1);
2029         }
2030         tc_writel(0, &tr->MAC_Ctl);
2031
2032         /* initialize registers to default value */
2033         tc_writel(0, &tr->DMA_Ctl);
2034         tc_writel(0, &tr->TxThrsh);
2035         tc_writel(0, &tr->TxPollCtr);
2036         tc_writel(0, &tr->RxFragSize);
2037         tc_writel(0, &tr->Int_En);
2038         tc_writel(0, &tr->FDA_Bas);
2039         tc_writel(0, &tr->FDA_Lim);
2040         tc_writel(0xffffffff, &tr->Int_Src);    /* Write 1 to clear */
2041         tc_writel(0, &tr->CAM_Ctl);
2042         tc_writel(0, &tr->Tx_Ctl);
2043         tc_writel(0, &tr->Rx_Ctl);
2044         tc_writel(0, &tr->CAM_Ena);
2045         (void)tc_readl(&tr->Miss_Cnt);  /* Read to clear */
2046
2047         /* initialize internal SRAM */
2048         tc_writel(DMA_TestMode, &tr->DMA_Ctl);
2049         for (i = 0; i < 0x1000; i += 4) {
2050                 tc_writel(i, &tr->CAM_Adr);
2051                 tc_writel(0, &tr->CAM_Data);
2052         }
2053         tc_writel(0, &tr->DMA_Ctl);
2054 }
2055
2056 static void tc35815_chip_init(struct net_device *dev)
2057 {
2058         struct tc35815_local *lp = netdev_priv(dev);
2059         struct tc35815_regs __iomem *tr =
2060                 (struct tc35815_regs __iomem *)dev->base_addr;
2061         unsigned long txctl = TX_CTL_CMD;
2062
2063         /* load station address to CAM */
2064         tc35815_set_cam_entry(dev, CAM_ENTRY_SOURCE, dev->dev_addr);
2065
2066         /* Enable CAM (broadcast and unicast) */
2067         tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
2068         tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
2069
2070         /* Use DMA_RxAlign_2 to make IP header 4-byte aligned. */
2071         if (HAVE_DMA_RXALIGN(lp))
2072                 tc_writel(DMA_BURST_SIZE | DMA_RxAlign_2, &tr->DMA_Ctl);
2073         else
2074                 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
2075         tc_writel(0, &tr->TxPollCtr);   /* Batch mode */
2076         tc_writel(TX_THRESHOLD, &tr->TxThrsh);
2077         tc_writel(INT_EN_CMD, &tr->Int_En);
2078
2079         /* set queues */
2080         tc_writel(fd_virt_to_bus(lp, lp->rfd_base), &tr->FDA_Bas);
2081         tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
2082                   &tr->FDA_Lim);
2083         /*
2084          * Activation method:
2085          * First, enable the MAC Transmitter and the DMA Receive circuits.
2086          * Then enable the DMA Transmitter and the MAC Receive circuits.
2087          */
2088         tc_writel(fd_virt_to_bus(lp, lp->fbl_ptr), &tr->BLFrmPtr);      /* start DMA receiver */
2089         tc_writel(RX_CTL_CMD, &tr->Rx_Ctl);     /* start MAC receiver */
2090
2091         /* start MAC transmitter */
2092         /* TX4939 does not have EnLCarr */
2093         if (lp->chiptype == TC35815_TX4939)
2094                 txctl &= ~Tx_EnLCarr;
2095         /* WORKAROUND: ignore LostCrS in full duplex operation */
2096         if (!dev->phydev || !lp->link || lp->duplex == DUPLEX_FULL)
2097                 txctl &= ~Tx_EnLCarr;
2098         tc_writel(txctl, &tr->Tx_Ctl);
2099 }
2100
2101 #ifdef CONFIG_PM
2102 static int tc35815_suspend(struct pci_dev *pdev, pm_message_t state)
2103 {
2104         struct net_device *dev = pci_get_drvdata(pdev);
2105         struct tc35815_local *lp = netdev_priv(dev);
2106         unsigned long flags;
2107
2108         pci_save_state(pdev);
2109         if (!netif_running(dev))
2110                 return 0;
2111         netif_device_detach(dev);
2112         if (dev->phydev)
2113                 phy_stop(dev->phydev);
2114         spin_lock_irqsave(&lp->lock, flags);
2115         tc35815_chip_reset(dev);
2116         spin_unlock_irqrestore(&lp->lock, flags);
2117         pci_set_power_state(pdev, PCI_D3hot);
2118         return 0;
2119 }
2120
2121 static int tc35815_resume(struct pci_dev *pdev)
2122 {
2123         struct net_device *dev = pci_get_drvdata(pdev);
2124
2125         pci_restore_state(pdev);
2126         if (!netif_running(dev))
2127                 return 0;
2128         pci_set_power_state(pdev, PCI_D0);
2129         tc35815_restart(dev);
2130         netif_carrier_off(dev);
2131         if (dev->phydev)
2132                 phy_start(dev->phydev);
2133         netif_device_attach(dev);
2134         return 0;
2135 }
2136 #endif /* CONFIG_PM */
2137
2138 static struct pci_driver tc35815_pci_driver = {
2139         .name           = MODNAME,
2140         .id_table       = tc35815_pci_tbl,
2141         .probe          = tc35815_init_one,
2142         .remove         = tc35815_remove_one,
2143 #ifdef CONFIG_PM
2144         .suspend        = tc35815_suspend,
2145         .resume         = tc35815_resume,
2146 #endif
2147 };
2148
2149 module_param_named(speed, options.speed, int, 0);
2150 MODULE_PARM_DESC(speed, "0:auto, 10:10Mbps, 100:100Mbps");
2151 module_param_named(duplex, options.duplex, int, 0);
2152 MODULE_PARM_DESC(duplex, "0:auto, 1:half, 2:full");
2153
2154 module_pci_driver(tc35815_pci_driver);
2155 MODULE_DESCRIPTION("TOSHIBA TC35815 PCI 10M/100M Ethernet driver");
2156 MODULE_LICENSE("GPL");