drivers/net/wireless/iwlwifi/pcie/trans.c

   1 /******************************************************************************
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   6  * GPL LICENSE SUMMARY
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  51  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  53  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  54  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  60  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  61  *
  62  *****************************************************************************/
  63 #include <linux/pci.h>
  64 #include <linux/pci-aspm.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/debugfs.h>
  67 #include <linux/sched.h>
  68 #include <linux/bitops.h>
  69 #include <linux/gfp.h>
  70
  71 #include "iwl-drv.h"
  72 #include "iwl-trans.h"
  73 #include "iwl-csr.h"
  74 #include "iwl-prph.h"
  75 #include "iwl-agn-hw.h"
  76 #include "internal.h"
  77
  78 static void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans,
  79                                                   u32 reg, u32 mask, u32 value)
  80 {
  81         u32 v;
  82
  83 #ifdef CONFIG_IWLWIFI_DEBUG
  84         WARN_ON_ONCE(value & ~mask);
  85 #endif
  86
  87         v = iwl_read32(trans, reg);
  88         v &= ~mask;
  89         v |= value;
  90         iwl_write32(trans, reg, v);
  91 }
  92
  93 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans,
  94                                               u32 reg, u32 mask)
  95 {
  96         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0);
  97 }
  98
  99 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans,
 100                                             u32 reg, u32 mask)
 101 {
 102         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask);
 103 }
 104
 105 static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux)
 106 {
 107         if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold))
 108                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 109                                        APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
 110                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 111         else
 112                 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG,
 113                                        APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
 114                                        ~APMG_PS_CTRL_MSK_PWR_SRC);
 115 }
 116
 117 /* PCI registers */
 118 #define PCI_CFG_RETRY_TIMEOUT   0x041
 119
 120 static void iwl_pcie_apm_config(struct iwl_trans *trans)
 121 {
 122         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 123         u16 lctl;
 124
 125         /*
 126          * HW bug W/A for instability in PCIe bus L0S->L1 transition.
 127          * Check if BIOS (or OS) enabled L1-ASPM on this device.
 128          * If so (likely), disable L0S, so device moves directly L0->L1;
 129          *    costs negligible amount of power savings.
 130          * If not (unlikely), enable L0S, so there is at least some
 131          *    power savings, even without L1.
 132          */
 133         pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl);
 134         if (lctl & PCI_EXP_LNKCTL_ASPM_L1) {
 135                 /* L1-ASPM enabled; disable(!) L0S */
 136                 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 137                 dev_info(trans->dev, "L1 Enabled; Disabling L0S\n");
 138         } else {
 139                 /* L1-ASPM disabled; enable(!) L0S */
 140                 iwl_clear_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 141                 dev_info(trans->dev, "L1 Disabled; Enabling L0S\n");
 142         }
 143         trans->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S);
 144 }
 145
 146 /*
 147  * Start up NIC's basic functionality after it has been reset
 148  * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
 149  * NOTE:  This does not load uCode nor start the embedded processor
 150  */
 151 static int iwl_pcie_apm_init(struct iwl_trans *trans)
 152 {
 153         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 154         int ret = 0;
 155         IWL_DEBUG_INFO(trans, "Init card's basic functions\n");
 156
 157         /*
 158          * Use "set_bit" below rather than "write", to preserve any hardware
 159          * bits already set by default after reset.
 160          */
 161
 162         /* Disable L0S exit timer (platform NMI Work/Around) */
 163         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 164                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 165
 166         /*
 167          * Disable L0s without affecting L1;
 168          *  don't wait for ICH L0s (ICH bug W/A)
 169          */
 170         iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS,
 171                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 172
 173         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 174         iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 175
 176         /*
 177          * Enable HAP INTA (interrupt from management bus) to
 178          * wake device's PCI Express link L1a -> L0s
 179          */
 180         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 181                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 182
 183         iwl_pcie_apm_config(trans);
 184
 185         /* Configure analog phase-lock-loop before activating to D0A */
 186         if (trans->cfg->base_params->pll_cfg_val)
 187                 iwl_set_bit(trans, CSR_ANA_PLL_CFG,
 188                             trans->cfg->base_params->pll_cfg_val);
 189
 190         /*
 191          * Set "initialization complete" bit to move adapter from
 192          * D0U* --> D0A* (powered-up active) state.
 193          */
 194         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 195
 196         /*
 197          * Wait for clock stabilization; once stabilized, access to
 198          * device-internal resources is supported, e.g. iwl_write_prph()
 199          * and accesses to uCode SRAM.
 200          */
 201         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 202                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 203                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 204         if (ret < 0) {
 205                 IWL_DEBUG_INFO(trans, "Failed to init the card\n");
 206                 goto out;
 207         }
 208
 209         /*
 210          * Enable DMA clock and wait for it to stabilize.
 211          *
 212          * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
 213          * do not disable clocks.  This preserves any hardware bits already
 214          * set by default in "CLK_CTRL_REG" after reset.
 215          */
 216         iwl_write_prph(trans, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 217         udelay(20);
 218
 219         /* Disable L1-Active */
 220         iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG,
 221                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 222
 223         set_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 224
 225 out:
 226         return ret;
 227 }
 228
 229 static int iwl_pcie_apm_stop_master(struct iwl_trans *trans)
 230 {
 231         int ret = 0;
 232
 233         /* stop device's busmaster DMA activity */
 234         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
 235
 236         ret = iwl_poll_bit(trans, CSR_RESET,
 237                            CSR_RESET_REG_FLAG_MASTER_DISABLED,
 238                            CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
 239         if (ret)
 240                 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n");
 241
 242         IWL_DEBUG_INFO(trans, "stop master\n");
 243
 244         return ret;
 245 }
 246
 247 static void iwl_pcie_apm_stop(struct iwl_trans *trans)
 248 {
 249         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 250         IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n");
 251
 252         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 253
 254         /* Stop device's DMA activity */
 255         iwl_pcie_apm_stop_master(trans);
 256
 257         /* Reset the entire device */
 258         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 259
 260         udelay(10);
 261
 262         /*
 263          * Clear "initialization complete" bit to move adapter from
 264          * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
 265          */
 266         iwl_clear_bit(trans, CSR_GP_CNTRL,
 267                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 268 }
 269
 270 static int iwl_pcie_nic_init(struct iwl_trans *trans)
 271 {
 272         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 273         unsigned long flags;
 274
 275         /* nic_init */
 276         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 277         iwl_pcie_apm_init(trans);
 278
 279         /* Set interrupt coalescing calibration timer to default (512 usecs) */
 280         iwl_write8(trans, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
 281
 282         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 283
 284         iwl_pcie_set_pwr(trans, false);
 285
 286         iwl_op_mode_nic_config(trans->op_mode);
 287
 288         /* Allocate the RX queue, or reset if it is already allocated */
 289         iwl_pcie_rx_init(trans);
 290
 291         /* Allocate or reset and init all Tx and Command queues */
 292         if (iwl_pcie_tx_init(trans))
 293                 return -ENOMEM;
 294
 295         if (trans->cfg->base_params->shadow_reg_enable) {
 296                 /* enable shadow regs in HW */
 297                 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF);
 298                 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n");
 299         }
 300
 301         return 0;
 302 }
 303
 304 #define HW_READY_TIMEOUT (50)
 305
 306 /* Note: returns poll_bit return value, which is >= 0 if success */
 307 static int iwl_pcie_set_hw_ready(struct iwl_trans *trans)
 308 {
 309         int ret;
 310
 311         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 312                     CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
 313
 314         /* See if we got it */
 315         ret = iwl_poll_bit(trans, CSR_HW_IF_CONFIG_REG,
 316                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 317                            CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
 318                            HW_READY_TIMEOUT);
 319
 320         IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret < 0 ? " not" : "");
 321         return ret;
 322 }
 323
 324 /* Note: returns standard 0/-ERROR code */
 325 static int iwl_pcie_prepare_card_hw(struct iwl_trans *trans)
 326 {
 327         int ret;
 328         int t = 0;
 329
 330         IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n");
 331
 332         ret = iwl_pcie_set_hw_ready(trans);
 333         /* If the card is ready, exit 0 */
 334         if (ret >= 0)
 335                 return 0;
 336
 337         /* If HW is not ready, prepare the conditions to check again */
 338         iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
 339                     CSR_HW_IF_CONFIG_REG_PREPARE);
 340
 341         do {
 342                 ret = iwl_pcie_set_hw_ready(trans);
 343                 if (ret >= 0)
 344                         return 0;
 345
 346                 usleep_range(200, 1000);
 347                 t += 200;
 348         } while (t < 150000);
 349
 350         return ret;
 351 }
 352
 353 /*
 354  * ucode
 355  */
 356 static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, u32 dst_addr,
 357                                    dma_addr_t phy_addr, u32 byte_cnt)
 358 {
 359         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 360         int ret;
 361
 362         trans_pcie->ucode_write_complete = false;
 363
 364         iwl_write_direct32(trans,
 365                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 366                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 367
 368         iwl_write_direct32(trans,
 369                            FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL),
 370                            dst_addr);
 371
 372         iwl_write_direct32(trans,
 373                            FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 374                            phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 375
 376         iwl_write_direct32(trans,
 377                            FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 378                            (iwl_get_dma_hi_addr(phy_addr)
 379                                 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 380
 381         iwl_write_direct32(trans,
 382                            FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 383                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 384                            1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 385                            FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 386
 387         iwl_write_direct32(trans,
 388                            FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 389                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE    |
 390                            FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE |
 391                            FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 392
 393         ret = wait_event_timeout(trans_pcie->ucode_write_waitq,
 394                                  trans_pcie->ucode_write_complete, 5 * HZ);
 395         if (!ret) {
 396                 IWL_ERR(trans, "Failed to load firmware chunk!\n");
 397                 return -ETIMEDOUT;
 398         }
 399
 400         return 0;
 401 }
 402
 403 static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num,
 404                             const struct fw_desc *section)
 405 {
 406         u8 *v_addr;
 407         dma_addr_t p_addr;
 408         u32 offset, chunk_sz = section->len;
 409         int ret = 0;
 410
 411         IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n",
 412                      section_num);
 413
 414         v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr,
 415                                     GFP_KERNEL | __GFP_NOWARN);
 416         if (!v_addr) {
 417                 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n");
 418                 chunk_sz = PAGE_SIZE;
 419                 v_addr = dma_alloc_coherent(trans->dev, chunk_sz,
 420                                             &p_addr, GFP_KERNEL);
 421                 if (!v_addr)
 422                         return -ENOMEM;
 423         }
 424
 425         for (offset = 0; offset < section->len; offset += chunk_sz) {
 426                 u32 copy_size;
 427
 428                 copy_size = min_t(u32, chunk_sz, section->len - offset);
 429
 430                 memcpy(v_addr, (u8 *)section->data + offset, copy_size);
 431                 ret = iwl_pcie_load_firmware_chunk(trans,
 432                                                    section->offset + offset,
 433                                                    p_addr, copy_size);
 434                 if (ret) {
 435                         IWL_ERR(trans,
 436                                 "Could not load the [%d] uCode section\n",
 437                                 section_num);
 438                         break;
 439                 }
 440         }
 441
 442         dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr);
 443         return ret;
 444 }
 445
 446 static int iwl_pcie_load_given_ucode(struct iwl_trans *trans,
 447                                 const struct fw_img *image)
 448 {
 449         int i, ret = 0;
 450
 451         for (i = 0; i < IWL_UCODE_SECTION_MAX; i++) {
 452                 if (!image->sec[i].data)
 453                         break;
 454
 455                 ret = iwl_pcie_load_section(trans, i, &image->sec[i]);
 456                 if (ret)
 457                         return ret;
 458         }
 459
 460         /* Remove all resets to allow NIC to operate */
 461         iwl_write32(trans, CSR_RESET, 0);
 462
 463         return 0;
 464 }
 465
 466 static int iwl_trans_pcie_start_fw(struct iwl_trans *trans,
 467                                    const struct fw_img *fw, bool run_in_rfkill)
 468 {
 469         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 470         int ret;
 471         bool hw_rfkill;
 472
 473         /* This may fail if AMT took ownership of the device */
 474         if (iwl_pcie_prepare_card_hw(trans)) {
 475                 IWL_WARN(trans, "Exit HW not ready\n");
 476                 return -EIO;
 477         }
 478
 479         clear_bit(STATUS_FW_ERROR, &trans_pcie->status);
 480
 481         iwl_enable_rfkill_int(trans);
 482
 483         /* If platform's RF_KILL switch is NOT set to KILL */
 484         hw_rfkill = iwl_is_rfkill_set(trans);
 485         if (hw_rfkill)
 486                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 487         else
 488                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 489         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 490         if (hw_rfkill && !run_in_rfkill)
 491                 return -ERFKILL;
 492
 493         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 494
 495         ret = iwl_pcie_nic_init(trans);
 496         if (ret) {
 497                 IWL_ERR(trans, "Unable to init nic\n");
 498                 return ret;
 499         }
 500
 501         /* make sure rfkill handshake bits are cleared */
 502         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 503         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR,
 504                     CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
 505
 506         /* clear (again), then enable host interrupts */
 507         iwl_write32(trans, CSR_INT, 0xFFFFFFFF);
 508         iwl_enable_interrupts(trans);
 509
 510         /* really make sure rfkill handshake bits are cleared */
 511         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 512         iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
 513
 514         /* Load the given image to the HW */
 515         return iwl_pcie_load_given_ucode(trans, fw);
 516 }
 517
 518 static void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr)
 519 {
 520         iwl_pcie_reset_ict(trans);
 521         iwl_pcie_tx_start(trans, scd_addr);
 522 }
 523
 524 static void iwl_trans_pcie_stop_device(struct iwl_trans *trans)
 525 {
 526         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 527         unsigned long flags;
 528
 529         /* tell the device to stop sending interrupts */
 530         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 531         iwl_disable_interrupts(trans);
 532         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 533
 534         /* device going down, Stop using ICT table */
 535         iwl_pcie_disable_ict(trans);
 536
 537         /*
 538          * If a HW restart happens during firmware loading,
 539          * then the firmware loading might call this function
 540          * and later it might be called again due to the
 541          * restart. So don't process again if the device is
 542          * already dead.
 543          */
 544         if (test_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status)) {
 545                 iwl_pcie_tx_stop(trans);
 546                 iwl_pcie_rx_stop(trans);
 547
 548                 /* Power-down device's busmaster DMA clocks */
 549                 iwl_write_prph(trans, APMG_CLK_DIS_REG,
 550                                APMG_CLK_VAL_DMA_CLK_RQT);
 551                 udelay(5);
 552         }
 553
 554         /* Make sure (redundant) we've released our request to stay awake */
 555         iwl_clear_bit(trans, CSR_GP_CNTRL,
 556                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 557
 558         /* Stop the device, and put it in low power state */
 559         iwl_pcie_apm_stop(trans);
 560
 561         /* Upon stop, the APM issues an interrupt if HW RF kill is set.
 562          * Clean again the interrupt here
 563          */
 564         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 565         iwl_disable_interrupts(trans);
 566         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 567
 568         iwl_enable_rfkill_int(trans);
 569
 570         /* stop and reset the on-board processor */
 571         iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
 572
 573         /* clear all status bits */
 574         clear_bit(STATUS_HCMD_ACTIVE, &trans_pcie->status);
 575         clear_bit(STATUS_INT_ENABLED, &trans_pcie->status);
 576         clear_bit(STATUS_DEVICE_ENABLED, &trans_pcie->status);
 577         clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 578         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 579 }
 580
 581 static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
 582 {
 583         iwl_disable_interrupts(trans);
 584
 585         /*
 586          * in testing mode, the host stays awake and the
 587          * hardware won't be reset (not even partially)
 588          */
 589         if (test)
 590                 return;
 591
 592         iwl_pcie_disable_ict(trans);
 593
 594         iwl_clear_bit(trans, CSR_GP_CNTRL,
 595                       CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 596         iwl_clear_bit(trans, CSR_GP_CNTRL,
 597                       CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 598
 599         /*
 600          * reset TX queues -- some of their registers reset during S3
 601          * so if we don't reset everything here the D3 image would try
 602          * to execute some invalid memory upon resume
 603          */
 604         iwl_trans_pcie_tx_reset(trans);
 605
 606         iwl_pcie_set_pwr(trans, true);
 607 }
 608
 609 static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
 610                                     enum iwl_d3_status *status,
 611                                     bool test)
 612 {
 613         u32 val;
 614         int ret;
 615
 616         if (test) {
 617                 iwl_enable_interrupts(trans);
 618                 *status = IWL_D3_STATUS_ALIVE;
 619                 return 0;
 620         }
 621
 622         iwl_pcie_set_pwr(trans, false);
 623
 624         val = iwl_read32(trans, CSR_RESET);
 625         if (val & CSR_RESET_REG_FLAG_NEVO_RESET) {
 626                 *status = IWL_D3_STATUS_RESET;
 627                 return 0;
 628         }
 629
 630         /*
 631          * Also enables interrupts - none will happen as the device doesn't
 632          * know we're waking it up, only when the opmode actually tells it
 633          * after this call.
 634          */
 635         iwl_pcie_reset_ict(trans);
 636
 637         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 638         iwl_set_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 639
 640         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 641                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 642                            CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
 643                            25000);
 644         if (ret) {
 645                 IWL_ERR(trans, "Failed to resume the device (mac ready)\n");
 646                 return ret;
 647         }
 648
 649         iwl_trans_pcie_tx_reset(trans);
 650
 651         ret = iwl_pcie_rx_init(trans);
 652         if (ret) {
 653                 IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
 654                 return ret;
 655         }
 656
 657         *status = IWL_D3_STATUS_ALIVE;
 658         return 0;
 659 }
 660
 661 static int iwl_trans_pcie_start_hw(struct iwl_trans *trans)
 662 {
 663         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 664         bool hw_rfkill;
 665         int err;
 666
 667         err = iwl_pcie_prepare_card_hw(trans);
 668         if (err) {
 669                 IWL_ERR(trans, "Error while preparing HW: %d\n", err);
 670                 return err;
 671         }
 672
 673         /* Reset the entire device */
 674         iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 675
 676         usleep_range(10, 15);
 677
 678         iwl_pcie_apm_init(trans);
 679
 680         /* From now on, the op_mode will be kept updated about RF kill state */
 681         iwl_enable_rfkill_int(trans);
 682
 683         hw_rfkill = iwl_is_rfkill_set(trans);
 684         if (hw_rfkill)
 685                 set_bit(STATUS_RFKILL, &trans_pcie->status);
 686         else
 687                 clear_bit(STATUS_RFKILL, &trans_pcie->status);
 688         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 689
 690         return 0;
 691 }
 692
 693 static void iwl_trans_pcie_stop_hw(struct iwl_trans *trans,
 694                                    bool op_mode_leaving)
 695 {
 696         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 697         bool hw_rfkill;
 698         unsigned long flags;
 699
 700         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 701         iwl_disable_interrupts(trans);
 702         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 703
 704         iwl_pcie_apm_stop(trans);
 705
 706         spin_lock_irqsave(&trans_pcie->irq_lock, flags);
 707         iwl_disable_interrupts(trans);
 708         spin_unlock_irqrestore(&trans_pcie->irq_lock, flags);
 709
 710         iwl_pcie_disable_ict(trans);
 711
 712         if (!op_mode_leaving) {
 713                 /*
 714                  * Even if we stop the HW, we still want the RF kill
 715                  * interrupt
 716                  */
 717                 iwl_enable_rfkill_int(trans);
 718
 719                 /*
 720                  * Check again since the RF kill state may have changed while
 721                  * all the interrupts were disabled, in this case we couldn't
 722                  * receive the RF kill interrupt and update the state in the
 723                  * op_mode.
 724                  */
 725                 hw_rfkill = iwl_is_rfkill_set(trans);
 726                 if (hw_rfkill)
 727                         set_bit(STATUS_RFKILL, &trans_pcie->status);
 728                 else
 729                         clear_bit(STATUS_RFKILL, &trans_pcie->status);
 730                 iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 731         }
 732 }
 733
 734 static void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val)
 735 {
 736         writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 737 }
 738
 739 static void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val)
 740 {
 741         writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 742 }
 743
 744 static u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs)
 745 {
 746         return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs);
 747 }
 748
 749 static u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg)
 750 {
 751         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR,
 752                                ((reg & 0x000FFFFF) | (3 << 24)));
 753         return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT);
 754 }
 755
 756 static void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr,
 757                                       u32 val)
 758 {
 759         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR,
 760                                ((addr & 0x000FFFFF) | (3 << 24)));
 761         iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val);
 762 }
 763
 764 static void iwl_trans_pcie_configure(struct iwl_trans *trans,
 765                                      const struct iwl_trans_config *trans_cfg)
 766 {
 767         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 768
 769         trans_pcie->cmd_queue = trans_cfg->cmd_queue;
 770         trans_pcie->cmd_fifo = trans_cfg->cmd_fifo;
 771         if (WARN_ON(trans_cfg->n_no_reclaim_cmds > MAX_NO_RECLAIM_CMDS))
 772                 trans_pcie->n_no_reclaim_cmds = 0;
 773         else
 774                 trans_pcie->n_no_reclaim_cmds = trans_cfg->n_no_reclaim_cmds;
 775         if (trans_pcie->n_no_reclaim_cmds)
 776                 memcpy(trans_pcie->no_reclaim_cmds, trans_cfg->no_reclaim_cmds,
 777                        trans_pcie->n_no_reclaim_cmds * sizeof(u8));
 778
 779         trans_pcie->rx_buf_size_8k = trans_cfg->rx_buf_size_8k;
 780         if (trans_pcie->rx_buf_size_8k)
 781                 trans_pcie->rx_page_order = get_order(8 * 1024);
 782         else
 783                 trans_pcie->rx_page_order = get_order(4 * 1024);
 784
 785         trans_pcie->wd_timeout =
 786                 msecs_to_jiffies(trans_cfg->queue_watchdog_timeout);
 787
 788         trans_pcie->command_names = trans_cfg->command_names;
 789         trans_pcie->bc_table_dword = trans_cfg->bc_table_dword;
 790 }
 791
 792 void iwl_trans_pcie_free(struct iwl_trans *trans)
 793 {
 794         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 795
 796         synchronize_irq(trans_pcie->pci_dev->irq);
 797
 798         iwl_pcie_tx_free(trans);
 799         iwl_pcie_rx_free(trans);
 800
 801         free_irq(trans_pcie->pci_dev->irq, trans);
 802         iwl_pcie_free_ict(trans);
 803
 804         pci_disable_msi(trans_pcie->pci_dev);
 805         iounmap(trans_pcie->hw_base);
 806         pci_release_regions(trans_pcie->pci_dev);
 807         pci_disable_device(trans_pcie->pci_dev);
 808         kmem_cache_destroy(trans->dev_cmd_pool);
 809
 810         kfree(trans);
 811 }
 812
 813 static void iwl_trans_pcie_set_pmi(struct iwl_trans *trans, bool state)
 814 {
 815         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 816
 817         if (state)
 818                 set_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 819         else
 820                 clear_bit(STATUS_TPOWER_PMI, &trans_pcie->status);
 821 }
 822
 823 #ifdef CONFIG_PM_SLEEP
 824 static int iwl_trans_pcie_suspend(struct iwl_trans *trans)
 825 {
 826         return 0;
 827 }
 828
 829 static int iwl_trans_pcie_resume(struct iwl_trans *trans)
 830 {
 831         bool hw_rfkill;
 832
 833         iwl_enable_rfkill_int(trans);
 834
 835         hw_rfkill = iwl_is_rfkill_set(trans);
 836         iwl_op_mode_hw_rf_kill(trans->op_mode, hw_rfkill);
 837
 838         return 0;
 839 }
 840 #endif /* CONFIG_PM_SLEEP */
 841
 842 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent,
 843                                                 unsigned long *flags)
 844 {
 845         int ret;
 846         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 847
 848         spin_lock_irqsave(&trans_pcie->reg_lock, *flags);
 849
 850         /* this bit wakes up the NIC */
 851         __iwl_trans_pcie_set_bit(trans, CSR_GP_CNTRL,
 852                                  CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 853
 854         /*
 855          * These bits say the device is running, and should keep running for
 856          * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
 857          * but they do not indicate that embedded SRAM is restored yet;
 858          * 3945 and 4965 have volatile SRAM, and must save/restore contents
 859          * to/from host DRAM when sleeping/waking for power-saving.
 860          * Each direction takes approximately 1/4 millisecond; with this
 861          * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
 862          * series of register accesses are expected (e.g. reading Event Log),
 863          * to keep device from sleeping.
 864          *
 865          * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
 866          * SRAM is okay/restored.  We don't check that here because this call
 867          * is just for hardware register access; but GP1 MAC_SLEEP check is a
 868          * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
 869          *
 870          * 5000 series and later (including 1000 series) have non-volatile SRAM,
 871          * and do not save/restore SRAM when power cycling.
 872          */
 873         ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
 874                            CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
 875                            (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
 876                             CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
 877         if (unlikely(ret < 0)) {
 878                 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
 879                 if (!silent) {
 880                         u32 val = iwl_read32(trans, CSR_GP_CNTRL);
 881                         WARN_ONCE(1,
 882                                   "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
 883                                   val);
 884                         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 885                         return false;
 886                 }
 887         }
 888
 889         /*
 890          * Fool sparse by faking we release the lock - sparse will
 891          * track nic_access anyway.
 892          */
 893         __release(&trans_pcie->reg_lock);
 894         return true;
 895 }
 896
 897 static void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans,
 898                                               unsigned long *flags)
 899 {
 900         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 901
 902         lockdep_assert_held(&trans_pcie->reg_lock);
 903
 904         /*
 905          * Fool sparse by faking we acquiring the lock - sparse will
 906          * track nic_access anyway.
 907          */
 908         __acquire(&trans_pcie->reg_lock);
 909
 910         __iwl_trans_pcie_clear_bit(trans, CSR_GP_CNTRL,
 911                                    CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
 912         /*
 913          * Above we read the CSR_GP_CNTRL register, which will flush
 914          * any previous writes, but we need the write that clears the
 915          * MAC_ACCESS_REQ bit to be performed before any other writes
 916          * scheduled on different CPUs (after we drop reg_lock).
 917          */
 918         mmiowb();
 919         spin_unlock_irqrestore(&trans_pcie->reg_lock, *flags);
 920 }
 921
 922 static int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr,
 923                                    void *buf, int dwords)
 924 {
 925         unsigned long flags;
 926         int offs, ret = 0;
 927         u32 *vals = buf;
 928
 929         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
 930                 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
 931                 for (offs = 0; offs < dwords; offs++)
 932                         vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
 933                 iwl_trans_release_nic_access(trans, &flags);
 934         } else {
 935                 ret = -EBUSY;
 936         }
 937         return ret;
 938 }
 939
 940 static int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr,
 941                                     const void *buf, int dwords)
 942 {
 943         unsigned long flags;
 944         int offs, ret = 0;
 945         const u32 *vals = buf;
 946
 947         if (iwl_trans_grab_nic_access(trans, false, &flags)) {
 948                 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
 949                 for (offs = 0; offs < dwords; offs++)
 950                         iwl_write32(trans, HBUS_TARG_MEM_WDAT,
 951                                     vals ? vals[offs] : 0);
 952                 iwl_trans_release_nic_access(trans, &flags);
 953         } else {
 954                 ret = -EBUSY;
 955         }
 956         return ret;
 957 }
 958
 959 #define IWL_FLUSH_WAIT_MS       2000
 960
 961 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans)
 962 {
 963         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
 964         struct iwl_txq *txq;
 965         struct iwl_queue *q;
 966         int cnt;
 967         unsigned long now = jiffies;
 968         u32 scd_sram_addr;
 969         u8 buf[16];
 970         int ret = 0;
 971
 972         /* waiting for all the tx frames complete might take a while */
 973         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
 974                 if (cnt == trans_pcie->cmd_queue)
 975                         continue;
 976                 txq = &trans_pcie->txq[cnt];
 977                 q = &txq->q;
 978                 while (q->read_ptr != q->write_ptr && !time_after(jiffies,
 979                        now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS)))
 980                         msleep(1);
 981
 982                 if (q->read_ptr != q->write_ptr) {
 983                         IWL_ERR(trans,
 984                                 "fail to flush all tx fifo queues Q %d\n", cnt);
 985                         ret = -ETIMEDOUT;
 986                         break;
 987                 }
 988         }
 989
 990         if (!ret)
 991                 return 0;
 992
 993         IWL_ERR(trans, "Current SW read_ptr %d write_ptr %d\n",
 994                 txq->q.read_ptr, txq->q.write_ptr);
 995
 996         scd_sram_addr = trans_pcie->scd_base_addr +
 997                         SCD_TX_STTS_QUEUE_OFFSET(txq->q.id);
 998         iwl_trans_read_mem_bytes(trans, scd_sram_addr, buf, sizeof(buf));
 999
1000         iwl_print_hex_error(trans, buf, sizeof(buf));
1001
1002         for (cnt = 0; cnt < FH_TCSR_CHNL_NUM; cnt++)
1003                 IWL_ERR(trans, "FH TRBs(%d) = 0x%08x\n", cnt,
1004                         iwl_read_direct32(trans, FH_TX_TRB_REG(cnt)));
1005
1006         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1007                 u32 status = iwl_read_prph(trans, SCD_QUEUE_STATUS_BITS(cnt));
1008                 u8 fifo = (status >> SCD_QUEUE_STTS_REG_POS_TXF) & 0x7;
1009                 bool active = !!(status & BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE));
1010                 u32 tbl_dw =
1011                         iwl_trans_read_mem32(trans, trans_pcie->scd_base_addr +
1012                                              SCD_TRANS_TBL_OFFSET_QUEUE(cnt));
1013
1014                 if (cnt & 0x1)
1015                         tbl_dw = (tbl_dw & 0xFFFF0000) >> 16;
1016                 else
1017                         tbl_dw = tbl_dw & 0x0000FFFF;
1018
1019                 IWL_ERR(trans,
1020                         "Q %d is %sactive and mapped to fifo %d ra_tid 0x%04x [%d,%d]\n",
1021                         cnt, active ? "" : "in", fifo, tbl_dw,
1022                         iwl_read_prph(trans,
1023                                       SCD_QUEUE_RDPTR(cnt)) & (txq->q.n_bd - 1),
1024                         iwl_read_prph(trans, SCD_QUEUE_WRPTR(cnt)));
1025         }
1026
1027         return ret;
1028 }
1029
1030 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg,
1031                                          u32 mask, u32 value)
1032 {
1033         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1034         unsigned long flags;
1035
1036         spin_lock_irqsave(&trans_pcie->reg_lock, flags);
1037         __iwl_trans_pcie_set_bits_mask(trans, reg, mask, value);
1038         spin_unlock_irqrestore(&trans_pcie->reg_lock, flags);
1039 }
1040
1041 static const char *get_fh_string(int cmd)
1042 {
1043 #define IWL_CMD(x) case x: return #x
1044         switch (cmd) {
1045         IWL_CMD(FH_RSCSR_CHNL0_STTS_WPTR_REG);
1046         IWL_CMD(FH_RSCSR_CHNL0_RBDCB_BASE_REG);
1047         IWL_CMD(FH_RSCSR_CHNL0_WPTR);
1048         IWL_CMD(FH_MEM_RCSR_CHNL0_CONFIG_REG);
1049         IWL_CMD(FH_MEM_RSSR_SHARED_CTRL_REG);
1050         IWL_CMD(FH_MEM_RSSR_RX_STATUS_REG);
1051         IWL_CMD(FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV);
1052         IWL_CMD(FH_TSSR_TX_STATUS_REG);
1053         IWL_CMD(FH_TSSR_TX_ERROR_REG);
1054         default:
1055                 return "UNKNOWN";
1056         }
1057 #undef IWL_CMD
1058 }
1059
1060 int iwl_pcie_dump_fh(struct iwl_trans *trans, char **buf)
1061 {
1062         int i;
1063         static const u32 fh_tbl[] = {
1064                 FH_RSCSR_CHNL0_STTS_WPTR_REG,
1065                 FH_RSCSR_CHNL0_RBDCB_BASE_REG,
1066                 FH_RSCSR_CHNL0_WPTR,
1067                 FH_MEM_RCSR_CHNL0_CONFIG_REG,
1068                 FH_MEM_RSSR_SHARED_CTRL_REG,
1069                 FH_MEM_RSSR_RX_STATUS_REG,
1070                 FH_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV,
1071                 FH_TSSR_TX_STATUS_REG,
1072                 FH_TSSR_TX_ERROR_REG
1073         };
1074
1075 #ifdef CONFIG_IWLWIFI_DEBUGFS
1076         if (buf) {
1077                 int pos = 0;
1078                 size_t bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40;
1079
1080                 *buf = kmalloc(bufsz, GFP_KERNEL);
1081                 if (!*buf)
1082                         return -ENOMEM;
1083
1084                 pos += scnprintf(*buf + pos, bufsz - pos,
1085                                 "FH register values:\n");
1086
1087                 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++)
1088                         pos += scnprintf(*buf + pos, bufsz - pos,
1089                                 "  %34s: 0X%08x\n",
1090                                 get_fh_string(fh_tbl[i]),
1091                                 iwl_read_direct32(trans, fh_tbl[i]));
1092
1093                 return pos;
1094         }
1095 #endif
1096
1097         IWL_ERR(trans, "FH register values:\n");
1098         for (i = 0; i <  ARRAY_SIZE(fh_tbl); i++)
1099                 IWL_ERR(trans, "  %34s: 0X%08x\n",
1100                         get_fh_string(fh_tbl[i]),
1101                         iwl_read_direct32(trans, fh_tbl[i]));
1102
1103         return 0;
1104 }
1105
1106 static const char *get_csr_string(int cmd)
1107 {
1108 #define IWL_CMD(x) case x: return #x
1109         switch (cmd) {
1110         IWL_CMD(CSR_HW_IF_CONFIG_REG);
1111         IWL_CMD(CSR_INT_COALESCING);
1112         IWL_CMD(CSR_INT);
1113         IWL_CMD(CSR_INT_MASK);
1114         IWL_CMD(CSR_FH_INT_STATUS);
1115         IWL_CMD(CSR_GPIO_IN);
1116         IWL_CMD(CSR_RESET);
1117         IWL_CMD(CSR_GP_CNTRL);
1118         IWL_CMD(CSR_HW_REV);
1119         IWL_CMD(CSR_EEPROM_REG);
1120         IWL_CMD(CSR_EEPROM_GP);
1121         IWL_CMD(CSR_OTP_GP_REG);
1122         IWL_CMD(CSR_GIO_REG);
1123         IWL_CMD(CSR_GP_UCODE_REG);
1124         IWL_CMD(CSR_GP_DRIVER_REG);
1125         IWL_CMD(CSR_UCODE_DRV_GP1);
1126         IWL_CMD(CSR_UCODE_DRV_GP2);
1127         IWL_CMD(CSR_LED_REG);
1128         IWL_CMD(CSR_DRAM_INT_TBL_REG);
1129         IWL_CMD(CSR_GIO_CHICKEN_BITS);
1130         IWL_CMD(CSR_ANA_PLL_CFG);
1131         IWL_CMD(CSR_HW_REV_WA_REG);
1132         IWL_CMD(CSR_DBG_HPET_MEM_REG);
1133         default:
1134                 return "UNKNOWN";
1135         }
1136 #undef IWL_CMD
1137 }
1138
1139 void iwl_pcie_dump_csr(struct iwl_trans *trans)
1140 {
1141         int i;
1142         static const u32 csr_tbl[] = {
1143                 CSR_HW_IF_CONFIG_REG,
1144                 CSR_INT_COALESCING,
1145                 CSR_INT,
1146                 CSR_INT_MASK,
1147                 CSR_FH_INT_STATUS,
1148                 CSR_GPIO_IN,
1149                 CSR_RESET,
1150                 CSR_GP_CNTRL,
1151                 CSR_HW_REV,
1152                 CSR_EEPROM_REG,
1153                 CSR_EEPROM_GP,
1154                 CSR_OTP_GP_REG,
1155                 CSR_GIO_REG,
1156                 CSR_GP_UCODE_REG,
1157                 CSR_GP_DRIVER_REG,
1158                 CSR_UCODE_DRV_GP1,
1159                 CSR_UCODE_DRV_GP2,
1160                 CSR_LED_REG,
1161                 CSR_DRAM_INT_TBL_REG,
1162                 CSR_GIO_CHICKEN_BITS,
1163                 CSR_ANA_PLL_CFG,
1164                 CSR_HW_REV_WA_REG,
1165                 CSR_DBG_HPET_MEM_REG
1166         };
1167         IWL_ERR(trans, "CSR values:\n");
1168         IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is "
1169                 "CSR_INT_PERIODIC_REG)\n");
1170         for (i = 0; i <  ARRAY_SIZE(csr_tbl); i++) {
1171                 IWL_ERR(trans, "  %25s: 0X%08x\n",
1172                         get_csr_string(csr_tbl[i]),
1173                         iwl_read32(trans, csr_tbl[i]));
1174         }
1175 }
1176
1177 #ifdef CONFIG_IWLWIFI_DEBUGFS
1178 /* create and remove of files */
1179 #define DEBUGFS_ADD_FILE(name, parent, mode) do {                       \
1180         if (!debugfs_create_file(#name, mode, parent, trans,            \
1181                                  &iwl_dbgfs_##name##_ops))              \
1182                 goto err;                                               \
1183 } while (0)
1184
1185 /* file operation */
1186 #define DEBUGFS_READ_FUNC(name)                                         \
1187 static ssize_t iwl_dbgfs_##name##_read(struct file *file,               \
1188                                         char __user *user_buf,          \
1189                                         size_t count, loff_t *ppos);
1190
1191 #define DEBUGFS_WRITE_FUNC(name)                                        \
1192 static ssize_t iwl_dbgfs_##name##_write(struct file *file,              \
1193                                         const char __user *user_buf,    \
1194                                         size_t count, loff_t *ppos);
1195
1196 #define DEBUGFS_READ_FILE_OPS(name)                                     \
1197         DEBUGFS_READ_FUNC(name);                                        \
1198 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1199         .read = iwl_dbgfs_##name##_read,                                \
1200         .open = simple_open,                                            \
1201         .llseek = generic_file_llseek,                                  \
1202 };
1203
1204 #define DEBUGFS_WRITE_FILE_OPS(name)                                    \
1205         DEBUGFS_WRITE_FUNC(name);                                       \
1206 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1207         .write = iwl_dbgfs_##name##_write,                              \
1208         .open = simple_open,                                            \
1209         .llseek = generic_file_llseek,                                  \
1210 };
1211
1212 #define DEBUGFS_READ_WRITE_FILE_OPS(name)                               \
1213         DEBUGFS_READ_FUNC(name);                                        \
1214         DEBUGFS_WRITE_FUNC(name);                                       \
1215 static const struct file_operations iwl_dbgfs_##name##_ops = {          \
1216         .write = iwl_dbgfs_##name##_write,                              \
1217         .read = iwl_dbgfs_##name##_read,                                \
1218         .open = simple_open,                                            \
1219         .llseek = generic_file_llseek,                                  \
1220 };
1221
1222 static ssize_t iwl_dbgfs_tx_queue_read(struct file *file,
1223                                        char __user *user_buf,
1224                                        size_t count, loff_t *ppos)
1225 {
1226         struct iwl_trans *trans = file->private_data;
1227         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1228         struct iwl_txq *txq;
1229         struct iwl_queue *q;
1230         char *buf;
1231         int pos = 0;
1232         int cnt;
1233         int ret;
1234         size_t bufsz;
1235
1236         bufsz = sizeof(char) * 64 * trans->cfg->base_params->num_of_queues;
1237
1238         if (!trans_pcie->txq)
1239                 return -EAGAIN;
1240
1241         buf = kzalloc(bufsz, GFP_KERNEL);
1242         if (!buf)
1243                 return -ENOMEM;
1244
1245         for (cnt = 0; cnt < trans->cfg->base_params->num_of_queues; cnt++) {
1246                 txq = &trans_pcie->txq[cnt];
1247                 q = &txq->q;
1248                 pos += scnprintf(buf + pos, bufsz - pos,
1249                                 "hwq %.2d: read=%u write=%u use=%d stop=%d\n",
1250                                 cnt, q->read_ptr, q->write_ptr,
1251                                 !!test_bit(cnt, trans_pcie->queue_used),
1252                                 !!test_bit(cnt, trans_pcie->queue_stopped));
1253         }
1254         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1255         kfree(buf);
1256         return ret;
1257 }
1258
1259 static ssize_t iwl_dbgfs_rx_queue_read(struct file *file,
1260                                        char __user *user_buf,
1261                                        size_t count, loff_t *ppos)
1262 {
1263         struct iwl_trans *trans = file->private_data;
1264         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1265         struct iwl_rxq *rxq = &trans_pcie->rxq;
1266         char buf[256];
1267         int pos = 0;
1268         const size_t bufsz = sizeof(buf);
1269
1270         pos += scnprintf(buf + pos, bufsz - pos, "read: %u\n",
1271                                                 rxq->read);
1272         pos += scnprintf(buf + pos, bufsz - pos, "write: %u\n",
1273                                                 rxq->write);
1274         pos += scnprintf(buf + pos, bufsz - pos, "free_count: %u\n",
1275                                                 rxq->free_count);
1276         if (rxq->rb_stts) {
1277                 pos += scnprintf(buf + pos, bufsz - pos, "closed_rb_num: %u\n",
1278                          le16_to_cpu(rxq->rb_stts->closed_rb_num) &  0x0FFF);
1279         } else {
1280                 pos += scnprintf(buf + pos, bufsz - pos,
1281                                         "closed_rb_num: Not Allocated\n");
1282         }
1283         return simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1284 }
1285
1286 static ssize_t iwl_dbgfs_interrupt_read(struct file *file,
1287                                         char __user *user_buf,
1288                                         size_t count, loff_t *ppos)
1289 {
1290         struct iwl_trans *trans = file->private_data;
1291         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1292         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1293
1294         int pos = 0;
1295         char *buf;
1296         int bufsz = 24 * 64; /* 24 items * 64 char per item */
1297         ssize_t ret;
1298
1299         buf = kzalloc(bufsz, GFP_KERNEL);
1300         if (!buf)
1301                 return -ENOMEM;
1302
1303         pos += scnprintf(buf + pos, bufsz - pos,
1304                         "Interrupt Statistics Report:\n");
1305
1306         pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n",
1307                 isr_stats->hw);
1308         pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n",
1309                 isr_stats->sw);
1310         if (isr_stats->sw || isr_stats->hw) {
1311                 pos += scnprintf(buf + pos, bufsz - pos,
1312                         "\tLast Restarting Code:  0x%X\n",
1313                         isr_stats->err_code);
1314         }
1315 #ifdef CONFIG_IWLWIFI_DEBUG
1316         pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n",
1317                 isr_stats->sch);
1318         pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n",
1319                 isr_stats->alive);
1320 #endif
1321         pos += scnprintf(buf + pos, bufsz - pos,
1322                 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill);
1323
1324         pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n",
1325                 isr_stats->ctkill);
1326
1327         pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n",
1328                 isr_stats->wakeup);
1329
1330         pos += scnprintf(buf + pos, bufsz - pos,
1331                 "Rx command responses:\t\t %u\n", isr_stats->rx);
1332
1333         pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n",
1334                 isr_stats->tx);
1335
1336         pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n",
1337                 isr_stats->unhandled);
1338
1339         ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos);
1340         kfree(buf);
1341         return ret;
1342 }
1343
1344 static ssize_t iwl_dbgfs_interrupt_write(struct file *file,
1345                                          const char __user *user_buf,
1346                                          size_t count, loff_t *ppos)
1347 {
1348         struct iwl_trans *trans = file->private_data;
1349         struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1350         struct isr_statistics *isr_stats = &trans_pcie->isr_stats;
1351
1352         char buf[8];
1353         int buf_size;
1354         u32 reset_flag;
1355
1356         memset(buf, 0, sizeof(buf));
1357         buf_size = min(count, sizeof(buf) -  1);
1358         if (copy_from_user(buf, user_buf, buf_size))
1359                 return -EFAULT;
1360         if (sscanf(buf, "%x", &reset_flag) != 1)
1361                 return -EFAULT;
1362         if (reset_flag == 0)
1363                 memset(isr_stats, 0, sizeof(*isr_stats));
1364
1365         return count;
1366 }
1367
1368 static ssize_t iwl_dbgfs_csr_write(struct file *file,
1369                                    const char __user *user_buf,
1370                                    size_t count, loff_t *ppos)
1371 {
1372         struct iwl_trans *trans = file->private_data;
1373         char buf[8];
1374         int buf_size;
1375         int csr;
1376
1377         memset(buf, 0, sizeof(buf));
1378         buf_size = min(count, sizeof(buf) -  1);
1379         if (copy_from_user(buf, user_buf, buf_size))
1380                 return -EFAULT;
1381         if (sscanf(buf, "%d", &csr) != 1)
1382                 return -EFAULT;
1383
1384         iwl_pcie_dump_csr(trans);
1385
1386         return count;
1387 }
1388
1389 static ssize_t iwl_dbgfs_fh_reg_read(struct file *file,
1390                                      char __user *user_buf,
1391                                      size_t count, loff_t *ppos)
1392 {
1393         struct iwl_trans *trans = file->private_data;
1394         char *buf = NULL;
1395         int pos = 0;
1396         ssize_t ret = -EFAULT;
1397
1398         ret = pos = iwl_pcie_dump_fh(trans, &buf);
1399         if (buf) {
1400                 ret = simple_read_from_buffer(user_buf,
1401                                               count, ppos, buf, pos);
1402                 kfree(buf);
1403         }
1404
1405         return ret;
1406 }
1407
1408 DEBUGFS_READ_WRITE_FILE_OPS(interrupt);
1409 DEBUGFS_READ_FILE_OPS(fh_reg);
1410 DEBUGFS_READ_FILE_OPS(rx_queue);
1411 DEBUGFS_READ_FILE_OPS(tx_queue);
1412 DEBUGFS_WRITE_FILE_OPS(csr);
1413
1414 /*
1415  * Create the debugfs files and directories
1416  *
1417  */
1418 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1419                                          struct dentry *dir)
1420 {
1421         DEBUGFS_ADD_FILE(rx_queue, dir, S_IRUSR);
1422         DEBUGFS_ADD_FILE(tx_queue, dir, S_IRUSR);
1423         DEBUGFS_ADD_FILE(interrupt, dir, S_IWUSR | S_IRUSR);
1424         DEBUGFS_ADD_FILE(csr, dir, S_IWUSR);
1425         DEBUGFS_ADD_FILE(fh_reg, dir, S_IRUSR);
1426         return 0;
1427
1428 err:
1429         IWL_ERR(trans, "failed to create the trans debugfs entry\n");
1430         return -ENOMEM;
1431 }
1432 #else
1433 static int iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans,
1434                                          struct dentry *dir)
1435 {
1436         return 0;
1437 }
1438 #endif /*CONFIG_IWLWIFI_DEBUGFS */
1439
1440 static const struct iwl_trans_ops trans_ops_pcie = {
1441         .start_hw = iwl_trans_pcie_start_hw,
1442         .stop_hw = iwl_trans_pcie_stop_hw,
1443         .fw_alive = iwl_trans_pcie_fw_alive,
1444         .start_fw = iwl_trans_pcie_start_fw,
1445         .stop_device = iwl_trans_pcie_stop_device,
1446
1447         .d3_suspend = iwl_trans_pcie_d3_suspend,
1448         .d3_resume = iwl_trans_pcie_d3_resume,
1449
1450         .send_cmd = iwl_trans_pcie_send_hcmd,
1451
1452         .tx = iwl_trans_pcie_tx,
1453         .reclaim = iwl_trans_pcie_reclaim,
1454
1455         .txq_disable = iwl_trans_pcie_txq_disable,
1456         .txq_enable = iwl_trans_pcie_txq_enable,
1457
1458         .dbgfs_register = iwl_trans_pcie_dbgfs_register,
1459
1460         .wait_tx_queue_empty = iwl_trans_pcie_wait_txq_empty,
1461
1462 #ifdef CONFIG_PM_SLEEP
1463         .suspend = iwl_trans_pcie_suspend,
1464         .resume = iwl_trans_pcie_resume,
1465 #endif
1466         .write8 = iwl_trans_pcie_write8,
1467         .write32 = iwl_trans_pcie_write32,
1468         .read32 = iwl_trans_pcie_read32,
1469         .read_prph = iwl_trans_pcie_read_prph,
1470         .write_prph = iwl_trans_pcie_write_prph,
1471         .read_mem = iwl_trans_pcie_read_mem,
1472         .write_mem = iwl_trans_pcie_write_mem,
1473         .configure = iwl_trans_pcie_configure,
1474         .set_pmi = iwl_trans_pcie_set_pmi,
1475         .grab_nic_access = iwl_trans_pcie_grab_nic_access,
1476         .release_nic_access = iwl_trans_pcie_release_nic_access,
1477         .set_bits_mask = iwl_trans_pcie_set_bits_mask,
1478 };
1479
1480 struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
1481                                        const struct pci_device_id *ent,
1482                                        const struct iwl_cfg *cfg)
1483 {
1484         struct iwl_trans_pcie *trans_pcie;
1485         struct iwl_trans *trans;
1486         u16 pci_cmd;
1487         int err;
1488
1489         trans = kzalloc(sizeof(struct iwl_trans) +
1490                         sizeof(struct iwl_trans_pcie), GFP_KERNEL);
1491
1492         if (!trans)
1493                 return NULL;
1494
1495         trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
1496
1497         trans->ops = &trans_ops_pcie;
1498         trans->cfg = cfg;
1499         trans_lockdep_init(trans);
1500         trans_pcie->trans = trans;
1501         spin_lock_init(&trans_pcie->irq_lock);
1502         spin_lock_init(&trans_pcie->reg_lock);
1503         init_waitqueue_head(&trans_pcie->ucode_write_waitq);
1504
1505         /* W/A - seems to solve weird behavior. We need to remove this if we
1506          * don't want to stay in L1 all the time. This wastes a lot of power */
1507         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
1508                                PCIE_LINK_STATE_CLKPM);
1509
1510         if (pci_enable_device(pdev)) {
1511                 err = -ENODEV;
1512                 goto out_no_pci;
1513         }
1514
1515         pci_set_master(pdev);
1516
1517         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
1518         if (!err)
1519                 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
1520         if (err) {
1521                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1522                 if (!err)
1523                         err = pci_set_consistent_dma_mask(pdev,
1524                                                           DMA_BIT_MASK(32));
1525                 /* both attempts failed: */
1526                 if (err) {
1527                         dev_err(&pdev->dev, "No suitable DMA available\n");
1528                         goto out_pci_disable_device;
1529                 }
1530         }
1531
1532         err = pci_request_regions(pdev, DRV_NAME);
1533         if (err) {
1534                 dev_err(&pdev->dev, "pci_request_regions failed\n");
1535                 goto out_pci_disable_device;
1536         }
1537
1538         trans_pcie->hw_base = pci_ioremap_bar(pdev, 0);
1539         if (!trans_pcie->hw_base) {
1540                 dev_err(&pdev->dev, "pci_ioremap_bar failed\n");
1541                 err = -ENODEV;
1542                 goto out_pci_release_regions;
1543         }
1544
1545         /* We disable the RETRY_TIMEOUT register (0x41) to keep
1546          * PCI Tx retries from interfering with C3 CPU state */
1547         pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
1548
1549         err = pci_enable_msi(pdev);
1550         if (err) {
1551                 dev_err(&pdev->dev, "pci_enable_msi failed(0X%x)\n", err);
1552                 /* enable rfkill interrupt: hw bug w/a */
1553                 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
1554                 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
1555                         pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
1556                         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
1557                 }
1558         }
1559
1560         trans->dev = &pdev->dev;
1561         trans_pcie->pci_dev = pdev;
1562         trans->hw_rev = iwl_read32(trans, CSR_HW_REV);
1563         trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;
1564         snprintf(trans->hw_id_str, sizeof(trans->hw_id_str),
1565                  "PCI ID: 0x%04X:0x%04X", pdev->device, pdev->subsystem_device);
1566
1567         /* Initialize the wait queue for commands */
1568         init_waitqueue_head(&trans_pcie->wait_command_queue);
1569
1570         snprintf(trans->dev_cmd_pool_name, sizeof(trans->dev_cmd_pool_name),
1571                  "iwl_cmd_pool:%s", dev_name(trans->dev));
1572
1573         trans->dev_cmd_headroom = 0;
1574         trans->dev_cmd_pool =
1575                 kmem_cache_create(trans->dev_cmd_pool_name,
1576                                   sizeof(struct iwl_device_cmd)
1577                                   + trans->dev_cmd_headroom,
1578                                   sizeof(void *),
1579                                   SLAB_HWCACHE_ALIGN,
1580                                   NULL);
1581
1582         if (!trans->dev_cmd_pool)
1583                 goto out_pci_disable_msi;
1584
1585         trans_pcie->inta_mask = CSR_INI_SET_MASK;
1586
1587         if (iwl_pcie_alloc_ict(trans))
1588                 goto out_free_cmd_pool;
1589
1590         if (request_threaded_irq(pdev->irq, iwl_pcie_isr_ict,
1591                                  iwl_pcie_irq_handler,
1592                                  IRQF_SHARED, DRV_NAME, trans)) {
1593                 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq);
1594                 goto out_free_ict;
1595         }
1596
1597         return trans;
1598
1599 out_free_ict:
1600         iwl_pcie_free_ict(trans);
1601 out_free_cmd_pool:
1602         kmem_cache_destroy(trans->dev_cmd_pool);
1603 out_pci_disable_msi:
1604         pci_disable_msi(pdev);
1605 out_pci_release_regions:
1606         pci_release_regions(pdev);
1607 out_pci_disable_device:
1608         pci_disable_device(pdev);
1609 out_no_pci:
1610         kfree(trans);
1611         return NULL;
1612 }