drivers/nvme/host/pci.c

   1 /*
   2  * NVM Express device driver
   3  * Copyright (c) 2011-2014, Intel Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  */
  14
  15 #include <linux/aer.h>
  16 #include <linux/bitops.h>
  17 #include <linux/blkdev.h>
  18 #include <linux/blk-mq.h>
  19 #include <linux/blk-mq-pci.h>
  20 #include <linux/dmi.h>
  21 #include <linux/init.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/io.h>
  24 #include <linux/mm.h>
  25 #include <linux/module.h>
  26 #include <linux/mutex.h>
  27 #include <linux/pci.h>
  28 #include <linux/poison.h>
  29 #include <linux/t10-pi.h>
  30 #include <linux/timer.h>
  31 #include <linux/types.h>
  32 #include <linux/io-64-nonatomic-lo-hi.h>
  33 #include <asm/unaligned.h>
  34 #include <linux/sed-opal.h>
  35
  36 #include "nvme.h"
  37
  38 #define NVME_Q_DEPTH            1024
  39 #define NVME_AQ_DEPTH           256
  40 #define SQ_SIZE(depth)          (depth * sizeof(struct nvme_command))
  41 #define CQ_SIZE(depth)          (depth * sizeof(struct nvme_completion))
  42
  43 /*
  44  * We handle AEN commands ourselves and don't even let the
  45  * block layer know about them.
  46  */
  47 #define NVME_AQ_BLKMQ_DEPTH     (NVME_AQ_DEPTH - NVME_NR_AERS)
  48
  49 static int use_threaded_interrupts;
  50 module_param(use_threaded_interrupts, int, 0);
  51
  52 static bool use_cmb_sqes = true;
  53 module_param(use_cmb_sqes, bool, 0644);
  54 MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  55
  56 static unsigned int max_host_mem_size_mb = 128;
  57 module_param(max_host_mem_size_mb, uint, 0444);
  58 MODULE_PARM_DESC(max_host_mem_size_mb,
  59         "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  60
  61 struct nvme_dev;
  62 struct nvme_queue;
  63
  64 static void nvme_process_cq(struct nvme_queue *nvmeq);
  65 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
  66
  67 /*
  68  * Represents an NVM Express device.  Each nvme_dev is a PCI function.
  69  */
  70 struct nvme_dev {
  71         struct nvme_queue **queues;
  72         struct blk_mq_tag_set tagset;
  73         struct blk_mq_tag_set admin_tagset;
  74         u32 __iomem *dbs;
  75         struct device *dev;
  76         struct dma_pool *prp_page_pool;
  77         struct dma_pool *prp_small_pool;
  78         unsigned queue_count;
  79         unsigned online_queues;
  80         unsigned max_qid;
  81         int q_depth;
  82         u32 db_stride;
  83         void __iomem *bar;
  84         unsigned long bar_mapped_size;
  85         struct work_struct remove_work;
  86         struct mutex shutdown_lock;
  87         bool subsystem;
  88         void __iomem *cmb;
  89         dma_addr_t cmb_dma_addr;
  90         u64 cmb_size;
  91         u32 cmbsz;
  92         u32 cmbloc;
  93         struct nvme_ctrl ctrl;
  94         struct completion ioq_wait;
  95
  96         /* shadow doorbell buffer support: */
  97         u32 *dbbuf_dbs;
  98         dma_addr_t dbbuf_dbs_dma_addr;
  99         u32 *dbbuf_eis;
 100         dma_addr_t dbbuf_eis_dma_addr;
 101
 102         /* host memory buffer support: */
 103         u64 host_mem_size;
 104         u32 nr_host_mem_descs;
 105         struct nvme_host_mem_buf_desc *host_mem_descs;
 106         void **host_mem_desc_bufs;
 107 };
 108
 109 static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 110 {
 111         return qid * 2 * stride;
 112 }
 113
 114 static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 115 {
 116         return (qid * 2 + 1) * stride;
 117 }
 118
 119 static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 120 {
 121         return container_of(ctrl, struct nvme_dev, ctrl);
 122 }
 123
 124 /*
 125  * An NVM Express queue.  Each device has at least two (one for admin
 126  * commands and one for I/O commands).
 127  */
 128 struct nvme_queue {
 129         struct device *q_dmadev;
 130         struct nvme_dev *dev;
 131         spinlock_t q_lock;
 132         struct nvme_command *sq_cmds;
 133         struct nvme_command __iomem *sq_cmds_io;
 134         volatile struct nvme_completion *cqes;
 135         struct blk_mq_tags **tags;
 136         dma_addr_t sq_dma_addr;
 137         dma_addr_t cq_dma_addr;
 138         u32 __iomem *q_db;
 139         u16 q_depth;
 140         s16 cq_vector;
 141         u16 sq_tail;
 142         u16 cq_head;
 143         u16 qid;
 144         u8 cq_phase;
 145         u8 cqe_seen;
 146         u32 *dbbuf_sq_db;
 147         u32 *dbbuf_cq_db;
 148         u32 *dbbuf_sq_ei;
 149         u32 *dbbuf_cq_ei;
 150 };
 151
 152 /*
 153  * The nvme_iod describes the data in an I/O, including the list of PRP
 154  * entries.  You can't see it in this data structure because C doesn't let
 155  * me express that.  Use nvme_init_iod to ensure there's enough space
 156  * allocated to store the PRP list.
 157  */
 158 struct nvme_iod {
 159         struct nvme_request req;
 160         struct nvme_queue *nvmeq;
 161         int aborted;
 162         int npages;             /* In the PRP list. 0 means small pool in use */
 163         int nents;              /* Used in scatterlist */
 164         int length;             /* Of data, in bytes */
 165         dma_addr_t first_dma;
 166         struct scatterlist meta_sg; /* metadata requires single contiguous buffer */
 167         struct scatterlist *sg;
 168         struct scatterlist inline_sg[0];
 169 };
 170
 171 /*
 172  * Check we didin't inadvertently grow the command struct
 173  */
 174 static inline void _nvme_check_size(void)
 175 {
 176         BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
 177         BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
 178         BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
 179         BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
 180         BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
 181         BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
 182         BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
 183         BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
 184         BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != NVME_IDENTIFY_DATA_SIZE);
 185         BUILD_BUG_ON(sizeof(struct nvme_id_ns) != NVME_IDENTIFY_DATA_SIZE);
 186         BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
 187         BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
 188         BUILD_BUG_ON(sizeof(struct nvme_dbbuf) != 64);
 189 }
 190
 191 static inline unsigned int nvme_dbbuf_size(u32 stride)
 192 {
 193         return ((num_possible_cpus() + 1) * 8 * stride);
 194 }
 195
 196 static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 197 {
 198         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 199
 200         if (dev->dbbuf_dbs)
 201                 return 0;
 202
 203         dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 204                                             &dev->dbbuf_dbs_dma_addr,
 205                                             GFP_KERNEL);
 206         if (!dev->dbbuf_dbs)
 207                 return -ENOMEM;
 208         dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 209                                             &dev->dbbuf_eis_dma_addr,
 210                                             GFP_KERNEL);
 211         if (!dev->dbbuf_eis) {
 212                 dma_free_coherent(dev->dev, mem_size,
 213                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 214                 dev->dbbuf_dbs = NULL;
 215                 return -ENOMEM;
 216         }
 217
 218         return 0;
 219 }
 220
 221 static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 222 {
 223         unsigned int mem_size = nvme_dbbuf_size(dev->db_stride);
 224
 225         if (dev->dbbuf_dbs) {
 226                 dma_free_coherent(dev->dev, mem_size,
 227                                   dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 228                 dev->dbbuf_dbs = NULL;
 229         }
 230         if (dev->dbbuf_eis) {
 231                 dma_free_coherent(dev->dev, mem_size,
 232                                   dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 233                 dev->dbbuf_eis = NULL;
 234         }
 235 }
 236
 237 static void nvme_dbbuf_init(struct nvme_dev *dev,
 238                             struct nvme_queue *nvmeq, int qid)
 239 {
 240         if (!dev->dbbuf_dbs || !qid)
 241                 return;
 242
 243         nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 244         nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 245         nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 246         nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 247 }
 248
 249 static void nvme_dbbuf_set(struct nvme_dev *dev)
 250 {
 251         struct nvme_command c;
 252
 253         if (!dev->dbbuf_dbs)
 254                 return;
 255
 256         memset(&c, 0, sizeof(c));
 257         c.dbbuf.opcode = nvme_admin_dbbuf;
 258         c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 259         c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 260
 261         if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 262                 dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 263                 /* Free memory and continue on */
 264                 nvme_dbbuf_dma_free(dev);
 265         }
 266 }
 267
 268 static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 269 {
 270         return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 271 }
 272
 273 /* Update dbbuf and return true if an MMIO is required */
 274 static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 275                                               volatile u32 *dbbuf_ei)
 276 {
 277         if (dbbuf_db) {
 278                 u16 old_value;
 279
 280                 /*
 281                  * Ensure that the queue is written before updating
 282                  * the doorbell in memory
 283                  */
 284                 wmb();
 285
 286                 old_value = *dbbuf_db;
 287                 *dbbuf_db = value;
 288
 289                 if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 290                         return false;
 291         }
 292
 293         return true;
 294 }
 295
 296 /*
 297  * Max size of iod being embedded in the request payload
 298  */
 299 #define NVME_INT_PAGES          2
 300 #define NVME_INT_BYTES(dev)     (NVME_INT_PAGES * (dev)->ctrl.page_size)
 301
 302 /*
 303  * Will slightly overestimate the number of pages needed.  This is OK
 304  * as it only leads to a small amount of wasted memory for the lifetime of
 305  * the I/O.
 306  */
 307 static int nvme_npages(unsigned size, struct nvme_dev *dev)
 308 {
 309         unsigned nprps = DIV_ROUND_UP(size + dev->ctrl.page_size,
 310                                       dev->ctrl.page_size);
 311         return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 312 }
 313
 314 static unsigned int nvme_iod_alloc_size(struct nvme_dev *dev,
 315                 unsigned int size, unsigned int nseg)
 316 {
 317         return sizeof(__le64 *) * nvme_npages(size, dev) +
 318                         sizeof(struct scatterlist) * nseg;
 319 }
 320
 321 static unsigned int nvme_cmd_size(struct nvme_dev *dev)
 322 {
 323         return sizeof(struct nvme_iod) +
 324                 nvme_iod_alloc_size(dev, NVME_INT_BYTES(dev), NVME_INT_PAGES);
 325 }
 326
 327 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 328                                 unsigned int hctx_idx)
 329 {
 330         struct nvme_dev *dev = data;
 331         struct nvme_queue *nvmeq = dev->queues[0];
 332
 333         WARN_ON(hctx_idx != 0);
 334         WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 335         WARN_ON(nvmeq->tags);
 336
 337         hctx->driver_data = nvmeq;
 338         nvmeq->tags = &dev->admin_tagset.tags[0];
 339         return 0;
 340 }
 341
 342 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx *hctx, unsigned int hctx_idx)
 343 {
 344         struct nvme_queue *nvmeq = hctx->driver_data;
 345
 346         nvmeq->tags = NULL;
 347 }
 348
 349 static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 350                           unsigned int hctx_idx)
 351 {
 352         struct nvme_dev *dev = data;
 353         struct nvme_queue *nvmeq = dev->queues[hctx_idx + 1];
 354
 355         if (!nvmeq->tags)
 356                 nvmeq->tags = &dev->tagset.tags[hctx_idx];
 357
 358         WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 359         hctx->driver_data = nvmeq;
 360         return 0;
 361 }
 362
 363 static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 364                 unsigned int hctx_idx, unsigned int numa_node)
 365 {
 366         struct nvme_dev *dev = set->driver_data;
 367         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 368         int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 369         struct nvme_queue *nvmeq = dev->queues[queue_idx];
 370
 371         BUG_ON(!nvmeq);
 372         iod->nvmeq = nvmeq;
 373         return 0;
 374 }
 375
 376 static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 377 {
 378         struct nvme_dev *dev = set->driver_data;
 379
 380         return blk_mq_pci_map_queues(set, to_pci_dev(dev->dev));
 381 }
 382
 383 /**
 384  * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 385  * @nvmeq: The queue to use
 386  * @cmd: The command to send
 387  *
 388  * Safe to use from interrupt context
 389  */
 390 static void __nvme_submit_cmd(struct nvme_queue *nvmeq,
 391                                                 struct nvme_command *cmd)
 392 {
 393         u16 tail = nvmeq->sq_tail;
 394
 395         if (nvmeq->sq_cmds_io)
 396                 memcpy_toio(&nvmeq->sq_cmds_io[tail], cmd, sizeof(*cmd));
 397         else
 398                 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
 399
 400         if (++tail == nvmeq->q_depth)
 401                 tail = 0;
 402         if (nvme_dbbuf_update_and_check_event(tail, nvmeq->dbbuf_sq_db,
 403                                               nvmeq->dbbuf_sq_ei))
 404                 writel(tail, nvmeq->q_db);
 405         nvmeq->sq_tail = tail;
 406 }
 407
 408 static __le64 **iod_list(struct request *req)
 409 {
 410         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 411         return (__le64 **)(iod->sg + blk_rq_nr_phys_segments(req));
 412 }
 413
 414 static blk_status_t nvme_init_iod(struct request *rq, struct nvme_dev *dev)
 415 {
 416         struct nvme_iod *iod = blk_mq_rq_to_pdu(rq);
 417         int nseg = blk_rq_nr_phys_segments(rq);
 418         unsigned int size = blk_rq_payload_bytes(rq);
 419
 420         if (nseg > NVME_INT_PAGES || size > NVME_INT_BYTES(dev)) {
 421                 iod->sg = kmalloc(nvme_iod_alloc_size(dev, size, nseg), GFP_ATOMIC);
 422                 if (!iod->sg)
 423                         return BLK_STS_RESOURCE;
 424         } else {
 425                 iod->sg = iod->inline_sg;
 426         }
 427
 428         iod->aborted = 0;
 429         iod->npages = -1;
 430         iod->nents = 0;
 431         iod->length = size;
 432
 433         return BLK_STS_OK;
 434 }
 435
 436 static void nvme_free_iod(struct nvme_dev *dev, struct request *req)
 437 {
 438         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 439         const int last_prp = dev->ctrl.page_size / 8 - 1;
 440         int i;
 441         __le64 **list = iod_list(req);
 442         dma_addr_t prp_dma = iod->first_dma;
 443
 444         if (iod->npages == 0)
 445                 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
 446         for (i = 0; i < iod->npages; i++) {
 447                 __le64 *prp_list = list[i];
 448                 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
 449                 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
 450                 prp_dma = next_prp_dma;
 451         }
 452
 453         if (iod->sg != iod->inline_sg)
 454                 kfree(iod->sg);
 455 }
 456
 457 #ifdef CONFIG_BLK_DEV_INTEGRITY
 458 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 459 {
 460         if (be32_to_cpu(pi->ref_tag) == v)
 461                 pi->ref_tag = cpu_to_be32(p);
 462 }
 463
 464 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 465 {
 466         if (be32_to_cpu(pi->ref_tag) == p)
 467                 pi->ref_tag = cpu_to_be32(v);
 468 }
 469
 470 /**
 471  * nvme_dif_remap - remaps ref tags to bip seed and physical lba
 472  *
 473  * The virtual start sector is the one that was originally submitted by the
 474  * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
 475  * start sector may be different. Remap protection information to match the
 476  * physical LBA on writes, and back to the original seed on reads.
 477  *
 478  * Type 0 and 3 do not have a ref tag, so no remapping required.
 479  */
 480 static void nvme_dif_remap(struct request *req,
 481                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 482 {
 483         struct nvme_ns *ns = req->rq_disk->private_data;
 484         struct bio_integrity_payload *bip;
 485         struct t10_pi_tuple *pi;
 486         void *p, *pmap;
 487         u32 i, nlb, ts, phys, virt;
 488
 489         if (!ns->pi_type || ns->pi_type == NVME_NS_DPS_PI_TYPE3)
 490                 return;
 491
 492         bip = bio_integrity(req->bio);
 493         if (!bip)
 494                 return;
 495
 496         pmap = kmap_atomic(bip->bip_vec->bv_page) + bip->bip_vec->bv_offset;
 497
 498         p = pmap;
 499         virt = bip_get_seed(bip);
 500         phys = nvme_block_nr(ns, blk_rq_pos(req));
 501         nlb = (blk_rq_bytes(req) >> ns->lba_shift);
 502         ts = ns->disk->queue->integrity.tuple_size;
 503
 504         for (i = 0; i < nlb; i++, virt++, phys++) {
 505                 pi = (struct t10_pi_tuple *)p;
 506                 dif_swap(phys, virt, pi);
 507                 p += ts;
 508         }
 509         kunmap_atomic(pmap);
 510 }
 511 #else /* CONFIG_BLK_DEV_INTEGRITY */
 512 static void nvme_dif_remap(struct request *req,
 513                         void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
 514 {
 515 }
 516 static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
 517 {
 518 }
 519 static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
 520 {
 521 }
 522 #endif
 523
 524 static bool nvme_setup_prps(struct nvme_dev *dev, struct request *req)
 525 {
 526         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 527         struct dma_pool *pool;
 528         int length = blk_rq_payload_bytes(req);
 529         struct scatterlist *sg = iod->sg;
 530         int dma_len = sg_dma_len(sg);
 531         u64 dma_addr = sg_dma_address(sg);
 532         u32 page_size = dev->ctrl.page_size;
 533         int offset = dma_addr & (page_size - 1);
 534         __le64 *prp_list;
 535         __le64 **list = iod_list(req);
 536         dma_addr_t prp_dma;
 537         int nprps, i;
 538
 539         length -= (page_size - offset);
 540         if (length <= 0)
 541                 return true;
 542
 543         dma_len -= (page_size - offset);
 544         if (dma_len) {
 545                 dma_addr += (page_size - offset);
 546         } else {
 547                 sg = sg_next(sg);
 548                 dma_addr = sg_dma_address(sg);
 549                 dma_len = sg_dma_len(sg);
 550         }
 551
 552         if (length <= page_size) {
 553                 iod->first_dma = dma_addr;
 554                 return true;
 555         }
 556
 557         nprps = DIV_ROUND_UP(length, page_size);
 558         if (nprps <= (256 / 8)) {
 559                 pool = dev->prp_small_pool;
 560                 iod->npages = 0;
 561         } else {
 562                 pool = dev->prp_page_pool;
 563                 iod->npages = 1;
 564         }
 565
 566         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 567         if (!prp_list) {
 568                 iod->first_dma = dma_addr;
 569                 iod->npages = -1;
 570                 return false;
 571         }
 572         list[0] = prp_list;
 573         iod->first_dma = prp_dma;
 574         i = 0;
 575         for (;;) {
 576                 if (i == page_size >> 3) {
 577                         __le64 *old_prp_list = prp_list;
 578                         prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 579                         if (!prp_list)
 580                                 return false;
 581                         list[iod->npages++] = prp_list;
 582                         prp_list[0] = old_prp_list[i - 1];
 583                         old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 584                         i = 1;
 585                 }
 586                 prp_list[i++] = cpu_to_le64(dma_addr);
 587                 dma_len -= page_size;
 588                 dma_addr += page_size;
 589                 length -= page_size;
 590                 if (length <= 0)
 591                         break;
 592                 if (dma_len > 0)
 593                         continue;
 594                 BUG_ON(dma_len < 0);
 595                 sg = sg_next(sg);
 596                 dma_addr = sg_dma_address(sg);
 597                 dma_len = sg_dma_len(sg);
 598         }
 599
 600         return true;
 601 }
 602
 603 static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 604                 struct nvme_command *cmnd)
 605 {
 606         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 607         struct request_queue *q = req->q;
 608         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 609                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 610         blk_status_t ret = BLK_STS_IOERR;
 611
 612         sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 613         iod->nents = blk_rq_map_sg(q, req, iod->sg);
 614         if (!iod->nents)
 615                 goto out;
 616
 617         ret = BLK_STS_RESOURCE;
 618         if (!dma_map_sg_attrs(dev->dev, iod->sg, iod->nents, dma_dir,
 619                                 DMA_ATTR_NO_WARN))
 620                 goto out;
 621
 622         if (!nvme_setup_prps(dev, req))
 623                 goto out_unmap;
 624
 625         ret = BLK_STS_IOERR;
 626         if (blk_integrity_rq(req)) {
 627                 if (blk_rq_count_integrity_sg(q, req->bio) != 1)
 628                         goto out_unmap;
 629
 630                 sg_init_table(&iod->meta_sg, 1);
 631                 if (blk_rq_map_integrity_sg(q, req->bio, &iod->meta_sg) != 1)
 632                         goto out_unmap;
 633
 634                 if (rq_data_dir(req))
 635                         nvme_dif_remap(req, nvme_dif_prep);
 636
 637                 if (!dma_map_sg(dev->dev, &iod->meta_sg, 1, dma_dir))
 638                         goto out_unmap;
 639         }
 640
 641         cmnd->rw.dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 642         cmnd->rw.dptr.prp2 = cpu_to_le64(iod->first_dma);
 643         if (blk_integrity_rq(req))
 644                 cmnd->rw.metadata = cpu_to_le64(sg_dma_address(&iod->meta_sg));
 645         return BLK_STS_OK;
 646
 647 out_unmap:
 648         dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 649 out:
 650         return ret;
 651 }
 652
 653 static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 654 {
 655         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 656         enum dma_data_direction dma_dir = rq_data_dir(req) ?
 657                         DMA_TO_DEVICE : DMA_FROM_DEVICE;
 658
 659         if (iod->nents) {
 660                 dma_unmap_sg(dev->dev, iod->sg, iod->nents, dma_dir);
 661                 if (blk_integrity_rq(req)) {
 662                         if (!rq_data_dir(req))
 663                                 nvme_dif_remap(req, nvme_dif_complete);
 664                         dma_unmap_sg(dev->dev, &iod->meta_sg, 1, dma_dir);
 665                 }
 666         }
 667
 668         nvme_cleanup_cmd(req);
 669         nvme_free_iod(dev, req);
 670 }
 671
 672 /*
 673  * NOTE: ns is NULL when called on the admin queue.
 674  */
 675 static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 676                          const struct blk_mq_queue_data *bd)
 677 {
 678         struct nvme_ns *ns = hctx->queue->queuedata;
 679         struct nvme_queue *nvmeq = hctx->driver_data;
 680         struct nvme_dev *dev = nvmeq->dev;
 681         struct request *req = bd->rq;
 682         struct nvme_command cmnd;
 683         blk_status_t ret;
 684
 685         ret = nvme_setup_cmd(ns, req, &cmnd);
 686         if (ret)
 687                 return ret;
 688
 689         ret = nvme_init_iod(req, dev);
 690         if (ret)
 691                 goto out_free_cmd;
 692
 693         if (blk_rq_nr_phys_segments(req)) {
 694                 ret = nvme_map_data(dev, req, &cmnd);
 695                 if (ret)
 696                         goto out_cleanup_iod;
 697         }
 698
 699         blk_mq_start_request(req);
 700
 701         spin_lock_irq(&nvmeq->q_lock);
 702         if (unlikely(nvmeq->cq_vector < 0)) {
 703                 ret = BLK_STS_IOERR;
 704                 spin_unlock_irq(&nvmeq->q_lock);
 705                 goto out_cleanup_iod;
 706         }
 707         __nvme_submit_cmd(nvmeq, &cmnd);
 708         nvme_process_cq(nvmeq);
 709         spin_unlock_irq(&nvmeq->q_lock);
 710         return BLK_STS_OK;
 711 out_cleanup_iod:
 712         nvme_free_iod(dev, req);
 713 out_free_cmd:
 714         nvme_cleanup_cmd(req);
 715         return ret;
 716 }
 717
 718 static void nvme_pci_complete_rq(struct request *req)
 719 {
 720         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 721
 722         nvme_unmap_data(iod->nvmeq->dev, req);
 723         nvme_complete_rq(req);
 724 }
 725
 726 /* We read the CQE phase first to check if the rest of the entry is valid */
 727 static inline bool nvme_cqe_valid(struct nvme_queue *nvmeq, u16 head,
 728                 u16 phase)
 729 {
 730         return (le16_to_cpu(nvmeq->cqes[head].status) & 1) == phase;
 731 }
 732
 733 static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 734 {
 735         u16 head = nvmeq->cq_head;
 736
 737         if (likely(nvmeq->cq_vector >= 0)) {
 738                 if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 739                                                       nvmeq->dbbuf_cq_ei))
 740                         writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 741         }
 742 }
 743
 744 static inline void nvme_handle_cqe(struct nvme_queue *nvmeq,
 745                 struct nvme_completion *cqe)
 746 {
 747         struct request *req;
 748
 749         if (unlikely(cqe->command_id >= nvmeq->q_depth)) {
 750                 dev_warn(nvmeq->dev->ctrl.device,
 751                         "invalid id %d completed on queue %d\n",
 752                         cqe->command_id, le16_to_cpu(cqe->sq_id));
 753                 return;
 754         }
 755
 756         /*
 757          * AEN requests are special as they don't time out and can
 758          * survive any kind of queue freeze and often don't respond to
 759          * aborts.  We don't even bother to allocate a struct request
 760          * for them but rather special case them here.
 761          */
 762         if (unlikely(nvmeq->qid == 0 &&
 763                         cqe->command_id >= NVME_AQ_BLKMQ_DEPTH)) {
 764                 nvme_complete_async_event(&nvmeq->dev->ctrl,
 765                                 cqe->status, &cqe->result);
 766                 return;
 767         }
 768
 769         req = blk_mq_tag_to_rq(*nvmeq->tags, cqe->command_id);
 770         nvme_end_request(req, cqe->status, cqe->result);
 771 }
 772
 773 static inline bool nvme_read_cqe(struct nvme_queue *nvmeq,
 774                 struct nvme_completion *cqe)
 775 {
 776         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 777                 *cqe = nvmeq->cqes[nvmeq->cq_head];
 778
 779                 if (++nvmeq->cq_head == nvmeq->q_depth) {
 780                         nvmeq->cq_head = 0;
 781                         nvmeq->cq_phase = !nvmeq->cq_phase;
 782                 }
 783                 return true;
 784         }
 785         return false;
 786 }
 787
 788 static void __nvme_process_cq(struct nvme_queue *nvmeq, int *tag)
 789 {
 790         struct nvme_completion cqe;
 791         int consumed = 0;
 792
 793         while (nvme_read_cqe(nvmeq, &cqe)) {
 794                 nvme_handle_cqe(nvmeq, &cqe);
 795                 consumed++;
 796
 797                 if (tag && *tag == cqe.command_id) {
 798                         *tag = -1;
 799                         break;
 800                 }
 801         }
 802
 803         if (consumed) {
 804                 nvme_ring_cq_doorbell(nvmeq);
 805                 nvmeq->cqe_seen = 1;
 806         }
 807 }
 808
 809 static void nvme_process_cq(struct nvme_queue *nvmeq)
 810 {
 811         __nvme_process_cq(nvmeq, NULL);
 812 }
 813
 814 static irqreturn_t nvme_irq(int irq, void *data)
 815 {
 816         irqreturn_t result;
 817         struct nvme_queue *nvmeq = data;
 818         spin_lock(&nvmeq->q_lock);
 819         nvme_process_cq(nvmeq);
 820         result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
 821         nvmeq->cqe_seen = 0;
 822         spin_unlock(&nvmeq->q_lock);
 823         return result;
 824 }
 825
 826 static irqreturn_t nvme_irq_check(int irq, void *data)
 827 {
 828         struct nvme_queue *nvmeq = data;
 829         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase))
 830                 return IRQ_WAKE_THREAD;
 831         return IRQ_NONE;
 832 }
 833
 834 static int __nvme_poll(struct nvme_queue *nvmeq, unsigned int tag)
 835 {
 836         if (nvme_cqe_valid(nvmeq, nvmeq->cq_head, nvmeq->cq_phase)) {
 837                 spin_lock_irq(&nvmeq->q_lock);
 838                 __nvme_process_cq(nvmeq, &tag);
 839                 spin_unlock_irq(&nvmeq->q_lock);
 840
 841                 if (tag == -1)
 842                         return 1;
 843         }
 844
 845         return 0;
 846 }
 847
 848 static int nvme_poll(struct blk_mq_hw_ctx *hctx, unsigned int tag)
 849 {
 850         struct nvme_queue *nvmeq = hctx->driver_data;
 851
 852         return __nvme_poll(nvmeq, tag);
 853 }
 854
 855 static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl, int aer_idx)
 856 {
 857         struct nvme_dev *dev = to_nvme_dev(ctrl);
 858         struct nvme_queue *nvmeq = dev->queues[0];
 859         struct nvme_command c;
 860
 861         memset(&c, 0, sizeof(c));
 862         c.common.opcode = nvme_admin_async_event;
 863         c.common.command_id = NVME_AQ_BLKMQ_DEPTH + aer_idx;
 864
 865         spin_lock_irq(&nvmeq->q_lock);
 866         __nvme_submit_cmd(nvmeq, &c);
 867         spin_unlock_irq(&nvmeq->q_lock);
 868 }
 869
 870 static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
 871 {
 872         struct nvme_command c;
 873
 874         memset(&c, 0, sizeof(c));
 875         c.delete_queue.opcode = opcode;
 876         c.delete_queue.qid = cpu_to_le16(id);
 877
 878         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 879 }
 880
 881 static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
 882                                                 struct nvme_queue *nvmeq)
 883 {
 884         struct nvme_command c;
 885         int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
 886
 887         /*
 888          * Note: we (ab)use the fact the the prp fields survive if no data
 889          * is attached to the request.
 890          */
 891         memset(&c, 0, sizeof(c));
 892         c.create_cq.opcode = nvme_admin_create_cq;
 893         c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
 894         c.create_cq.cqid = cpu_to_le16(qid);
 895         c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 896         c.create_cq.cq_flags = cpu_to_le16(flags);
 897         c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
 898
 899         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 900 }
 901
 902 static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
 903                                                 struct nvme_queue *nvmeq)
 904 {
 905         struct nvme_command c;
 906         int flags = NVME_QUEUE_PHYS_CONTIG;
 907
 908         /*
 909          * Note: we (ab)use the fact the the prp fields survive if no data
 910          * is attached to the request.
 911          */
 912         memset(&c, 0, sizeof(c));
 913         c.create_sq.opcode = nvme_admin_create_sq;
 914         c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
 915         c.create_sq.sqid = cpu_to_le16(qid);
 916         c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
 917         c.create_sq.sq_flags = cpu_to_le16(flags);
 918         c.create_sq.cqid = cpu_to_le16(qid);
 919
 920         return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
 921 }
 922
 923 static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
 924 {
 925         return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
 926 }
 927
 928 static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
 929 {
 930         return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
 931 }
 932
 933 static void abort_endio(struct request *req, blk_status_t error)
 934 {
 935         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 936         struct nvme_queue *nvmeq = iod->nvmeq;
 937
 938         dev_warn(nvmeq->dev->ctrl.device,
 939                  "Abort status: 0x%x", nvme_req(req)->status);
 940         atomic_inc(&nvmeq->dev->ctrl.abort_limit);
 941         blk_mq_free_request(req);
 942 }
 943
 944 static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
 945 {
 946
 947         /* If true, indicates loss of adapter communication, possibly by a
 948          * NVMe Subsystem reset.
 949          */
 950         bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
 951
 952         /* If there is a reset ongoing, we shouldn't reset again. */
 953         if (dev->ctrl.state == NVME_CTRL_RESETTING)
 954                 return false;
 955
 956         /* We shouldn't reset unless the controller is on fatal error state
 957          * _or_ if we lost the communication with it.
 958          */
 959         if (!(csts & NVME_CSTS_CFS) && !nssro)
 960                 return false;
 961
 962         /* If PCI error recovery process is happening, we cannot reset or
 963          * the recovery mechanism will surely fail.
 964          */
 965         if (pci_channel_offline(to_pci_dev(dev->dev)))
 966                 return false;
 967
 968         return true;
 969 }
 970
 971 static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
 972 {
 973         /* Read a config register to help see what died. */
 974         u16 pci_status;
 975         int result;
 976
 977         result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
 978                                       &pci_status);
 979         if (result == PCIBIOS_SUCCESSFUL)
 980                 dev_warn(dev->ctrl.device,
 981                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
 982                          csts, pci_status);
 983         else
 984                 dev_warn(dev->ctrl.device,
 985                          "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
 986                          csts, result);
 987 }
 988
 989 static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
 990 {
 991         struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 992         struct nvme_queue *nvmeq = iod->nvmeq;
 993         struct nvme_dev *dev = nvmeq->dev;
 994         struct request *abort_req;
 995         struct nvme_command cmd;
 996         u32 csts = readl(dev->bar + NVME_REG_CSTS);
 997
 998         /*
 999          * Reset immediately if the controller is failed
1000          */
1001         if (nvme_should_reset(dev, csts)) {
1002                 nvme_warn_reset(dev, csts);
1003                 nvme_dev_disable(dev, false);
1004                 nvme_reset_ctrl(&dev->ctrl);
1005                 return BLK_EH_HANDLED;
1006         }
1007
1008         /*
1009          * Did we miss an interrupt?
1010          */
1011         if (__nvme_poll(nvmeq, req->tag)) {
1012                 dev_warn(dev->ctrl.device,
1013                          "I/O %d QID %d timeout, completion polled\n",
1014                          req->tag, nvmeq->qid);
1015                 return BLK_EH_HANDLED;
1016         }
1017
1018         /*
1019          * Shutdown immediately if controller times out while starting. The
1020          * reset work will see the pci device disabled when it gets the forced
1021          * cancellation error. All outstanding requests are completed on
1022          * shutdown, so we return BLK_EH_HANDLED.
1023          */
1024         if (dev->ctrl.state == NVME_CTRL_RESETTING) {
1025                 dev_warn(dev->ctrl.device,
1026                          "I/O %d QID %d timeout, disable controller\n",
1027                          req->tag, nvmeq->qid);
1028                 nvme_dev_disable(dev, false);
1029                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1030                 return BLK_EH_HANDLED;
1031         }
1032
1033         /*
1034          * Shutdown the controller immediately and schedule a reset if the
1035          * command was already aborted once before and still hasn't been
1036          * returned to the driver, or if this is the admin queue.
1037          */
1038         if (!nvmeq->qid || iod->aborted) {
1039                 dev_warn(dev->ctrl.device,
1040                          "I/O %d QID %d timeout, reset controller\n",
1041                          req->tag, nvmeq->qid);
1042                 nvme_dev_disable(dev, false);
1043                 nvme_reset_ctrl(&dev->ctrl);
1044
1045                 /*
1046                  * Mark the request as handled, since the inline shutdown
1047                  * forces all outstanding requests to complete.
1048                  */
1049                 nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1050                 return BLK_EH_HANDLED;
1051         }
1052
1053         if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1054                 atomic_inc(&dev->ctrl.abort_limit);
1055                 return BLK_EH_RESET_TIMER;
1056         }
1057         iod->aborted = 1;
1058
1059         memset(&cmd, 0, sizeof(cmd));
1060         cmd.abort.opcode = nvme_admin_abort_cmd;
1061         cmd.abort.cid = req->tag;
1062         cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1063
1064         dev_warn(nvmeq->dev->ctrl.device,
1065                 "I/O %d QID %d timeout, aborting\n",
1066                  req->tag, nvmeq->qid);
1067
1068         abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1069                         BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1070         if (IS_ERR(abort_req)) {
1071                 atomic_inc(&dev->ctrl.abort_limit);
1072                 return BLK_EH_RESET_TIMER;
1073         }
1074
1075         abort_req->timeout = ADMIN_TIMEOUT;
1076         abort_req->end_io_data = NULL;
1077         blk_execute_rq_nowait(abort_req->q, NULL, abort_req, 0, abort_endio);
1078
1079         /*
1080          * The aborted req will be completed on receiving the abort req.
1081          * We enable the timer again. If hit twice, it'll cause a device reset,
1082          * as the device then is in a faulty state.
1083          */
1084         return BLK_EH_RESET_TIMER;
1085 }
1086
1087 static void nvme_free_queue(struct nvme_queue *nvmeq)
1088 {
1089         dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1090                                 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1091         if (nvmeq->sq_cmds)
1092                 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1093                                         nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1094         kfree(nvmeq);
1095 }
1096
1097 static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1098 {
1099         int i;
1100
1101         for (i = dev->queue_count - 1; i >= lowest; i--) {
1102                 struct nvme_queue *nvmeq = dev->queues[i];
1103                 dev->queue_count--;
1104                 dev->queues[i] = NULL;
1105                 nvme_free_queue(nvmeq);
1106         }
1107 }
1108
1109 /**
1110  * nvme_suspend_queue - put queue into suspended state
1111  * @nvmeq - queue to suspend
1112  */
1113 static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1114 {
1115         int vector;
1116
1117         spin_lock_irq(&nvmeq->q_lock);
1118         if (nvmeq->cq_vector == -1) {
1119                 spin_unlock_irq(&nvmeq->q_lock);
1120                 return 1;
1121         }
1122         vector = nvmeq->cq_vector;
1123         nvmeq->dev->online_queues--;
1124         nvmeq->cq_vector = -1;
1125         spin_unlock_irq(&nvmeq->q_lock);
1126
1127         if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1128                 blk_mq_stop_hw_queues(nvmeq->dev->ctrl.admin_q);
1129
1130         pci_free_irq(to_pci_dev(nvmeq->dev->dev), vector, nvmeq);
1131
1132         return 0;
1133 }
1134
1135 static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1136 {
1137         struct nvme_queue *nvmeq = dev->queues[0];
1138
1139         if (!nvmeq)
1140                 return;
1141         if (nvme_suspend_queue(nvmeq))
1142                 return;
1143
1144         if (shutdown)
1145                 nvme_shutdown_ctrl(&dev->ctrl);
1146         else
1147                 nvme_disable_ctrl(&dev->ctrl, lo_hi_readq(
1148                                                 dev->bar + NVME_REG_CAP));
1149
1150         spin_lock_irq(&nvmeq->q_lock);
1151         nvme_process_cq(nvmeq);
1152         spin_unlock_irq(&nvmeq->q_lock);
1153 }
1154
1155 static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1156                                 int entry_size)
1157 {
1158         int q_depth = dev->q_depth;
1159         unsigned q_size_aligned = roundup(q_depth * entry_size,
1160                                           dev->ctrl.page_size);
1161
1162         if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1163                 u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1164                 mem_per_q = round_down(mem_per_q, dev->ctrl.page_size);
1165                 q_depth = div_u64(mem_per_q, entry_size);
1166
1167                 /*
1168                  * Ensure the reduced q_depth is above some threshold where it
1169                  * would be better to map queues in system memory with the
1170                  * original depth
1171                  */
1172                 if (q_depth < 64)
1173                         return -ENOMEM;
1174         }
1175
1176         return q_depth;
1177 }
1178
1179 static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1180                                 int qid, int depth)
1181 {
1182         if (qid && dev->cmb && use_cmb_sqes && NVME_CMB_SQS(dev->cmbsz)) {
1183                 unsigned offset = (qid - 1) * roundup(SQ_SIZE(depth),
1184                                                       dev->ctrl.page_size);
1185                 nvmeq->sq_dma_addr = dev->cmb_dma_addr + offset;
1186                 nvmeq->sq_cmds_io = dev->cmb + offset;
1187         } else {
1188                 nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(depth),
1189                                         &nvmeq->sq_dma_addr, GFP_KERNEL);
1190                 if (!nvmeq->sq_cmds)
1191                         return -ENOMEM;
1192         }
1193
1194         return 0;
1195 }
1196
1197 static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1198                                                         int depth, int node)
1199 {
1200         struct nvme_queue *nvmeq = kzalloc_node(sizeof(*nvmeq), GFP_KERNEL,
1201                                                         node);
1202         if (!nvmeq)
1203                 return NULL;
1204
1205         nvmeq->cqes = dma_zalloc_coherent(dev->dev, CQ_SIZE(depth),
1206                                           &nvmeq->cq_dma_addr, GFP_KERNEL);
1207         if (!nvmeq->cqes)
1208                 goto free_nvmeq;
1209
1210         if (nvme_alloc_sq_cmds(dev, nvmeq, qid, depth))
1211                 goto free_cqdma;
1212
1213         nvmeq->q_dmadev = dev->dev;
1214         nvmeq->dev = dev;
1215         spin_lock_init(&nvmeq->q_lock);
1216         nvmeq->cq_head = 0;
1217         nvmeq->cq_phase = 1;
1218         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1219         nvmeq->q_depth = depth;
1220         nvmeq->qid = qid;
1221         nvmeq->cq_vector = -1;
1222         dev->queues[qid] = nvmeq;
1223         dev->queue_count++;
1224
1225         return nvmeq;
1226
1227  free_cqdma:
1228         dma_free_coherent(dev->dev, CQ_SIZE(depth), (void *)nvmeq->cqes,
1229                                                         nvmeq->cq_dma_addr);
1230  free_nvmeq:
1231         kfree(nvmeq);
1232         return NULL;
1233 }
1234
1235 static int queue_request_irq(struct nvme_queue *nvmeq)
1236 {
1237         struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1238         int nr = nvmeq->dev->ctrl.instance;
1239
1240         if (use_threaded_interrupts) {
1241                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1242                                 nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1243         } else {
1244                 return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1245                                 NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1246         }
1247 }
1248
1249 static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1250 {
1251         struct nvme_dev *dev = nvmeq->dev;
1252
1253         spin_lock_irq(&nvmeq->q_lock);
1254         nvmeq->sq_tail = 0;
1255         nvmeq->cq_head = 0;
1256         nvmeq->cq_phase = 1;
1257         nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1258         memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1259         nvme_dbbuf_init(dev, nvmeq, qid);
1260         dev->online_queues++;
1261         spin_unlock_irq(&nvmeq->q_lock);
1262 }
1263
1264 static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1265 {
1266         struct nvme_dev *dev = nvmeq->dev;
1267         int result;
1268
1269         nvmeq->cq_vector = qid - 1;
1270         result = adapter_alloc_cq(dev, qid, nvmeq);
1271         if (result < 0)
1272                 return result;
1273
1274         result = adapter_alloc_sq(dev, qid, nvmeq);
1275         if (result < 0)
1276                 goto release_cq;
1277
1278         result = queue_request_irq(nvmeq);
1279         if (result < 0)
1280                 goto release_sq;
1281
1282         nvme_init_queue(nvmeq, qid);
1283         return result;
1284
1285  release_sq:
1286         adapter_delete_sq(dev, qid);
1287  release_cq:
1288         adapter_delete_cq(dev, qid);
1289         return result;
1290 }
1291
1292 static const struct blk_mq_ops nvme_mq_admin_ops = {
1293         .queue_rq       = nvme_queue_rq,
1294         .complete       = nvme_pci_complete_rq,
1295         .init_hctx      = nvme_admin_init_hctx,
1296         .exit_hctx      = nvme_admin_exit_hctx,
1297         .init_request   = nvme_init_request,
1298         .timeout        = nvme_timeout,
1299 };
1300
1301 static const struct blk_mq_ops nvme_mq_ops = {
1302         .queue_rq       = nvme_queue_rq,
1303         .complete       = nvme_pci_complete_rq,
1304         .init_hctx      = nvme_init_hctx,
1305         .init_request   = nvme_init_request,
1306         .map_queues     = nvme_pci_map_queues,
1307         .timeout        = nvme_timeout,
1308         .poll           = nvme_poll,
1309 };
1310
1311 static void nvme_dev_remove_admin(struct nvme_dev *dev)
1312 {
1313         if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1314                 /*
1315                  * If the controller was reset during removal, it's possible
1316                  * user requests may be waiting on a stopped queue. Start the
1317                  * queue to flush these to completion.
1318                  */
1319                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1320                 blk_cleanup_queue(dev->ctrl.admin_q);
1321                 blk_mq_free_tag_set(&dev->admin_tagset);
1322         }
1323 }
1324
1325 static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1326 {
1327         if (!dev->ctrl.admin_q) {
1328                 dev->admin_tagset.ops = &nvme_mq_admin_ops;
1329                 dev->admin_tagset.nr_hw_queues = 1;
1330
1331                 /*
1332                  * Subtract one to leave an empty queue entry for 'Full Queue'
1333                  * condition. See NVM-Express 1.2 specification, section 4.1.2.
1334                  */
1335                 dev->admin_tagset.queue_depth = NVME_AQ_BLKMQ_DEPTH - 1;
1336                 dev->admin_tagset.timeout = ADMIN_TIMEOUT;
1337                 dev->admin_tagset.numa_node = dev_to_node(dev->dev);
1338                 dev->admin_tagset.cmd_size = nvme_cmd_size(dev);
1339                 dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1340                 dev->admin_tagset.driver_data = dev;
1341
1342                 if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1343                         return -ENOMEM;
1344
1345                 dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1346                 if (IS_ERR(dev->ctrl.admin_q)) {
1347                         blk_mq_free_tag_set(&dev->admin_tagset);
1348                         return -ENOMEM;
1349                 }
1350                 if (!blk_get_queue(dev->ctrl.admin_q)) {
1351                         nvme_dev_remove_admin(dev);
1352                         dev->ctrl.admin_q = NULL;
1353                         return -ENODEV;
1354                 }
1355         } else
1356                 blk_mq_start_stopped_hw_queues(dev->ctrl.admin_q, true);
1357
1358         return 0;
1359 }
1360
1361 static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1362 {
1363         return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1364 }
1365
1366 static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1367 {
1368         struct pci_dev *pdev = to_pci_dev(dev->dev);
1369
1370         if (size <= dev->bar_mapped_size)
1371                 return 0;
1372         if (size > pci_resource_len(pdev, 0))
1373                 return -ENOMEM;
1374         if (dev->bar)
1375                 iounmap(dev->bar);
1376         dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1377         if (!dev->bar) {
1378                 dev->bar_mapped_size = 0;
1379                 return -ENOMEM;
1380         }
1381         dev->bar_mapped_size = size;
1382         dev->dbs = dev->bar + NVME_REG_DBS;
1383
1384         return 0;
1385 }
1386
1387 static int nvme_configure_admin_queue(struct nvme_dev *dev)
1388 {
1389         int result;
1390         u32 aqa;
1391         u64 cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1392         struct nvme_queue *nvmeq;
1393
1394         result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1395         if (result < 0)
1396                 return result;
1397
1398         dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1399                                                 NVME_CAP_NSSRC(cap) : 0;
1400
1401         if (dev->subsystem &&
1402             (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1403                 writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1404
1405         result = nvme_disable_ctrl(&dev->ctrl, cap);
1406         if (result < 0)
1407                 return result;
1408
1409         nvmeq = dev->queues[0];
1410         if (!nvmeq) {
1411                 nvmeq = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH,
1412                                         dev_to_node(dev->dev));
1413                 if (!nvmeq)
1414                         return -ENOMEM;
1415         }
1416
1417         aqa = nvmeq->q_depth - 1;
1418         aqa |= aqa << 16;
1419
1420         writel(aqa, dev->bar + NVME_REG_AQA);
1421         lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1422         lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1423
1424         result = nvme_enable_ctrl(&dev->ctrl, cap);
1425         if (result)
1426                 return result;
1427
1428         nvmeq->cq_vector = 0;
1429         result = queue_request_irq(nvmeq);
1430         if (result) {
1431                 nvmeq->cq_vector = -1;
1432                 return result;
1433         }
1434
1435         return result;
1436 }
1437
1438 static int nvme_create_io_queues(struct nvme_dev *dev)
1439 {
1440         unsigned i, max;
1441         int ret = 0;
1442
1443         for (i = dev->queue_count; i <= dev->max_qid; i++) {
1444                 /* vector == qid - 1, match nvme_create_queue */
1445                 if (!nvme_alloc_queue(dev, i, dev->q_depth,
1446                      pci_irq_get_node(to_pci_dev(dev->dev), i - 1))) {
1447                         ret = -ENOMEM;
1448                         break;
1449                 }
1450         }
1451
1452         max = min(dev->max_qid, dev->queue_count - 1);
1453         for (i = dev->online_queues; i <= max; i++) {
1454                 ret = nvme_create_queue(dev->queues[i], i);
1455                 if (ret)
1456                         break;
1457         }
1458
1459         /*
1460          * Ignore failing Create SQ/CQ commands, we can continue with less
1461          * than the desired aount of queues, and even a controller without
1462          * I/O queues an still be used to issue admin commands.  This might
1463          * be useful to upgrade a buggy firmware for example.
1464          */
1465         return ret >= 0 ? 0 : ret;
1466 }
1467
1468 static ssize_t nvme_cmb_show(struct device *dev,
1469                              struct device_attribute *attr,
1470                              char *buf)
1471 {
1472         struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1473
1474         return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1475                        ndev->cmbloc, ndev->cmbsz);
1476 }
1477 static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1478
1479 static void __iomem *nvme_map_cmb(struct nvme_dev *dev)
1480 {
1481         u64 szu, size, offset;
1482         resource_size_t bar_size;
1483         struct pci_dev *pdev = to_pci_dev(dev->dev);
1484         void __iomem *cmb;
1485         dma_addr_t dma_addr;
1486
1487         dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1488         if (!(NVME_CMB_SZ(dev->cmbsz)))
1489                 return NULL;
1490         dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1491
1492         if (!use_cmb_sqes)
1493                 return NULL;
1494
1495         szu = (u64)1 << (12 + 4 * NVME_CMB_SZU(dev->cmbsz));
1496         size = szu * NVME_CMB_SZ(dev->cmbsz);
1497         offset = szu * NVME_CMB_OFST(dev->cmbloc);
1498         bar_size = pci_resource_len(pdev, NVME_CMB_BIR(dev->cmbloc));
1499
1500         if (offset > bar_size)
1501                 return NULL;
1502
1503         /*
1504          * Controllers may support a CMB size larger than their BAR,
1505          * for example, due to being behind a bridge. Reduce the CMB to
1506          * the reported size of the BAR
1507          */
1508         if (size > bar_size - offset)
1509                 size = bar_size - offset;
1510
1511         dma_addr = pci_resource_start(pdev, NVME_CMB_BIR(dev->cmbloc)) + offset;
1512         cmb = ioremap_wc(dma_addr, size);
1513         if (!cmb)
1514                 return NULL;
1515
1516         dev->cmb_dma_addr = dma_addr;
1517         dev->cmb_size = size;
1518         return cmb;
1519 }
1520
1521 static inline void nvme_release_cmb(struct nvme_dev *dev)
1522 {
1523         if (dev->cmb) {
1524                 iounmap(dev->cmb);
1525                 dev->cmb = NULL;
1526                 if (dev->cmbsz) {
1527                         sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1528                                                      &dev_attr_cmb.attr, NULL);
1529                         dev->cmbsz = 0;
1530                 }
1531         }
1532 }
1533
1534 static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1535 {
1536         size_t len = dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs);
1537         struct nvme_command c;
1538         u64 dma_addr;
1539         int ret;
1540
1541         dma_addr = dma_map_single(dev->dev, dev->host_mem_descs, len,
1542                         DMA_TO_DEVICE);
1543         if (dma_mapping_error(dev->dev, dma_addr))
1544                 return -ENOMEM;
1545
1546         memset(&c, 0, sizeof(c));
1547         c.features.opcode       = nvme_admin_set_features;
1548         c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1549         c.features.dword11      = cpu_to_le32(bits);
1550         c.features.dword12      = cpu_to_le32(dev->host_mem_size >>
1551                                               ilog2(dev->ctrl.page_size));
1552         c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1553         c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1554         c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1555
1556         ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1557         if (ret) {
1558                 dev_warn(dev->ctrl.device,
1559                          "failed to set host mem (err %d, flags %#x).\n",
1560                          ret, bits);
1561         }
1562         dma_unmap_single(dev->dev, dma_addr, len, DMA_TO_DEVICE);
1563         return ret;
1564 }
1565
1566 static void nvme_free_host_mem(struct nvme_dev *dev)
1567 {
1568         int i;
1569
1570         for (i = 0; i < dev->nr_host_mem_descs; i++) {
1571                 struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1572                 size_t size = le32_to_cpu(desc->size) * dev->ctrl.page_size;
1573
1574                 dma_free_coherent(dev->dev, size, dev->host_mem_desc_bufs[i],
1575                                 le64_to_cpu(desc->addr));
1576         }
1577
1578         kfree(dev->host_mem_desc_bufs);
1579         dev->host_mem_desc_bufs = NULL;
1580         kfree(dev->host_mem_descs);
1581         dev->host_mem_descs = NULL;
1582 }
1583
1584 static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
1585 {
1586         struct nvme_host_mem_buf_desc *descs;
1587         u32 chunk_size, max_entries, i = 0;
1588         void **bufs;
1589         u64 size, tmp;
1590
1591         /* start big and work our way down */
1592         chunk_size = min(preferred, (u64)PAGE_SIZE << MAX_ORDER);
1593 retry:
1594         tmp = (preferred + chunk_size - 1);
1595         do_div(tmp, chunk_size);
1596         max_entries = tmp;
1597         descs = kcalloc(max_entries, sizeof(*descs), GFP_KERNEL);
1598         if (!descs)
1599                 goto out;
1600
1601         bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1602         if (!bufs)
1603                 goto out_free_descs;
1604
1605         for (size = 0; size < preferred; size += chunk_size) {
1606                 u32 len = min_t(u64, chunk_size, preferred - size);
1607                 dma_addr_t dma_addr;
1608
1609                 bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1610                                 DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1611                 if (!bufs[i])
1612                         break;
1613
1614                 descs[i].addr = cpu_to_le64(dma_addr);
1615                 descs[i].size = cpu_to_le32(len / dev->ctrl.page_size);
1616                 i++;
1617         }
1618
1619         if (!size || (min && size < min)) {
1620                 dev_warn(dev->ctrl.device,
1621                         "failed to allocate host memory buffer.\n");
1622                 goto out_free_bufs;
1623         }
1624
1625         dev_info(dev->ctrl.device,
1626                 "allocated %lld MiB host memory buffer.\n",
1627                 size >> ilog2(SZ_1M));
1628         dev->nr_host_mem_descs = i;
1629         dev->host_mem_size = size;
1630         dev->host_mem_descs = descs;
1631         dev->host_mem_desc_bufs = bufs;
1632         return 0;
1633
1634 out_free_bufs:
1635         while (--i >= 0) {
1636                 size_t size = le32_to_cpu(descs[i].size) * dev->ctrl.page_size;
1637
1638                 dma_free_coherent(dev->dev, size, bufs[i],
1639                                 le64_to_cpu(descs[i].addr));
1640         }
1641
1642         kfree(bufs);
1643 out_free_descs:
1644         kfree(descs);
1645 out:
1646         /* try a smaller chunk size if we failed early */
1647         if (chunk_size >= PAGE_SIZE * 2 && (i == 0 || size < min)) {
1648                 chunk_size /= 2;
1649                 goto retry;
1650         }
1651         dev->host_mem_descs = NULL;
1652         return -ENOMEM;
1653 }
1654
1655 static void nvme_setup_host_mem(struct nvme_dev *dev)
1656 {
1657         u64 max = (u64)max_host_mem_size_mb * SZ_1M;
1658         u64 preferred = (u64)dev->ctrl.hmpre * 4096;
1659         u64 min = (u64)dev->ctrl.hmmin * 4096;
1660         u32 enable_bits = NVME_HOST_MEM_ENABLE;
1661
1662         preferred = min(preferred, max);
1663         if (min > max) {
1664                 dev_warn(dev->ctrl.device,
1665                         "min host memory (%lld MiB) above limit (%d MiB).\n",
1666                         min >> ilog2(SZ_1M), max_host_mem_size_mb);
1667                 nvme_free_host_mem(dev);
1668                 return;
1669         }
1670
1671         /*
1672          * If we already have a buffer allocated check if we can reuse it.
1673          */
1674         if (dev->host_mem_descs) {
1675                 if (dev->host_mem_size >= min)
1676                         enable_bits |= NVME_HOST_MEM_RETURN;
1677                 else
1678                         nvme_free_host_mem(dev);
1679         }
1680
1681         if (!dev->host_mem_descs) {
1682                 if (nvme_alloc_host_mem(dev, min, preferred))
1683                         return;
1684         }
1685
1686         if (nvme_set_host_mem(dev, enable_bits))
1687                 nvme_free_host_mem(dev);
1688 }
1689
1690 static int nvme_setup_io_queues(struct nvme_dev *dev)
1691 {
1692         struct nvme_queue *adminq = dev->queues[0];
1693         struct pci_dev *pdev = to_pci_dev(dev->dev);
1694         int result, nr_io_queues;
1695         unsigned long size;
1696
1697         nr_io_queues = num_online_cpus();
1698         result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
1699         if (result < 0)
1700                 return result;
1701
1702         if (nr_io_queues == 0)
1703                 return 0;
1704
1705         if (dev->cmb && NVME_CMB_SQS(dev->cmbsz)) {
1706                 result = nvme_cmb_qdepth(dev, nr_io_queues,
1707                                 sizeof(struct nvme_command));
1708                 if (result > 0)
1709                         dev->q_depth = result;
1710                 else
1711                         nvme_release_cmb(dev);
1712         }
1713
1714         do {
1715                 size = db_bar_size(dev, nr_io_queues);
1716                 result = nvme_remap_bar(dev, size);
1717                 if (!result)
1718                         break;
1719                 if (!--nr_io_queues)
1720                         return -ENOMEM;
1721         } while (1);
1722         adminq->q_db = dev->dbs;
1723
1724         /* Deregister the admin queue's interrupt */
1725         pci_free_irq(pdev, 0, adminq);
1726
1727         /*
1728          * If we enable msix early due to not intx, disable it again before
1729          * setting up the full range we need.
1730          */
1731         pci_free_irq_vectors(pdev);
1732         nr_io_queues = pci_alloc_irq_vectors(pdev, 1, nr_io_queues,
1733                         PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY);
1734         if (nr_io_queues <= 0)
1735                 return -EIO;
1736         dev->max_qid = nr_io_queues;
1737
1738         /*
1739          * Should investigate if there's a performance win from allocating
1740          * more queues than interrupt vectors; it might allow the submission
1741          * path to scale better, even if the receive path is limited by the
1742          * number of interrupts.
1743          */
1744
1745         result = queue_request_irq(adminq);
1746         if (result) {
1747                 adminq->cq_vector = -1;
1748                 return result;
1749         }
1750         return nvme_create_io_queues(dev);
1751 }
1752
1753 static void nvme_del_queue_end(struct request *req, blk_status_t error)
1754 {
1755         struct nvme_queue *nvmeq = req->end_io_data;
1756
1757         blk_mq_free_request(req);
1758         complete(&nvmeq->dev->ioq_wait);
1759 }
1760
1761 static void nvme_del_cq_end(struct request *req, blk_status_t error)
1762 {
1763         struct nvme_queue *nvmeq = req->end_io_data;
1764
1765         if (!error) {
1766                 unsigned long flags;
1767
1768                 /*
1769                  * We might be called with the AQ q_lock held
1770                  * and the I/O queue q_lock should always
1771                  * nest inside the AQ one.
1772                  */
1773                 spin_lock_irqsave_nested(&nvmeq->q_lock, flags,
1774                                         SINGLE_DEPTH_NESTING);
1775                 nvme_process_cq(nvmeq);
1776                 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
1777         }
1778
1779         nvme_del_queue_end(req, error);
1780 }
1781
1782 static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
1783 {
1784         struct request_queue *q = nvmeq->dev->ctrl.admin_q;
1785         struct request *req;
1786         struct nvme_command cmd;
1787
1788         memset(&cmd, 0, sizeof(cmd));
1789         cmd.delete_queue.opcode = opcode;
1790         cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
1791
1792         req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT, NVME_QID_ANY);
1793         if (IS_ERR(req))
1794                 return PTR_ERR(req);
1795
1796         req->timeout = ADMIN_TIMEOUT;
1797         req->end_io_data = nvmeq;
1798
1799         blk_execute_rq_nowait(q, NULL, req, false,
1800                         opcode == nvme_admin_delete_cq ?
1801                                 nvme_del_cq_end : nvme_del_queue_end);
1802         return 0;
1803 }
1804
1805 static void nvme_disable_io_queues(struct nvme_dev *dev, int queues)
1806 {
1807         int pass;
1808         unsigned long timeout;
1809         u8 opcode = nvme_admin_delete_sq;
1810
1811         for (pass = 0; pass < 2; pass++) {
1812                 int sent = 0, i = queues;
1813
1814                 reinit_completion(&dev->ioq_wait);
1815  retry:
1816                 timeout = ADMIN_TIMEOUT;
1817                 for (; i > 0; i--, sent++)
1818                         if (nvme_delete_queue(dev->queues[i], opcode))
1819                                 break;
1820
1821                 while (sent--) {
1822                         timeout = wait_for_completion_io_timeout(&dev->ioq_wait, timeout);
1823                         if (timeout == 0)
1824                                 return;
1825                         if (i)
1826                                 goto retry;
1827                 }
1828                 opcode = nvme_admin_delete_cq;
1829         }
1830 }
1831
1832 /*
1833  * Return: error value if an error occurred setting up the queues or calling
1834  * Identify Device.  0 if these succeeded, even if adding some of the
1835  * namespaces failed.  At the moment, these failures are silent.  TBD which
1836  * failures should be reported.
1837  */
1838 static int nvme_dev_add(struct nvme_dev *dev)
1839 {
1840         if (!dev->ctrl.tagset) {
1841                 dev->tagset.ops = &nvme_mq_ops;
1842                 dev->tagset.nr_hw_queues = dev->online_queues - 1;
1843                 dev->tagset.timeout = NVME_IO_TIMEOUT;
1844                 dev->tagset.numa_node = dev_to_node(dev->dev);
1845                 dev->tagset.queue_depth =
1846                                 min_t(int, dev->q_depth, BLK_MQ_MAX_DEPTH) - 1;
1847                 dev->tagset.cmd_size = nvme_cmd_size(dev);
1848                 dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
1849                 dev->tagset.driver_data = dev;
1850
1851                 if (blk_mq_alloc_tag_set(&dev->tagset))
1852                         return 0;
1853                 dev->ctrl.tagset = &dev->tagset;
1854
1855                 nvme_dbbuf_set(dev);
1856         } else {
1857                 blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
1858
1859                 /* Free previously allocated queues that are no longer usable */
1860                 nvme_free_queues(dev, dev->online_queues);
1861         }
1862
1863         return 0;
1864 }
1865
1866 static int nvme_pci_enable(struct nvme_dev *dev)
1867 {
1868         u64 cap;
1869         int result = -ENOMEM;
1870         struct pci_dev *pdev = to_pci_dev(dev->dev);
1871
1872         if (pci_enable_device_mem(pdev))
1873                 return result;
1874
1875         pci_set_master(pdev);
1876
1877         if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(64)) &&
1878             dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(32)))
1879                 goto disable;
1880
1881         if (readl(dev->bar + NVME_REG_CSTS) == -1) {
1882                 result = -ENODEV;
1883                 goto disable;
1884         }
1885
1886         /*
1887          * Some devices and/or platforms don't advertise or work with INTx
1888          * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1889          * adjust this later.
1890          */
1891         result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
1892         if (result < 0)
1893                 return result;
1894
1895         cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
1896
1897         dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
1898         dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
1899         dev->dbs = dev->bar + 4096;
1900
1901         /*
1902          * Temporary fix for the Apple controller found in the MacBook8,1 and
1903          * some MacBook7,1 to avoid controller resets and data loss.
1904          */
1905         if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
1906                 dev->q_depth = 2;
1907                 dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
1908                         "set queue depth=%u to work around controller resets\n",
1909                         dev->q_depth);
1910         }
1911
1912         /*
1913          * CMBs can currently only exist on >=1.2 PCIe devices. We only
1914          * populate sysfs if a CMB is implemented. Note that we add the
1915          * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1916          * it on exit. Since nvme_dev_attrs_group has no name we can pass
1917          * NULL as final argument to sysfs_add_file_to_group.
1918          */
1919
1920         if (readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 2, 0)) {
1921                 dev->cmb = nvme_map_cmb(dev);
1922
1923                 if (dev->cmbsz) {
1924                         if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1925                                                     &dev_attr_cmb.attr, NULL))
1926                                 dev_warn(dev->ctrl.device,
1927                                          "failed to add sysfs attribute for CMB\n");
1928                 }
1929         }
1930
1931         pci_enable_pcie_error_reporting(pdev);
1932         pci_save_state(pdev);
1933         return 0;
1934
1935  disable:
1936         pci_disable_device(pdev);
1937         return result;
1938 }
1939
1940 static void nvme_dev_unmap(struct nvme_dev *dev)
1941 {
1942         if (dev->bar)
1943                 iounmap(dev->bar);
1944         pci_release_mem_regions(to_pci_dev(dev->dev));
1945 }
1946
1947 static void nvme_pci_disable(struct nvme_dev *dev)
1948 {
1949         struct pci_dev *pdev = to_pci_dev(dev->dev);
1950
1951         nvme_release_cmb(dev);
1952         pci_free_irq_vectors(pdev);
1953
1954         if (pci_is_enabled(pdev)) {
1955                 pci_disable_pcie_error_reporting(pdev);
1956                 pci_disable_device(pdev);
1957         }
1958 }
1959
1960 static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
1961 {
1962         int i, queues;
1963         bool dead = true;
1964         struct pci_dev *pdev = to_pci_dev(dev->dev);
1965
1966         mutex_lock(&dev->shutdown_lock);
1967         if (pci_is_enabled(pdev)) {
1968                 u32 csts = readl(dev->bar + NVME_REG_CSTS);
1969
1970                 if (dev->ctrl.state == NVME_CTRL_LIVE)
1971                         nvme_start_freeze(&dev->ctrl);
1972                 dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
1973                         pdev->error_state  != pci_channel_io_normal);
1974         }
1975
1976         /*
1977          * Give the controller a chance to complete all entered requests if
1978          * doing a safe shutdown.
1979          */
1980         if (!dead) {
1981                 if (shutdown)
1982                         nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
1983
1984                 /*
1985                  * If the controller is still alive tell it to stop using the
1986                  * host memory buffer.  In theory the shutdown / reset should
1987                  * make sure that it doesn't access the host memoery anymore,
1988                  * but I'd rather be safe than sorry..
1989                  */
1990                 if (dev->host_mem_descs)
1991                         nvme_set_host_mem(dev, 0);
1992
1993         }
1994         nvme_stop_queues(&dev->ctrl);
1995
1996         queues = dev->online_queues - 1;
1997         for (i = dev->queue_count - 1; i > 0; i--)
1998                 nvme_suspend_queue(dev->queues[i]);
1999
2000         if (dead) {
2001                 /* A device might become IO incapable very soon during
2002                  * probe, before the admin queue is configured. Thus,
2003                  * queue_count can be 0 here.
2004                  */
2005                 if (dev->queue_count)
2006                         nvme_suspend_queue(dev->queues[0]);
2007         } else {
2008                 nvme_disable_io_queues(dev, queues);
2009                 nvme_disable_admin_queue(dev, shutdown);
2010         }
2011         nvme_pci_disable(dev);
2012
2013         blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2014         blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2015
2016         /*
2017          * The driver will not be starting up queues again if shutting down so
2018          * must flush all entered requests to their failed completion to avoid
2019          * deadlocking blk-mq hot-cpu notifier.
2020          */
2021         if (shutdown)
2022                 nvme_start_queues(&dev->ctrl);
2023         mutex_unlock(&dev->shutdown_lock);
2024 }
2025
2026 static int nvme_setup_prp_pools(struct nvme_dev *dev)
2027 {
2028         dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2029                                                 PAGE_SIZE, PAGE_SIZE, 0);
2030         if (!dev->prp_page_pool)
2031                 return -ENOMEM;
2032
2033         /* Optimisation for I/Os between 4k and 128k */
2034         dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2035                                                 256, 256, 0);
2036         if (!dev->prp_small_pool) {
2037                 dma_pool_destroy(dev->prp_page_pool);
2038                 return -ENOMEM;
2039         }
2040         return 0;
2041 }
2042
2043 static void nvme_release_prp_pools(struct nvme_dev *dev)
2044 {
2045         dma_pool_destroy(dev->prp_page_pool);
2046         dma_pool_destroy(dev->prp_small_pool);
2047 }
2048
2049 static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2050 {
2051         struct nvme_dev *dev = to_nvme_dev(ctrl);
2052
2053         nvme_dbbuf_dma_free(dev);
2054         put_device(dev->dev);
2055         if (dev->tagset.tags)
2056                 blk_mq_free_tag_set(&dev->tagset);
2057         if (dev->ctrl.admin_q)
2058                 blk_put_queue(dev->ctrl.admin_q);
2059         kfree(dev->queues);
2060         free_opal_dev(dev->ctrl.opal_dev);
2061         kfree(dev);
2062 }
2063
2064 static void nvme_remove_dead_ctrl(struct nvme_dev *dev, int status)
2065 {
2066         dev_warn(dev->ctrl.device, "Removing after probe failure status: %d\n", status);
2067
2068         kref_get(&dev->ctrl.kref);
2069         nvme_dev_disable(dev, false);
2070         if (!schedule_work(&dev->remove_work))
2071                 nvme_put_ctrl(&dev->ctrl);
2072 }
2073
2074 static void nvme_reset_work(struct work_struct *work)
2075 {
2076         struct nvme_dev *dev =
2077                 container_of(work, struct nvme_dev, ctrl.reset_work);
2078         bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2079         int result = -ENODEV;
2080
2081         if (WARN_ON(dev->ctrl.state != NVME_CTRL_RESETTING))
2082                 goto out;
2083
2084         /*
2085          * If we're called to reset a live controller first shut it down before
2086          * moving on.
2087          */
2088         if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2089                 nvme_dev_disable(dev, false);
2090
2091         result = nvme_pci_enable(dev);
2092         if (result)
2093                 goto out;
2094
2095         result = nvme_configure_admin_queue(dev);
2096         if (result)
2097                 goto out;
2098
2099         nvme_init_queue(dev->queues[0], 0);
2100         result = nvme_alloc_admin_tags(dev);
2101         if (result)
2102                 goto out;
2103
2104         result = nvme_init_identify(&dev->ctrl);
2105         if (result)
2106                 goto out;
2107
2108         if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2109                 if (!dev->ctrl.opal_dev)
2110                         dev->ctrl.opal_dev =
2111                                 init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2112                 else if (was_suspend)
2113                         opal_unlock_from_suspend(dev->ctrl.opal_dev);
2114         } else {
2115                 free_opal_dev(dev->ctrl.opal_dev);
2116                 dev->ctrl.opal_dev = NULL;
2117         }
2118
2119         if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2120                 result = nvme_dbbuf_dma_alloc(dev);
2121                 if (result)
2122                         dev_warn(dev->dev,
2123                                  "unable to allocate dma for dbbuf\n");
2124         }
2125
2126         if (dev->ctrl.hmpre)
2127                 nvme_setup_host_mem(dev);
2128
2129         result = nvme_setup_io_queues(dev);
2130         if (result)
2131                 goto out;
2132
2133         /*
2134          * A controller that can not execute IO typically requires user
2135          * intervention to correct. For such degraded controllers, the driver
2136          * should not submit commands the user did not request, so skip
2137          * registering for asynchronous event notification on this condition.
2138          */
2139         if (dev->online_queues > 1)
2140                 nvme_queue_async_events(&dev->ctrl);
2141
2142         /*
2143          * Keep the controller around but remove all namespaces if we don't have
2144          * any working I/O queue.
2145          */
2146         if (dev->online_queues < 2) {
2147                 dev_warn(dev->ctrl.device, "IO queues not created\n");
2148                 nvme_kill_queues(&dev->ctrl);
2149                 nvme_remove_namespaces(&dev->ctrl);
2150         } else {
2151                 nvme_start_queues(&dev->ctrl);
2152                 nvme_wait_freeze(&dev->ctrl);
2153                 nvme_dev_add(dev);
2154                 nvme_unfreeze(&dev->ctrl);
2155         }
2156
2157         if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2158                 dev_warn(dev->ctrl.device, "failed to mark controller live\n");
2159                 goto out;
2160         }
2161
2162         if (dev->online_queues > 1)
2163                 nvme_queue_scan(&dev->ctrl);
2164         return;
2165
2166  out:
2167         nvme_remove_dead_ctrl(dev, result);
2168 }
2169
2170 static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2171 {
2172         struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2173         struct pci_dev *pdev = to_pci_dev(dev->dev);
2174
2175         nvme_kill_queues(&dev->ctrl);
2176         if (pci_get_drvdata(pdev))
2177                 device_release_driver(&pdev->dev);
2178         nvme_put_ctrl(&dev->ctrl);
2179 }
2180
2181 static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2182 {
2183         *val = readl(to_nvme_dev(ctrl)->bar + off);
2184         return 0;
2185 }
2186
2187 static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2188 {
2189         writel(val, to_nvme_dev(ctrl)->bar + off);
2190         return 0;
2191 }
2192
2193 static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2194 {
2195         *val = readq(to_nvme_dev(ctrl)->bar + off);
2196         return 0;
2197 }
2198
2199 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2200         .name                   = "pcie",
2201         .module                 = THIS_MODULE,
2202         .flags                  = NVME_F_METADATA_SUPPORTED,
2203         .reg_read32             = nvme_pci_reg_read32,
2204         .reg_write32            = nvme_pci_reg_write32,
2205         .reg_read64             = nvme_pci_reg_read64,
2206         .free_ctrl              = nvme_pci_free_ctrl,
2207         .submit_async_event     = nvme_pci_submit_async_event,
2208 };
2209
2210 static int nvme_dev_map(struct nvme_dev *dev)
2211 {
2212         struct pci_dev *pdev = to_pci_dev(dev->dev);
2213
2214         if (pci_request_mem_regions(pdev, "nvme"))
2215                 return -ENODEV;
2216
2217         if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2218                 goto release;
2219
2220         return 0;
2221   release:
2222         pci_release_mem_regions(pdev);
2223         return -ENODEV;
2224 }
2225
2226 static unsigned long check_dell_samsung_bug(struct pci_dev *pdev)
2227 {
2228         if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2229                 /*
2230                  * Several Samsung devices seem to drop off the PCIe bus
2231                  * randomly when APST is on and uses the deepest sleep state.
2232                  * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2233                  * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2234                  * 950 PRO 256GB", but it seems to be restricted to two Dell
2235                  * laptops.
2236                  */
2237                 if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2238                     (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2239                      dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2240                         return NVME_QUIRK_NO_DEEPEST_PS;
2241         }
2242
2243         return 0;
2244 }
2245
2246 static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2247 {
2248         int node, result = -ENOMEM;
2249         struct nvme_dev *dev;
2250         unsigned long quirks = id->driver_data;
2251
2252         node = dev_to_node(&pdev->dev);
2253         if (node == NUMA_NO_NODE)
2254                 set_dev_node(&pdev->dev, first_memory_node);
2255
2256         dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2257         if (!dev)
2258                 return -ENOMEM;
2259         dev->queues = kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2260                                                         GFP_KERNEL, node);
2261         if (!dev->queues)
2262                 goto free;
2263
2264         dev->dev = get_device(&pdev->dev);
2265         pci_set_drvdata(pdev, dev);
2266
2267         result = nvme_dev_map(dev);
2268         if (result)
2269                 goto free;
2270
2271         INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2272         INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2273         mutex_init(&dev->shutdown_lock);
2274         init_completion(&dev->ioq_wait);
2275
2276         result = nvme_setup_prp_pools(dev);
2277         if (result)
2278                 goto put_pci;
2279
2280         quirks |= check_dell_samsung_bug(pdev);
2281
2282         result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2283                         quirks);
2284         if (result)
2285                 goto release_pools;
2286
2287         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_RESETTING);
2288         dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2289
2290         queue_work(nvme_wq, &dev->ctrl.reset_work);
2291         return 0;
2292
2293  release_pools:
2294         nvme_release_prp_pools(dev);
2295  put_pci:
2296         put_device(dev->dev);
2297         nvme_dev_unmap(dev);
2298  free:
2299         kfree(dev->queues);
2300         kfree(dev);
2301         return result;
2302 }
2303
2304 static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2305 {
2306         struct nvme_dev *dev = pci_get_drvdata(pdev);
2307
2308         if (prepare)
2309                 nvme_dev_disable(dev, false);
2310         else
2311                 nvme_reset_ctrl(&dev->ctrl);
2312 }
2313
2314 static void nvme_shutdown(struct pci_dev *pdev)
2315 {
2316         struct nvme_dev *dev = pci_get_drvdata(pdev);
2317         nvme_dev_disable(dev, true);
2318 }
2319
2320 /*
2321  * The driver's remove may be called on a device in a partially initialized
2322  * state. This function must not have any dependencies on the device state in
2323  * order to proceed.
2324  */
2325 static void nvme_remove(struct pci_dev *pdev)
2326 {
2327         struct nvme_dev *dev = pci_get_drvdata(pdev);
2328
2329         nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2330
2331         cancel_work_sync(&dev->ctrl.reset_work);
2332         pci_set_drvdata(pdev, NULL);
2333
2334         if (!pci_device_is_present(pdev)) {
2335                 nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
2336                 nvme_dev_disable(dev, false);
2337         }
2338
2339         flush_work(&dev->ctrl.reset_work);
2340         nvme_uninit_ctrl(&dev->ctrl);
2341         nvme_dev_disable(dev, true);
2342         nvme_free_host_mem(dev);
2343         nvme_dev_remove_admin(dev);
2344         nvme_free_queues(dev, 0);
2345         nvme_release_prp_pools(dev);
2346         nvme_dev_unmap(dev);
2347         nvme_put_ctrl(&dev->ctrl);
2348 }
2349
2350 static int nvme_pci_sriov_configure(struct pci_dev *pdev, int numvfs)
2351 {
2352         int ret = 0;
2353
2354         if (numvfs == 0) {
2355                 if (pci_vfs_assigned(pdev)) {
2356                         dev_warn(&pdev->dev,
2357                                 "Cannot disable SR-IOV VFs while assigned\n");
2358                         return -EPERM;
2359                 }
2360                 pci_disable_sriov(pdev);
2361                 return 0;
2362         }
2363
2364         ret = pci_enable_sriov(pdev, numvfs);
2365         return ret ? ret : numvfs;
2366 }
2367
2368 #ifdef CONFIG_PM_SLEEP
2369 static int nvme_suspend(struct device *dev)
2370 {
2371         struct pci_dev *pdev = to_pci_dev(dev);
2372         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2373
2374         nvme_dev_disable(ndev, true);
2375         return 0;
2376 }
2377
2378 static int nvme_resume(struct device *dev)
2379 {
2380         struct pci_dev *pdev = to_pci_dev(dev);
2381         struct nvme_dev *ndev = pci_get_drvdata(pdev);
2382
2383         nvme_reset_ctrl(&ndev->ctrl);
2384         return 0;
2385 }
2386 #endif
2387
2388 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
2389
2390 static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
2391                                                 pci_channel_state_t state)
2392 {
2393         struct nvme_dev *dev = pci_get_drvdata(pdev);
2394
2395         /*
2396          * A frozen channel requires a reset. When detected, this method will
2397          * shutdown the controller to quiesce. The controller will be restarted
2398          * after the slot reset through driver's slot_reset callback.
2399          */
2400         switch (state) {
2401         case pci_channel_io_normal:
2402                 return PCI_ERS_RESULT_CAN_RECOVER;
2403         case pci_channel_io_frozen:
2404                 dev_warn(dev->ctrl.device,
2405                         "frozen state error detected, reset controller\n");
2406                 nvme_dev_disable(dev, false);
2407                 return PCI_ERS_RESULT_NEED_RESET;
2408         case pci_channel_io_perm_failure:
2409                 dev_warn(dev->ctrl.device,
2410                         "failure state error detected, request disconnect\n");
2411                 return PCI_ERS_RESULT_DISCONNECT;
2412         }
2413         return PCI_ERS_RESULT_NEED_RESET;
2414 }
2415
2416 static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
2417 {
2418         struct nvme_dev *dev = pci_get_drvdata(pdev);
2419
2420         dev_info(dev->ctrl.device, "restart after slot reset\n");
2421         pci_restore_state(pdev);
2422         nvme_reset_ctrl(&dev->ctrl);
2423         return PCI_ERS_RESULT_RECOVERED;
2424 }
2425
2426 static void nvme_error_resume(struct pci_dev *pdev)
2427 {
2428         pci_cleanup_aer_uncorrect_error_status(pdev);
2429 }
2430
2431 static const struct pci_error_handlers nvme_err_handler = {
2432         .error_detected = nvme_error_detected,
2433         .slot_reset     = nvme_slot_reset,
2434         .resume         = nvme_error_resume,
2435         .reset_notify   = nvme_reset_notify,
2436 };
2437
2438 static const struct pci_device_id nvme_id_table[] = {
2439         { PCI_VDEVICE(INTEL, 0x0953),
2440                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2441                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2442         { PCI_VDEVICE(INTEL, 0x0a53),
2443                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2444                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2445         { PCI_VDEVICE(INTEL, 0x0a54),
2446                 .driver_data = NVME_QUIRK_STRIPE_SIZE |
2447                                 NVME_QUIRK_DEALLOCATE_ZEROES, },
2448         { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
2449                 .driver_data = NVME_QUIRK_NO_DEEPEST_PS },
2450         { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
2451                 .driver_data = NVME_QUIRK_IDENTIFY_CNS, },
2452         { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
2453                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2454         { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
2455                 .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
2456         { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2457         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001) },
2458         { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
2459         { 0, }
2460 };
2461 MODULE_DEVICE_TABLE(pci, nvme_id_table);
2462
2463 static struct pci_driver nvme_driver = {
2464         .name           = "nvme",
2465         .id_table       = nvme_id_table,
2466         .probe          = nvme_probe,
2467         .remove         = nvme_remove,
2468         .shutdown       = nvme_shutdown,
2469         .driver         = {
2470                 .pm     = &nvme_dev_pm_ops,
2471         },
2472         .sriov_configure = nvme_pci_sriov_configure,
2473         .err_handler    = &nvme_err_handler,
2474 };
2475
2476 static int __init nvme_init(void)
2477 {
2478         return pci_register_driver(&nvme_driver);
2479 }
2480
2481 static void __exit nvme_exit(void)
2482 {
2483         pci_unregister_driver(&nvme_driver);
2484         _nvme_check_size();
2485 }
2486
2487 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2488 MODULE_LICENSE("GPL");
2489 MODULE_VERSION("1.0");
2490 module_init(nvme_init);
2491 module_exit(nvme_exit);