drivers/platform/x86/intel_pmc_core.c

   1 /*
   2  * Intel Core SoC Power Management Controller Driver
   3  *
   4  * Copyright (c) 2016, Intel Corporation.
   5  * All Rights Reserved.
   6  *
   7  * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   8  *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms and conditions of the GNU General Public License,
  12  * version 2, as published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  */
  20
  21 #include <linux/debugfs.h>
  22 #include <linux/device.h>
  23 #include <linux/init.h>
  24 #include <linux/io.h>
  25 #include <linux/pci.h>
  26 #include <linux/seq_file.h>
  27
  28 #include <asm/cpu_device_id.h>
  29 #include <asm/intel-family.h>
  30 #include <asm/pmc_core.h>
  31
  32 #include "intel_pmc_core.h"
  33
  34 static struct pmc_dev pmc;
  35
  36 static const struct pci_device_id pmc_pci_ids[] = {
  37         { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID), (kernel_ulong_t)NULL },
  38         { 0, },
  39 };
  40
  41 static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
  42 {
  43         return readl(pmcdev->regbase + reg_offset);
  44 }
  45
  46 static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
  47 {
  48         return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
  49 }
  50
  51 /**
  52  * intel_pmc_slp_s0_counter_read() - Read SLP_S0 residency.
  53  * @data: Out param that contains current SLP_S0 count.
  54  *
  55  * This API currently supports Intel Skylake SoC and Sunrise
  56  * Point Platform Controller Hub. Future platform support
  57  * should be added for platforms that support low power modes
  58  * beyond Package C10 state.
  59  *
  60  * SLP_S0_RESIDENCY counter counts in 100 us granularity per
  61  * step hence function populates the multiplied value in out
  62  * parameter @data.
  63  *
  64  * Return: an error code or 0 on success.
  65  */
  66 int intel_pmc_slp_s0_counter_read(u32 *data)
  67 {
  68         struct pmc_dev *pmcdev = &pmc;
  69         u32 value;
  70
  71         if (!pmcdev->has_slp_s0_res)
  72                 return -EACCES;
  73
  74         value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
  75         *data = pmc_core_adjust_slp_s0_step(value);
  76
  77         return 0;
  78 }
  79 EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
  80
  81 #if IS_ENABLED(CONFIG_DEBUG_FS)
  82 static int pmc_core_dev_state_show(struct seq_file *s, void *unused)
  83 {
  84         struct pmc_dev *pmcdev = s->private;
  85         u32 counter_val;
  86
  87         counter_val = pmc_core_reg_read(pmcdev,
  88                                         SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
  89         seq_printf(s, "%u\n", pmc_core_adjust_slp_s0_step(counter_val));
  90
  91         return 0;
  92 }
  93
  94 static int pmc_core_dev_state_open(struct inode *inode, struct file *file)
  95 {
  96         return single_open(file, pmc_core_dev_state_show, inode->i_private);
  97 }
  98
  99 static const struct file_operations pmc_core_dev_state_ops = {
 100         .open           = pmc_core_dev_state_open,
 101         .read           = seq_read,
 102         .llseek         = seq_lseek,
 103         .release        = single_release,
 104 };
 105
 106 static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 107 {
 108         debugfs_remove_recursive(pmcdev->dbgfs_dir);
 109 }
 110
 111 static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 112 {
 113         struct dentry *dir, *file;
 114
 115         dir = debugfs_create_dir("pmc_core", NULL);
 116         if (!dir)
 117                 return -ENOMEM;
 118
 119         pmcdev->dbgfs_dir = dir;
 120         file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
 121                                    dir, pmcdev, &pmc_core_dev_state_ops);
 122
 123         if (!file) {
 124                 pmc_core_dbgfs_unregister(pmcdev);
 125                 return -ENODEV;
 126         }
 127
 128         return 0;
 129 }
 130 #else
 131 static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
 132 {
 133         return 0;
 134 }
 135
 136 static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
 137 {
 138 }
 139 #endif /* CONFIG_DEBUG_FS */
 140
 141 static const struct x86_cpu_id intel_pmc_core_ids[] = {
 142         { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
 143                 (kernel_ulong_t)NULL},
 144         { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
 145                 (kernel_ulong_t)NULL},
 146         {}
 147 };
 148
 149 static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
 150 {
 151         struct device *ptr_dev = &dev->dev;
 152         struct pmc_dev *pmcdev = &pmc;
 153         const struct x86_cpu_id *cpu_id;
 154         int err;
 155
 156         cpu_id = x86_match_cpu(intel_pmc_core_ids);
 157         if (!cpu_id) {
 158                 dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
 159                 return -EINVAL;
 160         }
 161
 162         err = pcim_enable_device(dev);
 163         if (err < 0) {
 164                 dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
 165                 return err;
 166         }
 167
 168         err = pci_read_config_dword(dev,
 169                                     SPT_PMC_BASE_ADDR_OFFSET,
 170                                     &pmcdev->base_addr);
 171         if (err < 0) {
 172                 dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
 173                 return err;
 174         }
 175         dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
 176
 177         pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
 178                                               pmcdev->base_addr,
 179                                               SPT_PMC_MMIO_REG_LEN);
 180         if (!pmcdev->regbase) {
 181                 dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
 182                 return -ENOMEM;
 183         }
 184
 185         err = pmc_core_dbgfs_register(pmcdev);
 186         if (err < 0) {
 187                 dev_err(&dev->dev, "PMC Core: debugfs register failed.\n");
 188                 return err;
 189         }
 190
 191         pmc.has_slp_s0_res = true;
 192         return 0;
 193 }
 194
 195 static struct pci_driver intel_pmc_core_driver = {
 196         .name = "intel_pmc_core",
 197         .id_table = pmc_pci_ids,
 198         .probe = pmc_core_probe,
 199 };
 200
 201 builtin_pci_driver(intel_pmc_core_driver);