drivers/power/avs/qcom-cpr.c

   1 /*
   2  * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 and
   6  * only version 2 as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope that it will be useful,
   9  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/err.h>
  16 #include <linux/string.h>
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/init.h>
  20 #include <linux/io.h>
  21 #include <linux/bitops.h>
  22 #include <linux/slab.h>
  23 #include <linux/of.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/pm_opp.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/regmap.h>
  29 #include <linux/mfd/syscon.h>
  30 #include <linux/regulator/driver.h>
  31 #include <linux/regulator/machine.h>
  32 #include <linux/cpufreq.h>
  33 #include <linux/bitops.h>
  34 #include <linux/regulator/qcom_smd-regulator.h>
  35
  36 /* Register Offsets for RB-CPR and Bit Definitions */
  37
  38 /* RBCPR Version Register */
  39 #define REG_RBCPR_VERSION               0
  40 #define RBCPR_VER_2                     0x02
  41
  42 /* RBCPR Gate Count and Target Registers */
  43 #define REG_RBCPR_GCNT_TARGET(n)        (0x60 + 4 * (n))
  44
  45 #define RBCPR_GCNT_TARGET_TARGET_SHIFT  0
  46 #define RBCPR_GCNT_TARGET_TARGET_MASK   GENMASK(11, 0)
  47 #define RBCPR_GCNT_TARGET_GCNT_SHIFT    12
  48 #define RBCPR_GCNT_TARGET_GCNT_MASK     GENMASK(9, 0)
  49
  50 /* RBCPR Timer Control */
  51 #define REG_RBCPR_TIMER_INTERVAL        0x44
  52 #define REG_RBIF_TIMER_ADJUST           0x4c
  53
  54 #define RBIF_TIMER_ADJ_CONS_UP_MASK     GENMASK(3, 0)
  55 #define RBIF_TIMER_ADJ_CONS_UP_SHIFT    0
  56 #define RBIF_TIMER_ADJ_CONS_DOWN_MASK   GENMASK(3, 0)
  57 #define RBIF_TIMER_ADJ_CONS_DOWN_SHIFT  4
  58 #define RBIF_TIMER_ADJ_CLAMP_INT_MASK   GENMASK(7, 0)
  59 #define RBIF_TIMER_ADJ_CLAMP_INT_SHIFT  8
  60
  61 /* RBCPR Config Register */
  62 #define REG_RBIF_LIMIT                  0x48
  63 #define RBIF_LIMIT_CEILING_MASK         GENMASK(5, 0)
  64 #define RBIF_LIMIT_CEILING_SHIFT        6
  65 #define RBIF_LIMIT_FLOOR_BITS           6
  66 #define RBIF_LIMIT_FLOOR_MASK           GENMASK(5, 0)
  67
  68 #define RBIF_LIMIT_CEILING_DEFAULT      RBIF_LIMIT_CEILING_MASK
  69 #define RBIF_LIMIT_FLOOR_DEFAULT        0
  70
  71 #define REG_RBIF_SW_VLEVEL              0x94
  72 #define RBIF_SW_VLEVEL_DEFAULT          0x20
  73
  74 #define REG_RBCPR_STEP_QUOT             0x80
  75 #define RBCPR_STEP_QUOT_STEPQUOT_MASK   GENMASK(7, 0)
  76 #define RBCPR_STEP_QUOT_IDLE_CLK_MASK   GENMASK(3, 0)
  77 #define RBCPR_STEP_QUOT_IDLE_CLK_SHIFT  8
  78
  79 /* RBCPR Control Register */
  80 #define REG_RBCPR_CTL                   0x90
  81
  82 #define RBCPR_CTL_LOOP_EN                       BIT(0)
  83 #define RBCPR_CTL_TIMER_EN                      BIT(3)
  84 #define RBCPR_CTL_SW_AUTO_CONT_ACK_EN           BIT(5)
  85 #define RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN       BIT(6)
  86 #define RBCPR_CTL_COUNT_MODE                    BIT(10)
  87 #define RBCPR_CTL_UP_THRESHOLD_MASK     GENMASK(3, 0)
  88 #define RBCPR_CTL_UP_THRESHOLD_SHIFT    24
  89 #define RBCPR_CTL_DN_THRESHOLD_MASK     GENMASK(3, 0)
  90 #define RBCPR_CTL_DN_THRESHOLD_SHIFT    28
  91
  92 /* RBCPR Ack/Nack Response */
  93 #define REG_RBIF_CONT_ACK_CMD           0x98
  94 #define REG_RBIF_CONT_NACK_CMD          0x9c
  95
  96 /* RBCPR Result status Register */
  97 #define REG_RBCPR_RESULT_0              0xa0
  98
  99 #define RBCPR_RESULT0_BUSY_SHIFT        19
 100 #define RBCPR_RESULT0_BUSY_MASK         BIT(RBCPR_RESULT0_BUSY_SHIFT)
 101 #define RBCPR_RESULT0_ERROR_LT0_SHIFT   18
 102 #define RBCPR_RESULT0_ERROR_SHIFT       6
 103 #define RBCPR_RESULT0_ERROR_MASK        GENMASK(11, 0)
 104 #define RBCPR_RESULT0_ERROR_STEPS_SHIFT 2
 105 #define RBCPR_RESULT0_ERROR_STEPS_MASK  GENMASK(3, 0)
 106 #define RBCPR_RESULT0_STEP_UP_SHIFT     1
 107
 108 /* RBCPR Interrupt Control Register */
 109 #define REG_RBIF_IRQ_EN(n)              (0x100 + 4 * (n))
 110 #define REG_RBIF_IRQ_CLEAR              0x110
 111 #define REG_RBIF_IRQ_STATUS             0x114
 112
 113 #define CPR_INT_DONE            BIT(0)
 114 #define CPR_INT_MIN             BIT(1)
 115 #define CPR_INT_DOWN            BIT(2)
 116 #define CPR_INT_MID             BIT(3)
 117 #define CPR_INT_UP              BIT(4)
 118 #define CPR_INT_MAX             BIT(5)
 119 #define CPR_INT_CLAMP           BIT(6)
 120 #define CPR_INT_ALL     (CPR_INT_DONE | CPR_INT_MIN | CPR_INT_DOWN | \
 121                         CPR_INT_MID | CPR_INT_UP | CPR_INT_MAX | CPR_INT_CLAMP)
 122 #define CPR_INT_DEFAULT (CPR_INT_UP | CPR_INT_DOWN)
 123
 124 #define CPR_NUM_RING_OSC        8
 125
 126 /* RBCPR Clock Control Register */
 127 #define RBCPR_CLK_SEL_MASK      BIT(-1)
 128 #define RBCPR_CLK_SEL_19P2_MHZ  0
 129 #define RBCPR_CLK_SEL_AHB_CLK   BIT(0)
 130
 131 /* CPR eFuse parameters */
 132 #define CPR_FUSE_TARGET_QUOT_BITS_MASK  GENMASK(11, 0)
 133
 134 #define CPR_FUSE_MIN_QUOT_DIFF          50
 135
 136 #define SPEED_BIN_NONE                  UINT_MAX
 137
 138 #define FUSE_REVISION_UNKNOWN           (-1)
 139 #define FUSE_MAP_NO_MATCH               (-1)
 140 #define FUSE_PARAM_MATCH_ANY            0xffffffff
 141
 142 /**
 143  * enum vdd_mx_vmin_method - Method to determine vmin for vdd-mx
 144  * @VDD_MX_VMIN_APC:                     Use APC voltage
 145  * @VDD_MX_VMIN_APC_CORNER_CEILING:      Use PVS corner ceiling voltage
 146  * @VDD_MX_VMIN_APC_SLOW_CORNER_CEILING: Use slow speed corner ceiling
 147  * @VDD_MX_VMIN_MX_VMAX:                 Use specified vdd-mx-vmax voltage
 148  * @VDD_MX_VMIN_APC_CORNER_MAP:          Use APC corner mapped MX voltage
 149  */
 150 enum vdd_mx_vmin_method {
 151         VDD_MX_VMIN_APC,
 152         VDD_MX_VMIN_APC_CORNER_CEILING,
 153         VDD_MX_VMIN_APC_SLOW_CORNER_CEILING,
 154         VDD_MX_VMIN_MX_VMAX,
 155         VDD_MX_VMIN_APC_CORNER_MAP,
 156 };
 157 /* TODO: Trim these above to used values */
 158
 159 enum voltage_change_dir {
 160         NO_CHANGE,
 161         DOWN,
 162         UP,
 163 };
 164
 165 struct qfprom_offset {
 166         u16 offset;
 167         u8 width;
 168         u8 shift;
 169 };
 170
 171 struct cpr_fuse {
 172         struct qfprom_offset ring_osc;
 173         struct qfprom_offset init_voltage;
 174         struct qfprom_offset quotient;
 175         struct qfprom_offset quotient_offset;
 176 };
 177
 178 struct fuse_corner_data {
 179         int ref_uV;
 180         int max_uV;
 181         int min_uV;
 182         int max_quot_scale;
 183         int quot_offset;
 184         int quot_scale;
 185         int max_volt_scale;
 186         int vdd_mx_req;
 187 };
 188
 189 struct cpr_fuses {
 190         struct qfprom_offset redundant;
 191         u8 redundant_value;
 192         int init_voltage_step;
 193         struct fuse_corner_data *fuse_corner_data;
 194         struct cpr_fuse *cpr_fuse;
 195         struct qfprom_offset *disable;
 196 };
 197
 198 struct pvs_bin {
 199         int *uV;
 200 };
 201
 202 struct pvs_fuses {
 203         struct qfprom_offset redundant;
 204         u8 redundant_value;
 205         struct qfprom_offset *pvs_fuse;
 206         struct pvs_bin *pvs_bins;
 207 };
 208
 209 struct corner_data {
 210         unsigned int fuse_corner;
 211         unsigned long freq;
 212 };
 213
 214 struct freq_plan {
 215         u32 speed_bin;
 216         u32 pvs_version;
 217         const struct corner_data **plan;
 218 };
 219
 220 struct fuse_conditional_min_volt {
 221         struct qfprom_offset redundant;
 222         u8 expected;
 223         int min_uV;
 224 };
 225
 226 struct fuse_uplift_wa {
 227         struct qfprom_offset redundant;
 228         u8 expected;
 229         int uV;
 230         int *quot;
 231         int max_uV;
 232         int speed_bin;
 233 };
 234
 235 struct corner_override {
 236         u32 speed_bin;
 237         u32 pvs_version;
 238         int *max_uV;
 239         int *min_uV;
 240 };
 241
 242 struct corner_adjustment {
 243         u32 speed_bin;
 244         u32 pvs_version;
 245         u32 cpr_rev;
 246         u8 *ring_osc_idx;
 247         int *fuse_quot;
 248         int *fuse_quot_diff;
 249         int *fuse_quot_min;
 250         int *fuse_quot_offset;
 251         int *fuse_init_uV;
 252         int *quot;
 253         int *init_uV;
 254         bool disable_closed_loop;
 255 };
 256
 257 struct cpr_desc {
 258         unsigned int num_fuse_corners;
 259         unsigned int num_corners;
 260         enum vdd_mx_vmin_method vdd_mx_vmin_method;
 261         int vdd_mx_vmax;
 262         int min_diff_quot;
 263         int *step_quot;
 264         struct cpr_fuses cpr_fuses;
 265         struct qfprom_offset fuse_revision;
 266         struct qfprom_offset speed_bin;
 267         struct qfprom_offset pvs_version;
 268         struct corner_data *corner_data;
 269         struct freq_plan *freq_plans;
 270         size_t num_freq_plans;
 271         struct pvs_fuses *pvs_fuses;
 272         struct fuse_conditional_min_volt *min_volt_fuse;
 273         struct fuse_uplift_wa *uplift_wa;
 274         struct corner_override *corner_overrides;
 275         size_t num_corner_overrides;
 276         struct corner_adjustment *adjustments;
 277         size_t num_adjustments;
 278         bool reduce_to_fuse_uV;
 279         bool reduce_to_corner_uV;
 280 };
 281
 282 struct acc_desc {
 283         unsigned int    enable_reg;
 284         u32             enable_mask;
 285
 286         struct reg_sequence     *settings;
 287         struct reg_sequence     *override_settings;
 288         int                     num_regs_per_fuse;
 289
 290         struct qfprom_offset    override;
 291         u8                      override_value;
 292 };
 293
 294 struct fuse_corner {
 295         int min_uV;
 296         int max_uV;
 297         int uV;
 298         int quot;
 299         int step_quot;
 300         const struct reg_sequence *accs;
 301         int num_accs;
 302         int vdd_mx_req;
 303         unsigned long max_freq;
 304         u8 ring_osc_idx;
 305 };
 306
 307 struct corner {
 308         int min_uV;
 309         int max_uV;
 310         int uV;
 311         int last_uV;
 312         int quot_adjust;
 313         u32 save_ctl;
 314         u32 save_irq;
 315         unsigned long freq;
 316         struct fuse_corner *fuse_corner;
 317 };
 318
 319 struct cpr_drv {
 320         unsigned int            num_fuse_corners;
 321         unsigned int            num_corners;
 322
 323         unsigned int            nb_count;
 324         struct notifier_block   cpufreq_nb;
 325         bool                    switching_opp;
 326         struct notifier_block   reg_nb;
 327
 328         unsigned int            ref_clk_khz;
 329         unsigned int            timer_delay_us;
 330         unsigned int            timer_cons_up;
 331         unsigned int            timer_cons_down;
 332         unsigned int            up_threshold;
 333         unsigned int            down_threshold;
 334         unsigned int            idle_clocks;
 335         unsigned int            gcnt_us;
 336         unsigned int            vdd_apc_step_up_limit;
 337         unsigned int            vdd_apc_step_down_limit;
 338         unsigned int            clamp_timer_interval;
 339         int                     ceiling_max;
 340         enum vdd_mx_vmin_method vdd_mx_vmin_method;
 341         int                     vdd_mx_vmax;
 342
 343         struct mutex            lock;
 344         void __iomem            *base;
 345         struct corner           *corner;
 346         struct regulator        *vdd_apc;
 347         struct regulator        *vdd_mx;
 348         struct clk              *cpu_clk;
 349         struct device           *cpu_dev;
 350         struct regmap           *tcsr;
 351         bool                    loop_disabled;
 352         bool                    suspended;
 353         u32                     gcnt;
 354         unsigned long           flags;
 355 #define FLAGS_IGNORE_1ST_IRQ_STATUS     BIT(0)
 356
 357         struct fuse_corner      *fuse_corners;
 358         struct corner           *corners;
 359 };
 360
 361 static bool cpr_is_allowed(struct cpr_drv *drv)
 362 {
 363         if (drv->loop_disabled) /* || disabled in software */
 364                 return false;
 365         else
 366                 return true;
 367 }
 368
 369 static void cpr_write(struct cpr_drv *drv, u32 offset, u32 value)
 370 {
 371         writel_relaxed(value, drv->base + offset);
 372 }
 373
 374 static u32 cpr_read(struct cpr_drv *drv, u32 offset)
 375 {
 376         return readl_relaxed(drv->base + offset);
 377 }
 378
 379 static void
 380 cpr_masked_write(struct cpr_drv *drv, u32 offset, u32 mask, u32 value)
 381 {
 382         u32 val;
 383
 384         val = readl_relaxed(drv->base + offset);
 385         val &= ~mask;
 386         val |= value & mask;
 387         writel_relaxed(val, drv->base + offset);
 388 }
 389
 390 static void cpr_irq_clr(struct cpr_drv *drv)
 391 {
 392         cpr_write(drv, REG_RBIF_IRQ_CLEAR, CPR_INT_ALL);
 393 }
 394
 395 static void cpr_irq_clr_nack(struct cpr_drv *drv)
 396 {
 397         cpr_irq_clr(drv);
 398         cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
 399 }
 400
 401 static void cpr_irq_clr_ack(struct cpr_drv *drv)
 402 {
 403         cpr_irq_clr(drv);
 404         cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
 405 }
 406
 407 static void cpr_irq_set(struct cpr_drv *drv, u32 int_bits)
 408 {
 409         cpr_write(drv, REG_RBIF_IRQ_EN(0), int_bits);
 410 }
 411
 412 static void cpr_ctl_modify(struct cpr_drv *drv, u32 mask, u32 value)
 413 {
 414         cpr_masked_write(drv, REG_RBCPR_CTL, mask, value);
 415 }
 416
 417 static void cpr_ctl_enable(struct cpr_drv *drv, struct corner *corner)
 418 {
 419         u32 val, mask;
 420
 421         if (drv->suspended)
 422                 return;
 423
 424         /* Program Consecutive Up & Down */
 425         val = drv->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
 426         val |= drv->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
 427         mask = RBIF_TIMER_ADJ_CONS_UP_MASK | RBIF_TIMER_ADJ_CONS_DOWN_MASK;
 428         cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST, mask, val);
 429         cpr_masked_write(drv, REG_RBCPR_CTL,
 430                         RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
 431                         RBCPR_CTL_SW_AUTO_CONT_ACK_EN,
 432                         corner->save_ctl);
 433         cpr_irq_set(drv, corner->save_irq);
 434
 435         if (cpr_is_allowed(drv) /*&& drv->vreg_enabled */ &&
 436             corner->max_uV > corner->min_uV)
 437                 val = RBCPR_CTL_LOOP_EN;
 438         else
 439                 val = 0;
 440         cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, val);
 441 }
 442
 443 static void cpr_ctl_disable(struct cpr_drv *drv)
 444 {
 445         if (drv->suspended)
 446                 return;
 447
 448         cpr_irq_set(drv, 0);
 449         cpr_ctl_modify(drv, RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN |
 450                         RBCPR_CTL_SW_AUTO_CONT_ACK_EN, 0);
 451         cpr_masked_write(drv, REG_RBIF_TIMER_ADJUST,
 452                         RBIF_TIMER_ADJ_CONS_UP_MASK |
 453                         RBIF_TIMER_ADJ_CONS_DOWN_MASK, 0);
 454         cpr_irq_clr(drv);
 455         cpr_write(drv, REG_RBIF_CONT_ACK_CMD, 1);
 456         cpr_write(drv, REG_RBIF_CONT_NACK_CMD, 1);
 457         cpr_ctl_modify(drv, RBCPR_CTL_LOOP_EN, 0);
 458 }
 459
 460 static bool cpr_ctl_is_enabled(struct cpr_drv *drv)
 461 {
 462         u32 reg_val;
 463
 464         reg_val = cpr_read(drv, REG_RBCPR_CTL);
 465         return reg_val & RBCPR_CTL_LOOP_EN;
 466 }
 467
 468 static bool cpr_ctl_is_busy(struct cpr_drv *drv)
 469 {
 470         u32 reg_val;
 471
 472         reg_val = cpr_read(drv, REG_RBCPR_RESULT_0);
 473         return reg_val & RBCPR_RESULT0_BUSY_MASK;
 474 }
 475
 476 static void cpr_corner_save(struct cpr_drv *drv, struct corner *corner)
 477 {
 478         corner->save_ctl = cpr_read(drv, REG_RBCPR_CTL);
 479         corner->save_irq = cpr_read(drv, REG_RBIF_IRQ_EN(0));
 480 }
 481
 482 static void cpr_corner_restore(struct cpr_drv *drv, struct corner *corner)
 483 {
 484         u32 gcnt, ctl, irq, ro_sel, step_quot;
 485         struct fuse_corner *fuse = corner->fuse_corner;
 486         int i;
 487
 488         ro_sel = fuse->ring_osc_idx;
 489         gcnt = drv->gcnt;
 490         gcnt |= fuse->quot - corner->quot_adjust;
 491
 492         /* Program the step quotient and idle clocks */
 493         step_quot = drv->idle_clocks << RBCPR_STEP_QUOT_IDLE_CLK_SHIFT;
 494         step_quot |= fuse->step_quot;
 495         cpr_write(drv, REG_RBCPR_STEP_QUOT, step_quot);
 496
 497         /* Clear the target quotient value and gate count of all ROs */
 498         for (i = 0; i < CPR_NUM_RING_OSC; i++)
 499                 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
 500
 501         cpr_write(drv, REG_RBCPR_GCNT_TARGET(ro_sel), gcnt);
 502         ctl = corner->save_ctl;
 503         cpr_write(drv, REG_RBCPR_CTL, ctl);
 504         irq = corner->save_irq;
 505         cpr_irq_set(drv, irq);
 506         pr_debug("gcnt = 0x%08x, ctl = 0x%08x, irq = 0x%08x\n", gcnt, ctl, irq);
 507 }
 508
 509 static void cpr_corner_switch(struct cpr_drv *drv, struct corner *corner)
 510 {
 511         if (drv->corner == corner)
 512                 return;
 513
 514         cpr_corner_restore(drv, corner);
 515 }
 516
 517 static int
 518 cpr_mx_get(struct cpr_drv *drv, struct fuse_corner *fuse, int apc_volt)
 519 {
 520         int vdd_mx;
 521         struct fuse_corner *highest_fuse;
 522
 523         highest_fuse = &drv->fuse_corners[drv->num_fuse_corners - 1];
 524
 525         switch (drv->vdd_mx_vmin_method) {
 526         case VDD_MX_VMIN_APC:
 527                 vdd_mx = apc_volt;
 528                 break;
 529         case VDD_MX_VMIN_APC_CORNER_CEILING:
 530                 vdd_mx = fuse->max_uV;
 531                 break;
 532         case VDD_MX_VMIN_APC_SLOW_CORNER_CEILING:
 533                 vdd_mx = highest_fuse->max_uV;
 534                 break;
 535         case VDD_MX_VMIN_MX_VMAX:
 536                 vdd_mx = drv->vdd_mx_vmax;
 537                 break;
 538         case VDD_MX_VMIN_APC_CORNER_MAP:
 539                 vdd_mx = fuse->vdd_mx_req;
 540                 break;
 541         default:
 542                 BUG();
 543         }
 544
 545         return vdd_mx;
 546 }
 547
 548 static void cpr_set_acc(struct regmap *tcsr, struct fuse_corner *f,
 549                         struct fuse_corner *end)
 550 {
 551         if (f < end) {
 552                 for (f += 1; f <= end; f++)
 553                         regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
 554         } else {
 555                 for (f -= 1; f >= end; f--)
 556                         regmap_multi_reg_write(tcsr, f->accs, f->num_accs);
 557         }
 558 }
 559
 560 static int cpr_pre_voltage(struct cpr_drv *drv,
 561                            struct fuse_corner *fuse_corner,
 562                            enum voltage_change_dir dir, int vdd_mx_vmin)
 563 {
 564         int ret = 0;
 565         struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
 566
 567         if (drv->tcsr && dir == DOWN)
 568                 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
 569
 570         if (vdd_mx_vmin && dir == UP)
 571                 ret = qcom_rpm_set_corner(drv->vdd_mx, vdd_mx_vmin);
 572
 573         return ret;
 574 }
 575
 576 static int cpr_post_voltage(struct cpr_drv *drv,
 577                             struct fuse_corner *fuse_corner,
 578                             enum voltage_change_dir dir, int vdd_mx_vmin)
 579 {
 580         int ret = 0;
 581         struct fuse_corner *prev_fuse_corner = drv->corner->fuse_corner;
 582
 583         if (drv->tcsr && dir == UP)
 584                 cpr_set_acc(drv->tcsr, prev_fuse_corner, fuse_corner);
 585
 586         if (vdd_mx_vmin && dir == DOWN)
 587                 ret = qcom_rpm_set_corner(drv->vdd_mx, vdd_mx_vmin);
 588
 589         return ret;
 590 }
 591
 592 static int cpr_regulator_notifier(struct notifier_block *nb,
 593                                    unsigned long event, void *d)
 594 {
 595         struct cpr_drv *drv = container_of(nb, struct cpr_drv, reg_nb);
 596         u32 val, mask;
 597         int last_uV, new_uV;
 598
 599         switch (event) {
 600         case REGULATOR_EVENT_VOLTAGE_CHANGE:
 601                 new_uV = (int)(uintptr_t)d;
 602                 break;
 603         default:
 604                 return 0;
 605         }
 606
 607         mutex_lock(&drv->lock);
 608
 609         last_uV = drv->corner->last_uV;
 610
 611         if (drv->switching_opp) {
 612                 goto unlock;
 613         } else if (last_uV < new_uV) {
 614                 /* Disable auto nack down */
 615                 mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
 616                 val = 0;
 617         } else if (last_uV > new_uV) {
 618                 /* Restore default threshold for UP */
 619                 mask = RBCPR_CTL_UP_THRESHOLD_MASK;
 620                 mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
 621                 val = drv->up_threshold;
 622                 val <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
 623         } else { /* Somehow it's the same? */
 624                 goto unlock;
 625         }
 626
 627         cpr_ctl_modify(drv, mask, val);
 628
 629         /* Re-enable default interrupts */
 630         cpr_irq_set(drv, CPR_INT_DEFAULT);
 631
 632         /* Ack */
 633         cpr_irq_clr_ack(drv);
 634
 635         /* Save register values for the corner */
 636         cpr_corner_save(drv, drv->corner);
 637         drv->corner->last_uV = new_uV;
 638 unlock:
 639         mutex_unlock(&drv->lock);
 640
 641         return 0;
 642 }
 643
 644 static int cpr_scale(struct cpr_drv *drv, enum voltage_change_dir dir)
 645 {
 646         u32 val, error_steps, reg_mask;
 647         int last_uV, new_uV, step_uV;
 648         struct corner *corner;
 649         struct fuse_corner *fuse;
 650
 651         //step_uV = regulator_get_linear_step(drv->vdd_apc);
 652         step_uV = 12500; /*TODO: Get step volt here */
 653         corner = drv->corner;
 654         fuse = corner->fuse_corner;
 655
 656         val = cpr_read(drv, REG_RBCPR_RESULT_0);
 657
 658         error_steps = val >> RBCPR_RESULT0_ERROR_STEPS_SHIFT;
 659         error_steps &= RBCPR_RESULT0_ERROR_STEPS_MASK;
 660         last_uV = corner->last_uV;
 661
 662         if (dir == UP) {
 663                 if (drv->clamp_timer_interval &&
 664                     error_steps < drv->up_threshold) {
 665                         /*
 666                          * Handle the case where another measurement started
 667                          * after the interrupt was triggered due to a core
 668                          * exiting from power collapse.
 669                          */
 670                         error_steps = max(drv->up_threshold,
 671                                           drv->vdd_apc_step_up_limit);
 672                 }
 673
 674                 if (last_uV >= corner->max_uV) {
 675                         cpr_irq_clr_nack(drv);
 676
 677                         /* Maximize the UP threshold */
 678                         reg_mask = RBCPR_CTL_UP_THRESHOLD_MASK;
 679                         reg_mask <<= RBCPR_CTL_UP_THRESHOLD_SHIFT;
 680                         val = reg_mask;
 681                         cpr_ctl_modify(drv, reg_mask, val);
 682
 683                         /* Disable UP interrupt */
 684                         cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_UP);
 685
 686                         return 0;
 687                 }
 688
 689                 if (error_steps > drv->vdd_apc_step_up_limit)
 690                         error_steps = drv->vdd_apc_step_up_limit;
 691
 692                 /* Calculate new voltage */
 693                 new_uV = last_uV + error_steps * step_uV;
 694                 if (new_uV > corner->max_uV)
 695                         new_uV = corner->max_uV;
 696         } else if (dir == DOWN) {
 697                 if (drv->clamp_timer_interval
 698                                 && error_steps < drv->down_threshold) {
 699                         /*
 700                          * Handle the case where another measurement started
 701                          * after the interrupt was triggered due to a core
 702                          * exiting from power collapse.
 703                          */
 704                         error_steps = max(drv->down_threshold,
 705                                           drv->vdd_apc_step_down_limit);
 706                 }
 707
 708                 if (last_uV <= corner->min_uV) {
 709                         cpr_irq_clr_nack(drv);
 710
 711                         /* Enable auto nack down */
 712                         reg_mask = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
 713                         val = RBCPR_CTL_SW_AUTO_CONT_NACK_DN_EN;
 714
 715                         cpr_ctl_modify(drv, reg_mask, val);
 716
 717                         /* Disable DOWN interrupt */
 718                         cpr_irq_set(drv, CPR_INT_DEFAULT & ~CPR_INT_DOWN);
 719
 720                         return 0;
 721                 }
 722
 723                 if (error_steps > drv->vdd_apc_step_down_limit)
 724                         error_steps = drv->vdd_apc_step_down_limit;
 725
 726                 /* Calculate new voltage */
 727                 new_uV = last_uV - error_steps * step_uV;
 728                 if (new_uV < corner->min_uV)
 729                         new_uV = corner->min_uV;
 730         }
 731
 732         return new_uV;
 733 }
 734
 735 static irqreturn_t cpr_irq_handler(int irq, void *dev)
 736 {
 737         struct cpr_drv *drv = dev;
 738         u32 val;
 739         int new_uV = 0;
 740         struct corner *corner;
 741
 742         mutex_lock(&drv->lock);
 743
 744         val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
 745         if (drv->flags & FLAGS_IGNORE_1ST_IRQ_STATUS)
 746                 val = cpr_read(drv, REG_RBIF_IRQ_STATUS);
 747
 748         pr_debug("IRQ_STATUS = %#02x\n", val);
 749
 750         if (!cpr_ctl_is_enabled(drv)) {
 751                 pr_debug("CPR is disabled\n");
 752                 goto unlock;
 753         } else if (cpr_ctl_is_busy(drv) && !drv->clamp_timer_interval) {
 754                 pr_debug("CPR measurement is not ready\n");
 755                 goto unlock;
 756         } else if (!cpr_is_allowed(drv)) {
 757                 val = cpr_read(drv, REG_RBCPR_CTL);
 758                 pr_err_ratelimited("Interrupt broken? RBCPR_CTL = %#02x\n",
 759                                    val);
 760                 goto unlock;
 761         }
 762
 763         /* Following sequence of handling is as per each IRQ's priority */
 764         if (val & CPR_INT_UP) {
 765                 new_uV = cpr_scale(drv, UP);
 766         } else if (val & CPR_INT_DOWN) {
 767                 new_uV = cpr_scale(drv, DOWN);
 768         } else if (val & CPR_INT_MIN) {
 769                 cpr_irq_clr_nack(drv);
 770         } else if (val & CPR_INT_MAX) {
 771                 cpr_irq_clr_nack(drv);
 772         } else if (val & CPR_INT_MID) {
 773                 /* RBCPR_CTL_SW_AUTO_CONT_ACK_EN is enabled */
 774                 pr_debug("IRQ occurred for Mid Flag\n");
 775         } else {
 776                 pr_debug("IRQ occurred for unknown flag (%#08x)\n", val);
 777         }
 778
 779         /* Save register values for the corner */
 780         corner = drv->corner;
 781         cpr_corner_save(drv, corner);
 782 unlock:
 783         mutex_unlock(&drv->lock);
 784
 785         if (new_uV)
 786                 dev_pm_opp_adjust_voltage(drv->cpu_dev, corner->freq, new_uV);
 787
 788         return IRQ_HANDLED;
 789 }
 790
 791 /*
 792  * TODO: Register for hotplug notifier and turn on/off CPR when CPUs are offline
 793  */
 794 static int cpr_enable(struct cpr_drv *drv)
 795 {
 796         int ret;
 797
 798         /* Enable dependency power before vdd_apc */
 799         if (drv->vdd_mx) {
 800                 ret = regulator_enable(drv->vdd_mx);
 801                 if (ret)
 802                         return ret;
 803         }
 804
 805         ret = regulator_enable(drv->vdd_apc);
 806         if (ret)
 807                 return ret;
 808
 809         mutex_lock(&drv->lock);
 810         //drv->vreg_enabled = true;
 811         if (cpr_is_allowed(drv) && drv->corner) {
 812                 cpr_irq_clr(drv);
 813                 cpr_corner_restore(drv, drv->corner);
 814                 cpr_ctl_enable(drv, drv->corner);
 815         }
 816         mutex_unlock(&drv->lock);
 817         pr_info("CPR is enabled!\n");
 818
 819         return 0;
 820 }
 821
 822 static int cpr_disable(struct cpr_drv *drv)
 823 {
 824         int ret;
 825
 826         ret = regulator_disable(drv->vdd_apc);
 827         if (ret)
 828                 return ret;
 829
 830         if (drv->vdd_mx)
 831                 ret = regulator_disable(drv->vdd_mx);
 832         if (ret)
 833                 return ret;
 834
 835         mutex_lock(&drv->lock);
 836         //drv->vreg_enabled = false;
 837         if (cpr_is_allowed(drv))
 838                 cpr_ctl_disable(drv);
 839         mutex_unlock(&drv->lock);
 840
 841         return 0;
 842 }
 843
 844 #ifdef CONFIG_PM_SLEEP
 845 static int cpr_suspend(struct device *dev)
 846 {
 847         struct cpr_drv *drv = platform_get_drvdata(to_platform_device(dev));
 848
 849         if (cpr_is_allowed(drv)) {
 850                 mutex_lock(&drv->lock);
 851                 cpr_ctl_disable(drv);
 852                 cpr_irq_clr(drv);
 853                 drv->suspended = true;
 854                 mutex_unlock(&drv->lock);
 855         }
 856
 857         return 0;
 858 }
 859
 860 static int cpr_resume(struct device *dev)
 861 {
 862         struct cpr_drv *drv = platform_get_drvdata(to_platform_device(dev));
 863
 864         if (cpr_is_allowed(drv)) {
 865                 mutex_lock(&drv->lock);
 866                 drv->suspended = false;
 867                 cpr_irq_clr(drv);
 868                 cpr_ctl_enable(drv, drv->corner);
 869                 mutex_unlock(&drv->lock);
 870         }
 871
 872         return 0;
 873 }
 874 #endif
 875
 876 static SIMPLE_DEV_PM_OPS(cpr_pm_ops, cpr_suspend, cpr_resume);
 877
 878 static int cpr_config(struct cpr_drv *drv)
 879 {
 880         int i;
 881         u32 val, gcnt;
 882         struct corner *corner;
 883
 884         /* Disable interrupt and CPR */
 885         cpr_write(drv, REG_RBIF_IRQ_EN(0), 0);
 886         cpr_write(drv, REG_RBCPR_CTL, 0);
 887
 888         /* Program the default HW Ceiling, Floor and vlevel */
 889         val = RBIF_LIMIT_CEILING_DEFAULT << RBIF_LIMIT_CEILING_SHIFT;
 890         val |= RBIF_LIMIT_FLOOR_DEFAULT;
 891         cpr_write(drv, REG_RBIF_LIMIT, val);
 892         cpr_write(drv, REG_RBIF_SW_VLEVEL, RBIF_SW_VLEVEL_DEFAULT);
 893
 894         /* Clear the target quotient value and gate count of all ROs */
 895         for (i = 0; i < CPR_NUM_RING_OSC; i++)
 896                 cpr_write(drv, REG_RBCPR_GCNT_TARGET(i), 0);
 897
 898         /* Init and save gcnt */
 899         gcnt = (drv->ref_clk_khz * drv->gcnt_us) / 1000;
 900         gcnt = gcnt & RBCPR_GCNT_TARGET_GCNT_MASK;
 901         gcnt <<= RBCPR_GCNT_TARGET_GCNT_SHIFT;
 902         drv->gcnt = gcnt;
 903
 904         /* Program the delay count for the timer */
 905         val = (drv->ref_clk_khz * drv->timer_delay_us) / 1000;
 906         cpr_write(drv, REG_RBCPR_TIMER_INTERVAL, val);
 907         pr_debug("Timer count: 0x%0x (for %d us)\n", val, drv->timer_delay_us);
 908
 909         /* Program Consecutive Up & Down */
 910         val = drv->timer_cons_down << RBIF_TIMER_ADJ_CONS_DOWN_SHIFT;
 911         val |= drv->timer_cons_up << RBIF_TIMER_ADJ_CONS_UP_SHIFT;
 912         val |= drv->clamp_timer_interval << RBIF_TIMER_ADJ_CLAMP_INT_SHIFT;
 913         cpr_write(drv, REG_RBIF_TIMER_ADJUST, val);
 914
 915         /* Program the control register */
 916         val = drv->up_threshold << RBCPR_CTL_UP_THRESHOLD_SHIFT;
 917         val |= drv->down_threshold << RBCPR_CTL_DN_THRESHOLD_SHIFT;
 918         val |= RBCPR_CTL_TIMER_EN | RBCPR_CTL_COUNT_MODE;
 919         val |= RBCPR_CTL_SW_AUTO_CONT_ACK_EN;
 920         cpr_write(drv, REG_RBCPR_CTL, val);
 921
 922         for (i = 0; i < drv->num_corners; i++) {
 923                 corner = &drv->corners[i];
 924                 corner->save_ctl = val;
 925                 corner->save_irq = CPR_INT_DEFAULT;
 926         }
 927
 928         cpr_irq_set(drv, CPR_INT_DEFAULT);
 929
 930         val = cpr_read(drv, REG_RBCPR_VERSION);
 931         if (val <= RBCPR_VER_2)
 932                 drv->flags |= FLAGS_IGNORE_1ST_IRQ_STATUS;
 933
 934         return 0;
 935 }
 936
 937 /* Called twice for each CPU in policy, one pre and one post event */
 938 static int
 939 cpr_cpufreq_notifier(struct notifier_block *nb, unsigned long event, void *f)
 940 {
 941         struct cpr_drv *drv = container_of(nb, struct cpr_drv, cpufreq_nb);
 942         struct cpufreq_freqs *freqs = f;
 943         unsigned long old = freqs->old * 1000;
 944         unsigned long new = freqs->new * 1000;
 945         struct corner *corner, *end;
 946         enum voltage_change_dir dir;
 947         int ret = 0, new_uV;
 948         int vdd_mx_vmin = 0;
 949         struct fuse_corner *fuse_corner;
 950
 951         /* Determine direction */
 952         if (old > new)
 953                 dir = DOWN;
 954         else if (old < new)
 955                 dir = UP;
 956         else
 957                 dir = NO_CHANGE;
 958
 959         /* Determine new corner we're going to */
 960         corner = drv->corners;
 961         end = &corner[drv->num_corners - 1];
 962         for (; corner <= end; corner++)
 963                 if (corner->freq == new)
 964                         break;
 965
 966         if (corner > end)
 967                 return -EINVAL;
 968
 969         fuse_corner = corner->fuse_corner;
 970
 971         if (cpr_is_allowed(drv)) {
 972                 new_uV = corner->last_uV;
 973         } else {
 974                 new_uV = corner->uV;
 975         }
 976
 977         if (dir != NO_CHANGE && drv->vdd_mx)
 978                 vdd_mx_vmin = cpr_mx_get(drv, fuse_corner, new_uV);
 979
 980         mutex_lock(&drv->lock);
 981         if (event == CPUFREQ_PRECHANGE) {
 982                 if (drv->nb_count++)
 983                         goto unlock;
 984
 985                 pr_debug("Pre change [%ld] %p @ %lu?\n", corner - drv->corners,
 986                                                        corner, corner->freq);
 987                 if (cpr_is_allowed(drv))
 988                         cpr_ctl_disable(drv);
 989
 990                 ret = cpr_pre_voltage(drv, fuse_corner, dir, vdd_mx_vmin);
 991                 if (ret)
 992                         goto unlock;
 993
 994                 drv->switching_opp = true;
 995         }
 996
 997         if (event == CPUFREQ_POSTCHANGE) {
 998                 if (--drv->nb_count)
 999                         goto unlock;
1000
1001                 pr_debug("Post change [%ld] %p @ %lu?\n", corner - drv->corners,
1002                                                        corner, corner->freq);
1003
1004                 ret = cpr_post_voltage(drv, fuse_corner, dir, vdd_mx_vmin);
1005                 if (ret)
1006                         goto unlock;
1007
1008                 if (cpr_is_allowed(drv) /* && drv->vreg_enabled */) {
1009                         cpr_irq_clr(drv);
1010                         cpr_corner_switch(drv, corner);
1011                         cpr_ctl_enable(drv, corner);
1012                 }
1013
1014                 drv->corner = corner;
1015                 drv->switching_opp = false;
1016         }
1017 unlock:
1018         mutex_unlock(&drv->lock);
1019
1020         return ret;
1021 }
1022
1023 static u32 cpr_read_efuse(void __iomem *prom, const struct qfprom_offset *efuse)
1024 {
1025         u64 buffer = 0;
1026         u8 val;
1027         int i, num_bytes;
1028
1029         num_bytes = DIV_ROUND_UP(efuse->width + efuse->shift, BITS_PER_BYTE);
1030
1031         for (i = 0; i < num_bytes; i++) {
1032                 val = readb_relaxed(prom + efuse->offset + i);
1033                 buffer |= val << (i * BITS_PER_BYTE);
1034         }
1035
1036         buffer >>= efuse->shift;
1037         buffer &= BIT(efuse->width) - 1;
1038
1039         return buffer;
1040 }
1041
1042 static void
1043 cpr_populate_ring_osc_idx(const struct cpr_fuse *fuses, struct cpr_drv *drv,
1044                           void __iomem *prom)
1045 {
1046         struct fuse_corner *fuse = drv->fuse_corners;
1047         struct fuse_corner *end = fuse + drv->num_fuse_corners;
1048
1049         for (; fuse < end; fuse++, fuses++)
1050                 fuse->ring_osc_idx = cpr_read_efuse(prom, &fuses->ring_osc);
1051 }
1052
1053
1054 static const struct corner_adjustment *cpr_find_adjustment(u32 speed_bin,
1055                 u32 pvs_version, u32 cpr_rev, const struct cpr_desc *desc,
1056                 const struct cpr_drv *drv)
1057 {
1058         int i, j;
1059         u32 val, ro;
1060         struct corner_adjustment *a;
1061
1062         for (i = 0; i < desc->num_adjustments; i++) {
1063                 a = &desc->adjustments[i];
1064
1065                 if (a->speed_bin != speed_bin &&
1066                     a->speed_bin != FUSE_PARAM_MATCH_ANY)
1067                         continue;
1068                 if (a->pvs_version != pvs_version &&
1069                     a->pvs_version != FUSE_PARAM_MATCH_ANY)
1070                         continue;
1071                 if (a->cpr_rev != cpr_rev &&
1072                     a->cpr_rev != FUSE_PARAM_MATCH_ANY)
1073                         continue;
1074                 for (j = 0; j < drv->num_fuse_corners; j++) {
1075                         val = a->ring_osc_idx[j];
1076                         ro = drv->fuse_corners[j].ring_osc_idx;
1077                         if (val != ro && val != FUSE_PARAM_MATCH_ANY)
1078                                 break;
1079                 }
1080                 if (j == drv->num_fuse_corners)
1081                         return a;
1082         }
1083
1084         return NULL;
1085 }
1086
1087 static void cpr_fuse_corner_init(struct cpr_drv *drv,
1088                         const struct cpr_desc *desc,
1089                         void __iomem *qfprom,
1090                         const struct cpr_fuse *fuses, u32 speed,
1091                         const struct corner_adjustment *adjustments,
1092                         const struct acc_desc *acc_desc)
1093 {
1094         int i;
1095         unsigned int idx = 0;
1096         unsigned int step_volt;
1097         int steps, step_size_uv;
1098         const struct fuse_corner_data *fdata;
1099         struct fuse_corner *fuse, *end, *prev;
1100         const struct qfprom_offset *pvs_efuse;
1101         const struct qfprom_offset *init_v_efuse;
1102         const struct qfprom_offset *redun;
1103         const struct fuse_conditional_min_volt *min_v;
1104         const struct fuse_uplift_wa *up;
1105         bool do_min_v = false, do_uplift = false;
1106         const int *pvs_uV = NULL;
1107         const int *adj_uV, *adj_quot, *adj_min, *min_diff_quot;
1108         const int *step_quot;
1109         int uV, diff;
1110         u32 bits, bin;
1111         u32 min_uV;
1112         u8 expected;
1113         const struct reg_sequence *accs;
1114
1115         redun = &acc_desc->override;
1116         expected = acc_desc->override_value;
1117         if (redun->width && cpr_read_efuse(qfprom, redun) == expected)
1118                 accs = acc_desc->override_settings;
1119         else
1120                 accs = acc_desc->settings;
1121
1122         /* Figure out if we should apply workarounds */
1123         min_v = desc->min_volt_fuse;
1124         do_min_v = min_v &&
1125                    cpr_read_efuse(qfprom, &min_v->redundant) == min_v->expected;
1126         if (do_min_v)
1127                 min_uV = min_v->min_uV;
1128
1129         up = desc->uplift_wa;
1130         if (!do_min_v && up)
1131                 if (cpr_read_efuse(qfprom, &up->redundant) == up->expected)
1132                         do_uplift = up->speed_bin == speed;
1133
1134         adj_uV = adjustments ? adjustments->fuse_init_uV : NULL;
1135         adj_quot = adjustments ? adjustments->fuse_quot : NULL;
1136         adj_min = adjustments ? adjustments->fuse_quot_min : NULL;
1137         min_diff_quot = adjustments ? adjustments->fuse_quot_diff : NULL;
1138         fuse = drv->fuse_corners;
1139         end = &fuse[drv->num_fuse_corners - 1];
1140         fdata = desc->cpr_fuses.fuse_corner_data;
1141         step_quot = desc->step_quot;
1142
1143         /*
1144          * The initial voltage for each fuse corner may be determined by one of
1145          * two ways. Either initial voltages are encoded for each fuse corner
1146          * in a dedicated fuse per fuse corner (fuses::init_voltage), or we
1147          * use the PVS bin fuse to use a table of initial voltages (pvs_uV).
1148          */
1149         if (fuses->init_voltage.width) {
1150                 //step_volt = regulator_get_linear_step(drv->vdd_apc);
1151                 step_volt = 12500; /* TODO: Replace with ^ when apc_reg ready */
1152                 step_size_uv = desc->cpr_fuses.init_voltage_step;
1153         } else {
1154                 redun = &desc->pvs_fuses->redundant;
1155                 expected = desc->pvs_fuses->redundant_value;
1156                 if (redun->width)
1157                         idx = !!(cpr_read_efuse(qfprom, redun) == expected);
1158
1159                 pvs_efuse = &desc->pvs_fuses->pvs_fuse[idx];
1160                 bin = cpr_read_efuse(qfprom, pvs_efuse);
1161                 pvs_uV = desc->pvs_fuses->pvs_bins[bin].uV;
1162         }
1163
1164         /* Populate fuse_corner voltage and ring_osc_idx members */
1165         prev = NULL;
1166         for (i = 0; fuse <= end; fuse++, fuses++, i++) {
1167                 if (pvs_uV) {
1168                         uV = pvs_uV[i];
1169                 } else {
1170                         init_v_efuse = &fuses->init_voltage;
1171                         bits = cpr_read_efuse(qfprom, init_v_efuse);
1172                         /* Not two's complement.. instead highest bit is sign */
1173                         steps = bits & BIT(init_v_efuse->width - 1) ? -1 : 1;
1174                         steps *= bits & ~BIT(init_v_efuse->width - 1);
1175
1176                         uV = fdata[i].ref_uV + steps * step_size_uv;
1177                         uV = DIV_ROUND_UP(uV, step_volt) * step_volt;
1178                 }
1179
1180                 if (adj_uV)
1181                         uV += adj_uV[i];
1182
1183                 fuse->min_uV = fdata[i].min_uV;
1184                 fuse->max_uV = fdata[i].max_uV;
1185
1186                 if (do_min_v) {
1187                         if (fuse->max_uV < min_uV) {
1188                                 fuse->max_uV = min_uV;
1189                                 fuse->min_uV = min_uV;
1190                         } else if (fuse->min_uV < min_uV) {
1191                                 fuse->min_uV = min_uV;
1192                         }
1193                 }
1194
1195                 fuse->uV = clamp(uV, fuse->min_uV, fuse->max_uV);
1196
1197                 if (fuse == end) {
1198                         if (do_uplift) {
1199                                 end->uV += up->uV;
1200                                 end->uV = clamp(end->uV, 0, up->max_uV);
1201                         }
1202                         /*
1203                          * Allow the highest fuse corner's PVS voltage to
1204                          * define the ceiling voltage for that corner in order
1205                          * to support SoC's in which variable ceiling values
1206                          * are required.
1207                          */
1208                         end->max_uV = max(end->max_uV, end->uV);
1209                 }
1210
1211                 /* Unpack the target quotient by scaling. */
1212                 fuse->quot = cpr_read_efuse(qfprom, &fuses->quotient);
1213                 fuse->quot *= fdata[i].quot_scale;
1214                 fuse->quot += fdata[i].quot_offset;
1215
1216                 if (adj_quot) {
1217                         fuse->quot += adj_quot[i];
1218
1219                         if (prev && min_diff_quot) {
1220                                 diff = min_diff_quot[i];
1221                                 if (fuse->quot - prev->quot <= diff)
1222                                         fuse->quot = prev->quot + adj_min[i];
1223                         }
1224                         prev = fuse;
1225                 }
1226
1227                 if (do_uplift)
1228                         fuse->quot += up->quot[i];
1229
1230                 fuse->step_quot = step_quot[fuse->ring_osc_idx];
1231
1232                 fuse->accs = accs;
1233                 fuse->num_accs = acc_desc->num_regs_per_fuse;
1234                 accs += acc_desc->num_regs_per_fuse;
1235
1236                 fuse->vdd_mx_req = fdata[i].vdd_mx_req;
1237         }
1238
1239         /*
1240          * Restrict all fuse corner PVS voltages based upon per corner
1241          * ceiling and floor voltages.
1242          */
1243         for (fuse = drv->fuse_corners, i = 0; fuse <= end; fuse++, i++) {
1244                 if (fuse->uV > fuse->max_uV)
1245                         fuse->uV = fuse->max_uV;
1246                 else if (fuse->uV < fuse->min_uV)
1247                         fuse->uV = fuse->min_uV;
1248
1249                 pr_debug("fuse corner %d: [%d %d %d] RO%d quot %d squot %d\n", i,
1250                                 fuse->min_uV, fuse->uV, fuse->max_uV,
1251                                 fuse->ring_osc_idx, fuse->quot,
1252                                 fuse->step_quot);
1253         }
1254
1255         drv->ceiling_max = end->max_uV;
1256 }
1257
1258 static int cpr_populate_opps(struct device_node *of_node, struct cpr_drv *drv,
1259                              const struct corner_data **plan)
1260 {
1261         int i, j, ret, cpu;
1262         struct device *cpu_dev;
1263         struct device_node *np;
1264         struct corner *corner;
1265         const struct corner_data *p;
1266
1267         for (i = 0; (np = of_parse_phandle(of_node, "qcom,cpr-cpus", i)); i++) {
1268                 for_each_possible_cpu(cpu)
1269                         if (arch_find_n_match_cpu_physical_id(np, cpu, NULL))
1270                                 break;
1271
1272                 of_node_put(np);
1273                 if (cpu >= nr_cpu_ids) {
1274                         pr_err("Failed to find logical CPU for %s\n", np->name);
1275                         return -EINVAL;
1276                 }
1277
1278                 cpu_dev = get_cpu_device(cpu);
1279                 if (!cpu_dev)
1280                         return -EINVAL;
1281
1282                 /*
1283                  * Keep cpu_dev and its regulator and clock for monitoring
1284                  * voltage changes and updating OPPs later.
1285                  */
1286                 if (i == 0) {
1287                         drv->cpu_dev = cpu_dev;
1288                         drv->vdd_apc = devm_regulator_get(cpu_dev, "cpu");
1289                         if (IS_ERR(drv->vdd_apc))
1290                                 return PTR_ERR(drv->vdd_apc);
1291                         drv->cpu_clk = devm_clk_get(cpu_dev, NULL);
1292                         if (IS_ERR(drv->cpu_clk))
1293                                 return PTR_ERR(drv->cpu_clk);
1294                 }
1295
1296                 for (j = 0, corner = drv->corners; plan[j]; j++, corner++) {
1297                         p = plan[j];
1298                         ret = dev_pm_opp_add(cpu_dev, p->freq, corner->uV);
1299                         if (ret)
1300                                 return ret;
1301                         corner->freq = p->freq;
1302                 }
1303         }
1304
1305         return 0;
1306 }
1307
1308 static const struct corner_data **
1309 find_freq_plan(const struct cpr_desc *desc, u32 speed_bin, u32 pvs_version)
1310 {
1311         int i;
1312         const struct freq_plan *p;
1313
1314         for (i = 0; i < desc->num_freq_plans; i++) {
1315                 p = &desc->freq_plans[i];
1316
1317                 if (p->speed_bin != speed_bin &&
1318                     p->speed_bin != FUSE_PARAM_MATCH_ANY)
1319                         continue;
1320                 if (p->pvs_version != pvs_version &&
1321                     p->pvs_version != FUSE_PARAM_MATCH_ANY)
1322                         continue;
1323
1324                 return p->plan;
1325         }
1326
1327         return NULL;
1328
1329 }
1330
1331 static struct corner_override *find_corner_override(const struct cpr_desc *desc,
1332                 u32 speed_bin, u32 pvs_version)
1333 {
1334         int i;
1335         struct corner_override *o;
1336
1337         for (i = 0; i < desc->num_corner_overrides; i++) {
1338                 o = &desc->corner_overrides[i];
1339
1340                 if (o->speed_bin != speed_bin &&
1341                     o->speed_bin != FUSE_PARAM_MATCH_ANY)
1342                         continue;
1343                 if (o->pvs_version != pvs_version &&
1344                     o->pvs_version != FUSE_PARAM_MATCH_ANY)
1345                         continue;
1346
1347                 return o;
1348         }
1349
1350         return NULL;
1351
1352 }
1353
1354 static void cpr_corner_init(struct cpr_drv *drv, const struct cpr_desc *desc,
1355                         const struct cpr_fuse *fuses, u32 speed_bin,
1356                         u32 pvs_version, void __iomem *qfprom,
1357                         const struct corner_adjustment *adjustments,
1358                         const struct corner_data **plan)
1359 {
1360         int i, fnum, quot_diff, scaling;
1361         struct fuse_corner *fuse, *prev_fuse;
1362         struct corner *corner, *end;
1363         const struct corner_data *cdata, *p;
1364         const struct fuse_corner_data *fdata;
1365         bool apply_scaling = false;
1366         const int *adj_quot, *adj_volt, *adj_quot_offset;
1367         const struct qfprom_offset *quot_offset;
1368         unsigned long freq_corner, freq_diff, freq_diff_mhz;
1369         unsigned long freq_high, freq_low;
1370         int volt_high;
1371         u64 temp, temp_limit;
1372         int step_volt = 12500; /* TODO: Get from regulator APIs */
1373         const struct corner_override *override;
1374
1375         corner = drv->corners;
1376         end = &corner[drv->num_corners - 1];
1377         cdata = desc->corner_data;
1378         fdata = desc->cpr_fuses.fuse_corner_data;
1379         adj_quot = adjustments ? adjustments->quot : NULL;
1380         adj_volt = adjustments ? adjustments->init_uV : NULL;
1381         adj_quot_offset = adjustments ? adjustments->fuse_quot_offset : NULL;
1382
1383         override = find_corner_override(desc, speed_bin, pvs_version);
1384
1385         /*
1386          * Store maximum frequency for each fuse corner based on the frequency
1387          * plan
1388          */
1389         for (i = 0; plan[i]; i++) {
1390                 p = plan[i];
1391                 freq_corner = p->freq;
1392                 fnum = p->fuse_corner;
1393                 fuse = &drv->fuse_corners[fnum];
1394                 if (freq_corner > fuse->max_freq)
1395                         fuse->max_freq = freq_corner;
1396
1397         }
1398
1399         /*
1400          * Get the quotient adjustment scaling factor, according to:
1401          *
1402          * scaling = min(1000 * (QUOT(corner_N) - QUOT(corner_N-1))
1403          *              / (freq(corner_N) - freq(corner_N-1)), max_factor)
1404          *
1405          * QUOT(corner_N):      quotient read from fuse for fuse corner N
1406          * QUOT(corner_N-1):    quotient read from fuse for fuse corner (N - 1)
1407          * freq(corner_N):      max frequency in MHz supported by fuse corner N
1408          * freq(corner_N-1):    max frequency in MHz supported by fuse corner
1409          *                       (N - 1)
1410          *
1411          * Then walk through the corners mapped to each fuse corner
1412          * and calculate the quotient adjustment for each one using the
1413          * following formula:
1414          *
1415          * quot_adjust = (freq_max - freq_corner) * scaling / 1000
1416          *
1417          * freq_max: max frequency in MHz supported by the fuse corner
1418          * freq_corner: frequency in MHz corresponding to the corner
1419          * scaling: calculated from above equation
1420          *
1421          *
1422          *     +                           +
1423          *     |                         v |
1424          *   q |           f c           o |           f c
1425          *   u |         c               l |         c
1426          *   o |       f                 t |       f
1427          *   t |     c                   a |     c
1428          *     | c f                     g | c f
1429          *     |                         e |
1430          *     +---------------            +----------------
1431          *       0 1 2 3 4 5 6               0 1 2 3 4 5 6
1432          *          corner                      corner
1433          *
1434          *    c = corner
1435          *    f = fuse corner
1436          *
1437          */
1438         for (apply_scaling = false, i = 0; corner <= end; corner++, i++) {
1439                 freq_corner = cdata[i].freq;
1440                 fnum = cdata[i].fuse_corner;
1441                 fuse = &drv->fuse_corners[fnum];
1442                 if (fnum)
1443                         prev_fuse = &drv->fuse_corners[fnum - 1];
1444                 else
1445                         prev_fuse = NULL;
1446
1447                 corner->fuse_corner = fuse;
1448                 corner->uV = fuse->uV;
1449                 if (prev_fuse && cdata[i - 1].freq == prev_fuse->max_freq) {
1450                         quot_offset = &fuses[fnum].quotient_offset;
1451                         if (quot_offset->width) {
1452                                 quot_diff = cpr_read_efuse(qfprom, quot_offset);
1453                                 quot_diff *= fdata->quot_scale;
1454                                 if (adj_quot_offset)
1455                                         quot_diff += adj_quot_offset[fnum];
1456                         } else {
1457                                 quot_diff = fuse->quot - prev_fuse->quot;
1458                         }
1459
1460                         freq_diff = fuse->max_freq - prev_fuse->max_freq;
1461                         freq_diff /= 1000000; /* Convert to MHz */
1462                         scaling = 1000 * quot_diff / freq_diff;
1463                         scaling = min(scaling, fdata[fnum].max_quot_scale);
1464
1465                         apply_scaling = true;
1466                 } else if (freq_corner == fuse->max_freq) {
1467                         /* This is a fuse corner; don't scale anything */
1468                         apply_scaling = false;
1469                 }
1470
1471                 if (apply_scaling) {
1472                         freq_diff = fuse->max_freq - freq_corner;
1473                         freq_diff_mhz = freq_diff / 1000000;
1474                         corner->quot_adjust = scaling * freq_diff_mhz / 1000;
1475
1476                         freq_high = fuse->max_freq;
1477                         freq_low = fuse->max_freq;
1478                         volt_high = fuse->uV;
1479
1480                         /*
1481                         if (freq_high > freq_low && volt_high > volt_low &&
1482                             freq_high > freq_corner)
1483                         */
1484
1485                         temp = freq_diff * (fuse->uV - prev_fuse->uV);
1486                         do_div(temp, freq_high - freq_low);
1487
1488                         /*
1489                          * max_volt_scale has units of uV/MHz while freq values
1490                          * have units of Hz.  Divide by 1000000 to convert to.
1491                          */
1492                         temp_limit = freq_diff * fdata[fnum].max_volt_scale;
1493                         do_div(temp_limit, 1000000);
1494
1495                         corner->uV = volt_high - min(temp, temp_limit);
1496                         corner->uV = roundup(corner->uV, step_volt);
1497                 }
1498
1499                 if (adj_quot)
1500                         corner->quot_adjust -= adj_quot[i];
1501
1502                 if (adj_volt)
1503                         corner->uV += adj_volt[i];
1504
1505                 /* Load per corner ceiling and floor voltages if they exist. */
1506                 if (override) {
1507                         corner->max_uV = override->max_uV[i];
1508                         corner->min_uV = override->min_uV[i];
1509                 } else {
1510                         corner->max_uV = fuse->max_uV;
1511                         corner->min_uV = fuse->min_uV;
1512                 }
1513
1514                 if (drv->ceiling_max < corner->max_uV)
1515                         drv->ceiling_max = corner->max_uV;
1516
1517                 corner->uV = clamp(corner->uV, corner->min_uV, corner->max_uV);
1518                 corner->last_uV = corner->uV;
1519
1520                 /* Reduce the ceiling voltage if needed */
1521                 if (desc->reduce_to_corner_uV && corner->uV < corner->max_uV)
1522                         corner->max_uV = corner->uV;
1523                 else if (desc->reduce_to_fuse_uV && fuse->uV < corner->max_uV)
1524                         corner->max_uV = max(corner->min_uV, fuse->uV);
1525
1526                 pr_debug("corner %d: [%d %d %d] quot %d\n", i,
1527                                 corner->min_uV, corner->uV, corner->max_uV,
1528                                 fuse->quot - corner->quot_adjust);
1529         }
1530 }
1531
1532 static const struct cpr_fuse *
1533 cpr_get_fuses(const struct cpr_desc *desc, void __iomem *qfprom)
1534 {
1535         u32 expected = desc->cpr_fuses.redundant_value;
1536         const struct qfprom_offset *fuse = &desc->cpr_fuses.redundant;
1537         unsigned int idx;
1538
1539         idx = !!(fuse->width && cpr_read_efuse(qfprom, fuse) == expected);
1540
1541         return &desc->cpr_fuses.cpr_fuse[idx * desc->num_fuse_corners];
1542 }
1543
1544 static bool cpr_is_close_loop_disabled(struct cpr_drv *drv,
1545                 const struct cpr_desc *desc, void __iomem *qfprom,
1546                 const struct cpr_fuse *fuses,
1547                 const struct corner_adjustment *adj)
1548 {
1549         const struct qfprom_offset *disable;
1550         unsigned int idx;
1551         struct fuse_corner *highest_fuse, *second_highest_fuse;
1552         int min_diff_quot, diff_quot;
1553
1554         if (adj && adj->disable_closed_loop)
1555                 return true;
1556
1557         if (!desc->cpr_fuses.disable)
1558                 return false;
1559
1560         /*
1561          * Are the fuses the redundant ones? This avoids reading the fuse
1562          * redundant bit again
1563          */
1564         idx = !!(fuses == desc->cpr_fuses.cpr_fuse);
1565         disable = &desc->cpr_fuses.disable[idx];
1566
1567         if (cpr_read_efuse(qfprom, disable))
1568                 return true;
1569
1570         if (!fuses->quotient_offset.width) {
1571                 /*
1572                  * Check if the target quotients for the highest two fuse
1573                  * corners are too close together.
1574                  */
1575                 highest_fuse = &drv->fuse_corners[drv->num_fuse_corners - 1];
1576                 second_highest_fuse = highest_fuse - 1;
1577
1578                 min_diff_quot = desc->min_diff_quot;
1579                 diff_quot = highest_fuse->quot - second_highest_fuse->quot;
1580
1581                 return diff_quot < min_diff_quot;
1582         }
1583
1584         return false;
1585 }
1586
1587 static int cpr_init_parameters(struct platform_device *pdev,
1588                 struct cpr_drv *drv)
1589 {
1590         struct device_node *of_node = pdev->dev.of_node;
1591         int ret;
1592
1593         ret = of_property_read_u32(of_node, "qcom,cpr-ref-clk",
1594                           &drv->ref_clk_khz);
1595         if (ret)
1596                 return ret;
1597         ret = of_property_read_u32(of_node, "qcom,cpr-timer-delay-us",
1598                           &drv->timer_delay_us);
1599         if (ret)
1600                 return ret;
1601         ret = of_property_read_u32(of_node, "qcom,cpr-timer-cons-up",
1602                           &drv->timer_cons_up);
1603         if (ret)
1604                 return ret;
1605         ret = of_property_read_u32(of_node, "qcom,cpr-timer-cons-down",
1606                           &drv->timer_cons_down);
1607         if (ret)
1608                 return ret;
1609         drv->timer_cons_down &= RBIF_TIMER_ADJ_CONS_DOWN_MASK;
1610
1611         ret = of_property_read_u32(of_node, "qcom,cpr-up-threshold",
1612                           &drv->up_threshold);
1613         drv->up_threshold &= RBCPR_CTL_UP_THRESHOLD_MASK;
1614         if (ret)
1615                 return ret;
1616
1617         ret = of_property_read_u32(of_node, "qcom,cpr-down-threshold",
1618                           &drv->down_threshold);
1619         drv->down_threshold &= RBCPR_CTL_DN_THRESHOLD_MASK;
1620         if (ret)
1621                 return ret;
1622
1623         ret = of_property_read_u32(of_node, "qcom,cpr-idle-clocks",
1624                           &drv->idle_clocks);
1625         drv->idle_clocks &= RBCPR_STEP_QUOT_IDLE_CLK_MASK;
1626         if (ret)
1627                 return ret;
1628
1629         ret = of_property_read_u32(of_node, "qcom,cpr-gcnt-us", &drv->gcnt_us);
1630         if (ret)
1631                 return ret;
1632         ret = of_property_read_u32(of_node, "qcom,vdd-apc-step-up-limit",
1633                           &drv->vdd_apc_step_up_limit);
1634         if (ret)
1635                 return ret;
1636         ret = of_property_read_u32(of_node, "qcom,vdd-apc-step-down-limit",
1637                           &drv->vdd_apc_step_down_limit);
1638         if (ret)
1639                 return ret;
1640
1641         ret = of_property_read_u32(of_node, "qcom,cpr-clamp-timer-interval",
1642                                   &drv->clamp_timer_interval);
1643         if (ret && ret != -EINVAL)
1644                 return ret;
1645
1646         drv->clamp_timer_interval = min_t(unsigned int,
1647                                            drv->clamp_timer_interval,
1648                                            RBIF_TIMER_ADJ_CLAMP_INT_MASK);
1649
1650         pr_debug("up threshold = %u, down threshold = %u\n",
1651                 drv->up_threshold, drv->down_threshold);
1652
1653         return 0;
1654 }
1655
1656 static int cpr_init_and_enable_corner(struct cpr_drv *drv)
1657 {
1658         unsigned long rate;
1659         struct corner *end;
1660
1661         end = &drv->corners[drv->num_corners - 1];
1662         rate = clk_get_rate(drv->cpu_clk);
1663
1664         for (drv->corner = drv->corners; drv->corner <= end; drv->corner++)
1665                 if (drv->corner->freq == rate)
1666                         break;
1667
1668         if (drv->corner > end)
1669                 return -EINVAL;
1670
1671         return cpr_enable(drv);
1672 }
1673
1674 static struct corner_data msm8916_corner_data[] = {
1675         /* [corner] -> { fuse corner, freq } */
1676         { 0,  200000000 },
1677         { 0,  400000000 },
1678         { 1,  533330000 },
1679         { 1,  800000000 },
1680         { 2,  998400000 },
1681         { 2, 1094400000 },
1682         { 2, 1152000000 },
1683         { 2, 1209600000 },
1684         { 2, 1363200000 },
1685 };
1686
1687 static const struct cpr_desc msm8916_desc = {
1688         .num_fuse_corners = 3,
1689         .vdd_mx_vmin_method = VDD_MX_VMIN_APC_CORNER_MAP,
1690         .min_diff_quot = CPR_FUSE_MIN_QUOT_DIFF,
1691         .step_quot = (int []){ 26, 26, 26, 26, 26, 26, 26, 26 },
1692         .cpr_fuses = {
1693                 .init_voltage_step = 10000,
1694                 .fuse_corner_data = (struct fuse_corner_data[]){
1695                         /* ref_uV max_uV min_uV max_q q_off q_scl v_scl mx */
1696                         { 1050000, 1050000, 1050000,   0, 0, 1, 0, 3 },
1697                         { 1150000, 1150000, 1050000,   0, 0, 1, 0, 4 },
1698                         { 1350000, 1350000, 1162500, 650, 0, 1, 0, 6 },
1699                 },
1700                 .cpr_fuse = (struct cpr_fuse[]){
1701                         {
1702                                 .ring_osc = { 222, 3, 6},
1703                                 .init_voltage = { 220, 6, 2 },
1704                                 .quotient = { 221, 12, 2 },
1705                         },
1706                         {
1707                                 .ring_osc = { 222, 3, 6},
1708                                 .init_voltage = { 218, 6, 2 },
1709                                 .quotient = { 219, 12, 0 },
1710                         },
1711                         {
1712                                 .ring_osc = { 222, 3, 6},
1713                                 .init_voltage = { 216, 6, 0 },
1714                                 .quotient = { 216, 12, 6 },
1715                         },
1716                 },
1717                 .disable = &(struct qfprom_offset){ 223, 1, 1 },
1718         },
1719         .speed_bin = { 12, 3, 2 },
1720         .pvs_version = { 6, 2, 7 },
1721         .corner_data = msm8916_corner_data,
1722         .num_corners = ARRAY_SIZE(msm8916_corner_data),
1723         .num_freq_plans = 3,
1724         .freq_plans = (struct freq_plan[]){
1725                 {
1726                         .speed_bin = 0,
1727                         .pvs_version = 0,
1728                         .plan = (const struct corner_data* []){
1729                                 msm8916_corner_data + 0,
1730                                 msm8916_corner_data + 1,
1731                                 msm8916_corner_data + 2,
1732                                 msm8916_corner_data + 3,
1733                                 msm8916_corner_data + 4,
1734                                 msm8916_corner_data + 5,
1735                                 msm8916_corner_data + 6,
1736                                 msm8916_corner_data + 7,
1737                                 NULL
1738                         },
1739                 },
1740                 {
1741                         .speed_bin = 0,
1742                         .pvs_version = 1,
1743                         .plan = (const struct corner_data* []){
1744                                 msm8916_corner_data + 0,
1745                                 msm8916_corner_data + 1,
1746                                 msm8916_corner_data + 2,
1747                                 msm8916_corner_data + 3,
1748                                 msm8916_corner_data + 4,
1749                                 msm8916_corner_data + 5,
1750                                 msm8916_corner_data + 6,
1751                                 msm8916_corner_data + 7,
1752                                 NULL
1753                         },
1754                 },
1755                 {
1756                         .speed_bin = 2,
1757                         .pvs_version = 0,
1758                         .plan = (const struct corner_data* []){
1759                                 msm8916_corner_data + 0,
1760                                 msm8916_corner_data + 1,
1761                                 msm8916_corner_data + 2,
1762                                 msm8916_corner_data + 3,
1763                                 msm8916_corner_data + 4,
1764                                 msm8916_corner_data + 5,
1765                                 msm8916_corner_data + 6,
1766                                 msm8916_corner_data + 7,
1767                                 msm8916_corner_data + 8,
1768                                 NULL
1769                         },
1770                 },
1771         },
1772 };
1773
1774 static const struct acc_desc msm8916_acc_desc = {
1775         .settings = (struct reg_sequence[]){
1776                 { 0xf000, 0 },
1777                 { 0xf000, 0x100 },
1778                 { 0xf000, 0x101 }
1779         },
1780         .override_settings = (struct reg_sequence[]){
1781                 { 0xf000, 0 },
1782                 { 0xf000, 0x100 },
1783                 { 0xf000, 0x100 }
1784         },
1785         .num_regs_per_fuse = 1,
1786         .override = { 6, 1, 4 },
1787         .override_value = 1,
1788 };
1789
1790 static const struct of_device_id cpr_descs[] = {
1791         { .compatible = "qcom,qfprom-msm8916", .data = &msm8916_desc },
1792         { }
1793 };
1794
1795 static const struct of_device_id acc_descs[] = {
1796         { .compatible = "qcom,tcsr-msm8916", .data = &msm8916_acc_desc },
1797         { }
1798 };
1799
1800 static int cpr_probe(struct platform_device *pdev)
1801 {
1802         struct resource *res;
1803         struct device *dev = &pdev->dev;
1804         struct cpr_drv *drv;
1805         const struct cpr_fuse *cpr_fuses;
1806         const struct corner_adjustment *adj;
1807         const struct corner_data **plan;
1808         size_t len;
1809         int irq, ret;
1810         const struct cpr_desc *desc;
1811         const struct acc_desc *acc_desc;
1812         const struct of_device_id *match;
1813         struct device_node *np;
1814         void __iomem *qfprom;
1815         u32 cpr_rev = FUSE_REVISION_UNKNOWN;
1816         u32 speed_bin = SPEED_BIN_NONE;
1817         u32 pvs_version = 0;
1818         struct platform_device_info devinfo = { .name = "cpufreq-dt", };
1819
1820         np = of_parse_phandle(dev->of_node, "eeprom", 0);
1821         if (!np)
1822                 return -ENODEV;
1823
1824         match = of_match_node(cpr_descs, np);
1825         if (!match)
1826                 return -EINVAL;
1827         desc = match->data;
1828
1829         /* TODO: Get from eeprom API */
1830         qfprom = devm_ioremap(dev, 0x58000, 0x7000);
1831         if (!qfprom)
1832                 return -ENOMEM;
1833
1834         len = sizeof(*drv) +
1835               sizeof(*drv->fuse_corners) * desc->num_fuse_corners +
1836               sizeof(*drv->corners) * desc->num_corners;
1837
1838         drv = devm_kzalloc(dev, len, GFP_KERNEL);
1839         if (!drv)
1840                 return -ENOMEM;
1841
1842         np = of_parse_phandle(dev->of_node, "acc-syscon", 0);
1843         if (!np)
1844                 return -ENODEV;
1845
1846         match = of_match_node(acc_descs, np);
1847         if (!match)
1848                 return -EINVAL;
1849
1850         acc_desc = match->data;
1851         drv->tcsr = syscon_node_to_regmap(np);
1852         if (IS_ERR(drv->tcsr))
1853                 return PTR_ERR(drv->tcsr);
1854
1855         drv->num_fuse_corners = desc->num_fuse_corners;
1856         drv->num_corners = desc->num_corners;
1857         drv->fuse_corners = (struct fuse_corner *)(drv + 1);
1858         drv->corners = (struct corner *)(drv->fuse_corners +
1859                         drv->num_fuse_corners);
1860         mutex_init(&drv->lock);
1861
1862         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1863         drv->base = devm_ioremap_resource(&pdev->dev, res);
1864         if (IS_ERR(drv->base))
1865                 return PTR_ERR(drv->base);
1866
1867         irq = platform_get_irq(pdev, 0);
1868         if (irq < 0)
1869                 return -EINVAL;
1870
1871         drv->vdd_mx = devm_regulator_get(dev, "vdd-mx");
1872         if (IS_ERR(drv->vdd_mx))
1873                 return PTR_ERR(drv->vdd_mx);
1874
1875         drv->vdd_mx_vmin_method = desc->vdd_mx_vmin_method;
1876         drv->vdd_mx_vmax = desc->vdd_mx_vmax;
1877
1878         if (desc->fuse_revision.width)
1879                 cpr_rev = cpr_read_efuse(qfprom, &desc->fuse_revision);
1880         if (desc->speed_bin.width)
1881                 speed_bin = cpr_read_efuse(qfprom, &desc->speed_bin);
1882         if (desc->pvs_version.width)
1883                 pvs_version = cpr_read_efuse(qfprom, &desc->pvs_version);
1884
1885         plan = find_freq_plan(desc, speed_bin, pvs_version);
1886         if (!plan)
1887                 return -EINVAL;
1888
1889         cpr_fuses = cpr_get_fuses(desc, qfprom);
1890         cpr_populate_ring_osc_idx(cpr_fuses, drv, qfprom);
1891
1892         adj = cpr_find_adjustment(speed_bin, pvs_version, cpr_rev, desc, drv);
1893
1894         cpr_fuse_corner_init(drv, desc, qfprom, cpr_fuses, speed_bin, adj,
1895                              acc_desc);
1896         cpr_corner_init(drv, desc, cpr_fuses, speed_bin, pvs_version, qfprom,
1897                         adj, plan);
1898
1899         ret = cpr_populate_opps(dev->of_node, drv, plan);
1900         if (ret)
1901                 return ret;
1902
1903         drv->loop_disabled = cpr_is_close_loop_disabled(drv, desc, qfprom,
1904                         cpr_fuses, adj);
1905         pr_info("CPR closed loop is %sabled\n",
1906                 drv->loop_disabled ? "dis" : "en");
1907
1908         ret = cpr_init_parameters(pdev, drv);
1909         if (ret)
1910                 return ret;
1911
1912         /* Configure CPR HW but keep it disabled */
1913         ret = cpr_config(drv);
1914         if (ret)
1915                 return ret;
1916
1917         /* Enable ACC if required */
1918         if (acc_desc->enable_mask)
1919                 regmap_update_bits(drv->tcsr, acc_desc->enable_reg,
1920                                    acc_desc->enable_mask,
1921                                    acc_desc->enable_mask);
1922
1923         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1924                         cpr_irq_handler, IRQF_ONESHOT | IRQF_TRIGGER_RISING,
1925                         "cpr", drv);
1926         if (ret)
1927                 return ret;
1928
1929         ret = cpr_init_and_enable_corner(drv);
1930         if (ret)
1931                 return ret;
1932
1933         drv->reg_nb.notifier_call = cpr_regulator_notifier;
1934         ret = regulator_register_notifier(drv->vdd_apc, &drv->reg_nb);
1935         if (ret)
1936                 return ret;
1937
1938         drv->cpufreq_nb.notifier_call = cpr_cpufreq_notifier;
1939         ret = cpufreq_register_notifier(&drv->cpufreq_nb,
1940                                         CPUFREQ_TRANSITION_NOTIFIER);
1941         if (ret) {
1942                 regulator_unregister_notifier(drv->vdd_apc, &drv->reg_nb);
1943                 return ret;
1944         }
1945
1946         /*
1947          * Ensure that enable state accurately reflects the case in which CPR
1948          * is permanently disabled.
1949          */
1950         //cpr_vreg->enable &= !cpr_vreg->loop_disabled;
1951
1952         platform_set_drvdata(pdev, drv);
1953
1954         return PTR_ERR_OR_ZERO(platform_device_register_full(&devinfo));
1955 }
1956
1957 static int cpr_remove(struct platform_device *pdev)
1958 {
1959         struct cpr_drv *drv = platform_get_drvdata(pdev);
1960
1961         if (cpr_is_allowed(drv)) {
1962                 cpr_ctl_disable(drv);
1963                 cpr_irq_set(drv, 0);
1964         }
1965
1966         return 0;
1967 }
1968
1969 static const struct of_device_id cpr_match_table[] = {
1970         { .compatible = "qcom,cpr" },
1971         { }
1972 };
1973 MODULE_DEVICE_TABLE(of, cpr_match_table);
1974
1975 static struct platform_driver cpr_driver = {
1976         .probe          = cpr_probe,
1977         .remove         = cpr_remove,
1978         .driver         = {
1979                 .name   = "qcom-cpr",
1980                 .of_match_table = cpr_match_table,
1981                 .pm = &cpr_pm_ops,
1982         },
1983 };
1984 module_platform_driver(cpr_driver);
1985
1986 MODULE_DESCRIPTION("Core Power Reduction (CPR) driver");
1987 MODULE_LICENSE("GPL v2");
1988 MODULE_ALIAS("platform:qcom-cpr");