2 * Copyright (c) 2015, Sony Mobile Communications AB.
3 * Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/regulator/driver.h>
20 #include <linux/regulator/machine.h>
21 #include <linux/regulator/of_regulator.h>
22 #include <linux/soc/qcom/smd-rpm.h>
23 #include <linux/regulator/qcom_smd-regulator.h>
30 struct qcom_smd_rpm *rpm;
35 struct regulator_desc desc;
41 struct rpm_regulator_req {
47 #define RPM_KEY_SWEN 0x6e657773 /* "swen" */
48 #define RPM_KEY_UV 0x00007675 /* "uv" */
49 #define RPM_KEY_MA 0x0000616d /* "ma" */
50 #define RPM_KEY_FLOOR 0x00636676 /* "vfc" */
51 #define RPM_KEY_CORNER 0x6e726f63 /* "corn" */
53 #define RPM_MIN_FLOOR_CORNER 0
54 #define RPM_MAX_FLOOR_CORNER 6
56 static int rpm_reg_write_active(struct qcom_rpm_reg *vreg,
57 struct rpm_regulator_req *req,
60 return qcom_rpm_smd_write(vreg->rpm,
61 QCOM_SMD_RPM_ACTIVE_STATE,
67 int qcom_rpm_set_floor(struct regulator *regulator, int floor)
69 struct regulator_dev *rdev = regulator->rdev;
70 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
71 struct rpm_regulator_req req;
74 req.key = RPM_KEY_FLOOR;
75 req.nbytes = sizeof(u32);
78 if (floor < RPM_MIN_FLOOR_CORNER || floor > RPM_MAX_FLOOR_CORNER)
81 ret = rpm_reg_write_active(vreg, &req, sizeof(req));
83 dev_err(rdev_get_dev(rdev), "Failed to set floor %d\n", floor);
87 EXPORT_SYMBOL(qcom_rpm_set_floor);
89 int qcom_rpm_set_corner(struct regulator *regulator, int corner)
91 struct regulator_dev *rdev = regulator->rdev;
92 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
93 struct rpm_regulator_req req;
96 req.key = RPM_KEY_CORNER;
97 req.nbytes = sizeof(u32);
100 if (corner < RPM_MIN_FLOOR_CORNER || corner > RPM_MAX_FLOOR_CORNER)
103 ret = rpm_reg_write_active(vreg, &req, sizeof(req));
105 dev_err(rdev_get_dev(rdev), "Failed to set corner %d\n", corner);
109 EXPORT_SYMBOL(qcom_rpm_set_corner);
111 static int rpm_reg_enable(struct regulator_dev *rdev)
113 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
114 struct rpm_regulator_req req;
117 req.key = cpu_to_le32(RPM_KEY_SWEN);
118 req.nbytes = cpu_to_le32(sizeof(u32));
119 req.value = cpu_to_le32(1);
121 ret = rpm_reg_write_active(vreg, &req, sizeof(req));
123 vreg->is_enabled = 1;
128 static int rpm_reg_is_enabled(struct regulator_dev *rdev)
130 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
132 return vreg->is_enabled;
135 static int rpm_reg_disable(struct regulator_dev *rdev)
137 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
138 struct rpm_regulator_req req;
141 req.key = cpu_to_le32(RPM_KEY_SWEN);
142 req.nbytes = cpu_to_le32(sizeof(u32));
145 ret = rpm_reg_write_active(vreg, &req, sizeof(req));
147 vreg->is_enabled = 0;
152 static int rpm_reg_get_voltage(struct regulator_dev *rdev)
154 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
159 static int rpm_reg_set_voltage(struct regulator_dev *rdev,
164 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
165 struct rpm_regulator_req req;
168 req.key = cpu_to_le32(RPM_KEY_UV);
169 req.nbytes = cpu_to_le32(sizeof(u32));
170 req.value = cpu_to_le32(min_uV);
172 ret = rpm_reg_write_active(vreg, &req, sizeof(req));
179 static int rpm_reg_set_load(struct regulator_dev *rdev, int load_uA)
181 struct qcom_rpm_reg *vreg = rdev_get_drvdata(rdev);
182 struct rpm_regulator_req req;
184 req.key = cpu_to_le32(RPM_KEY_MA);
185 req.nbytes = cpu_to_le32(sizeof(u32));
186 req.value = cpu_to_le32(load_uA / 1000);
188 return rpm_reg_write_active(vreg, &req, sizeof(req));
191 static const struct regulator_ops rpm_smps_ldo_ops = {
192 .enable = rpm_reg_enable,
193 .disable = rpm_reg_disable,
194 .is_enabled = rpm_reg_is_enabled,
195 .list_voltage = regulator_list_voltage_linear_range,
197 .get_voltage = rpm_reg_get_voltage,
198 .set_voltage = rpm_reg_set_voltage,
200 .set_load = rpm_reg_set_load,
203 static const struct regulator_ops rpm_switch_ops = {
204 .enable = rpm_reg_enable,
205 .disable = rpm_reg_disable,
206 .is_enabled = rpm_reg_is_enabled,
209 static const struct regulator_desc pma8084_hfsmps = {
210 .linear_ranges = (struct regulator_linear_range[]) {
211 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
212 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
214 .n_linear_ranges = 2,
216 .ops = &rpm_smps_ldo_ops,
219 static const struct regulator_desc pma8084_ftsmps = {
220 .linear_ranges = (struct regulator_linear_range[]) {
221 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
222 REGULATOR_LINEAR_RANGE(700000, 185, 339, 10000),
224 .n_linear_ranges = 2,
226 .ops = &rpm_smps_ldo_ops,
229 static const struct regulator_desc pma8084_pldo = {
230 .linear_ranges = (struct regulator_linear_range[]) {
231 REGULATOR_LINEAR_RANGE(750000, 0, 30, 25000),
232 REGULATOR_LINEAR_RANGE(1500000, 31, 99, 50000),
234 .n_linear_ranges = 2,
236 .ops = &rpm_smps_ldo_ops,
239 static const struct regulator_desc pma8084_nldo = {
240 .linear_ranges = (struct regulator_linear_range[]) {
241 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
243 .n_linear_ranges = 1,
245 .ops = &rpm_smps_ldo_ops,
248 static const struct regulator_desc pma8084_switch = {
249 .ops = &rpm_switch_ops,
252 static const struct regulator_desc pm8x41_hfsmps = {
253 .linear_ranges = (struct regulator_linear_range[]) {
254 REGULATOR_LINEAR_RANGE( 375000, 0, 95, 12500),
255 REGULATOR_LINEAR_RANGE(1550000, 96, 158, 25000),
257 .n_linear_ranges = 2,
259 .ops = &rpm_smps_ldo_ops,
262 static const struct regulator_desc pm8841_ftsmps = {
263 .linear_ranges = (struct regulator_linear_range[]) {
264 REGULATOR_LINEAR_RANGE(350000, 0, 184, 5000),
265 REGULATOR_LINEAR_RANGE(700000, 185, 339, 10000),
267 .n_linear_ranges = 2,
269 .ops = &rpm_smps_ldo_ops,
272 static const struct regulator_desc pm8941_boost = {
273 .linear_ranges = (struct regulator_linear_range[]) {
274 REGULATOR_LINEAR_RANGE(4000000, 0, 15, 100000),
276 .n_linear_ranges = 1,
278 .ops = &rpm_smps_ldo_ops,
281 static const struct regulator_desc pm8941_pldo = {
282 .linear_ranges = (struct regulator_linear_range[]) {
283 REGULATOR_LINEAR_RANGE( 750000, 0, 30, 25000),
284 REGULATOR_LINEAR_RANGE(1500000, 31, 99, 50000),
286 .n_linear_ranges = 2,
288 .ops = &rpm_smps_ldo_ops,
291 static const struct regulator_desc pm8941_nldo = {
292 .linear_ranges = (struct regulator_linear_range[]) {
293 REGULATOR_LINEAR_RANGE(750000, 0, 63, 12500),
295 .n_linear_ranges = 1,
297 .ops = &rpm_smps_ldo_ops,
300 static const struct regulator_desc pm8941_lnldo = {
303 .ops = &rpm_smps_ldo_ops,
306 static const struct regulator_desc pm8941_switch = {
307 .ops = &rpm_switch_ops,
310 static const struct regulator_desc pm8916_pldo = {
311 .linear_ranges = (struct regulator_linear_range[]) {
312 REGULATOR_LINEAR_RANGE(750000, 0, 208, 12500),
314 .n_linear_ranges = 1,
316 .ops = &rpm_smps_ldo_ops,
319 static const struct regulator_desc pm8916_nldo = {
320 .linear_ranges = (struct regulator_linear_range[]) {
321 REGULATOR_LINEAR_RANGE(375000, 0, 93, 12500),
323 .n_linear_ranges = 1,
325 .ops = &rpm_smps_ldo_ops,
328 static const struct regulator_desc pm8916_buck_lvo_smps = {
329 .linear_ranges = (struct regulator_linear_range[]) {
330 REGULATOR_LINEAR_RANGE(375000, 0, 95, 12500),
331 REGULATOR_LINEAR_RANGE(750000, 96, 127, 25000),
333 .n_linear_ranges = 2,
335 .ops = &rpm_smps_ldo_ops,
338 static const struct regulator_desc pm8916_buck_hvo_smps = {
339 .linear_ranges = (struct regulator_linear_range[]) {
340 REGULATOR_LINEAR_RANGE(1550000, 0, 31, 25000),
342 .n_linear_ranges = 1,
344 .ops = &rpm_smps_ldo_ops,
347 struct rpm_regulator_data {
351 const struct regulator_desc *desc;
355 static const struct rpm_regulator_data rpm_pm8841_regulators[] = {
356 { "s1", QCOM_SMD_RPM_SMPB, 1, &pm8x41_hfsmps, "vdd_s1" },
357 { "s2", QCOM_SMD_RPM_SMPB, 2, &pm8841_ftsmps, "vdd_s2" },
358 { "s3", QCOM_SMD_RPM_SMPB, 3, &pm8x41_hfsmps, "vdd_s3" },
359 { "s4", QCOM_SMD_RPM_SMPB, 4, &pm8841_ftsmps, "vdd_s4" },
360 { "s5", QCOM_SMD_RPM_SMPB, 5, &pm8841_ftsmps, "vdd_s5" },
361 { "s6", QCOM_SMD_RPM_SMPB, 6, &pm8841_ftsmps, "vdd_s6" },
362 { "s7", QCOM_SMD_RPM_SMPB, 7, &pm8841_ftsmps, "vdd_s7" },
363 { "s8", QCOM_SMD_RPM_SMPB, 8, &pm8841_ftsmps, "vdd_s8" },
367 static const struct rpm_regulator_data rpm_pm8916_regulators[] = {
368 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8916_buck_lvo_smps, "vdd_s1" },
369 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8916_buck_lvo_smps, "vdd_s2" },
370 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8916_buck_lvo_smps, "vdd_s3" },
371 { "s4", QCOM_SMD_RPM_SMPA, 4, &pm8916_buck_hvo_smps, "vdd_s4" },
372 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8916_nldo, "vdd_l1_l2_l3" },
373 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8916_nldo, "vdd_l1_l2_l3" },
374 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8916_nldo, "vdd_l1_l2_l3" },
375 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8916_pldo, "vdd_l4_l5_l6" },
376 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8916_pldo, "vdd_l4_l5_l6" },
377 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8916_pldo, "vdd_l4_l5_l6" },
378 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8916_pldo, "vdd_l7" },
379 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
380 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18" },
381 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
382 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
383 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
384 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
385 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
386 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
387 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
388 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
389 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8916_pldo, "vdd_l8_l9_l10_l11_l12_l13_l14_l15_l16_l17_l18"},
393 static const struct rpm_regulator_data rpm_pm8941_regulators[] = {
394 { "s1", QCOM_SMD_RPM_SMPA, 1, &pm8x41_hfsmps, "vdd_s1" },
395 { "s2", QCOM_SMD_RPM_SMPA, 2, &pm8x41_hfsmps, "vdd_s2" },
396 { "s3", QCOM_SMD_RPM_SMPA, 3, &pm8x41_hfsmps, "vdd_s3" },
397 { "s4", QCOM_SMD_RPM_BOOST, 1, &pm8941_boost },
399 { "l1", QCOM_SMD_RPM_LDOA, 1, &pm8941_nldo, "vdd_l1_l3" },
400 { "l2", QCOM_SMD_RPM_LDOA, 2, &pm8941_nldo, "vdd_l2_lvs1_2_3" },
401 { "l3", QCOM_SMD_RPM_LDOA, 3, &pm8941_nldo, "vdd_l1_l3" },
402 { "l4", QCOM_SMD_RPM_LDOA, 4, &pm8941_nldo, "vdd_l4_l11" },
403 { "l5", QCOM_SMD_RPM_LDOA, 5, &pm8941_lnldo, "vdd_l5_l7" },
404 { "l6", QCOM_SMD_RPM_LDOA, 6, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
405 { "l7", QCOM_SMD_RPM_LDOA, 7, &pm8941_lnldo, "vdd_l5_l7" },
406 { "l8", QCOM_SMD_RPM_LDOA, 8, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
407 { "l9", QCOM_SMD_RPM_LDOA, 9, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
408 { "l10", QCOM_SMD_RPM_LDOA, 10, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
409 { "l11", QCOM_SMD_RPM_LDOA, 11, &pm8941_nldo, "vdd_l4_l11" },
410 { "l12", QCOM_SMD_RPM_LDOA, 12, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
411 { "l13", QCOM_SMD_RPM_LDOA, 13, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
412 { "l14", QCOM_SMD_RPM_LDOA, 14, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
413 { "l15", QCOM_SMD_RPM_LDOA, 15, &pm8941_pldo, "vdd_l6_l12_l14_l15" },
414 { "l16", QCOM_SMD_RPM_LDOA, 16, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
415 { "l17", QCOM_SMD_RPM_LDOA, 17, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
416 { "l18", QCOM_SMD_RPM_LDOA, 18, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
417 { "l19", QCOM_SMD_RPM_LDOA, 19, &pm8941_pldo, "vdd_l8_l16_l18_l19" },
418 { "l20", QCOM_SMD_RPM_LDOA, 20, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
419 { "l21", QCOM_SMD_RPM_LDOA, 21, &pm8941_pldo, "vdd_l21" },
420 { "l22", QCOM_SMD_RPM_LDOA, 22, &pm8941_pldo, "vdd_l9_l10_l17_l22" },
421 { "l23", QCOM_SMD_RPM_LDOA, 23, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
422 { "l24", QCOM_SMD_RPM_LDOA, 24, &pm8941_pldo, "vdd_l13_l20_l23_l24" },
424 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pm8941_switch, "vdd_l2_lvs1_2_3" },
425 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pm8941_switch, "vdd_l2_lvs1_2_3" },
426 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pm8941_switch, "vdd_l2_lvs1_2_3" },
428 { "5vs1", QCOM_SMD_RPM_VSA, 4, &pm8941_switch, "vin_5vs" },
429 { "5vs2", QCOM_SMD_RPM_VSA, 5, &pm8941_switch, "vin_5vs" },
434 static const struct rpm_regulator_data rpm_pma8084_regulators[] = {
435 { "s1", QCOM_SMD_RPM_SMPA, 1, &pma8084_ftsmps, "vdd_s1" },
436 { "s2", QCOM_SMD_RPM_SMPA, 2, &pma8084_ftsmps, "vdd_s2" },
437 { "s3", QCOM_SMD_RPM_SMPA, 3, &pma8084_hfsmps, "vdd_s3" },
438 { "s4", QCOM_SMD_RPM_SMPA, 4, &pma8084_hfsmps, "vdd_s4" },
439 { "s5", QCOM_SMD_RPM_SMPA, 5, &pma8084_hfsmps, "vdd_s5" },
440 { "s6", QCOM_SMD_RPM_SMPA, 6, &pma8084_ftsmps, "vdd_s6" },
441 { "s7", QCOM_SMD_RPM_SMPA, 7, &pma8084_ftsmps, "vdd_s7" },
442 { "s8", QCOM_SMD_RPM_SMPA, 8, &pma8084_ftsmps, "vdd_s8" },
443 { "s9", QCOM_SMD_RPM_SMPA, 9, &pma8084_ftsmps, "vdd_s9" },
444 { "s10", QCOM_SMD_RPM_SMPA, 10, &pma8084_ftsmps, "vdd_s10" },
445 { "s11", QCOM_SMD_RPM_SMPA, 11, &pma8084_ftsmps, "vdd_s11" },
446 { "s12", QCOM_SMD_RPM_SMPA, 12, &pma8084_ftsmps, "vdd_s12" },
448 { "l1", QCOM_SMD_RPM_LDOA, 1, &pma8084_nldo, "vdd_l1_l11" },
449 { "l2", QCOM_SMD_RPM_LDOA, 2, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
450 { "l3", QCOM_SMD_RPM_LDOA, 3, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
451 { "l4", QCOM_SMD_RPM_LDOA, 4, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
452 { "l5", QCOM_SMD_RPM_LDOA, 5, &pma8084_pldo, "vdd_l5_l7" },
453 { "l6", QCOM_SMD_RPM_LDOA, 6, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
454 { "l7", QCOM_SMD_RPM_LDOA, 7, &pma8084_pldo, "vdd_l5_l7" },
455 { "l8", QCOM_SMD_RPM_LDOA, 8, &pma8084_pldo, "vdd_l8" },
456 { "l9", QCOM_SMD_RPM_LDOA, 9, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
457 { "l10", QCOM_SMD_RPM_LDOA, 10, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
458 { "l11", QCOM_SMD_RPM_LDOA, 11, &pma8084_nldo, "vdd_l1_l11" },
459 { "l12", QCOM_SMD_RPM_LDOA, 12, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
460 { "l13", QCOM_SMD_RPM_LDOA, 13, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
461 { "l14", QCOM_SMD_RPM_LDOA, 14, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
462 { "l15", QCOM_SMD_RPM_LDOA, 15, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
463 { "l16", QCOM_SMD_RPM_LDOA, 16, &pma8084_pldo, "vdd_l16_l25" },
464 { "l17", QCOM_SMD_RPM_LDOA, 17, &pma8084_pldo, "vdd_l17" },
465 { "l18", QCOM_SMD_RPM_LDOA, 18, &pma8084_pldo, "vdd_l18" },
466 { "l19", QCOM_SMD_RPM_LDOA, 19, &pma8084_pldo, "vdd_l19" },
467 { "l20", QCOM_SMD_RPM_LDOA, 20, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
468 { "l21", QCOM_SMD_RPM_LDOA, 21, &pma8084_pldo, "vdd_l21" },
469 { "l22", QCOM_SMD_RPM_LDOA, 22, &pma8084_pldo, "vdd_l22" },
470 { "l23", QCOM_SMD_RPM_LDOA, 23, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
471 { "l24", QCOM_SMD_RPM_LDOA, 24, &pma8084_pldo, "vdd_l9_l10_l13_l20_l23_l24" },
472 { "l25", QCOM_SMD_RPM_LDOA, 25, &pma8084_pldo, "vdd_l16_l25" },
473 { "l26", QCOM_SMD_RPM_LDOA, 26, &pma8084_pldo, "vdd_l6_l12_l14_l15_l26" },
474 { "l27", QCOM_SMD_RPM_LDOA, 27, &pma8084_nldo, "vdd_l2_l3_l4_l27" },
476 { "lvs1", QCOM_SMD_RPM_VSA, 1, &pma8084_switch },
477 { "lvs2", QCOM_SMD_RPM_VSA, 2, &pma8084_switch },
478 { "lvs3", QCOM_SMD_RPM_VSA, 3, &pma8084_switch },
479 { "lvs4", QCOM_SMD_RPM_VSA, 4, &pma8084_switch },
480 { "5vs1", QCOM_SMD_RPM_VSA, 5, &pma8084_switch },
485 static const struct of_device_id rpm_of_match[] = {
486 { .compatible = "qcom,rpm-pm8841-regulators", .data = &rpm_pm8841_regulators },
487 { .compatible = "qcom,rpm-pm8916-regulators", .data = &rpm_pm8916_regulators },
488 { .compatible = "qcom,rpm-pm8941-regulators", .data = &rpm_pm8941_regulators },
489 { .compatible = "qcom,rpm-pma8084-regulators", .data = &rpm_pma8084_regulators },
492 MODULE_DEVICE_TABLE(of, rpm_of_match);
494 static int rpm_reg_probe(struct platform_device *pdev)
496 const struct rpm_regulator_data *reg;
497 const struct of_device_id *match;
498 struct regulator_config config = { };
499 struct regulator_dev *rdev;
500 struct qcom_rpm_reg *vreg;
501 struct qcom_smd_rpm *rpm;
503 rpm = dev_get_drvdata(pdev->dev.parent);
505 dev_err(&pdev->dev, "unable to retrieve handle to rpm\n");
509 match = of_match_device(rpm_of_match, &pdev->dev);
510 for (reg = match->data; reg->name; reg++) {
511 vreg = devm_kzalloc(&pdev->dev, sizeof(*vreg), GFP_KERNEL);
515 vreg->dev = &pdev->dev;
516 vreg->type = reg->type;
520 memcpy(&vreg->desc, reg->desc, sizeof(vreg->desc));
523 vreg->desc.owner = THIS_MODULE;
524 vreg->desc.type = REGULATOR_VOLTAGE;
525 vreg->desc.name = reg->name;
526 vreg->desc.supply_name = reg->supply;
527 vreg->desc.of_match = reg->name;
529 config.dev = &pdev->dev;
530 config.driver_data = vreg;
531 rdev = devm_regulator_register(&pdev->dev, &vreg->desc, &config);
533 dev_err(&pdev->dev, "failed to register %s\n", reg->name);
534 return PTR_ERR(rdev);
541 static struct platform_driver rpm_reg_driver = {
542 .probe = rpm_reg_probe,
544 .name = "qcom_rpm_smd_regulator",
545 .of_match_table = rpm_of_match,
549 static int __init rpm_reg_init(void)
551 return platform_driver_register(&rpm_reg_driver);
553 subsys_initcall(rpm_reg_init);
555 static void __exit rpm_reg_exit(void)
557 platform_driver_unregister(&rpm_reg_driver);
559 module_exit(rpm_reg_exit)
561 MODULE_DESCRIPTION("Qualcomm RPM regulator driver");
562 MODULE_LICENSE("GPL v2");