2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
3 * Copyright (C) 2013, Intel Corporation
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/bitops.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/ioport.h>
21 #include <linux/errno.h>
22 #include <linux/err.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/platform_device.h>
27 #include <linux/spi/pxa2xx_spi.h>
28 #include <linux/spi/spi.h>
29 #include <linux/delay.h>
30 #include <linux/gpio.h>
31 #include <linux/slab.h>
32 #include <linux/clk.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/acpi.h>
36 #include "spi-pxa2xx.h"
38 MODULE_AUTHOR("Stephen Street");
39 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller");
40 MODULE_LICENSE("GPL");
41 MODULE_ALIAS("platform:pxa2xx-spi");
43 #define TIMOUT_DFLT 1000
46 * for testing SSCR1 changes that require SSP restart, basically
47 * everything except the service and interrupt enables, the pxa270 developer
48 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this
49 * list, but the PXA255 dev man says all bits without really meaning the
50 * service and interrupt enables
52 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \
53 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \
54 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \
55 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \
56 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \
57 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
59 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \
60 | QUARK_X1000_SSCR1_EFWR \
61 | QUARK_X1000_SSCR1_RFT \
62 | QUARK_X1000_SSCR1_TFT \
63 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM)
65 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24)
66 #define LPSS_CS_CONTROL_SW_MODE BIT(0)
67 #define LPSS_CS_CONTROL_CS_HIGH BIT(1)
68 #define LPSS_CAPS_CS_EN_SHIFT 9
69 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT)
72 /* LPSS offset from drv_data->ioaddr */
74 /* Register offsets from drv_data->lpss_base or -1 */
83 /* Chip select control */
84 unsigned cs_sel_shift;
89 /* Keep these sorted with enum pxa_ssp_type */
90 static const struct lpss_config lpss_platforms[] = {
96 .reg_capabilities = -1,
98 .tx_threshold_lo = 160,
99 .tx_threshold_hi = 224,
106 .reg_capabilities = -1,
108 .tx_threshold_lo = 160,
109 .tx_threshold_hi = 224,
116 .reg_capabilities = -1,
118 .tx_threshold_lo = 160,
119 .tx_threshold_hi = 224,
121 .cs_sel_mask = 1 << 2,
129 .reg_capabilities = -1,
131 .tx_threshold_lo = 32,
132 .tx_threshold_hi = 56,
139 .reg_capabilities = 0xfc,
141 .tx_threshold_lo = 16,
142 .tx_threshold_hi = 48,
144 .cs_sel_mask = 3 << 8,
148 static inline const struct lpss_config
149 *lpss_get_config(const struct driver_data *drv_data)
151 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP];
154 static bool is_lpss_ssp(const struct driver_data *drv_data)
156 switch (drv_data->ssp_type) {
168 static bool is_quark_x1000_ssp(const struct driver_data *drv_data)
170 return drv_data->ssp_type == QUARK_X1000_SSP;
173 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data)
175 switch (drv_data->ssp_type) {
176 case QUARK_X1000_SSP:
177 return QUARK_X1000_SSCR1_CHANGE_MASK;
179 return SSCR1_CHANGE_MASK;
184 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data)
186 switch (drv_data->ssp_type) {
187 case QUARK_X1000_SSP:
188 return RX_THRESH_QUARK_X1000_DFLT;
190 return RX_THRESH_DFLT;
194 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data)
198 switch (drv_data->ssp_type) {
199 case QUARK_X1000_SSP:
200 mask = QUARK_X1000_SSSR_TFL_MASK;
203 mask = SSSR_TFL_MASK;
207 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask;
210 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data,
215 switch (drv_data->ssp_type) {
216 case QUARK_X1000_SSP:
217 mask = QUARK_X1000_SSCR1_RFT;
226 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data,
227 u32 *sccr1_reg, u32 threshold)
229 switch (drv_data->ssp_type) {
230 case QUARK_X1000_SSP:
231 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold);
234 *sccr1_reg |= SSCR1_RxTresh(threshold);
239 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data,
240 u32 clk_div, u8 bits)
242 switch (drv_data->ssp_type) {
243 case QUARK_X1000_SSP:
245 | QUARK_X1000_SSCR0_Motorola
246 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits)
251 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits)
253 | (bits > 16 ? SSCR0_EDSS : 0);
258 * Read and write LPSS SSP private registers. Caller must first check that
259 * is_lpss_ssp() returns true before these can be called.
261 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset)
263 WARN_ON(!drv_data->lpss_base);
264 return readl(drv_data->lpss_base + offset);
267 static void __lpss_ssp_write_priv(struct driver_data *drv_data,
268 unsigned offset, u32 value)
270 WARN_ON(!drv_data->lpss_base);
271 writel(value, drv_data->lpss_base + offset);
275 * lpss_ssp_setup - perform LPSS SSP specific setup
276 * @drv_data: pointer to the driver private data
278 * Perform LPSS SSP specific setup. This function must be called first if
279 * one is going to use LPSS SSP private registers.
281 static void lpss_ssp_setup(struct driver_data *drv_data)
283 const struct lpss_config *config;
286 config = lpss_get_config(drv_data);
287 drv_data->lpss_base = drv_data->ioaddr + config->offset;
289 /* Enable software chip select control */
290 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
291 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH);
292 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH;
293 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
295 /* Enable multiblock DMA transfers */
296 if (drv_data->master_info->enable_dma) {
297 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1);
299 if (config->reg_general >= 0) {
300 value = __lpss_ssp_read_priv(drv_data,
301 config->reg_general);
302 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE;
303 __lpss_ssp_write_priv(drv_data,
304 config->reg_general, value);
309 static void lpss_ssp_select_cs(struct driver_data *drv_data,
310 const struct lpss_config *config)
314 if (!config->cs_sel_mask)
317 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
319 cs = drv_data->master->cur_msg->spi->chip_select;
320 cs <<= config->cs_sel_shift;
321 if (cs != (value & config->cs_sel_mask)) {
323 * When switching another chip select output active the
324 * output must be selected first and wait 2 ssp_clk cycles
325 * before changing state to active. Otherwise a short
326 * glitch will occur on the previous chip select since
327 * output select is latched but state control is not.
329 value &= ~config->cs_sel_mask;
331 __lpss_ssp_write_priv(drv_data,
332 config->reg_cs_ctrl, value);
334 (drv_data->master->max_speed_hz / 2));
338 static void lpss_ssp_cs_control(struct driver_data *drv_data, bool enable)
340 const struct lpss_config *config;
343 config = lpss_get_config(drv_data);
346 lpss_ssp_select_cs(drv_data, config);
348 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl);
350 value &= ~LPSS_CS_CONTROL_CS_HIGH;
352 value |= LPSS_CS_CONTROL_CS_HIGH;
353 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value);
356 static void cs_assert(struct driver_data *drv_data)
358 struct chip_data *chip = drv_data->cur_chip;
360 if (drv_data->ssp_type == CE4100_SSP) {
361 pxa2xx_spi_write(drv_data, SSSR, drv_data->cur_chip->frm);
365 if (chip->cs_control) {
366 chip->cs_control(PXA2XX_CS_ASSERT);
370 if (gpio_is_valid(chip->gpio_cs)) {
371 gpio_set_value(chip->gpio_cs, chip->gpio_cs_inverted);
375 if (is_lpss_ssp(drv_data))
376 lpss_ssp_cs_control(drv_data, true);
379 static void cs_deassert(struct driver_data *drv_data)
381 struct chip_data *chip = drv_data->cur_chip;
383 if (drv_data->ssp_type == CE4100_SSP)
386 if (chip->cs_control) {
387 chip->cs_control(PXA2XX_CS_DEASSERT);
391 if (gpio_is_valid(chip->gpio_cs)) {
392 gpio_set_value(chip->gpio_cs, !chip->gpio_cs_inverted);
396 if (is_lpss_ssp(drv_data))
397 lpss_ssp_cs_control(drv_data, false);
400 int pxa2xx_spi_flush(struct driver_data *drv_data)
402 unsigned long limit = loops_per_jiffy << 1;
405 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
406 pxa2xx_spi_read(drv_data, SSDR);
407 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit);
408 write_SSSR_CS(drv_data, SSSR_ROR);
413 static int null_writer(struct driver_data *drv_data)
415 u8 n_bytes = drv_data->n_bytes;
417 if (pxa2xx_spi_txfifo_full(drv_data)
418 || (drv_data->tx == drv_data->tx_end))
421 pxa2xx_spi_write(drv_data, SSDR, 0);
422 drv_data->tx += n_bytes;
427 static int null_reader(struct driver_data *drv_data)
429 u8 n_bytes = drv_data->n_bytes;
431 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
432 && (drv_data->rx < drv_data->rx_end)) {
433 pxa2xx_spi_read(drv_data, SSDR);
434 drv_data->rx += n_bytes;
437 return drv_data->rx == drv_data->rx_end;
440 static int u8_writer(struct driver_data *drv_data)
442 if (pxa2xx_spi_txfifo_full(drv_data)
443 || (drv_data->tx == drv_data->tx_end))
446 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx));
452 static int u8_reader(struct driver_data *drv_data)
454 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
455 && (drv_data->rx < drv_data->rx_end)) {
456 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
460 return drv_data->rx == drv_data->rx_end;
463 static int u16_writer(struct driver_data *drv_data)
465 if (pxa2xx_spi_txfifo_full(drv_data)
466 || (drv_data->tx == drv_data->tx_end))
469 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx));
475 static int u16_reader(struct driver_data *drv_data)
477 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
478 && (drv_data->rx < drv_data->rx_end)) {
479 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
483 return drv_data->rx == drv_data->rx_end;
486 static int u32_writer(struct driver_data *drv_data)
488 if (pxa2xx_spi_txfifo_full(drv_data)
489 || (drv_data->tx == drv_data->tx_end))
492 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx));
498 static int u32_reader(struct driver_data *drv_data)
500 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE)
501 && (drv_data->rx < drv_data->rx_end)) {
502 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR);
506 return drv_data->rx == drv_data->rx_end;
509 void *pxa2xx_spi_next_transfer(struct driver_data *drv_data)
511 struct spi_message *msg = drv_data->master->cur_msg;
512 struct spi_transfer *trans = drv_data->cur_transfer;
514 /* Move to next transfer */
515 if (trans->transfer_list.next != &msg->transfers) {
516 drv_data->cur_transfer =
517 list_entry(trans->transfer_list.next,
520 return RUNNING_STATE;
525 /* caller already set message->status; dma and pio irqs are blocked */
526 static void giveback(struct driver_data *drv_data)
528 struct spi_transfer* last_transfer;
529 struct spi_message *msg;
530 unsigned long timeout;
532 msg = drv_data->master->cur_msg;
533 drv_data->cur_transfer = NULL;
535 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
538 /* Delay if requested before any change in chip select */
539 if (last_transfer->delay_usecs)
540 udelay(last_transfer->delay_usecs);
542 /* Wait until SSP becomes idle before deasserting the CS */
543 timeout = jiffies + msecs_to_jiffies(10);
544 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY &&
545 !time_after(jiffies, timeout))
548 /* Drop chip select UNLESS cs_change is true or we are returning
549 * a message with an error, or next message is for another chip
551 if (!last_transfer->cs_change)
552 cs_deassert(drv_data);
554 struct spi_message *next_msg;
556 /* Holding of cs was hinted, but we need to make sure
557 * the next message is for the same chip. Don't waste
558 * time with the following tests unless this was hinted.
560 * We cannot postpone this until pump_messages, because
561 * after calling msg->complete (below) the driver that
562 * sent the current message could be unloaded, which
563 * could invalidate the cs_control() callback...
566 /* get a pointer to the next message, if any */
567 next_msg = spi_get_next_queued_message(drv_data->master);
569 /* see if the next and current messages point
572 if ((next_msg && next_msg->spi != msg->spi) ||
573 msg->state == ERROR_STATE)
574 cs_deassert(drv_data);
577 drv_data->cur_chip = NULL;
578 spi_finalize_current_message(drv_data->master);
581 static void reset_sccr1(struct driver_data *drv_data)
583 struct chip_data *chip = drv_data->cur_chip;
586 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1;
587 switch (drv_data->ssp_type) {
588 case QUARK_X1000_SSP:
589 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT;
592 sccr1_reg &= ~SSCR1_RFT;
595 sccr1_reg |= chip->threshold;
596 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
599 static void int_error_stop(struct driver_data *drv_data, const char* msg)
601 /* Stop and reset SSP */
602 write_SSSR_CS(drv_data, drv_data->clear_sr);
603 reset_sccr1(drv_data);
604 if (!pxa25x_ssp_comp(drv_data))
605 pxa2xx_spi_write(drv_data, SSTO, 0);
606 pxa2xx_spi_flush(drv_data);
607 pxa2xx_spi_write(drv_data, SSCR0,
608 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
610 dev_err(&drv_data->pdev->dev, "%s\n", msg);
612 drv_data->master->cur_msg->state = ERROR_STATE;
613 tasklet_schedule(&drv_data->pump_transfers);
616 static void int_transfer_complete(struct driver_data *drv_data)
618 /* Clear and disable interrupts */
619 write_SSSR_CS(drv_data, drv_data->clear_sr);
620 reset_sccr1(drv_data);
621 if (!pxa25x_ssp_comp(drv_data))
622 pxa2xx_spi_write(drv_data, SSTO, 0);
624 /* Update total byte transferred return count actual bytes read */
625 drv_data->master->cur_msg->actual_length += drv_data->len -
626 (drv_data->rx_end - drv_data->rx);
628 /* Transfer delays and chip select release are
629 * handled in pump_transfers or giveback
632 /* Move to next transfer */
633 drv_data->master->cur_msg->state = pxa2xx_spi_next_transfer(drv_data);
635 /* Schedule transfer tasklet */
636 tasklet_schedule(&drv_data->pump_transfers);
639 static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
641 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ?
642 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS;
644 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask;
646 if (irq_status & SSSR_ROR) {
647 int_error_stop(drv_data, "interrupt_transfer: fifo overrun");
651 if (irq_status & SSSR_TINT) {
652 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT);
653 if (drv_data->read(drv_data)) {
654 int_transfer_complete(drv_data);
659 /* Drain rx fifo, Fill tx fifo and prevent overruns */
661 if (drv_data->read(drv_data)) {
662 int_transfer_complete(drv_data);
665 } while (drv_data->write(drv_data));
667 if (drv_data->read(drv_data)) {
668 int_transfer_complete(drv_data);
672 if (drv_data->tx == drv_data->tx_end) {
676 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
677 sccr1_reg &= ~SSCR1_TIE;
680 * PXA25x_SSP has no timeout, set up rx threshould for the
681 * remaining RX bytes.
683 if (pxa25x_ssp_comp(drv_data)) {
686 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg);
688 bytes_left = drv_data->rx_end - drv_data->rx;
689 switch (drv_data->n_bytes) {
696 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data);
697 if (rx_thre > bytes_left)
698 rx_thre = bytes_left;
700 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre);
702 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg);
705 /* We did something */
709 static irqreturn_t ssp_int(int irq, void *dev_id)
711 struct driver_data *drv_data = dev_id;
713 u32 mask = drv_data->mask_sr;
717 * The IRQ might be shared with other peripherals so we must first
718 * check that are we RPM suspended or not. If we are we assume that
719 * the IRQ was not for us (we shouldn't be RPM suspended when the
720 * interrupt is enabled).
722 if (pm_runtime_suspended(&drv_data->pdev->dev))
726 * If the device is not yet in RPM suspended state and we get an
727 * interrupt that is meant for another device, check if status bits
728 * are all set to one. That means that the device is already
731 status = pxa2xx_spi_read(drv_data, SSSR);
735 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
737 /* Ignore possible writes if we don't need to write */
738 if (!(sccr1_reg & SSCR1_TIE))
741 /* Ignore RX timeout interrupt if it is disabled */
742 if (!(sccr1_reg & SSCR1_TINTE))
745 if (!(status & mask))
748 if (!drv_data->master->cur_msg) {
750 pxa2xx_spi_write(drv_data, SSCR0,
751 pxa2xx_spi_read(drv_data, SSCR0)
753 pxa2xx_spi_write(drv_data, SSCR1,
754 pxa2xx_spi_read(drv_data, SSCR1)
755 & ~drv_data->int_cr1);
756 if (!pxa25x_ssp_comp(drv_data))
757 pxa2xx_spi_write(drv_data, SSTO, 0);
758 write_SSSR_CS(drv_data, drv_data->clear_sr);
760 dev_err(&drv_data->pdev->dev,
761 "bad message state in interrupt handler\n");
767 return drv_data->transfer_handler(drv_data);
771 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply
772 * input frequency by fractions of 2^24. It also has a divider by 5.
774 * There are formulas to get baud rate value for given input frequency and
775 * divider parameters, such as DDS_CLK_RATE and SCR:
779 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1)
780 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2)
782 * DDS_CLK_RATE either 2^n or 2^n / 5.
783 * SCR is in range 0 .. 255
785 * Divisor = 5^i * 2^j * 2 * k
786 * i = [0, 1] i = 1 iff j = 0 or j > 3
787 * j = [0, 23] j = 0 iff i = 1
789 * Special case: j = 0, i = 1: Divisor = 2 / 5
791 * Accordingly to the specification the recommended values for DDS_CLK_RATE
793 * Case 1: 2^n, n = [0, 23]
794 * Case 2: 2^24 * 2 / 5 (0x666666)
795 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333)
797 * In all cases the lowest possible value is better.
799 * The function calculates parameters for all cases and chooses the one closest
800 * to the asked baud rate.
802 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds)
804 unsigned long xtal = 200000000;
805 unsigned long fref = xtal / 2; /* mandatory division by 2,
808 unsigned long fref1 = fref / 2; /* case 1 */
809 unsigned long fref2 = fref * 2 / 5; /* case 2 */
811 unsigned long q, q1, q2;
817 /* Set initial value for DDS_CLK_RATE */
818 mul = (1 << 24) >> 1;
820 /* Calculate initial quot */
821 q1 = DIV_ROUND_UP(fref1, rate);
823 /* Scale q1 if it's too big */
825 /* Scale q1 to range [1, 512] */
826 scale = fls_long(q1 - 1);
832 /* Round the result if we have a remainder */
836 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */
841 /* Get the remainder */
842 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate);
846 q2 = DIV_ROUND_UP(fref2, rate);
847 r2 = abs(fref2 / q2 - rate);
850 * Choose the best between two: less remainder we have the better. We
851 * can't go case 2 if q2 is greater than 256 since SCR register can
852 * hold only values 0 .. 255.
854 if (r2 >= r1 || q2 > 256) {
855 /* case 1 is better */
859 /* case 2 is better */
862 mul = (1 << 24) * 2 / 5;
865 /* Check case 3 only if the divisor is big enough */
866 if (fref / rate >= 80) {
870 /* Calculate initial quot */
871 q1 = DIV_ROUND_UP(fref, rate);
874 /* Get the remainder */
875 fssp = (u64)fref * m;
876 do_div(fssp, 1 << 24);
877 r1 = abs(fssp - rate);
879 /* Choose this one if it suits better */
881 /* case 3 is better */
891 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate)
893 unsigned long ssp_clk = drv_data->master->max_speed_hz;
894 const struct ssp_device *ssp = drv_data->ssp;
896 rate = min_t(int, ssp_clk, rate);
898 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP)
899 return (ssp_clk / (2 * rate) - 1) & 0xff;
901 return (ssp_clk / rate - 1) & 0xfff;
904 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data,
907 struct chip_data *chip = drv_data->cur_chip;
908 unsigned int clk_div;
910 switch (drv_data->ssp_type) {
911 case QUARK_X1000_SSP:
912 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate);
915 clk_div = ssp_get_clk_div(drv_data, rate);
921 static bool pxa2xx_spi_can_dma(struct spi_master *master,
922 struct spi_device *spi,
923 struct spi_transfer *xfer)
925 struct chip_data *chip = spi_get_ctldata(spi);
927 return chip->enable_dma &&
928 xfer->len <= MAX_DMA_LEN &&
929 xfer->len >= chip->dma_burst_size;
932 static void pump_transfers(unsigned long data)
934 struct driver_data *drv_data = (struct driver_data *)data;
935 struct spi_master *master = drv_data->master;
936 struct spi_message *message = master->cur_msg;
937 struct spi_transfer *transfer;
938 struct spi_transfer *previous;
939 struct chip_data *chip;
945 u32 dma_thresh = drv_data->cur_chip->dma_threshold;
946 u32 dma_burst = drv_data->cur_chip->dma_burst_size;
947 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data);
951 /* Get current state information */
952 transfer = drv_data->cur_transfer;
953 chip = drv_data->cur_chip;
955 /* Handle for abort */
956 if (message->state == ERROR_STATE) {
957 message->status = -EIO;
962 /* Handle end of message */
963 if (message->state == DONE_STATE) {
969 /* Delay if requested at end of transfer before CS change */
970 if (message->state == RUNNING_STATE) {
971 previous = list_entry(transfer->transfer_list.prev,
974 if (previous->delay_usecs)
975 udelay(previous->delay_usecs);
977 /* Drop chip select only if cs_change is requested */
978 if (previous->cs_change)
979 cs_deassert(drv_data);
982 /* Check if we can DMA this transfer */
983 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) {
985 /* reject already-mapped transfers; PIO won't always work */
986 if (message->is_dma_mapped
987 || transfer->rx_dma || transfer->tx_dma) {
988 dev_err(&drv_data->pdev->dev,
989 "pump_transfers: mapped transfer length of "
990 "%u is greater than %d\n",
991 transfer->len, MAX_DMA_LEN);
992 message->status = -EINVAL;
997 /* warn ... we force this to PIO mode */
998 dev_warn_ratelimited(&message->spi->dev,
999 "pump_transfers: DMA disabled for transfer length %ld "
1000 "greater than %d\n",
1001 (long)drv_data->len, MAX_DMA_LEN);
1004 /* Setup the transfer state based on the type of transfer */
1005 if (pxa2xx_spi_flush(drv_data) == 0) {
1006 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
1007 message->status = -EIO;
1011 drv_data->n_bytes = chip->n_bytes;
1012 drv_data->tx = (void *)transfer->tx_buf;
1013 drv_data->tx_end = drv_data->tx + transfer->len;
1014 drv_data->rx = transfer->rx_buf;
1015 drv_data->rx_end = drv_data->rx + transfer->len;
1016 drv_data->len = transfer->len;
1017 drv_data->write = drv_data->tx ? chip->write : null_writer;
1018 drv_data->read = drv_data->rx ? chip->read : null_reader;
1020 /* Change speed and bit per word on a per transfer */
1021 bits = transfer->bits_per_word;
1022 speed = transfer->speed_hz;
1024 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed);
1027 drv_data->n_bytes = 1;
1028 drv_data->read = drv_data->read != null_reader ?
1029 u8_reader : null_reader;
1030 drv_data->write = drv_data->write != null_writer ?
1031 u8_writer : null_writer;
1032 } else if (bits <= 16) {
1033 drv_data->n_bytes = 2;
1034 drv_data->read = drv_data->read != null_reader ?
1035 u16_reader : null_reader;
1036 drv_data->write = drv_data->write != null_writer ?
1037 u16_writer : null_writer;
1038 } else if (bits <= 32) {
1039 drv_data->n_bytes = 4;
1040 drv_data->read = drv_data->read != null_reader ?
1041 u32_reader : null_reader;
1042 drv_data->write = drv_data->write != null_writer ?
1043 u32_writer : null_writer;
1046 * if bits/word is changed in dma mode, then must check the
1047 * thresholds and burst also
1049 if (chip->enable_dma) {
1050 if (pxa2xx_spi_set_dma_burst_and_threshold(chip,
1054 dev_warn_ratelimited(&message->spi->dev,
1055 "pump_transfers: DMA burst size reduced to match bits_per_word\n");
1058 message->state = RUNNING_STATE;
1060 dma_mapped = master->can_dma &&
1061 master->can_dma(master, message->spi, transfer) &&
1062 master->cur_msg_mapped;
1065 /* Ensure we have the correct interrupt handler */
1066 drv_data->transfer_handler = pxa2xx_spi_dma_transfer;
1068 err = pxa2xx_spi_dma_prepare(drv_data, dma_burst);
1070 message->status = err;
1075 /* Clear status and start DMA engine */
1076 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1;
1077 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr);
1079 pxa2xx_spi_dma_start(drv_data);
1081 /* Ensure we have the correct interrupt handler */
1082 drv_data->transfer_handler = interrupt_transfer;
1085 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1;
1086 write_SSSR_CS(drv_data, drv_data->clear_sr);
1089 /* NOTE: PXA25x_SSP _could_ use external clocking ... */
1090 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits);
1091 if (!pxa25x_ssp_comp(drv_data))
1092 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1093 master->max_speed_hz
1094 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)),
1095 dma_mapped ? "DMA" : "PIO");
1097 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n",
1098 master->max_speed_hz / 2
1099 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)),
1100 dma_mapped ? "DMA" : "PIO");
1102 if (is_lpss_ssp(drv_data)) {
1103 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff)
1104 != chip->lpss_rx_threshold)
1105 pxa2xx_spi_write(drv_data, SSIRF,
1106 chip->lpss_rx_threshold);
1107 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff)
1108 != chip->lpss_tx_threshold)
1109 pxa2xx_spi_write(drv_data, SSITF,
1110 chip->lpss_tx_threshold);
1113 if (is_quark_x1000_ssp(drv_data) &&
1114 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate))
1115 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate);
1117 /* see if we need to reload the config registers */
1118 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0)
1119 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask)
1120 != (cr1 & change_mask)) {
1121 /* stop the SSP, and update the other bits */
1122 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE);
1123 if (!pxa25x_ssp_comp(drv_data))
1124 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1125 /* first set CR1 without interrupt and service enables */
1126 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask);
1127 /* restart the SSP */
1128 pxa2xx_spi_write(drv_data, SSCR0, cr0);
1131 if (!pxa25x_ssp_comp(drv_data))
1132 pxa2xx_spi_write(drv_data, SSTO, chip->timeout);
1135 cs_assert(drv_data);
1137 /* after chip select, release the data by enabling service
1138 * requests and interrupts, without changing any mode bits */
1139 pxa2xx_spi_write(drv_data, SSCR1, cr1);
1142 static int pxa2xx_spi_transfer_one_message(struct spi_master *master,
1143 struct spi_message *msg)
1145 struct driver_data *drv_data = spi_master_get_devdata(master);
1147 /* Initial message state*/
1148 msg->state = START_STATE;
1149 drv_data->cur_transfer = list_entry(msg->transfers.next,
1150 struct spi_transfer,
1153 /* prepare to setup the SSP, in pump_transfers, using the per
1154 * chip configuration */
1155 drv_data->cur_chip = spi_get_ctldata(msg->spi);
1157 /* Mark as busy and launch transfers */
1158 tasklet_schedule(&drv_data->pump_transfers);
1162 static int pxa2xx_spi_unprepare_transfer(struct spi_master *master)
1164 struct driver_data *drv_data = spi_master_get_devdata(master);
1166 /* Disable the SSP now */
1167 pxa2xx_spi_write(drv_data, SSCR0,
1168 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
1173 static int setup_cs(struct spi_device *spi, struct chip_data *chip,
1174 struct pxa2xx_spi_chip *chip_info)
1178 if (chip == NULL || chip_info == NULL)
1181 /* NOTE: setup() can be called multiple times, possibly with
1182 * different chip_info, release previously requested GPIO
1184 if (gpio_is_valid(chip->gpio_cs))
1185 gpio_free(chip->gpio_cs);
1187 /* If (*cs_control) is provided, ignore GPIO chip select */
1188 if (chip_info->cs_control) {
1189 chip->cs_control = chip_info->cs_control;
1193 if (gpio_is_valid(chip_info->gpio_cs)) {
1194 err = gpio_request(chip_info->gpio_cs, "SPI_CS");
1196 dev_err(&spi->dev, "failed to request chip select GPIO%d\n",
1197 chip_info->gpio_cs);
1201 chip->gpio_cs = chip_info->gpio_cs;
1202 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH;
1204 err = gpio_direction_output(chip->gpio_cs,
1205 !chip->gpio_cs_inverted);
1211 static int setup(struct spi_device *spi)
1213 struct pxa2xx_spi_chip *chip_info;
1214 struct chip_data *chip;
1215 const struct lpss_config *config;
1216 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1217 uint tx_thres, tx_hi_thres, rx_thres;
1219 switch (drv_data->ssp_type) {
1220 case QUARK_X1000_SSP:
1221 tx_thres = TX_THRESH_QUARK_X1000_DFLT;
1223 rx_thres = RX_THRESH_QUARK_X1000_DFLT;
1230 config = lpss_get_config(drv_data);
1231 tx_thres = config->tx_threshold_lo;
1232 tx_hi_thres = config->tx_threshold_hi;
1233 rx_thres = config->rx_threshold;
1236 tx_thres = TX_THRESH_DFLT;
1238 rx_thres = RX_THRESH_DFLT;
1242 /* Only alloc on first setup */
1243 chip = spi_get_ctldata(spi);
1245 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1249 if (drv_data->ssp_type == CE4100_SSP) {
1250 if (spi->chip_select > 4) {
1252 "failed setup: cs number must not be > 4.\n");
1257 chip->frm = spi->chip_select;
1260 chip->enable_dma = drv_data->master_info->enable_dma;
1261 chip->timeout = TIMOUT_DFLT;
1264 /* protocol drivers may change the chip settings, so...
1265 * if chip_info exists, use it */
1266 chip_info = spi->controller_data;
1268 /* chip_info isn't always needed */
1271 if (chip_info->timeout)
1272 chip->timeout = chip_info->timeout;
1273 if (chip_info->tx_threshold)
1274 tx_thres = chip_info->tx_threshold;
1275 if (chip_info->tx_hi_threshold)
1276 tx_hi_thres = chip_info->tx_hi_threshold;
1277 if (chip_info->rx_threshold)
1278 rx_thres = chip_info->rx_threshold;
1279 chip->dma_threshold = 0;
1280 if (chip_info->enable_loopback)
1281 chip->cr1 = SSCR1_LBM;
1284 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres);
1285 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres)
1286 | SSITF_TxHiThresh(tx_hi_thres);
1288 /* set dma burst and threshold outside of chip_info path so that if
1289 * chip_info goes away after setting chip->enable_dma, the
1290 * burst and threshold can still respond to changes in bits_per_word */
1291 if (chip->enable_dma) {
1292 /* set up legal burst and threshold for dma */
1293 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi,
1295 &chip->dma_burst_size,
1296 &chip->dma_threshold)) {
1298 "in setup: DMA burst size reduced to match bits_per_word\n");
1302 switch (drv_data->ssp_type) {
1303 case QUARK_X1000_SSP:
1304 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres)
1305 & QUARK_X1000_SSCR1_RFT)
1306 | (QUARK_X1000_SSCR1_TxTresh(tx_thres)
1307 & QUARK_X1000_SSCR1_TFT);
1310 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) |
1311 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT);
1315 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH);
1316 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0)
1317 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0);
1319 if (spi->mode & SPI_LOOP)
1320 chip->cr1 |= SSCR1_LBM;
1322 if (spi->bits_per_word <= 8) {
1324 chip->read = u8_reader;
1325 chip->write = u8_writer;
1326 } else if (spi->bits_per_word <= 16) {
1328 chip->read = u16_reader;
1329 chip->write = u16_writer;
1330 } else if (spi->bits_per_word <= 32) {
1332 chip->read = u32_reader;
1333 chip->write = u32_writer;
1336 spi_set_ctldata(spi, chip);
1338 if (drv_data->ssp_type == CE4100_SSP)
1341 return setup_cs(spi, chip, chip_info);
1344 static void cleanup(struct spi_device *spi)
1346 struct chip_data *chip = spi_get_ctldata(spi);
1347 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1352 if (drv_data->ssp_type != CE4100_SSP && gpio_is_valid(chip->gpio_cs))
1353 gpio_free(chip->gpio_cs);
1361 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = {
1362 { "INT33C0", LPSS_LPT_SSP },
1363 { "INT33C1", LPSS_LPT_SSP },
1364 { "INT3430", LPSS_LPT_SSP },
1365 { "INT3431", LPSS_LPT_SSP },
1366 { "80860F0E", LPSS_BYT_SSP },
1367 { "8086228E", LPSS_BSW_SSP },
1370 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match);
1372 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1377 if (adev && adev->pnp.unique_id &&
1378 !kstrtouint(adev->pnp.unique_id, 0, &devid))
1382 #else /* !CONFIG_ACPI */
1383 static int pxa2xx_spi_get_port_id(struct acpi_device *adev)
1390 * PCI IDs of compound devices that integrate both host controller and private
1391 * integrated DMA engine. Please note these are not used in module
1392 * autoloading and probing in this module but matching the LPSS SSP type.
1394 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = {
1396 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP },
1397 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP },
1399 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP },
1400 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP },
1402 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP },
1403 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP },
1405 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP },
1406 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP },
1407 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP },
1409 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP },
1410 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP },
1411 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP },
1413 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP },
1414 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP },
1415 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP },
1419 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param)
1421 struct device *dev = param;
1423 if (dev != chan->device->dev->parent)
1429 static struct pxa2xx_spi_master *
1430 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1432 struct pxa2xx_spi_master *pdata;
1433 struct acpi_device *adev;
1434 struct ssp_device *ssp;
1435 struct resource *res;
1436 const struct acpi_device_id *adev_id = NULL;
1437 const struct pci_device_id *pcidev_id = NULL;
1440 adev = ACPI_COMPANION(&pdev->dev);
1442 if (dev_is_pci(pdev->dev.parent))
1443 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match,
1444 to_pci_dev(pdev->dev.parent));
1446 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
1452 type = (int)adev_id->driver_data;
1454 type = (int)pcidev_id->driver_data;
1458 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1462 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1468 ssp->phys_base = res->start;
1469 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res);
1470 if (IS_ERR(ssp->mmio_base))
1474 pdata->tx_param = pdev->dev.parent;
1475 pdata->rx_param = pdev->dev.parent;
1476 pdata->dma_filter = pxa2xx_spi_idma_filter;
1479 ssp->clk = devm_clk_get(&pdev->dev, NULL);
1480 ssp->irq = platform_get_irq(pdev, 0);
1483 ssp->port_id = pxa2xx_spi_get_port_id(adev);
1485 pdata->num_chipselect = 1;
1486 pdata->enable_dma = true;
1491 #else /* !CONFIG_PCI */
1492 static inline struct pxa2xx_spi_master *
1493 pxa2xx_spi_init_pdata(struct platform_device *pdev)
1499 static int pxa2xx_spi_fw_translate_cs(struct spi_master *master, unsigned cs)
1501 struct driver_data *drv_data = spi_master_get_devdata(master);
1503 if (has_acpi_companion(&drv_data->pdev->dev)) {
1504 switch (drv_data->ssp_type) {
1506 * For Atoms the ACPI DeviceSelection used by the Windows
1507 * driver starts from 1 instead of 0 so translate it here
1508 * to match what Linux expects.
1522 static int pxa2xx_spi_probe(struct platform_device *pdev)
1524 struct device *dev = &pdev->dev;
1525 struct pxa2xx_spi_master *platform_info;
1526 struct spi_master *master;
1527 struct driver_data *drv_data;
1528 struct ssp_device *ssp;
1529 const struct lpss_config *config;
1533 platform_info = dev_get_platdata(dev);
1534 if (!platform_info) {
1535 platform_info = pxa2xx_spi_init_pdata(pdev);
1536 if (!platform_info) {
1537 dev_err(&pdev->dev, "missing platform data\n");
1542 ssp = pxa_ssp_request(pdev->id, pdev->name);
1544 ssp = &platform_info->ssp;
1546 if (!ssp->mmio_base) {
1547 dev_err(&pdev->dev, "failed to get ssp\n");
1551 master = spi_alloc_master(dev, sizeof(struct driver_data));
1553 dev_err(&pdev->dev, "cannot alloc spi_master\n");
1557 drv_data = spi_master_get_devdata(master);
1558 drv_data->master = master;
1559 drv_data->master_info = platform_info;
1560 drv_data->pdev = pdev;
1561 drv_data->ssp = ssp;
1563 master->dev.of_node = pdev->dev.of_node;
1564 /* the spi->mode bits understood by this driver: */
1565 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
1567 master->bus_num = ssp->port_id;
1568 master->dma_alignment = DMA_ALIGNMENT;
1569 master->cleanup = cleanup;
1570 master->setup = setup;
1571 master->transfer_one_message = pxa2xx_spi_transfer_one_message;
1572 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer;
1573 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs;
1574 master->auto_runtime_pm = true;
1575 master->flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX;
1577 drv_data->ssp_type = ssp->type;
1579 drv_data->ioaddr = ssp->mmio_base;
1580 drv_data->ssdr_physical = ssp->phys_base + SSDR;
1581 if (pxa25x_ssp_comp(drv_data)) {
1582 switch (drv_data->ssp_type) {
1583 case QUARK_X1000_SSP:
1584 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1587 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
1591 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE;
1592 drv_data->dma_cr1 = 0;
1593 drv_data->clear_sr = SSSR_ROR;
1594 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR;
1596 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
1597 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE;
1598 drv_data->dma_cr1 = DEFAULT_DMA_CR1;
1599 drv_data->clear_sr = SSSR_ROR | SSSR_TINT;
1600 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR;
1603 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev),
1606 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq);
1607 goto out_error_master_alloc;
1610 /* Setup DMA if requested */
1611 if (platform_info->enable_dma) {
1612 status = pxa2xx_spi_dma_setup(drv_data);
1614 dev_dbg(dev, "no DMA channels available, using PIO\n");
1615 platform_info->enable_dma = false;
1617 master->can_dma = pxa2xx_spi_can_dma;
1621 /* Enable SOC clock */
1622 clk_prepare_enable(ssp->clk);
1624 master->max_speed_hz = clk_get_rate(ssp->clk);
1626 /* Load default SSP configuration */
1627 pxa2xx_spi_write(drv_data, SSCR0, 0);
1628 switch (drv_data->ssp_type) {
1629 case QUARK_X1000_SSP:
1630 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT)
1631 | QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT);
1632 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1634 /* using the Motorola SPI protocol and use 8 bit frame */
1635 pxa2xx_spi_write(drv_data, SSCR0,
1636 QUARK_X1000_SSCR0_Motorola
1637 | QUARK_X1000_SSCR0_DataSize(8));
1640 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) |
1641 SSCR1_TxTresh(TX_THRESH_DFLT);
1642 pxa2xx_spi_write(drv_data, SSCR1, tmp);
1643 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8);
1644 pxa2xx_spi_write(drv_data, SSCR0, tmp);
1648 if (!pxa25x_ssp_comp(drv_data))
1649 pxa2xx_spi_write(drv_data, SSTO, 0);
1651 if (!is_quark_x1000_ssp(drv_data))
1652 pxa2xx_spi_write(drv_data, SSPSP, 0);
1654 if (is_lpss_ssp(drv_data)) {
1655 lpss_ssp_setup(drv_data);
1656 config = lpss_get_config(drv_data);
1657 if (config->reg_capabilities >= 0) {
1658 tmp = __lpss_ssp_read_priv(drv_data,
1659 config->reg_capabilities);
1660 tmp &= LPSS_CAPS_CS_EN_MASK;
1661 tmp >>= LPSS_CAPS_CS_EN_SHIFT;
1662 platform_info->num_chipselect = ffz(tmp);
1663 } else if (config->cs_num) {
1664 platform_info->num_chipselect = config->cs_num;
1667 master->num_chipselect = platform_info->num_chipselect;
1669 tasklet_init(&drv_data->pump_transfers, pump_transfers,
1670 (unsigned long)drv_data);
1672 pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
1673 pm_runtime_use_autosuspend(&pdev->dev);
1674 pm_runtime_set_active(&pdev->dev);
1675 pm_runtime_enable(&pdev->dev);
1677 /* Register with the SPI framework */
1678 platform_set_drvdata(pdev, drv_data);
1679 status = devm_spi_register_master(&pdev->dev, master);
1681 dev_err(&pdev->dev, "problem registering spi master\n");
1682 goto out_error_clock_enabled;
1687 out_error_clock_enabled:
1688 clk_disable_unprepare(ssp->clk);
1689 pxa2xx_spi_dma_release(drv_data);
1690 free_irq(ssp->irq, drv_data);
1692 out_error_master_alloc:
1693 spi_master_put(master);
1698 static int pxa2xx_spi_remove(struct platform_device *pdev)
1700 struct driver_data *drv_data = platform_get_drvdata(pdev);
1701 struct ssp_device *ssp;
1705 ssp = drv_data->ssp;
1707 pm_runtime_get_sync(&pdev->dev);
1709 /* Disable the SSP at the peripheral and SOC level */
1710 pxa2xx_spi_write(drv_data, SSCR0, 0);
1711 clk_disable_unprepare(ssp->clk);
1714 if (drv_data->master_info->enable_dma)
1715 pxa2xx_spi_dma_release(drv_data);
1717 pm_runtime_put_noidle(&pdev->dev);
1718 pm_runtime_disable(&pdev->dev);
1721 free_irq(ssp->irq, drv_data);
1729 static void pxa2xx_spi_shutdown(struct platform_device *pdev)
1733 if ((status = pxa2xx_spi_remove(pdev)) != 0)
1734 dev_err(&pdev->dev, "shutdown failed with %d\n", status);
1737 #ifdef CONFIG_PM_SLEEP
1738 static int pxa2xx_spi_suspend(struct device *dev)
1740 struct driver_data *drv_data = dev_get_drvdata(dev);
1741 struct ssp_device *ssp = drv_data->ssp;
1744 status = spi_master_suspend(drv_data->master);
1747 pxa2xx_spi_write(drv_data, SSCR0, 0);
1749 if (!pm_runtime_suspended(dev))
1750 clk_disable_unprepare(ssp->clk);
1755 static int pxa2xx_spi_resume(struct device *dev)
1757 struct driver_data *drv_data = dev_get_drvdata(dev);
1758 struct ssp_device *ssp = drv_data->ssp;
1761 /* Enable the SSP clock */
1762 if (!pm_runtime_suspended(dev))
1763 clk_prepare_enable(ssp->clk);
1765 /* Restore LPSS private register bits */
1766 if (is_lpss_ssp(drv_data))
1767 lpss_ssp_setup(drv_data);
1769 /* Start the queue running */
1770 status = spi_master_resume(drv_data->master);
1772 dev_err(dev, "problem starting queue (%d)\n", status);
1781 static int pxa2xx_spi_runtime_suspend(struct device *dev)
1783 struct driver_data *drv_data = dev_get_drvdata(dev);
1785 clk_disable_unprepare(drv_data->ssp->clk);
1789 static int pxa2xx_spi_runtime_resume(struct device *dev)
1791 struct driver_data *drv_data = dev_get_drvdata(dev);
1793 clk_prepare_enable(drv_data->ssp->clk);
1798 static const struct dev_pm_ops pxa2xx_spi_pm_ops = {
1799 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume)
1800 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend,
1801 pxa2xx_spi_runtime_resume, NULL)
1804 static struct platform_driver driver = {
1806 .name = "pxa2xx-spi",
1807 .pm = &pxa2xx_spi_pm_ops,
1808 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match),
1810 .probe = pxa2xx_spi_probe,
1811 .remove = pxa2xx_spi_remove,
1812 .shutdown = pxa2xx_spi_shutdown,
1815 static int __init pxa2xx_spi_init(void)
1817 return platform_driver_register(&driver);
1819 subsys_initcall(pxa2xx_spi_init);
1821 static void __exit pxa2xx_spi_exit(void)
1823 platform_driver_unregister(&driver);
1825 module_exit(pxa2xx_spi_exit);