drivers/staging/comedi/drivers/cb_pcidas64.c

   1 /*
   2     comedi/drivers/cb_pcidas64.c
   3     This is a driver for the ComputerBoards/MeasurementComputing PCI-DAS
   4     64xx, 60xx, and 4020 cards.
   5
   6     Author:  Frank Mori Hess <fmhess@users.sourceforge.net>
   7     Copyright (C) 2001, 2002 Frank Mori Hess
   8
   9     Thanks also go to the following people:
  10
  11     Steve Rosenbluth, for providing the source code for
  12     his pci-das6402 driver, and source code for working QNX pci-6402
  13     drivers by Greg Laird and Mariusz Bogacz.  None of the code was
  14     used directly here, but it was useful as an additional source of
  15     documentation on how to program the boards.
  16
  17     John Sims, for much testing and feedback on pcidas-4020 support.
  18
  19     COMEDI - Linux Control and Measurement Device Interface
  20     Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
  21
  22     This program is free software; you can redistribute it and/or modify
  23     it under the terms of the GNU General Public License as published by
  24     the Free Software Foundation; either version 2 of the License, or
  25     (at your option) any later version.
  26
  27     This program is distributed in the hope that it will be useful,
  28     but WITHOUT ANY WARRANTY; without even the implied warranty of
  29     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  30     GNU General Public License for more details.
  31 */
  32
  33 /*
  34  * Driver: cb_pcidas64
  35  * Description: MeasurementComputing PCI-DAS64xx, 60XX, and 4020 series
  36  *   with the PLX 9080 PCI controller
  37  * Author: Frank Mori Hess <fmhess@users.sourceforge.net>
  38  * Status: works
  39  * Updated: Fri, 02 Nov 2012 18:58:55 +0000
  40  * Devices: [Measurement Computing] PCI-DAS6402/16 (cb_pcidas64),
  41  *   PCI-DAS6402/12, PCI-DAS64/M1/16, PCI-DAS64/M2/16,
  42  *   PCI-DAS64/M3/16, PCI-DAS6402/16/JR, PCI-DAS64/M1/16/JR,
  43  *   PCI-DAS64/M2/16/JR, PCI-DAS64/M3/16/JR, PCI-DAS64/M1/14,
  44  *   PCI-DAS64/M2/14, PCI-DAS64/M3/14, PCI-DAS6013, PCI-DAS6014,
  45  *   PCI-DAS6023, PCI-DAS6025, PCI-DAS6030,
  46  *   PCI-DAS6031, PCI-DAS6032, PCI-DAS6033, PCI-DAS6034,
  47  *   PCI-DAS6035, PCI-DAS6036, PCI-DAS6040, PCI-DAS6052,
  48  *   PCI-DAS6070, PCI-DAS6071, PCI-DAS4020/12
  49  *
  50  * Configuration options:
  51  *   None.
  52  *
  53  * Manual attachment of PCI cards with the comedi_config utility is not
  54  * supported by this driver; they are attached automatically.
  55  *
  56  * These boards may be autocalibrated with the comedi_calibrate utility.
  57  *
  58  * To select the bnc trigger input on the 4020 (instead of the dio input),
  59  * specify a nonzero channel in the chanspec.  If you wish to use an external
  60  * master clock on the 4020, you may do so by setting the scan_begin_src
  61  * to TRIG_OTHER, and using an INSN_CONFIG_TIMER_1 configuration insn
  62  * to configure the divisor to use for the external clock.
  63  *
  64  * Some devices are not identified because the PCI device IDs are not yet
  65  * known. If you have such a board, please let the maintainers know.
  66  */
  67
  68 /*
  69
  70 TODO:
  71         make it return error if user attempts an ai command that uses the
  72         external queue, and an ao command simultaneously user counter subdevice
  73         there are a number of boards this driver will support when they are
  74         fully released, but does not yet since the pci device id numbers
  75         are not yet available.
  76
  77         support prescaled 100khz clock for slow pacing (not available on 6000
  78         series?)
  79
  80         make ao fifo size adjustable like ai fifo
  81 */
  82
  83 #include <linux/module.h>
  84 #include <linux/delay.h>
  85 #include <linux/interrupt.h>
  86
  87 #include "../comedi_pci.h"
  88
  89 #include "8255.h"
  90 #include "plx9080.h"
  91
  92 #define TIMER_BASE 25           /*  40MHz master clock */
  93 /* 100kHz 'prescaled' clock for slow acquisition,
  94  * maybe I'll support this someday */
  95 #define PRESCALED_TIMER_BASE    10000
  96 #define DMA_BUFFER_SIZE 0x1000
  97
  98 /* maximum value that can be loaded into board's 24-bit counters*/
  99 static const int max_counter_value = 0xffffff;
 100
 101 /* PCI-DAS64xxx base addresses */
 102
 103 /* devpriv->main_iobase registers */
 104 enum write_only_registers {
 105         INTR_ENABLE_REG = 0x0,  /*  interrupt enable register */
 106         HW_CONFIG_REG = 0x2,    /*  hardware config register */
 107         DAQ_SYNC_REG = 0xc,
 108         DAQ_ATRIG_LOW_4020_REG = 0xc,
 109         ADC_CONTROL0_REG = 0x10,        /*  adc control register 0 */
 110         ADC_CONTROL1_REG = 0x12,        /*  adc control register 1 */
 111         CALIBRATION_REG = 0x14,
 112         /*  lower 16 bits of adc sample interval counter */
 113         ADC_SAMPLE_INTERVAL_LOWER_REG = 0x16,
 114         /*  upper 8 bits of adc sample interval counter */
 115         ADC_SAMPLE_INTERVAL_UPPER_REG = 0x18,
 116         /*  lower 16 bits of delay interval counter */
 117         ADC_DELAY_INTERVAL_LOWER_REG = 0x1a,
 118         /*  upper 8 bits of delay interval counter */
 119         ADC_DELAY_INTERVAL_UPPER_REG = 0x1c,
 120         /*  lower 16 bits of hardware conversion/scan counter */
 121         ADC_COUNT_LOWER_REG = 0x1e,
 122         /*  upper 8 bits of hardware conversion/scan counter */
 123         ADC_COUNT_UPPER_REG = 0x20,
 124         ADC_START_REG = 0x22,   /*  software trigger to start acquisition */
 125         ADC_CONVERT_REG = 0x24, /*  initiates single conversion */
 126         ADC_QUEUE_CLEAR_REG = 0x26,     /*  clears adc queue */
 127         ADC_QUEUE_LOAD_REG = 0x28,      /*  loads adc queue */
 128         ADC_BUFFER_CLEAR_REG = 0x2a,
 129         /*  high channel for internal queue, use adc_chan_bits() inline above */
 130         ADC_QUEUE_HIGH_REG = 0x2c,
 131         DAC_CONTROL0_REG = 0x50,        /*  dac control register 0 */
 132         DAC_CONTROL1_REG = 0x52,        /*  dac control register 0 */
 133         /*  lower 16 bits of dac sample interval counter */
 134         DAC_SAMPLE_INTERVAL_LOWER_REG = 0x54,
 135         /*  upper 8 bits of dac sample interval counter */
 136         DAC_SAMPLE_INTERVAL_UPPER_REG = 0x56,
 137         DAC_SELECT_REG = 0x60,
 138         DAC_START_REG = 0x64,
 139         DAC_BUFFER_CLEAR_REG = 0x66,    /*  clear dac buffer */
 140 };
 141
 142 static inline unsigned int dac_convert_reg(unsigned int channel)
 143 {
 144         return 0x70 + (2 * (channel & 0x1));
 145 }
 146
 147 static inline unsigned int dac_lsb_4020_reg(unsigned int channel)
 148 {
 149         return 0x70 + (4 * (channel & 0x1));
 150 }
 151
 152 static inline unsigned int dac_msb_4020_reg(unsigned int channel)
 153 {
 154         return 0x72 + (4 * (channel & 0x1));
 155 }
 156
 157 enum read_only_registers {
 158         /*
 159          * hardware status register,
 160          * reading this apparently clears pending interrupts as well
 161          */
 162         HW_STATUS_REG = 0x0,
 163         PIPE1_READ_REG = 0x4,
 164         ADC_READ_PNTR_REG = 0x8,
 165         LOWER_XFER_REG = 0x10,
 166         ADC_WRITE_PNTR_REG = 0xc,
 167         PREPOST_REG = 0x14,
 168 };
 169
 170 enum read_write_registers {
 171         I8255_4020_REG = 0x48,  /*  8255 offset, for 4020 only */
 172         /*  external channel/gain queue, uses same bits as ADC_QUEUE_LOAD_REG */
 173         ADC_QUEUE_FIFO_REG = 0x100,
 174         ADC_FIFO_REG = 0x200,   /* adc data fifo */
 175         /* dac data fifo, has weird interactions with external channel queue */
 176         DAC_FIFO_REG = 0x300,
 177 };
 178
 179 /* dev->mmio registers */
 180 enum dio_counter_registers {
 181         DIO_8255_OFFSET = 0x0,
 182         DO_REG = 0x20,
 183         DI_REG = 0x28,
 184         DIO_DIRECTION_60XX_REG = 0x40,
 185         DIO_DATA_60XX_REG = 0x48,
 186 };
 187
 188 /* bit definitions for write-only registers */
 189
 190 enum intr_enable_contents {
 191         ADC_INTR_SRC_MASK = 0x3,        /*  adc interrupt source mask */
 192         ADC_INTR_QFULL_BITS = 0x0,      /*  interrupt fifo quarter full */
 193         ADC_INTR_EOC_BITS = 0x1,        /*  interrupt end of conversion */
 194         ADC_INTR_EOSCAN_BITS = 0x2,     /*  interrupt end of scan */
 195         ADC_INTR_EOSEQ_BITS = 0x3,      /*  interrupt end of sequence mask */
 196         EN_ADC_INTR_SRC_BIT = 0x4,      /*  enable adc interrupt source */
 197         EN_ADC_DONE_INTR_BIT = 0x8,     /*  enable adc acquisition done intr */
 198         DAC_INTR_SRC_MASK = 0x30,
 199         DAC_INTR_QEMPTY_BITS = 0x0,
 200         DAC_INTR_HIGH_CHAN_BITS = 0x10,
 201         EN_DAC_INTR_SRC_BIT = 0x40,     /*  enable dac interrupt source */
 202         EN_DAC_DONE_INTR_BIT = 0x80,
 203         EN_ADC_ACTIVE_INTR_BIT = 0x200, /*  enable adc active interrupt */
 204         EN_ADC_STOP_INTR_BIT = 0x400,   /*  enable adc stop trigger interrupt */
 205         EN_DAC_ACTIVE_INTR_BIT = 0x800, /*  enable dac active interrupt */
 206         EN_DAC_UNDERRUN_BIT = 0x4000,   /*  enable dac underrun status bit */
 207         EN_ADC_OVERRUN_BIT = 0x8000,    /*  enable adc overrun status bit */
 208 };
 209
 210 enum hw_config_contents {
 211         MASTER_CLOCK_4020_MASK = 0x3,   /*  master clock source mask for 4020 */
 212         INTERNAL_CLOCK_4020_BITS = 0x1, /*  use 40 MHz internal master clock */
 213         BNC_CLOCK_4020_BITS = 0x2,      /*  use BNC input for master clock */
 214         EXT_CLOCK_4020_BITS = 0x3,      /*  use dio input for master clock */
 215         EXT_QUEUE_BIT = 0x200,          /*  use external channel/gain queue */
 216         /*  use 225 nanosec strobe when loading dac instead of 50 nanosec */
 217         SLOW_DAC_BIT = 0x400,
 218         /*  bit with unknown function yet given as default value in pci-das64
 219          *  manual */
 220         HW_CONFIG_DUMMY_BITS = 0x2000,
 221         /*  bit selects channels 1/0 for analog input/output, otherwise 0/1 */
 222         DMA_CH_SELECT_BIT = 0x8000,
 223         FIFO_SIZE_REG = 0x4,            /*  allows adjustment of fifo sizes */
 224         DAC_FIFO_SIZE_MASK = 0xff00,    /*  bits that set dac fifo size */
 225         DAC_FIFO_BITS = 0xf800,         /*  8k sample ao fifo */
 226 };
 227 #define DAC_FIFO_SIZE 0x2000
 228
 229 enum daq_atrig_low_4020_contents {
 230         /*  use trig/ext clk bnc input for analog gate signal */
 231         EXT_AGATE_BNC_BIT = 0x8000,
 232         /*  use trig/ext clk bnc input for external stop trigger signal */
 233         EXT_STOP_TRIG_BNC_BIT = 0x4000,
 234         /*  use trig/ext clk bnc input for external start trigger signal */
 235         EXT_START_TRIG_BNC_BIT = 0x2000,
 236 };
 237
 238 static inline uint16_t analog_trig_low_threshold_bits(uint16_t threshold)
 239 {
 240         return threshold & 0xfff;
 241 }
 242
 243 enum adc_control0_contents {
 244         ADC_GATE_SRC_MASK = 0x3,        /*  bits that select gate */
 245         ADC_SOFT_GATE_BITS = 0x1,       /*  software gate */
 246         ADC_EXT_GATE_BITS = 0x2,        /*  external digital gate */
 247         ADC_ANALOG_GATE_BITS = 0x3,     /*  analog level gate */
 248         /*  level-sensitive gate (for digital) */
 249         ADC_GATE_LEVEL_BIT = 0x4,
 250         ADC_GATE_POLARITY_BIT = 0x8,    /*  gate active low */
 251         ADC_START_TRIG_SOFT_BITS = 0x10,
 252         ADC_START_TRIG_EXT_BITS = 0x20,
 253         ADC_START_TRIG_ANALOG_BITS = 0x30,
 254         ADC_START_TRIG_MASK = 0x30,
 255         ADC_START_TRIG_FALLING_BIT = 0x40,      /*  trig 1 uses falling edge */
 256         /*  external pacing uses falling edge */
 257         ADC_EXT_CONV_FALLING_BIT = 0x800,
 258         /*  enable hardware scan counter */
 259         ADC_SAMPLE_COUNTER_EN_BIT = 0x1000,
 260         ADC_DMA_DISABLE_BIT = 0x4000,   /*  disables dma */
 261         ADC_ENABLE_BIT = 0x8000,        /*  master adc enable */
 262 };
 263
 264 enum adc_control1_contents {
 265         /*  should be set for boards with > 16 channels */
 266         ADC_QUEUE_CONFIG_BIT = 0x1,
 267         CONVERT_POLARITY_BIT = 0x10,
 268         EOC_POLARITY_BIT = 0x20,
 269         ADC_SW_GATE_BIT = 0x40, /*  software gate of adc */
 270         ADC_DITHER_BIT = 0x200, /*  turn on extra noise for dithering */
 271         RETRIGGER_BIT = 0x800,
 272         ADC_LO_CHANNEL_4020_MASK = 0x300,
 273         ADC_HI_CHANNEL_4020_MASK = 0xc00,
 274         TWO_CHANNEL_4020_BITS = 0x1000, /*  two channel mode for 4020 */
 275         FOUR_CHANNEL_4020_BITS = 0x2000, /*  four channel mode for 4020 */
 276         CHANNEL_MODE_4020_MASK = 0x3000,
 277         ADC_MODE_MASK = 0xf000,
 278 };
 279
 280 static inline uint16_t adc_lo_chan_4020_bits(unsigned int channel)
 281 {
 282         return (channel & 0x3) << 8;
 283 };
 284
 285 static inline uint16_t adc_hi_chan_4020_bits(unsigned int channel)
 286 {
 287         return (channel & 0x3) << 10;
 288 };
 289
 290 static inline uint16_t adc_mode_bits(unsigned int mode)
 291 {
 292         return (mode & 0xf) << 12;
 293 };
 294
 295 enum calibration_contents {
 296         SELECT_8800_BIT = 0x1,
 297         SELECT_8402_64XX_BIT = 0x2,
 298         SELECT_1590_60XX_BIT = 0x2,
 299         CAL_EN_64XX_BIT = 0x40, /*  calibration enable for 64xx series */
 300         SERIAL_DATA_IN_BIT = 0x80,
 301         SERIAL_CLOCK_BIT = 0x100,
 302         CAL_EN_60XX_BIT = 0x200, /*  calibration enable for 60xx series */
 303         CAL_GAIN_BIT = 0x800,
 304 };
 305
 306 /*
 307  * calibration sources for 6025 are:
 308  *  0 : ground
 309  *  1 : 10V
 310  *  2 : 5V
 311  *  3 : 0.5V
 312  *  4 : 0.05V
 313  *  5 : ground
 314  *  6 : dac channel 0
 315  *  7 : dac channel 1
 316  */
 317
 318 static inline uint16_t adc_src_bits(unsigned int source)
 319 {
 320         return (source & 0xf) << 3;
 321 };
 322
 323 static inline uint16_t adc_convert_chan_4020_bits(unsigned int channel)
 324 {
 325         return (channel & 0x3) << 8;
 326 };
 327
 328 enum adc_queue_load_contents {
 329         UNIP_BIT = 0x800,       /*  unipolar/bipolar bit */
 330         ADC_SE_DIFF_BIT = 0x1000,       /*  single-ended/ differential bit */
 331         /*  non-referenced single-ended (common-mode input) */
 332         ADC_COMMON_BIT = 0x2000,
 333         QUEUE_EOSEQ_BIT = 0x4000,       /*  queue end of sequence */
 334         QUEUE_EOSCAN_BIT = 0x8000,      /*  queue end of scan */
 335 };
 336
 337 static inline uint16_t adc_chan_bits(unsigned int channel)
 338 {
 339         return channel & 0x3f;
 340 };
 341
 342 enum dac_control0_contents {
 343         DAC_ENABLE_BIT = 0x8000,        /*  dac controller enable bit */
 344         DAC_CYCLIC_STOP_BIT = 0x4000,
 345         DAC_WAVEFORM_MODE_BIT = 0x100,
 346         DAC_EXT_UPDATE_FALLING_BIT = 0x80,
 347         DAC_EXT_UPDATE_ENABLE_BIT = 0x40,
 348         WAVEFORM_TRIG_MASK = 0x30,
 349         WAVEFORM_TRIG_DISABLED_BITS = 0x0,
 350         WAVEFORM_TRIG_SOFT_BITS = 0x10,
 351         WAVEFORM_TRIG_EXT_BITS = 0x20,
 352         WAVEFORM_TRIG_ADC1_BITS = 0x30,
 353         WAVEFORM_TRIG_FALLING_BIT = 0x8,
 354         WAVEFORM_GATE_LEVEL_BIT = 0x4,
 355         WAVEFORM_GATE_ENABLE_BIT = 0x2,
 356         WAVEFORM_GATE_SELECT_BIT = 0x1,
 357 };
 358
 359 enum dac_control1_contents {
 360         DAC_WRITE_POLARITY_BIT = 0x800, /* board-dependent setting */
 361         DAC1_EXT_REF_BIT = 0x200,
 362         DAC0_EXT_REF_BIT = 0x100,
 363         DAC_OUTPUT_ENABLE_BIT = 0x80,   /*  dac output enable bit */
 364         DAC_UPDATE_POLARITY_BIT = 0x40, /* board-dependent setting */
 365         DAC_SW_GATE_BIT = 0x20,
 366         DAC1_UNIPOLAR_BIT = 0x8,
 367         DAC0_UNIPOLAR_BIT = 0x2,
 368 };
 369
 370 /* bit definitions for read-only registers */
 371 enum hw_status_contents {
 372         DAC_UNDERRUN_BIT = 0x1,
 373         ADC_OVERRUN_BIT = 0x2,
 374         DAC_ACTIVE_BIT = 0x4,
 375         ADC_ACTIVE_BIT = 0x8,
 376         DAC_INTR_PENDING_BIT = 0x10,
 377         ADC_INTR_PENDING_BIT = 0x20,
 378         DAC_DONE_BIT = 0x40,
 379         ADC_DONE_BIT = 0x80,
 380         EXT_INTR_PENDING_BIT = 0x100,
 381         ADC_STOP_BIT = 0x200,
 382 };
 383
 384 static inline uint16_t pipe_full_bits(uint16_t hw_status_bits)
 385 {
 386         return (hw_status_bits >> 10) & 0x3;
 387 };
 388
 389 static inline unsigned int dma_chain_flag_bits(uint16_t prepost_bits)
 390 {
 391         return (prepost_bits >> 6) & 0x3;
 392 }
 393
 394 static inline unsigned int adc_upper_read_ptr_code(uint16_t prepost_bits)
 395 {
 396         return (prepost_bits >> 12) & 0x3;
 397 }
 398
 399 static inline unsigned int adc_upper_write_ptr_code(uint16_t prepost_bits)
 400 {
 401         return (prepost_bits >> 14) & 0x3;
 402 }
 403
 404 /* I2C addresses for 4020 */
 405 enum i2c_addresses {
 406         RANGE_CAL_I2C_ADDR = 0x20,
 407         CALDAC0_I2C_ADDR = 0xc,
 408         CALDAC1_I2C_ADDR = 0xd,
 409 };
 410
 411 enum range_cal_i2c_contents {
 412         /*  bits that set what source the adc converter measures */
 413         ADC_SRC_4020_MASK = 0x70,
 414         /*  make bnc trig/ext clock threshold 0V instead of 2.5V */
 415         BNC_TRIG_THRESHOLD_0V_BIT = 0x80,
 416 };
 417
 418 static inline uint8_t adc_src_4020_bits(unsigned int source)
 419 {
 420         return (source << 4) & ADC_SRC_4020_MASK;
 421 };
 422
 423 static inline uint8_t attenuate_bit(unsigned int channel)
 424 {
 425         /*  attenuate channel (+-5V input range) */
 426         return 1 << (channel & 0x3);
 427 };
 428
 429 /* analog input ranges for 64xx boards */
 430 static const struct comedi_lrange ai_ranges_64xx = {
 431         8, {
 432                 BIP_RANGE(10),
 433                 BIP_RANGE(5),
 434                 BIP_RANGE(2.5),
 435                 BIP_RANGE(1.25),
 436                 UNI_RANGE(10),
 437                 UNI_RANGE(5),
 438                 UNI_RANGE(2.5),
 439                 UNI_RANGE(1.25)
 440         }
 441 };
 442
 443 static const uint8_t ai_range_code_64xx[8] = {
 444         0x0, 0x1, 0x2, 0x3,     /* bipolar 10, 5, 2,5, 1.25 */
 445         0x8, 0x9, 0xa, 0xb      /* unipolar 10, 5, 2.5, 1.25 */
 446 };
 447
 448 /* analog input ranges for 64-Mx boards */
 449 static const struct comedi_lrange ai_ranges_64_mx = {
 450         7, {
 451                 BIP_RANGE(5),
 452                 BIP_RANGE(2.5),
 453                 BIP_RANGE(1.25),
 454                 BIP_RANGE(0.625),
 455                 UNI_RANGE(5),
 456                 UNI_RANGE(2.5),
 457                 UNI_RANGE(1.25)
 458         }
 459 };
 460
 461 static const uint8_t ai_range_code_64_mx[7] = {
 462         0x0, 0x1, 0x2, 0x3,     /* bipolar 5, 2.5, 1.25, 0.625 */
 463         0x9, 0xa, 0xb           /* unipolar 5, 2.5, 1.25 */
 464 };
 465
 466 /* analog input ranges for 60xx boards */
 467 static const struct comedi_lrange ai_ranges_60xx = {
 468         4, {
 469                 BIP_RANGE(10),
 470                 BIP_RANGE(5),
 471                 BIP_RANGE(0.5),
 472                 BIP_RANGE(0.05)
 473         }
 474 };
 475
 476 static const uint8_t ai_range_code_60xx[4] = {
 477         0x0, 0x1, 0x4, 0x7      /* bipolar 10, 5, 0.5, 0.05 */
 478 };
 479
 480 /* analog input ranges for 6030, etc boards */
 481 static const struct comedi_lrange ai_ranges_6030 = {
 482         14, {
 483                 BIP_RANGE(10),
 484                 BIP_RANGE(5),
 485                 BIP_RANGE(2),
 486                 BIP_RANGE(1),
 487                 BIP_RANGE(0.5),
 488                 BIP_RANGE(0.2),
 489                 BIP_RANGE(0.1),
 490                 UNI_RANGE(10),
 491                 UNI_RANGE(5),
 492                 UNI_RANGE(2),
 493                 UNI_RANGE(1),
 494                 UNI_RANGE(0.5),
 495                 UNI_RANGE(0.2),
 496                 UNI_RANGE(0.1)
 497         }
 498 };
 499
 500 static const uint8_t ai_range_code_6030[14] = {
 501         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, /* bip 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 502         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf  /* uni 10, 5, 2, 1, 0.5, 0.2, 0.1 */
 503 };
 504
 505 /* analog input ranges for 6052, etc boards */
 506 static const struct comedi_lrange ai_ranges_6052 = {
 507         15, {
 508                 BIP_RANGE(10),
 509                 BIP_RANGE(5),
 510                 BIP_RANGE(2.5),
 511                 BIP_RANGE(1),
 512                 BIP_RANGE(0.5),
 513                 BIP_RANGE(0.25),
 514                 BIP_RANGE(0.1),
 515                 BIP_RANGE(0.05),
 516                 UNI_RANGE(10),
 517                 UNI_RANGE(5),
 518                 UNI_RANGE(2),
 519                 UNI_RANGE(1),
 520                 UNI_RANGE(0.5),
 521                 UNI_RANGE(0.2),
 522                 UNI_RANGE(0.1)
 523         }
 524 };
 525
 526 static const uint8_t ai_range_code_6052[15] = {
 527         0x0, 0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, /* bipolar 10 ... 0.05 */
 528         0x9, 0xa, 0xb, 0xc, 0xd, 0xe, 0xf       /* unipolar 10 ... 0.1 */
 529 };
 530
 531 /* analog input ranges for 4020 board */
 532 static const struct comedi_lrange ai_ranges_4020 = {
 533         2, {
 534                 BIP_RANGE(5),
 535                 BIP_RANGE(1)
 536         }
 537 };
 538
 539 /* analog output ranges */
 540 static const struct comedi_lrange ao_ranges_64xx = {
 541         4, {
 542                 BIP_RANGE(5),
 543                 BIP_RANGE(10),
 544                 UNI_RANGE(5),
 545                 UNI_RANGE(10)
 546         }
 547 };
 548
 549 static const int ao_range_code_64xx[] = {
 550         0x0,
 551         0x1,
 552         0x2,
 553         0x3,
 554 };
 555
 556 static const int ao_range_code_60xx[] = {
 557         0x0,
 558 };
 559
 560 static const struct comedi_lrange ao_ranges_6030 = {
 561         2, {
 562                 BIP_RANGE(10),
 563                 UNI_RANGE(10)
 564         }
 565 };
 566
 567 static const int ao_range_code_6030[] = {
 568         0x0,
 569         0x2,
 570 };
 571
 572 static const struct comedi_lrange ao_ranges_4020 = {
 573         2, {
 574                 BIP_RANGE(5),
 575                 BIP_RANGE(10)
 576         }
 577 };
 578
 579 static const int ao_range_code_4020[] = {
 580         0x1,
 581         0x0,
 582 };
 583
 584 enum register_layout {
 585         LAYOUT_60XX,
 586         LAYOUT_64XX,
 587         LAYOUT_4020,
 588 };
 589
 590 struct hw_fifo_info {
 591         unsigned int num_segments;
 592         unsigned int max_segment_length;
 593         unsigned int sample_packing_ratio;
 594         uint16_t fifo_size_reg_mask;
 595 };
 596
 597 enum pcidas64_boardid {
 598         BOARD_PCIDAS6402_16,
 599         BOARD_PCIDAS6402_12,
 600         BOARD_PCIDAS64_M1_16,
 601         BOARD_PCIDAS64_M2_16,
 602         BOARD_PCIDAS64_M3_16,
 603         BOARD_PCIDAS6013,
 604         BOARD_PCIDAS6014,
 605         BOARD_PCIDAS6023,
 606         BOARD_PCIDAS6025,
 607         BOARD_PCIDAS6030,
 608         BOARD_PCIDAS6031,
 609         BOARD_PCIDAS6032,
 610         BOARD_PCIDAS6033,
 611         BOARD_PCIDAS6034,
 612         BOARD_PCIDAS6035,
 613         BOARD_PCIDAS6036,
 614         BOARD_PCIDAS6040,
 615         BOARD_PCIDAS6052,
 616         BOARD_PCIDAS6070,
 617         BOARD_PCIDAS6071,
 618         BOARD_PCIDAS4020_12,
 619         BOARD_PCIDAS6402_16_JR,
 620         BOARD_PCIDAS64_M1_16_JR,
 621         BOARD_PCIDAS64_M2_16_JR,
 622         BOARD_PCIDAS64_M3_16_JR,
 623         BOARD_PCIDAS64_M1_14,
 624         BOARD_PCIDAS64_M2_14,
 625         BOARD_PCIDAS64_M3_14,
 626 };
 627
 628 struct pcidas64_board {
 629         const char *name;
 630         int ai_se_chans;        /*  number of ai inputs in single-ended mode */
 631         int ai_bits;            /*  analog input resolution */
 632         int ai_speed;           /*  fastest conversion period in ns */
 633         const struct comedi_lrange *ai_range_table;
 634         const uint8_t *ai_range_code;
 635         int ao_nchan;           /*  number of analog out channels */
 636         int ao_bits;            /*  analog output resolution */
 637         int ao_scan_speed;      /*  analog output scan speed */
 638         const struct comedi_lrange *ao_range_table;
 639         const int *ao_range_code;
 640         const struct hw_fifo_info *const ai_fifo;
 641         /*  different board families have slightly different registers */
 642         enum register_layout layout;
 643         unsigned has_8255:1;
 644 };
 645
 646 static const struct hw_fifo_info ai_fifo_4020 = {
 647         .num_segments = 2,
 648         .max_segment_length = 0x8000,
 649         .sample_packing_ratio = 2,
 650         .fifo_size_reg_mask = 0x7f,
 651 };
 652
 653 static const struct hw_fifo_info ai_fifo_64xx = {
 654         .num_segments = 4,
 655         .max_segment_length = 0x800,
 656         .sample_packing_ratio = 1,
 657         .fifo_size_reg_mask = 0x3f,
 658 };
 659
 660 static const struct hw_fifo_info ai_fifo_60xx = {
 661         .num_segments = 4,
 662         .max_segment_length = 0x800,
 663         .sample_packing_ratio = 1,
 664         .fifo_size_reg_mask = 0x7f,
 665 };
 666
 667 /*
 668  * maximum number of dma transfers we will chain together into a ring
 669  * (and the maximum number of dma buffers we maintain)
 670  */
 671 #define MAX_AI_DMA_RING_COUNT (0x80000 / DMA_BUFFER_SIZE)
 672 #define MIN_AI_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 673 #define AO_DMA_RING_COUNT (0x10000 / DMA_BUFFER_SIZE)
 674 static inline unsigned int ai_dma_ring_count(const struct pcidas64_board *board)
 675 {
 676         if (board->layout == LAYOUT_4020)
 677                 return MAX_AI_DMA_RING_COUNT;
 678
 679         return MIN_AI_DMA_RING_COUNT;
 680 }
 681
 682 static const int bytes_in_sample = 2;
 683
 684 static const struct pcidas64_board pcidas64_boards[] = {
 685         [BOARD_PCIDAS6402_16] = {
 686                 .name           = "pci-das6402/16",
 687                 .ai_se_chans    = 64,
 688                 .ai_bits        = 16,
 689                 .ai_speed       = 5000,
 690                 .ao_nchan       = 2,
 691                 .ao_bits        = 16,
 692                 .ao_scan_speed  = 10000,
 693                 .layout         = LAYOUT_64XX,
 694                 .ai_range_table = &ai_ranges_64xx,
 695                 .ai_range_code  = ai_range_code_64xx,
 696                 .ao_range_table = &ao_ranges_64xx,
 697                 .ao_range_code  = ao_range_code_64xx,
 698                 .ai_fifo        = &ai_fifo_64xx,
 699                 .has_8255       = 1,
 700         },
 701         [BOARD_PCIDAS6402_12] = {
 702                 .name           = "pci-das6402/12",     /*  XXX check */
 703                 .ai_se_chans    = 64,
 704                 .ai_bits        = 12,
 705                 .ai_speed       = 5000,
 706                 .ao_nchan       = 2,
 707                 .ao_bits        = 12,
 708                 .ao_scan_speed  = 10000,
 709                 .layout         = LAYOUT_64XX,
 710                 .ai_range_table = &ai_ranges_64xx,
 711                 .ai_range_code  = ai_range_code_64xx,
 712                 .ao_range_table = &ao_ranges_64xx,
 713                 .ao_range_code  = ao_range_code_64xx,
 714                 .ai_fifo        = &ai_fifo_64xx,
 715                 .has_8255       = 1,
 716         },
 717         [BOARD_PCIDAS64_M1_16] = {
 718                 .name           = "pci-das64/m1/16",
 719                 .ai_se_chans    = 64,
 720                 .ai_bits        = 16,
 721                 .ai_speed       = 1000,
 722                 .ao_nchan       = 2,
 723                 .ao_bits        = 16,
 724                 .ao_scan_speed  = 10000,
 725                 .layout         = LAYOUT_64XX,
 726                 .ai_range_table = &ai_ranges_64_mx,
 727                 .ai_range_code  = ai_range_code_64_mx,
 728                 .ao_range_table = &ao_ranges_64xx,
 729                 .ao_range_code  = ao_range_code_64xx,
 730                 .ai_fifo        = &ai_fifo_64xx,
 731                 .has_8255       = 1,
 732         },
 733         [BOARD_PCIDAS64_M2_16] = {
 734                 .name = "pci-das64/m2/16",
 735                 .ai_se_chans    = 64,
 736                 .ai_bits        = 16,
 737                 .ai_speed       = 500,
 738                 .ao_nchan       = 2,
 739                 .ao_bits        = 16,
 740                 .ao_scan_speed  = 10000,
 741                 .layout         = LAYOUT_64XX,
 742                 .ai_range_table = &ai_ranges_64_mx,
 743                 .ai_range_code  = ai_range_code_64_mx,
 744                 .ao_range_table = &ao_ranges_64xx,
 745                 .ao_range_code  = ao_range_code_64xx,
 746                 .ai_fifo        = &ai_fifo_64xx,
 747                 .has_8255       = 1,
 748         },
 749         [BOARD_PCIDAS64_M3_16] = {
 750                 .name           = "pci-das64/m3/16",
 751                 .ai_se_chans    = 64,
 752                 .ai_bits        = 16,
 753                 .ai_speed       = 333,
 754                 .ao_nchan       = 2,
 755                 .ao_bits        = 16,
 756                 .ao_scan_speed  = 10000,
 757                 .layout         = LAYOUT_64XX,
 758                 .ai_range_table = &ai_ranges_64_mx,
 759                 .ai_range_code  = ai_range_code_64_mx,
 760                 .ao_range_table = &ao_ranges_64xx,
 761                 .ao_range_code  = ao_range_code_64xx,
 762                 .ai_fifo        = &ai_fifo_64xx,
 763                 .has_8255       = 1,
 764         },
 765         [BOARD_PCIDAS6013] = {
 766                 .name           = "pci-das6013",
 767                 .ai_se_chans    = 16,
 768                 .ai_bits        = 16,
 769                 .ai_speed       = 5000,
 770                 .ao_nchan       = 0,
 771                 .ao_bits        = 16,
 772                 .layout         = LAYOUT_60XX,
 773                 .ai_range_table = &ai_ranges_60xx,
 774                 .ai_range_code  = ai_range_code_60xx,
 775                 .ao_range_table = &range_bipolar10,
 776                 .ao_range_code  = ao_range_code_60xx,
 777                 .ai_fifo        = &ai_fifo_60xx,
 778                 .has_8255       = 0,
 779         },
 780         [BOARD_PCIDAS6014] = {
 781                 .name           = "pci-das6014",
 782                 .ai_se_chans    = 16,
 783                 .ai_bits        = 16,
 784                 .ai_speed       = 5000,
 785                 .ao_nchan       = 2,
 786                 .ao_bits        = 16,
 787                 .ao_scan_speed  = 100000,
 788                 .layout         = LAYOUT_60XX,
 789                 .ai_range_table = &ai_ranges_60xx,
 790                 .ai_range_code  = ai_range_code_60xx,
 791                 .ao_range_table = &range_bipolar10,
 792                 .ao_range_code  = ao_range_code_60xx,
 793                 .ai_fifo        = &ai_fifo_60xx,
 794                 .has_8255       = 0,
 795         },
 796         [BOARD_PCIDAS6023] = {
 797                 .name           = "pci-das6023",
 798                 .ai_se_chans    = 16,
 799                 .ai_bits        = 12,
 800                 .ai_speed       = 5000,
 801                 .ao_nchan       = 0,
 802                 .ao_scan_speed  = 100000,
 803                 .layout         = LAYOUT_60XX,
 804                 .ai_range_table = &ai_ranges_60xx,
 805                 .ai_range_code  = ai_range_code_60xx,
 806                 .ao_range_table = &range_bipolar10,
 807                 .ao_range_code  = ao_range_code_60xx,
 808                 .ai_fifo        = &ai_fifo_60xx,
 809                 .has_8255       = 1,
 810         },
 811         [BOARD_PCIDAS6025] = {
 812                 .name           = "pci-das6025",
 813                 .ai_se_chans    = 16,
 814                 .ai_bits        = 12,
 815                 .ai_speed       = 5000,
 816                 .ao_nchan       = 2,
 817                 .ao_bits        = 12,
 818                 .ao_scan_speed  = 100000,
 819                 .layout         = LAYOUT_60XX,
 820                 .ai_range_table = &ai_ranges_60xx,
 821                 .ai_range_code  = ai_range_code_60xx,
 822                 .ao_range_table = &range_bipolar10,
 823                 .ao_range_code  = ao_range_code_60xx,
 824                 .ai_fifo        = &ai_fifo_60xx,
 825                 .has_8255       = 1,
 826         },
 827         [BOARD_PCIDAS6030] = {
 828                 .name           = "pci-das6030",
 829                 .ai_se_chans    = 16,
 830                 .ai_bits        = 16,
 831                 .ai_speed       = 10000,
 832                 .ao_nchan       = 2,
 833                 .ao_bits        = 16,
 834                 .ao_scan_speed  = 10000,
 835                 .layout         = LAYOUT_60XX,
 836                 .ai_range_table = &ai_ranges_6030,
 837                 .ai_range_code  = ai_range_code_6030,
 838                 .ao_range_table = &ao_ranges_6030,
 839                 .ao_range_code  = ao_range_code_6030,
 840                 .ai_fifo        = &ai_fifo_60xx,
 841                 .has_8255       = 0,
 842         },
 843         [BOARD_PCIDAS6031] = {
 844                 .name           = "pci-das6031",
 845                 .ai_se_chans    = 64,
 846                 .ai_bits        = 16,
 847                 .ai_speed       = 10000,
 848                 .ao_nchan       = 2,
 849                 .ao_bits        = 16,
 850                 .ao_scan_speed  = 10000,
 851                 .layout         = LAYOUT_60XX,
 852                 .ai_range_table = &ai_ranges_6030,
 853                 .ai_range_code  = ai_range_code_6030,
 854                 .ao_range_table = &ao_ranges_6030,
 855                 .ao_range_code  = ao_range_code_6030,
 856                 .ai_fifo        = &ai_fifo_60xx,
 857                 .has_8255       = 0,
 858         },
 859         [BOARD_PCIDAS6032] = {
 860                 .name           = "pci-das6032",
 861                 .ai_se_chans    = 16,
 862                 .ai_bits        = 16,
 863                 .ai_speed       = 10000,
 864                 .ao_nchan       = 0,
 865                 .layout         = LAYOUT_60XX,
 866                 .ai_range_table = &ai_ranges_6030,
 867                 .ai_range_code  = ai_range_code_6030,
 868                 .ai_fifo        = &ai_fifo_60xx,
 869                 .has_8255       = 0,
 870         },
 871         [BOARD_PCIDAS6033] = {
 872                 .name           = "pci-das6033",
 873                 .ai_se_chans    = 64,
 874                 .ai_bits        = 16,
 875                 .ai_speed       = 10000,
 876                 .ao_nchan       = 0,
 877                 .layout         = LAYOUT_60XX,
 878                 .ai_range_table = &ai_ranges_6030,
 879                 .ai_range_code  = ai_range_code_6030,
 880                 .ai_fifo        = &ai_fifo_60xx,
 881                 .has_8255       = 0,
 882         },
 883         [BOARD_PCIDAS6034] = {
 884                 .name           = "pci-das6034",
 885                 .ai_se_chans    = 16,
 886                 .ai_bits        = 16,
 887                 .ai_speed       = 5000,
 888                 .ao_nchan       = 0,
 889                 .ao_scan_speed  = 0,
 890                 .layout         = LAYOUT_60XX,
 891                 .ai_range_table = &ai_ranges_60xx,
 892                 .ai_range_code  = ai_range_code_60xx,
 893                 .ai_fifo        = &ai_fifo_60xx,
 894                 .has_8255       = 0,
 895         },
 896         [BOARD_PCIDAS6035] = {
 897                 .name           = "pci-das6035",
 898                 .ai_se_chans    = 16,
 899                 .ai_bits        = 16,
 900                 .ai_speed       = 5000,
 901                 .ao_nchan       = 2,
 902                 .ao_bits        = 12,
 903                 .ao_scan_speed  = 100000,
 904                 .layout         = LAYOUT_60XX,
 905                 .ai_range_table = &ai_ranges_60xx,
 906                 .ai_range_code  = ai_range_code_60xx,
 907                 .ao_range_table = &range_bipolar10,
 908                 .ao_range_code  = ao_range_code_60xx,
 909                 .ai_fifo        = &ai_fifo_60xx,
 910                 .has_8255       = 0,
 911         },
 912         [BOARD_PCIDAS6036] = {
 913                 .name           = "pci-das6036",
 914                 .ai_se_chans    = 16,
 915                 .ai_bits        = 16,
 916                 .ai_speed       = 5000,
 917                 .ao_nchan       = 2,
 918                 .ao_bits        = 16,
 919                 .ao_scan_speed  = 100000,
 920                 .layout         = LAYOUT_60XX,
 921                 .ai_range_table = &ai_ranges_60xx,
 922                 .ai_range_code  = ai_range_code_60xx,
 923                 .ao_range_table = &range_bipolar10,
 924                 .ao_range_code  = ao_range_code_60xx,
 925                 .ai_fifo        = &ai_fifo_60xx,
 926                 .has_8255       = 0,
 927         },
 928         [BOARD_PCIDAS6040] = {
 929                 .name           = "pci-das6040",
 930                 .ai_se_chans    = 16,
 931                 .ai_bits        = 12,
 932                 .ai_speed       = 2000,
 933                 .ao_nchan       = 2,
 934                 .ao_bits        = 12,
 935                 .ao_scan_speed  = 1000,
 936                 .layout         = LAYOUT_60XX,
 937                 .ai_range_table = &ai_ranges_6052,
 938                 .ai_range_code  = ai_range_code_6052,
 939                 .ao_range_table = &ao_ranges_6030,
 940                 .ao_range_code  = ao_range_code_6030,
 941                 .ai_fifo        = &ai_fifo_60xx,
 942                 .has_8255       = 0,
 943         },
 944         [BOARD_PCIDAS6052] = {
 945                 .name           = "pci-das6052",
 946                 .ai_se_chans    = 16,
 947                 .ai_bits        = 16,
 948                 .ai_speed       = 3333,
 949                 .ao_nchan       = 2,
 950                 .ao_bits        = 16,
 951                 .ao_scan_speed  = 3333,
 952                 .layout         = LAYOUT_60XX,
 953                 .ai_range_table = &ai_ranges_6052,
 954                 .ai_range_code  = ai_range_code_6052,
 955                 .ao_range_table = &ao_ranges_6030,
 956                 .ao_range_code  = ao_range_code_6030,
 957                 .ai_fifo        = &ai_fifo_60xx,
 958                 .has_8255       = 0,
 959         },
 960         [BOARD_PCIDAS6070] = {
 961                 .name           = "pci-das6070",
 962                 .ai_se_chans    = 16,
 963                 .ai_bits        = 12,
 964                 .ai_speed       = 800,
 965                 .ao_nchan       = 2,
 966                 .ao_bits        = 12,
 967                 .ao_scan_speed  = 1000,
 968                 .layout         = LAYOUT_60XX,
 969                 .ai_range_table = &ai_ranges_6052,
 970                 .ai_range_code  = ai_range_code_6052,
 971                 .ao_range_table = &ao_ranges_6030,
 972                 .ao_range_code  = ao_range_code_6030,
 973                 .ai_fifo        = &ai_fifo_60xx,
 974                 .has_8255       = 0,
 975         },
 976         [BOARD_PCIDAS6071] = {
 977                 .name           = "pci-das6071",
 978                 .ai_se_chans    = 64,
 979                 .ai_bits        = 12,
 980                 .ai_speed       = 800,
 981                 .ao_nchan       = 2,
 982                 .ao_bits        = 12,
 983                 .ao_scan_speed  = 1000,
 984                 .layout         = LAYOUT_60XX,
 985                 .ai_range_table = &ai_ranges_6052,
 986                 .ai_range_code  = ai_range_code_6052,
 987                 .ao_range_table = &ao_ranges_6030,
 988                 .ao_range_code  = ao_range_code_6030,
 989                 .ai_fifo        = &ai_fifo_60xx,
 990                 .has_8255       = 0,
 991         },
 992         [BOARD_PCIDAS4020_12] = {
 993                 .name           = "pci-das4020/12",
 994                 .ai_se_chans    = 4,
 995                 .ai_bits        = 12,
 996                 .ai_speed       = 50,
 997                 .ao_bits        = 12,
 998                 .ao_nchan       = 2,
 999                 .ao_scan_speed  = 0,    /*  no hardware pacing on ao */
1000                 .layout         = LAYOUT_4020,
1001                 .ai_range_table = &ai_ranges_4020,
1002                 .ao_range_table = &ao_ranges_4020,
1003                 .ao_range_code  = ao_range_code_4020,
1004                 .ai_fifo        = &ai_fifo_4020,
1005                 .has_8255       = 1,
1006         },
1007 #if 0
1008         /*
1009          * The device id for these boards is unknown
1010          */
1011
1012         [BOARD_PCIDAS6402_16_JR] = {
1013                 .name           = "pci-das6402/16/jr",
1014                 .ai_se_chans    = 64,
1015                 .ai_bits        = 16,
1016                 .ai_speed       = 5000,
1017                 .ao_nchan       = 0,
1018                 .ao_scan_speed  = 10000,
1019                 .layout         = LAYOUT_64XX,
1020                 .ai_range_table = &ai_ranges_64xx,
1021                 .ai_range_code  = ai_range_code_64xx,
1022                 .ai_fifo        = ai_fifo_64xx,
1023                 .has_8255       = 1,
1024         },
1025         [BOARD_PCIDAS64_M1_16_JR] = {
1026                 .name           = "pci-das64/m1/16/jr",
1027                 .ai_se_chans    = 64,
1028                 .ai_bits        = 16,
1029                 .ai_speed       = 1000,
1030                 .ao_nchan       = 0,
1031                 .ao_scan_speed  = 10000,
1032                 .layout         = LAYOUT_64XX,
1033                 .ai_range_table = &ai_ranges_64_mx,
1034                 .ai_range_code  = ai_range_code_64_mx,
1035                 .ai_fifo        = ai_fifo_64xx,
1036                 .has_8255       = 1,
1037         },
1038         [BOARD_PCIDAS64_M2_16_JR] = {
1039                 .name = "pci-das64/m2/16/jr",
1040                 .ai_se_chans    = 64,
1041                 .ai_bits        = 16,
1042                 .ai_speed       = 500,
1043                 .ao_nchan       = 0,
1044                 .ao_scan_speed  = 10000,
1045                 .layout         = LAYOUT_64XX,
1046                 .ai_range_table = &ai_ranges_64_mx,
1047                 .ai_range_code  = ai_range_code_64_mx,
1048                 .ai_fifo        = ai_fifo_64xx,
1049                 .has_8255       = 1,
1050         },
1051         [BOARD_PCIDAS64_M3_16_JR] = {
1052                 .name           = "pci-das64/m3/16/jr",
1053                 .ai_se_chans    = 64,
1054                 .ai_bits        = 16,
1055                 .ai_speed       = 333,
1056                 .ao_nchan       = 0,
1057                 .ao_scan_speed  = 10000,
1058                 .layout         = LAYOUT_64XX,
1059                 .ai_range_table = &ai_ranges_64_mx,
1060                 .ai_range_code  = ai_range_code_64_mx,
1061                 .ai_fifo        = ai_fifo_64xx,
1062                 .has_8255       = 1,
1063         },
1064         [BOARD_PCIDAS64_M1_14] = {
1065                 .name           = "pci-das64/m1/14",
1066                 .ai_se_chans    = 64,
1067                 .ai_bits        = 14,
1068                 .ai_speed       = 1000,
1069                 .ao_nchan       = 2,
1070                 .ao_scan_speed  = 10000,
1071                 .layout         = LAYOUT_64XX,
1072                 .ai_range_table = &ai_ranges_64_mx,
1073                 .ai_range_code  = ai_range_code_64_mx,
1074                 .ai_fifo        = ai_fifo_64xx,
1075                 .has_8255       = 1,
1076         },
1077         [BOARD_PCIDAS64_M2_14] = {
1078                 .name           = "pci-das64/m2/14",
1079                 .ai_se_chans    = 64,
1080                 .ai_bits        = 14,
1081                 .ai_speed       = 500,
1082                 .ao_nchan       = 2,
1083                 .ao_scan_speed  = 10000,
1084                 .layout         = LAYOUT_64XX,
1085                 .ai_range_table = &ai_ranges_64_mx,
1086                 .ai_range_code  = ai_range_code_64_mx,
1087                 .ai_fifo        = ai_fifo_64xx,
1088                 .has_8255       = 1,
1089         },
1090         [BOARD_PCIDAS64_M3_14] = {
1091                 .name           = "pci-das64/m3/14",
1092                 .ai_se_chans    = 64,
1093                 .ai_bits        = 14,
1094                 .ai_speed       = 333,
1095                 .ao_nchan       = 2,
1096                 .ao_scan_speed  = 10000,
1097                 .layout         = LAYOUT_64XX,
1098                 .ai_range_table = &ai_ranges_64_mx,
1099                 .ai_range_code  = ai_range_code_64_mx,
1100                 .ai_fifo        = ai_fifo_64xx,
1101                 .has_8255       = 1,
1102         },
1103 #endif
1104 };
1105
1106 static inline unsigned short se_diff_bit_6xxx(struct comedi_device *dev,
1107                                               int use_differential)
1108 {
1109         const struct pcidas64_board *board = dev->board_ptr;
1110
1111         if ((board->layout == LAYOUT_64XX && !use_differential) ||
1112             (board->layout == LAYOUT_60XX && use_differential))
1113                 return ADC_SE_DIFF_BIT;
1114
1115         return 0;
1116 }
1117
1118 struct ext_clock_info {
1119         /*  master clock divisor to use for scans with external master clock */
1120         unsigned int divisor;
1121         /*  chanspec for master clock input when used as scan begin src */
1122         unsigned int chanspec;
1123 };
1124
1125 /* this structure is for data unique to this hardware driver. */
1126 struct pcidas64_private {
1127         /*  base addresses (physical) */
1128         resource_size_t main_phys_iobase;
1129         resource_size_t dio_counter_phys_iobase;
1130         /*  base addresses (ioremapped) */
1131         void __iomem *plx9080_iobase;
1132         void __iomem *main_iobase;
1133         /*  local address (used by dma controller) */
1134         uint32_t local0_iobase;
1135         uint32_t local1_iobase;
1136         /*  dma buffers for analog input */
1137         uint16_t *ai_buffer[MAX_AI_DMA_RING_COUNT];
1138         /*  physical addresses of ai dma buffers */
1139         dma_addr_t ai_buffer_bus_addr[MAX_AI_DMA_RING_COUNT];
1140         /*  array of ai dma descriptors read by plx9080,
1141          *  allocated to get proper alignment */
1142         struct plx_dma_desc *ai_dma_desc;
1143         /*  physical address of ai dma descriptor array */
1144         dma_addr_t ai_dma_desc_bus_addr;
1145         /*  index of the ai dma descriptor/buffer
1146          *  that is currently being used */
1147         unsigned int ai_dma_index;
1148         /*  dma buffers for analog output */
1149         uint16_t *ao_buffer[AO_DMA_RING_COUNT];
1150         /*  physical addresses of ao dma buffers */
1151         dma_addr_t ao_buffer_bus_addr[AO_DMA_RING_COUNT];
1152         struct plx_dma_desc *ao_dma_desc;
1153         dma_addr_t ao_dma_desc_bus_addr;
1154         /*  keeps track of buffer where the next ao sample should go */
1155         unsigned int ao_dma_index;
1156         unsigned int hw_revision;       /*  stc chip hardware revision number */
1157         /*  last bits sent to INTR_ENABLE_REG register */
1158         unsigned int intr_enable_bits;
1159         /*  last bits sent to ADC_CONTROL1_REG register */
1160         uint16_t adc_control1_bits;
1161         /*  last bits sent to FIFO_SIZE_REG register */
1162         uint16_t fifo_size_bits;
1163         /*  last bits sent to HW_CONFIG_REG register */
1164         uint16_t hw_config_bits;
1165         uint16_t dac_control1_bits;
1166         /*  last bits written to plx9080 control register */
1167         uint32_t plx_control_bits;
1168         /*  last bits written to plx interrupt control and status register */
1169         uint32_t plx_intcsr_bits;
1170         /*  index of calibration source readable through ai ch0 */
1171         int calibration_source;
1172         /*  bits written to i2c calibration/range register */
1173         uint8_t i2c_cal_range_bits;
1174         /*  configure digital triggers to trigger on falling edge */
1175         unsigned int ext_trig_falling;
1176         short ai_cmd_running;
1177         unsigned int ai_fifo_segment_length;
1178         struct ext_clock_info ext_clock;
1179         unsigned short ao_bounce_buffer[DAC_FIFO_SIZE];
1180 };
1181
1182 static unsigned int ai_range_bits_6xxx(const struct comedi_device *dev,
1183                                        unsigned int range_index)
1184 {
1185         const struct pcidas64_board *board = dev->board_ptr;
1186
1187         return board->ai_range_code[range_index] << 8;
1188 }
1189
1190 static unsigned int hw_revision(const struct comedi_device *dev,
1191                                 uint16_t hw_status_bits)
1192 {
1193         const struct pcidas64_board *board = dev->board_ptr;
1194
1195         if (board->layout == LAYOUT_4020)
1196                 return (hw_status_bits >> 13) & 0x7;
1197
1198         return (hw_status_bits >> 12) & 0xf;
1199 }
1200
1201 static void set_dac_range_bits(struct comedi_device *dev,
1202                                uint16_t *bits, unsigned int channel,
1203                                unsigned int range)
1204 {
1205         const struct pcidas64_board *board = dev->board_ptr;
1206         unsigned int code = board->ao_range_code[range];
1207
1208         if (channel > 1)
1209                 dev_err(dev->class_dev, "bug! bad channel?\n");
1210         if (code & ~0x3)
1211                 dev_err(dev->class_dev, "bug! bad range code?\n");
1212
1213         *bits &= ~(0x3 << (2 * channel));
1214         *bits |= code << (2 * channel);
1215 };
1216
1217 static inline int ao_cmd_is_supported(const struct pcidas64_board *board)
1218 {
1219         return board->ao_nchan && board->layout != LAYOUT_4020;
1220 }
1221
1222 static void abort_dma(struct comedi_device *dev, unsigned int channel)
1223 {
1224         struct pcidas64_private *devpriv = dev->private;
1225         unsigned long flags;
1226
1227         /*  spinlock for plx dma control/status reg */
1228         spin_lock_irqsave(&dev->spinlock, flags);
1229
1230         plx9080_abort_dma(devpriv->plx9080_iobase, channel);
1231
1232         spin_unlock_irqrestore(&dev->spinlock, flags);
1233 }
1234
1235 static void disable_plx_interrupts(struct comedi_device *dev)
1236 {
1237         struct pcidas64_private *devpriv = dev->private;
1238
1239         devpriv->plx_intcsr_bits = 0;
1240         writel(devpriv->plx_intcsr_bits,
1241                devpriv->plx9080_iobase + PLX_REG_INTCSR);
1242 }
1243
1244 static void disable_ai_interrupts(struct comedi_device *dev)
1245 {
1246         struct pcidas64_private *devpriv = dev->private;
1247         unsigned long flags;
1248
1249         spin_lock_irqsave(&dev->spinlock, flags);
1250         devpriv->intr_enable_bits &=
1251                 ~EN_ADC_INTR_SRC_BIT & ~EN_ADC_DONE_INTR_BIT &
1252                 ~EN_ADC_ACTIVE_INTR_BIT & ~EN_ADC_STOP_INTR_BIT &
1253                 ~EN_ADC_OVERRUN_BIT & ~ADC_INTR_SRC_MASK;
1254         writew(devpriv->intr_enable_bits,
1255                devpriv->main_iobase + INTR_ENABLE_REG);
1256         spin_unlock_irqrestore(&dev->spinlock, flags);
1257 }
1258
1259 static void enable_ai_interrupts(struct comedi_device *dev,
1260                                  const struct comedi_cmd *cmd)
1261 {
1262         const struct pcidas64_board *board = dev->board_ptr;
1263         struct pcidas64_private *devpriv = dev->private;
1264         uint32_t bits;
1265         unsigned long flags;
1266
1267         bits = EN_ADC_OVERRUN_BIT | EN_ADC_DONE_INTR_BIT |
1268                EN_ADC_ACTIVE_INTR_BIT | EN_ADC_STOP_INTR_BIT;
1269         /*
1270          * Use pio transfer and interrupt on end of conversion
1271          * if CMDF_WAKE_EOS flag is set.
1272          */
1273         if (cmd->flags & CMDF_WAKE_EOS) {
1274                 /*  4020 doesn't support pio transfers except for fifo dregs */
1275                 if (board->layout != LAYOUT_4020)
1276                         bits |= ADC_INTR_EOSCAN_BITS | EN_ADC_INTR_SRC_BIT;
1277         }
1278         spin_lock_irqsave(&dev->spinlock, flags);
1279         devpriv->intr_enable_bits |= bits;
1280         writew(devpriv->intr_enable_bits,
1281                devpriv->main_iobase + INTR_ENABLE_REG);
1282         spin_unlock_irqrestore(&dev->spinlock, flags);
1283 }
1284
1285 /* initialize plx9080 chip */
1286 static void init_plx9080(struct comedi_device *dev)
1287 {
1288         const struct pcidas64_board *board = dev->board_ptr;
1289         struct pcidas64_private *devpriv = dev->private;
1290         uint32_t bits;
1291         void __iomem *plx_iobase = devpriv->plx9080_iobase;
1292
1293         devpriv->plx_control_bits =
1294                 readl(devpriv->plx9080_iobase + PLX_REG_CNTRL);
1295
1296 #ifdef __BIG_ENDIAN
1297         bits = PLX_BIGEND_DMA0 | PLX_BIGEND_DMA1;
1298 #else
1299         bits = 0;
1300 #endif
1301         writel(bits, devpriv->plx9080_iobase + PLX_REG_BIGEND);
1302
1303         disable_plx_interrupts(dev);
1304
1305         abort_dma(dev, 0);
1306         abort_dma(dev, 1);
1307
1308         /*  configure dma0 mode */
1309         bits = 0;
1310         /*  enable ready input, not sure if this is necessary */
1311         bits |= PLX_DMAMODE_READYIEN;
1312         /*  enable bterm, not sure if this is necessary */
1313         bits |= PLX_DMAMODE_BTERMIEN;
1314         /*  enable dma chaining */
1315         bits |= PLX_DMAMODE_CHAINEN;
1316         /*  enable interrupt on dma done
1317          *  (probably don't need this, since chain never finishes) */
1318         bits |= PLX_DMAMODE_DONEIEN;
1319         /*  don't increment local address during transfers
1320          *  (we are transferring from a fixed fifo register) */
1321         bits |= PLX_DMAMODE_LACONST;
1322         /*  route dma interrupt to pci bus */
1323         bits |= PLX_DMAMODE_INTRPCI;
1324         /*  enable demand mode */
1325         bits |= PLX_DMAMODE_DEMAND;
1326         /*  enable local burst mode */
1327         bits |= PLX_DMAMODE_BURSTEN;
1328         /*  4020 uses 32 bit dma */
1329         if (board->layout == LAYOUT_4020)
1330                 bits |= PLX_DMAMODE_WIDTH32;
1331         else            /*  localspace0 bus is 16 bits wide */
1332                 bits |= PLX_DMAMODE_WIDTH16;
1333         writel(bits, plx_iobase + PLX_REG_DMAMODE1);
1334         if (ao_cmd_is_supported(board))
1335                 writel(bits, plx_iobase + PLX_REG_DMAMODE0);
1336
1337         /*  enable interrupts on plx 9080 */
1338         devpriv->plx_intcsr_bits |=
1339             PLX_INTCSR_LSEABORTEN | PLX_INTCSR_LSEPARITYEN | PLX_INTCSR_PIEN |
1340             PLX_INTCSR_PLIEN | PLX_INTCSR_PABORTIEN | PLX_INTCSR_LIOEN |
1341             PLX_INTCSR_DMA0IEN | PLX_INTCSR_DMA1IEN;
1342         writel(devpriv->plx_intcsr_bits,
1343                devpriv->plx9080_iobase + PLX_REG_INTCSR);
1344 }
1345
1346 static void disable_ai_pacing(struct comedi_device *dev)
1347 {
1348         struct pcidas64_private *devpriv = dev->private;
1349         unsigned long flags;
1350
1351         disable_ai_interrupts(dev);
1352
1353         spin_lock_irqsave(&dev->spinlock, flags);
1354         devpriv->adc_control1_bits &= ~ADC_SW_GATE_BIT;
1355         writew(devpriv->adc_control1_bits,
1356                devpriv->main_iobase + ADC_CONTROL1_REG);
1357         spin_unlock_irqrestore(&dev->spinlock, flags);
1358
1359         /* disable pacing, triggering, etc */
1360         writew(ADC_DMA_DISABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT,
1361                devpriv->main_iobase + ADC_CONTROL0_REG);
1362 }
1363
1364 static int set_ai_fifo_segment_length(struct comedi_device *dev,
1365                                       unsigned int num_entries)
1366 {
1367         const struct pcidas64_board *board = dev->board_ptr;
1368         struct pcidas64_private *devpriv = dev->private;
1369         static const int increment_size = 0x100;
1370         const struct hw_fifo_info *const fifo = board->ai_fifo;
1371         unsigned int num_increments;
1372         uint16_t bits;
1373
1374         if (num_entries < increment_size)
1375                 num_entries = increment_size;
1376         if (num_entries > fifo->max_segment_length)
1377                 num_entries = fifo->max_segment_length;
1378
1379         /*  1 == 256 entries, 2 == 512 entries, etc */
1380         num_increments = DIV_ROUND_CLOSEST(num_entries, increment_size);
1381
1382         bits = (~(num_increments - 1)) & fifo->fifo_size_reg_mask;
1383         devpriv->fifo_size_bits &= ~fifo->fifo_size_reg_mask;
1384         devpriv->fifo_size_bits |= bits;
1385         writew(devpriv->fifo_size_bits,
1386                devpriv->main_iobase + FIFO_SIZE_REG);
1387
1388         devpriv->ai_fifo_segment_length = num_increments * increment_size;
1389
1390         return devpriv->ai_fifo_segment_length;
1391 }
1392
1393 /*
1394  * adjusts the size of hardware fifo (which determines block size for dma xfers)
1395  */
1396 static int set_ai_fifo_size(struct comedi_device *dev, unsigned int num_samples)
1397 {
1398         const struct pcidas64_board *board = dev->board_ptr;
1399         unsigned int num_fifo_entries;
1400         int retval;
1401         const struct hw_fifo_info *const fifo = board->ai_fifo;
1402
1403         num_fifo_entries = num_samples / fifo->sample_packing_ratio;
1404
1405         retval = set_ai_fifo_segment_length(dev,
1406                                             num_fifo_entries /
1407                                             fifo->num_segments);
1408         if (retval < 0)
1409                 return retval;
1410
1411         num_samples = retval * fifo->num_segments * fifo->sample_packing_ratio;
1412
1413         return num_samples;
1414 }
1415
1416 /* query length of fifo */
1417 static unsigned int ai_fifo_size(struct comedi_device *dev)
1418 {
1419         const struct pcidas64_board *board = dev->board_ptr;
1420         struct pcidas64_private *devpriv = dev->private;
1421
1422         return devpriv->ai_fifo_segment_length *
1423                board->ai_fifo->num_segments *
1424                board->ai_fifo->sample_packing_ratio;
1425 }
1426
1427 static void init_stc_registers(struct comedi_device *dev)
1428 {
1429         const struct pcidas64_board *board = dev->board_ptr;
1430         struct pcidas64_private *devpriv = dev->private;
1431         uint16_t bits;
1432         unsigned long flags;
1433
1434         spin_lock_irqsave(&dev->spinlock, flags);
1435
1436         /*
1437          * bit should be set for 6025,
1438          * although docs say boards with <= 16 chans should be cleared XXX
1439          */
1440         if (1)
1441                 devpriv->adc_control1_bits |= ADC_QUEUE_CONFIG_BIT;
1442         writew(devpriv->adc_control1_bits,
1443                devpriv->main_iobase + ADC_CONTROL1_REG);
1444
1445         /*  6402/16 manual says this register must be initialized to 0xff? */
1446         writew(0xff, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1447
1448         bits = SLOW_DAC_BIT | DMA_CH_SELECT_BIT;
1449         if (board->layout == LAYOUT_4020)
1450                 bits |= INTERNAL_CLOCK_4020_BITS;
1451         devpriv->hw_config_bits |= bits;
1452         writew(devpriv->hw_config_bits,
1453                devpriv->main_iobase + HW_CONFIG_REG);
1454
1455         writew(0, devpriv->main_iobase + DAQ_SYNC_REG);
1456         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1457
1458         spin_unlock_irqrestore(&dev->spinlock, flags);
1459
1460         /*  set fifos to maximum size */
1461         devpriv->fifo_size_bits |= DAC_FIFO_BITS;
1462         set_ai_fifo_segment_length(dev, board->ai_fifo->max_segment_length);
1463
1464         devpriv->dac_control1_bits = DAC_OUTPUT_ENABLE_BIT;
1465         devpriv->intr_enable_bits =
1466                 /* EN_DAC_INTR_SRC_BIT | DAC_INTR_QEMPTY_BITS | */
1467                 EN_DAC_DONE_INTR_BIT | EN_DAC_UNDERRUN_BIT;
1468         writew(devpriv->intr_enable_bits,
1469                devpriv->main_iobase + INTR_ENABLE_REG);
1470
1471         disable_ai_pacing(dev);
1472 };
1473
1474 static int alloc_and_init_dma_members(struct comedi_device *dev)
1475 {
1476         const struct pcidas64_board *board = dev->board_ptr;
1477         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1478         struct pcidas64_private *devpriv = dev->private;
1479         int i;
1480
1481         /*  allocate pci dma buffers */
1482         for (i = 0; i < ai_dma_ring_count(board); i++) {
1483                 devpriv->ai_buffer[i] =
1484                         dma_alloc_coherent(&pcidev->dev, DMA_BUFFER_SIZE,
1485                                            &devpriv->ai_buffer_bus_addr[i],
1486                                            GFP_KERNEL);
1487                 if (!devpriv->ai_buffer[i])
1488                         return -ENOMEM;
1489         }
1490         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1491                 if (ao_cmd_is_supported(board)) {
1492                         devpriv->ao_buffer[i] =
1493                                 dma_alloc_coherent(&pcidev->dev,
1494                                                    DMA_BUFFER_SIZE,
1495                                                    &devpriv->
1496                                                    ao_buffer_bus_addr[i],
1497                                                    GFP_KERNEL);
1498                         if (!devpriv->ao_buffer[i])
1499                                 return -ENOMEM;
1500                 }
1501         }
1502         /*  allocate dma descriptors */
1503         devpriv->ai_dma_desc =
1504                 dma_alloc_coherent(&pcidev->dev, sizeof(struct plx_dma_desc) *
1505                                    ai_dma_ring_count(board),
1506                                    &devpriv->ai_dma_desc_bus_addr, GFP_KERNEL);
1507         if (!devpriv->ai_dma_desc)
1508                 return -ENOMEM;
1509
1510         if (ao_cmd_is_supported(board)) {
1511                 devpriv->ao_dma_desc =
1512                         dma_alloc_coherent(&pcidev->dev,
1513                                            sizeof(struct plx_dma_desc) *
1514                                            AO_DMA_RING_COUNT,
1515                                            &devpriv->ao_dma_desc_bus_addr,
1516                                            GFP_KERNEL);
1517                 if (!devpriv->ao_dma_desc)
1518                         return -ENOMEM;
1519         }
1520         /*  initialize dma descriptors */
1521         for (i = 0; i < ai_dma_ring_count(board); i++) {
1522                 devpriv->ai_dma_desc[i].pci_start_addr =
1523                         cpu_to_le32(devpriv->ai_buffer_bus_addr[i]);
1524                 if (board->layout == LAYOUT_4020)
1525                         devpriv->ai_dma_desc[i].local_start_addr =
1526                                 cpu_to_le32(devpriv->local1_iobase +
1527                                             ADC_FIFO_REG);
1528                 else
1529                         devpriv->ai_dma_desc[i].local_start_addr =
1530                                 cpu_to_le32(devpriv->local0_iobase +
1531                                             ADC_FIFO_REG);
1532                 devpriv->ai_dma_desc[i].transfer_size = cpu_to_le32(0);
1533                 devpriv->ai_dma_desc[i].next =
1534                         cpu_to_le32((devpriv->ai_dma_desc_bus_addr +
1535                                      ((i + 1) % ai_dma_ring_count(board)) *
1536                                      sizeof(devpriv->ai_dma_desc[0])) |
1537                                     PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR |
1538                                     PLX_DMADPR_XFERL2P);
1539         }
1540         if (ao_cmd_is_supported(board)) {
1541                 for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1542                         devpriv->ao_dma_desc[i].pci_start_addr =
1543                                 cpu_to_le32(devpriv->ao_buffer_bus_addr[i]);
1544                         devpriv->ao_dma_desc[i].local_start_addr =
1545                                 cpu_to_le32(devpriv->local0_iobase +
1546                                             DAC_FIFO_REG);
1547                         devpriv->ao_dma_desc[i].transfer_size = cpu_to_le32(0);
1548                         devpriv->ao_dma_desc[i].next =
1549                                 cpu_to_le32((devpriv->ao_dma_desc_bus_addr +
1550                                              ((i + 1) % (AO_DMA_RING_COUNT)) *
1551                                              sizeof(devpriv->ao_dma_desc[0])) |
1552                                             PLX_DMADPR_DESCPCI |
1553                                             PLX_DMADPR_TCINTR);
1554                 }
1555         }
1556         return 0;
1557 }
1558
1559 static void cb_pcidas64_free_dma(struct comedi_device *dev)
1560 {
1561         const struct pcidas64_board *board = dev->board_ptr;
1562         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
1563         struct pcidas64_private *devpriv = dev->private;
1564         int i;
1565
1566         if (!devpriv)
1567                 return;
1568
1569         /* free pci dma buffers */
1570         for (i = 0; i < ai_dma_ring_count(board); i++) {
1571                 if (devpriv->ai_buffer[i])
1572                         dma_free_coherent(&pcidev->dev,
1573                                           DMA_BUFFER_SIZE,
1574                                           devpriv->ai_buffer[i],
1575                                           devpriv->ai_buffer_bus_addr[i]);
1576         }
1577         for (i = 0; i < AO_DMA_RING_COUNT; i++) {
1578                 if (devpriv->ao_buffer[i])
1579                         dma_free_coherent(&pcidev->dev,
1580                                           DMA_BUFFER_SIZE,
1581                                           devpriv->ao_buffer[i],
1582                                           devpriv->ao_buffer_bus_addr[i]);
1583         }
1584         /* free dma descriptors */
1585         if (devpriv->ai_dma_desc)
1586                 dma_free_coherent(&pcidev->dev,
1587                                   sizeof(struct plx_dma_desc) *
1588                                   ai_dma_ring_count(board),
1589                                   devpriv->ai_dma_desc,
1590                                   devpriv->ai_dma_desc_bus_addr);
1591         if (devpriv->ao_dma_desc)
1592                 dma_free_coherent(&pcidev->dev,
1593                                   sizeof(struct plx_dma_desc) *
1594                                   AO_DMA_RING_COUNT,
1595                                   devpriv->ao_dma_desc,
1596                                   devpriv->ao_dma_desc_bus_addr);
1597 }
1598
1599 static inline void warn_external_queue(struct comedi_device *dev)
1600 {
1601         dev_err(dev->class_dev,
1602                 "AO command and AI external channel queue cannot be used simultaneously\n");
1603         dev_err(dev->class_dev,
1604                 "Use internal AI channel queue (channels must be consecutive and use same range/aref)\n");
1605 }
1606
1607 /*
1608  * their i2c requires a huge delay on setting clock or data high for some reason
1609  */
1610 static const int i2c_high_udelay = 1000;
1611 static const int i2c_low_udelay = 10;
1612
1613 /* set i2c data line high or low */
1614 static void i2c_set_sda(struct comedi_device *dev, int state)
1615 {
1616         struct pcidas64_private *devpriv = dev->private;
1617         static const int data_bit = PLX_CNTRL_EEWB;
1618         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1619                                          PLX_REG_CNTRL;
1620
1621         if (state) {
1622                 /*  set data line high */
1623                 devpriv->plx_control_bits &= ~data_bit;
1624                 writel(devpriv->plx_control_bits, plx_control_addr);
1625                 udelay(i2c_high_udelay);
1626         } else {                /*  set data line low */
1627
1628                 devpriv->plx_control_bits |= data_bit;
1629                 writel(devpriv->plx_control_bits, plx_control_addr);
1630                 udelay(i2c_low_udelay);
1631         }
1632 }
1633
1634 /* set i2c clock line high or low */
1635 static void i2c_set_scl(struct comedi_device *dev, int state)
1636 {
1637         struct pcidas64_private *devpriv = dev->private;
1638         static const int clock_bit = PLX_CNTRL_USERO;
1639         void __iomem *plx_control_addr = devpriv->plx9080_iobase +
1640                                          PLX_REG_CNTRL;
1641
1642         if (state) {
1643                 /*  set clock line high */
1644                 devpriv->plx_control_bits &= ~clock_bit;
1645                 writel(devpriv->plx_control_bits, plx_control_addr);
1646                 udelay(i2c_high_udelay);
1647         } else {                /*  set clock line low */
1648
1649                 devpriv->plx_control_bits |= clock_bit;
1650                 writel(devpriv->plx_control_bits, plx_control_addr);
1651                 udelay(i2c_low_udelay);
1652         }
1653 }
1654
1655 static void i2c_write_byte(struct comedi_device *dev, uint8_t byte)
1656 {
1657         uint8_t bit;
1658         unsigned int num_bits = 8;
1659
1660         for (bit = 1 << (num_bits - 1); bit; bit >>= 1) {
1661                 i2c_set_scl(dev, 0);
1662                 if ((byte & bit))
1663                         i2c_set_sda(dev, 1);
1664                 else
1665                         i2c_set_sda(dev, 0);
1666                 i2c_set_scl(dev, 1);
1667         }
1668 }
1669
1670 /* we can't really read the lines, so fake it */
1671 static int i2c_read_ack(struct comedi_device *dev)
1672 {
1673         i2c_set_scl(dev, 0);
1674         i2c_set_sda(dev, 1);
1675         i2c_set_scl(dev, 1);
1676
1677         return 0;               /*  return fake acknowledge bit */
1678 }
1679
1680 /* send start bit */
1681 static void i2c_start(struct comedi_device *dev)
1682 {
1683         i2c_set_scl(dev, 1);
1684         i2c_set_sda(dev, 1);
1685         i2c_set_sda(dev, 0);
1686 }
1687
1688 /* send stop bit */
1689 static void i2c_stop(struct comedi_device *dev)
1690 {
1691         i2c_set_scl(dev, 0);
1692         i2c_set_sda(dev, 0);
1693         i2c_set_scl(dev, 1);
1694         i2c_set_sda(dev, 1);
1695 }
1696
1697 static void i2c_write(struct comedi_device *dev, unsigned int address,
1698                       const uint8_t *data, unsigned int length)
1699 {
1700         struct pcidas64_private *devpriv = dev->private;
1701         unsigned int i;
1702         uint8_t bitstream;
1703         static const int read_bit = 0x1;
1704
1705         /*
1706          * XXX need mutex to prevent simultaneous attempts to access
1707          * eeprom and i2c bus
1708          */
1709
1710         /*  make sure we dont send anything to eeprom */
1711         devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
1712
1713         i2c_stop(dev);
1714         i2c_start(dev);
1715
1716         /*  send address and write bit */
1717         bitstream = (address << 1) & ~read_bit;
1718         i2c_write_byte(dev, bitstream);
1719
1720         /*  get acknowledge */
1721         if (i2c_read_ack(dev) != 0) {
1722                 dev_err(dev->class_dev, "failed: no acknowledge\n");
1723                 i2c_stop(dev);
1724                 return;
1725         }
1726         /*  write data bytes */
1727         for (i = 0; i < length; i++) {
1728                 i2c_write_byte(dev, data[i]);
1729                 if (i2c_read_ack(dev) != 0) {
1730                         dev_err(dev->class_dev, "failed: no acknowledge\n");
1731                         i2c_stop(dev);
1732                         return;
1733                 }
1734         }
1735         i2c_stop(dev);
1736 }
1737
1738 static int cb_pcidas64_ai_eoc(struct comedi_device *dev,
1739                               struct comedi_subdevice *s,
1740                               struct comedi_insn *insn,
1741                               unsigned long context)
1742 {
1743         const struct pcidas64_board *board = dev->board_ptr;
1744         struct pcidas64_private *devpriv = dev->private;
1745         unsigned int status;
1746
1747         status = readw(devpriv->main_iobase + HW_STATUS_REG);
1748         if (board->layout == LAYOUT_4020) {
1749                 status = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG);
1750                 if (status)
1751                         return 0;
1752         } else {
1753                 if (pipe_full_bits(status))
1754                         return 0;
1755         }
1756         return -EBUSY;
1757 }
1758
1759 static int ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
1760                     struct comedi_insn *insn, unsigned int *data)
1761 {
1762         const struct pcidas64_board *board = dev->board_ptr;
1763         struct pcidas64_private *devpriv = dev->private;
1764         unsigned int bits = 0, n;
1765         unsigned int channel, range, aref;
1766         unsigned long flags;
1767         int ret;
1768
1769         channel = CR_CHAN(insn->chanspec);
1770         range = CR_RANGE(insn->chanspec);
1771         aref = CR_AREF(insn->chanspec);
1772
1773         /*  disable card's analog input interrupt sources and pacing */
1774         /*  4020 generates dac done interrupts even though they are disabled */
1775         disable_ai_pacing(dev);
1776
1777         spin_lock_irqsave(&dev->spinlock, flags);
1778         if (insn->chanspec & CR_ALT_FILTER)
1779                 devpriv->adc_control1_bits |= ADC_DITHER_BIT;
1780         else
1781                 devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
1782         writew(devpriv->adc_control1_bits,
1783                devpriv->main_iobase + ADC_CONTROL1_REG);
1784         spin_unlock_irqrestore(&dev->spinlock, flags);
1785
1786         if (board->layout != LAYOUT_4020) {
1787                 /*  use internal queue */
1788                 devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
1789                 writew(devpriv->hw_config_bits,
1790                        devpriv->main_iobase + HW_CONFIG_REG);
1791
1792                 /*  ALT_SOURCE is internal calibration reference */
1793                 if (insn->chanspec & CR_ALT_SOURCE) {
1794                         unsigned int cal_en_bit;
1795
1796                         if (board->layout == LAYOUT_60XX)
1797                                 cal_en_bit = CAL_EN_60XX_BIT;
1798                         else
1799                                 cal_en_bit = CAL_EN_64XX_BIT;
1800                         /*
1801                          * select internal reference source to connect
1802                          * to channel 0
1803                          */
1804                         writew(cal_en_bit |
1805                                adc_src_bits(devpriv->calibration_source),
1806                                devpriv->main_iobase + CALIBRATION_REG);
1807                 } else {
1808                         /*
1809                          * make sure internal calibration source
1810                          * is turned off
1811                          */
1812                         writew(0, devpriv->main_iobase + CALIBRATION_REG);
1813                 }
1814                 /*  load internal queue */
1815                 bits = 0;
1816                 /*  set gain */
1817                 bits |= ai_range_bits_6xxx(dev, CR_RANGE(insn->chanspec));
1818                 /*  set single-ended / differential */
1819                 bits |= se_diff_bit_6xxx(dev, aref == AREF_DIFF);
1820                 if (aref == AREF_COMMON)
1821                         bits |= ADC_COMMON_BIT;
1822                 bits |= adc_chan_bits(channel);
1823                 /*  set stop channel */
1824                 writew(adc_chan_bits(channel),
1825                        devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
1826                 /*  set start channel, and rest of settings */
1827                 writew(bits, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
1828         } else {
1829                 uint8_t old_cal_range_bits = devpriv->i2c_cal_range_bits;
1830
1831                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
1832                 if (insn->chanspec & CR_ALT_SOURCE) {
1833                         devpriv->i2c_cal_range_bits |=
1834                                 adc_src_4020_bits(devpriv->calibration_source);
1835                 } else {        /* select BNC inputs */
1836                         devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
1837                 }
1838                 /*  select range */
1839                 if (range == 0)
1840                         devpriv->i2c_cal_range_bits |= attenuate_bit(channel);
1841                 else
1842                         devpriv->i2c_cal_range_bits &= ~attenuate_bit(channel);
1843                 /*
1844                  * update calibration/range i2c register only if necessary,
1845                  * as it is very slow
1846                  */
1847                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
1848                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
1849
1850                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
1851                                   sizeof(i2c_data));
1852                 }
1853
1854                 /*
1855                  * 4020 manual asks that sample interval register to be set
1856                  * before writing to convert register.
1857                  * Using somewhat arbitrary setting of 4 master clock ticks
1858                  * = 0.1 usec
1859                  */
1860                 writew(0, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
1861                 writew(2, devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
1862         }
1863
1864         for (n = 0; n < insn->n; n++) {
1865                 /*  clear adc buffer (inside loop for 4020 sake) */
1866                 writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
1867
1868                 /* trigger conversion, bits sent only matter for 4020 */
1869                 writew(adc_convert_chan_4020_bits(CR_CHAN(insn->chanspec)),
1870                        devpriv->main_iobase + ADC_CONVERT_REG);
1871
1872                 /*  wait for data */
1873                 ret = comedi_timeout(dev, s, insn, cb_pcidas64_ai_eoc, 0);
1874                 if (ret)
1875                         return ret;
1876
1877                 if (board->layout == LAYOUT_4020)
1878                         data[n] = readl(dev->mmio + ADC_FIFO_REG) & 0xffff;
1879                 else
1880                         data[n] = readw(devpriv->main_iobase + PIPE1_READ_REG);
1881         }
1882
1883         return n;
1884 }
1885
1886 static int ai_config_calibration_source(struct comedi_device *dev,
1887                                         unsigned int *data)
1888 {
1889         const struct pcidas64_board *board = dev->board_ptr;
1890         struct pcidas64_private *devpriv = dev->private;
1891         unsigned int source = data[1];
1892         int num_calibration_sources;
1893
1894         if (board->layout == LAYOUT_60XX)
1895                 num_calibration_sources = 16;
1896         else
1897                 num_calibration_sources = 8;
1898         if (source >= num_calibration_sources) {
1899                 dev_dbg(dev->class_dev, "invalid calibration source: %i\n",
1900                         source);
1901                 return -EINVAL;
1902         }
1903
1904         devpriv->calibration_source = source;
1905
1906         return 2;
1907 }
1908
1909 static int ai_config_block_size(struct comedi_device *dev, unsigned int *data)
1910 {
1911         const struct pcidas64_board *board = dev->board_ptr;
1912         int fifo_size;
1913         const struct hw_fifo_info *const fifo = board->ai_fifo;
1914         unsigned int block_size, requested_block_size;
1915         int retval;
1916
1917         requested_block_size = data[1];
1918
1919         if (requested_block_size) {
1920                 fifo_size = requested_block_size * fifo->num_segments /
1921                             bytes_in_sample;
1922
1923                 retval = set_ai_fifo_size(dev, fifo_size);
1924                 if (retval < 0)
1925                         return retval;
1926         }
1927
1928         block_size = ai_fifo_size(dev) / fifo->num_segments * bytes_in_sample;
1929
1930         data[1] = block_size;
1931
1932         return 2;
1933 }
1934
1935 static int ai_config_master_clock_4020(struct comedi_device *dev,
1936                                        unsigned int *data)
1937 {
1938         struct pcidas64_private *devpriv = dev->private;
1939         unsigned int divisor = data[4];
1940         int retval = 0;
1941
1942         if (divisor < 2) {
1943                 divisor = 2;
1944                 retval = -EAGAIN;
1945         }
1946
1947         switch (data[1]) {
1948         case COMEDI_EV_SCAN_BEGIN:
1949                 devpriv->ext_clock.divisor = divisor;
1950                 devpriv->ext_clock.chanspec = data[2];
1951                 break;
1952         default:
1953                 return -EINVAL;
1954         }
1955
1956         data[4] = divisor;
1957
1958         return retval ? retval : 5;
1959 }
1960
1961 /* XXX could add support for 60xx series */
1962 static int ai_config_master_clock(struct comedi_device *dev, unsigned int *data)
1963 {
1964         const struct pcidas64_board *board = dev->board_ptr;
1965
1966         switch (board->layout) {
1967         case LAYOUT_4020:
1968                 return ai_config_master_clock_4020(dev, data);
1969         default:
1970                 return -EINVAL;
1971         }
1972
1973         return -EINVAL;
1974 }
1975
1976 static int ai_config_insn(struct comedi_device *dev, struct comedi_subdevice *s,
1977                           struct comedi_insn *insn, unsigned int *data)
1978 {
1979         int id = data[0];
1980
1981         switch (id) {
1982         case INSN_CONFIG_ALT_SOURCE:
1983                 return ai_config_calibration_source(dev, data);
1984         case INSN_CONFIG_BLOCK_SIZE:
1985                 return ai_config_block_size(dev, data);
1986         case INSN_CONFIG_TIMER_1:
1987                 return ai_config_master_clock(dev, data);
1988         default:
1989                 return -EINVAL;
1990         }
1991         return -EINVAL;
1992 }
1993
1994 /*
1995  * Gets nearest achievable timing given master clock speed, does not
1996  * take into account possible minimum/maximum divisor values.  Used
1997  * by other timing checking functions.
1998  */
1999 static unsigned int get_divisor(unsigned int ns, unsigned int flags)
2000 {
2001         unsigned int divisor;
2002
2003         switch (flags & CMDF_ROUND_MASK) {
2004         case CMDF_ROUND_UP:
2005                 divisor = (ns + TIMER_BASE - 1) / TIMER_BASE;
2006                 break;
2007         case CMDF_ROUND_DOWN:
2008                 divisor = ns / TIMER_BASE;
2009                 break;
2010         case CMDF_ROUND_NEAREST:
2011         default:
2012                 divisor = DIV_ROUND_CLOSEST(ns, TIMER_BASE);
2013                 break;
2014         }
2015         return divisor;
2016 }
2017
2018 /*
2019  * utility function that rounds desired timing to an achievable time, and
2020  * sets cmd members appropriately.
2021  * adc paces conversions from master clock by dividing by (x + 3) where x is
2022  * 24 bit number
2023  */
2024 static void check_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
2025 {
2026         const struct pcidas64_board *board = dev->board_ptr;
2027         unsigned long long convert_divisor = 0;
2028         unsigned int scan_divisor;
2029         static const int min_convert_divisor = 3;
2030         static const int max_convert_divisor =
2031                 max_counter_value + min_convert_divisor;
2032         static const int min_scan_divisor_4020 = 2;
2033         unsigned long long max_scan_divisor, min_scan_divisor;
2034
2035         if (cmd->convert_src == TRIG_TIMER) {
2036                 if (board->layout == LAYOUT_4020) {
2037                         cmd->convert_arg = 0;
2038                 } else {
2039                         convert_divisor = get_divisor(cmd->convert_arg,
2040                                                       cmd->flags);
2041                         if (convert_divisor > max_convert_divisor)
2042                                 convert_divisor = max_convert_divisor;
2043                         if (convert_divisor < min_convert_divisor)
2044                                 convert_divisor = min_convert_divisor;
2045                         cmd->convert_arg = convert_divisor * TIMER_BASE;
2046                 }
2047         } else if (cmd->convert_src == TRIG_NOW) {
2048                 cmd->convert_arg = 0;
2049         }
2050
2051         if (cmd->scan_begin_src == TRIG_TIMER) {
2052                 scan_divisor = get_divisor(cmd->scan_begin_arg, cmd->flags);
2053                 if (cmd->convert_src == TRIG_TIMER) {
2054                         min_scan_divisor = convert_divisor * cmd->chanlist_len;
2055                         max_scan_divisor =
2056                                 (convert_divisor * cmd->chanlist_len - 1) +
2057                                 max_counter_value;
2058                 } else {
2059                         min_scan_divisor = min_scan_divisor_4020;
2060                         max_scan_divisor = max_counter_value + min_scan_divisor;
2061                 }
2062                 if (scan_divisor > max_scan_divisor)
2063                         scan_divisor = max_scan_divisor;
2064                 if (scan_divisor < min_scan_divisor)
2065                         scan_divisor = min_scan_divisor;
2066                 cmd->scan_begin_arg = scan_divisor * TIMER_BASE;
2067         }
2068 }
2069
2070 static int cb_pcidas64_ai_check_chanlist(struct comedi_device *dev,
2071                                          struct comedi_subdevice *s,
2072                                          struct comedi_cmd *cmd)
2073 {
2074         const struct pcidas64_board *board = dev->board_ptr;
2075         unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
2076         int i;
2077
2078         for (i = 1; i < cmd->chanlist_len; i++) {
2079                 unsigned int aref = CR_AREF(cmd->chanlist[i]);
2080
2081                 if (aref != aref0) {
2082                         dev_dbg(dev->class_dev,
2083                                 "all elements in chanlist must use the same analog reference\n");
2084                         return -EINVAL;
2085                 }
2086         }
2087
2088         if (board->layout == LAYOUT_4020) {
2089                 unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
2090
2091                 for (i = 1; i < cmd->chanlist_len; i++) {
2092                         unsigned int chan = CR_CHAN(cmd->chanlist[i]);
2093
2094                         if (chan != (chan0 + i)) {
2095                                 dev_dbg(dev->class_dev,
2096                                         "chanlist must use consecutive channels\n");
2097                                 return -EINVAL;
2098                         }
2099                 }
2100                 if (cmd->chanlist_len == 3) {
2101                         dev_dbg(dev->class_dev,
2102                                 "chanlist cannot be 3 channels long, use 1, 2, or 4 channels\n");
2103                         return -EINVAL;
2104                 }
2105         }
2106
2107         return 0;
2108 }
2109
2110 static int ai_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
2111                       struct comedi_cmd *cmd)
2112 {
2113         const struct pcidas64_board *board = dev->board_ptr;
2114         int err = 0;
2115         unsigned int tmp_arg, tmp_arg2;
2116         unsigned int triggers;
2117
2118         /* Step 1 : check if triggers are trivially valid */
2119
2120         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
2121
2122         triggers = TRIG_TIMER;
2123         if (board->layout == LAYOUT_4020)
2124                 triggers |= TRIG_OTHER;
2125         else
2126                 triggers |= TRIG_FOLLOW;
2127         err |= comedi_check_trigger_src(&cmd->scan_begin_src, triggers);
2128
2129         triggers = TRIG_TIMER;
2130         if (board->layout == LAYOUT_4020)
2131                 triggers |= TRIG_NOW;
2132         else
2133                 triggers |= TRIG_EXT;
2134         err |= comedi_check_trigger_src(&cmd->convert_src, triggers);
2135         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
2136         err |= comedi_check_trigger_src(&cmd->stop_src,
2137                                         TRIG_COUNT | TRIG_EXT | TRIG_NONE);
2138
2139         if (err)
2140                 return 1;
2141
2142         /* Step 2a : make sure trigger sources are unique */
2143
2144         err |= comedi_check_trigger_is_unique(cmd->start_src);
2145         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
2146         err |= comedi_check_trigger_is_unique(cmd->convert_src);
2147         err |= comedi_check_trigger_is_unique(cmd->stop_src);
2148
2149         /* Step 2b : and mutually compatible */
2150
2151         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
2152                 err |= -EINVAL;
2153
2154         if (err)
2155                 return 2;
2156
2157         /* Step 3: check if arguments are trivially valid */
2158
2159         switch (cmd->start_src) {
2160         case TRIG_NOW:
2161                 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
2162                 break;
2163         case TRIG_EXT:
2164                 /*
2165                  * start_arg is the CR_CHAN | CR_INVERT of the
2166                  * external trigger.
2167                  */
2168                 break;
2169         }
2170
2171         if (cmd->convert_src == TRIG_TIMER) {
2172                 if (board->layout == LAYOUT_4020) {
2173                         err |= comedi_check_trigger_arg_is(&cmd->convert_arg,
2174                                                            0);
2175                 } else {
2176                         err |= comedi_check_trigger_arg_min(&cmd->convert_arg,
2177                                                             board->ai_speed);
2178                         /*
2179                          * if scans are timed faster than conversion rate
2180                          * allows
2181                          */
2182                         if (cmd->scan_begin_src == TRIG_TIMER) {
2183                                 err |= comedi_check_trigger_arg_min(
2184                                                 &cmd->scan_begin_arg,
2185                                                 cmd->convert_arg *
2186                                                 cmd->chanlist_len);
2187                         }
2188                 }
2189         }
2190
2191         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
2192         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
2193                                            cmd->chanlist_len);
2194
2195         switch (cmd->stop_src) {
2196         case TRIG_EXT:
2197                 break;
2198         case TRIG_COUNT:
2199                 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
2200                 break;
2201         case TRIG_NONE:
2202                 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
2203                 break;
2204         default:
2205                 break;
2206         }
2207
2208         if (err)
2209                 return 3;
2210
2211         /* step 4: fix up any arguments */
2212
2213         if (cmd->convert_src == TRIG_TIMER) {
2214                 tmp_arg = cmd->convert_arg;
2215                 tmp_arg2 = cmd->scan_begin_arg;
2216                 check_adc_timing(dev, cmd);
2217                 if (tmp_arg != cmd->convert_arg)
2218                         err++;
2219                 if (tmp_arg2 != cmd->scan_begin_arg)
2220                         err++;
2221         }
2222
2223         if (err)
2224                 return 4;
2225
2226         /* Step 5: check channel list if it exists */
2227         if (cmd->chanlist && cmd->chanlist_len > 0)
2228                 err |= cb_pcidas64_ai_check_chanlist(dev, s, cmd);
2229
2230         if (err)
2231                 return 5;
2232
2233         return 0;
2234 }
2235
2236 static int use_hw_sample_counter(struct comedi_cmd *cmd)
2237 {
2238 /* disable for now until I work out a race */
2239         return 0;
2240
2241         if (cmd->stop_src == TRIG_COUNT && cmd->stop_arg <= max_counter_value)
2242                 return 1;
2243
2244         return 0;
2245 }
2246
2247 static void setup_sample_counters(struct comedi_device *dev,
2248                                   struct comedi_cmd *cmd)
2249 {
2250         struct pcidas64_private *devpriv = dev->private;
2251
2252         /*  load hardware conversion counter */
2253         if (use_hw_sample_counter(cmd)) {
2254                 writew(cmd->stop_arg & 0xffff,
2255                        devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2256                 writew((cmd->stop_arg >> 16) & 0xff,
2257                        devpriv->main_iobase + ADC_COUNT_UPPER_REG);
2258         } else {
2259                 writew(1, devpriv->main_iobase + ADC_COUNT_LOWER_REG);
2260         }
2261 }
2262
2263 static inline unsigned int dma_transfer_size(struct comedi_device *dev)
2264 {
2265         const struct pcidas64_board *board = dev->board_ptr;
2266         struct pcidas64_private *devpriv = dev->private;
2267         unsigned int num_samples;
2268
2269         num_samples = devpriv->ai_fifo_segment_length *
2270                       board->ai_fifo->sample_packing_ratio;
2271         if (num_samples > DMA_BUFFER_SIZE / sizeof(uint16_t))
2272                 num_samples = DMA_BUFFER_SIZE / sizeof(uint16_t);
2273
2274         return num_samples;
2275 }
2276
2277 static uint32_t ai_convert_counter_6xxx(const struct comedi_device *dev,
2278                                         const struct comedi_cmd *cmd)
2279 {
2280         /*  supposed to load counter with desired divisor minus 3 */
2281         return cmd->convert_arg / TIMER_BASE - 3;
2282 }
2283
2284 static uint32_t ai_scan_counter_6xxx(struct comedi_device *dev,
2285                                      struct comedi_cmd *cmd)
2286 {
2287         uint32_t count;
2288
2289         /*  figure out how long we need to delay at end of scan */
2290         switch (cmd->scan_begin_src) {
2291         case TRIG_TIMER:
2292                 count = (cmd->scan_begin_arg -
2293                          (cmd->convert_arg * (cmd->chanlist_len - 1))) /
2294                         TIMER_BASE;
2295                 break;
2296         case TRIG_FOLLOW:
2297                 count = cmd->convert_arg / TIMER_BASE;
2298                 break;
2299         default:
2300                 return 0;
2301         }
2302         return count - 3;
2303 }
2304
2305 static uint32_t ai_convert_counter_4020(struct comedi_device *dev,
2306                                         struct comedi_cmd *cmd)
2307 {
2308         struct pcidas64_private *devpriv = dev->private;
2309         unsigned int divisor;
2310
2311         switch (cmd->scan_begin_src) {
2312         case TRIG_TIMER:
2313                 divisor = cmd->scan_begin_arg / TIMER_BASE;
2314                 break;
2315         case TRIG_OTHER:
2316                 divisor = devpriv->ext_clock.divisor;
2317                 break;
2318         default:                /*  should never happen */
2319                 dev_err(dev->class_dev, "bug! failed to set ai pacing!\n");
2320                 divisor = 1000;
2321                 break;
2322         }
2323
2324         /*  supposed to load counter with desired divisor minus 2 for 4020 */
2325         return divisor - 2;
2326 }
2327
2328 static void select_master_clock_4020(struct comedi_device *dev,
2329                                      const struct comedi_cmd *cmd)
2330 {
2331         struct pcidas64_private *devpriv = dev->private;
2332
2333         /*  select internal/external master clock */
2334         devpriv->hw_config_bits &= ~MASTER_CLOCK_4020_MASK;
2335         if (cmd->scan_begin_src == TRIG_OTHER) {
2336                 int chanspec = devpriv->ext_clock.chanspec;
2337
2338                 if (CR_CHAN(chanspec))
2339                         devpriv->hw_config_bits |= BNC_CLOCK_4020_BITS;
2340                 else
2341                         devpriv->hw_config_bits |= EXT_CLOCK_4020_BITS;
2342         } else {
2343                 devpriv->hw_config_bits |= INTERNAL_CLOCK_4020_BITS;
2344         }
2345         writew(devpriv->hw_config_bits,
2346                devpriv->main_iobase + HW_CONFIG_REG);
2347 }
2348
2349 static void select_master_clock(struct comedi_device *dev,
2350                                 const struct comedi_cmd *cmd)
2351 {
2352         const struct pcidas64_board *board = dev->board_ptr;
2353
2354         switch (board->layout) {
2355         case LAYOUT_4020:
2356                 select_master_clock_4020(dev, cmd);
2357                 break;
2358         default:
2359                 break;
2360         }
2361 }
2362
2363 static inline void dma_start_sync(struct comedi_device *dev,
2364                                   unsigned int channel)
2365 {
2366         struct pcidas64_private *devpriv = dev->private;
2367         unsigned long flags;
2368
2369         /*  spinlock for plx dma control/status reg */
2370         spin_lock_irqsave(&dev->spinlock, flags);
2371         writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_START | PLX_DMACSR_CLEARINTR,
2372                devpriv->plx9080_iobase + PLX_REG_DMACSR(channel));
2373         spin_unlock_irqrestore(&dev->spinlock, flags);
2374 }
2375
2376 static void set_ai_pacing(struct comedi_device *dev, struct comedi_cmd *cmd)
2377 {
2378         const struct pcidas64_board *board = dev->board_ptr;
2379         struct pcidas64_private *devpriv = dev->private;
2380         uint32_t convert_counter = 0, scan_counter = 0;
2381
2382         check_adc_timing(dev, cmd);
2383
2384         select_master_clock(dev, cmd);
2385
2386         if (board->layout == LAYOUT_4020) {
2387                 convert_counter = ai_convert_counter_4020(dev, cmd);
2388         } else {
2389                 convert_counter = ai_convert_counter_6xxx(dev, cmd);
2390                 scan_counter = ai_scan_counter_6xxx(dev, cmd);
2391         }
2392
2393         /*  load lower 16 bits of convert interval */
2394         writew(convert_counter & 0xffff,
2395                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_LOWER_REG);
2396         /*  load upper 8 bits of convert interval */
2397         writew((convert_counter >> 16) & 0xff,
2398                devpriv->main_iobase + ADC_SAMPLE_INTERVAL_UPPER_REG);
2399         /*  load lower 16 bits of scan delay */
2400         writew(scan_counter & 0xffff,
2401                devpriv->main_iobase + ADC_DELAY_INTERVAL_LOWER_REG);
2402         /*  load upper 8 bits of scan delay */
2403         writew((scan_counter >> 16) & 0xff,
2404                devpriv->main_iobase + ADC_DELAY_INTERVAL_UPPER_REG);
2405 }
2406
2407 static int use_internal_queue_6xxx(const struct comedi_cmd *cmd)
2408 {
2409         int i;
2410
2411         for (i = 0; i + 1 < cmd->chanlist_len; i++) {
2412                 if (CR_CHAN(cmd->chanlist[i + 1]) !=
2413                     CR_CHAN(cmd->chanlist[i]) + 1)
2414                         return 0;
2415                 if (CR_RANGE(cmd->chanlist[i + 1]) !=
2416                     CR_RANGE(cmd->chanlist[i]))
2417                         return 0;
2418                 if (CR_AREF(cmd->chanlist[i + 1]) != CR_AREF(cmd->chanlist[i]))
2419                         return 0;
2420         }
2421         return 1;
2422 }
2423
2424 static int setup_channel_queue(struct comedi_device *dev,
2425                                const struct comedi_cmd *cmd)
2426 {
2427         const struct pcidas64_board *board = dev->board_ptr;
2428         struct pcidas64_private *devpriv = dev->private;
2429         unsigned short bits;
2430         int i;
2431
2432         if (board->layout != LAYOUT_4020) {
2433                 if (use_internal_queue_6xxx(cmd)) {
2434                         devpriv->hw_config_bits &= ~EXT_QUEUE_BIT;
2435                         writew(devpriv->hw_config_bits,
2436                                devpriv->main_iobase + HW_CONFIG_REG);
2437                         bits = 0;
2438                         /*  set channel */
2439                         bits |= adc_chan_bits(CR_CHAN(cmd->chanlist[0]));
2440                         /*  set gain */
2441                         bits |= ai_range_bits_6xxx(dev,
2442                                                    CR_RANGE(cmd->chanlist[0]));
2443                         /*  set single-ended / differential */
2444                         bits |= se_diff_bit_6xxx(dev,
2445                                                  CR_AREF(cmd->chanlist[0]) ==
2446                                                  AREF_DIFF);
2447                         if (CR_AREF(cmd->chanlist[0]) == AREF_COMMON)
2448                                 bits |= ADC_COMMON_BIT;
2449                         /*  set stop channel */
2450                         writew(adc_chan_bits
2451                                (CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1])),
2452                                devpriv->main_iobase + ADC_QUEUE_HIGH_REG);
2453                         /*  set start channel, and rest of settings */
2454                         writew(bits,
2455                                devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2456                 } else {
2457                         /*  use external queue */
2458                         if (dev->write_subdev && dev->write_subdev->busy) {
2459                                 warn_external_queue(dev);
2460                                 return -EBUSY;
2461                         }
2462                         devpriv->hw_config_bits |= EXT_QUEUE_BIT;
2463                         writew(devpriv->hw_config_bits,
2464                                devpriv->main_iobase + HW_CONFIG_REG);
2465                         /*  clear DAC buffer to prevent weird interactions */
2466                         writew(0,
2467                                devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
2468                         /*  clear queue pointer */
2469                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2470                         /*  load external queue */
2471                         for (i = 0; i < cmd->chanlist_len; i++) {
2472                                 bits = 0;
2473                                 /*  set channel */
2474                                 bits |= adc_chan_bits(CR_CHAN(cmd->
2475                                                               chanlist[i]));
2476                                 /*  set gain */
2477                                 bits |= ai_range_bits_6xxx(dev,
2478                                                            CR_RANGE(cmd->
2479                                                                     chanlist
2480                                                                     [i]));
2481                                 /*  set single-ended / differential */
2482                                 bits |= se_diff_bit_6xxx(dev,
2483                                                          CR_AREF(cmd->
2484                                                                  chanlist[i]) ==
2485                                                          AREF_DIFF);
2486                                 if (CR_AREF(cmd->chanlist[i]) == AREF_COMMON)
2487                                         bits |= ADC_COMMON_BIT;
2488                                 /*  mark end of queue */
2489                                 if (i == cmd->chanlist_len - 1)
2490                                         bits |= QUEUE_EOSCAN_BIT |
2491                                                 QUEUE_EOSEQ_BIT;
2492                                 writew(bits,
2493                                        devpriv->main_iobase +
2494                                        ADC_QUEUE_FIFO_REG);
2495                         }
2496                         /*
2497                          * doing a queue clear is not specified in board docs,
2498                          * but required for reliable operation
2499                          */
2500                         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
2501                         /*  prime queue holding register */
2502                         writew(0, devpriv->main_iobase + ADC_QUEUE_LOAD_REG);
2503                 }
2504         } else {
2505                 unsigned short old_cal_range_bits = devpriv->i2c_cal_range_bits;
2506
2507                 devpriv->i2c_cal_range_bits &= ~ADC_SRC_4020_MASK;
2508                 /* select BNC inputs */
2509                 devpriv->i2c_cal_range_bits |= adc_src_4020_bits(4);
2510                 /*  select ranges */
2511                 for (i = 0; i < cmd->chanlist_len; i++) {
2512                         unsigned int channel = CR_CHAN(cmd->chanlist[i]);
2513                         unsigned int range = CR_RANGE(cmd->chanlist[i]);
2514
2515                         if (range == 0)
2516                                 devpriv->i2c_cal_range_bits |=
2517                                         attenuate_bit(channel);
2518                         else
2519                                 devpriv->i2c_cal_range_bits &=
2520                                         ~attenuate_bit(channel);
2521                 }
2522                 /*
2523                  * update calibration/range i2c register only if necessary,
2524                  * as it is very slow
2525                  */
2526                 if (old_cal_range_bits != devpriv->i2c_cal_range_bits) {
2527                         uint8_t i2c_data = devpriv->i2c_cal_range_bits;
2528
2529                         i2c_write(dev, RANGE_CAL_I2C_ADDR, &i2c_data,
2530                                   sizeof(i2c_data));
2531                 }
2532         }
2533         return 0;
2534 }
2535
2536 static inline void load_first_dma_descriptor(struct comedi_device *dev,
2537                                              unsigned int dma_channel,
2538                                              unsigned int descriptor_bits)
2539 {
2540         struct pcidas64_private *devpriv = dev->private;
2541
2542         /*
2543          * The transfer size, pci address, and local address registers
2544          * are supposedly unused during chained dma,
2545          * but I have found that left over values from last operation
2546          * occasionally cause problems with transfer of first dma
2547          * block.  Initializing them to zero seems to fix the problem.
2548          */
2549         if (dma_channel) {
2550                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ1);
2551                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR1);
2552                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR1);
2553                 writel(descriptor_bits,
2554                        devpriv->plx9080_iobase + PLX_REG_DMADPR1);
2555         } else {
2556                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMASIZ0);
2557                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2558                 writel(0, devpriv->plx9080_iobase + PLX_REG_DMALADR0);
2559                 writel(descriptor_bits,
2560                        devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2561         }
2562 }
2563
2564 static int ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
2565 {
2566         const struct pcidas64_board *board = dev->board_ptr;
2567         struct pcidas64_private *devpriv = dev->private;
2568         struct comedi_async *async = s->async;
2569         struct comedi_cmd *cmd = &async->cmd;
2570         uint32_t bits;
2571         unsigned int i;
2572         unsigned long flags;
2573         int retval;
2574
2575         disable_ai_pacing(dev);
2576         abort_dma(dev, 1);
2577
2578         retval = setup_channel_queue(dev, cmd);
2579         if (retval < 0)
2580                 return retval;
2581
2582         /*  make sure internal calibration source is turned off */
2583         writew(0, devpriv->main_iobase + CALIBRATION_REG);
2584
2585         set_ai_pacing(dev, cmd);
2586
2587         setup_sample_counters(dev, cmd);
2588
2589         enable_ai_interrupts(dev, cmd);
2590
2591         spin_lock_irqsave(&dev->spinlock, flags);
2592         /* set mode, allow conversions through software gate */
2593         devpriv->adc_control1_bits |= ADC_SW_GATE_BIT;
2594         devpriv->adc_control1_bits &= ~ADC_DITHER_BIT;
2595         if (board->layout != LAYOUT_4020) {
2596                 devpriv->adc_control1_bits &= ~ADC_MODE_MASK;
2597                 if (cmd->convert_src == TRIG_EXT)
2598                         /*  good old mode 13 */
2599                         devpriv->adc_control1_bits |= adc_mode_bits(13);
2600                 else
2601                         /*  mode 8.  What else could you need? */
2602                         devpriv->adc_control1_bits |= adc_mode_bits(8);
2603         } else {
2604                 devpriv->adc_control1_bits &= ~CHANNEL_MODE_4020_MASK;
2605                 if (cmd->chanlist_len == 4)
2606                         devpriv->adc_control1_bits |= FOUR_CHANNEL_4020_BITS;
2607                 else if (cmd->chanlist_len == 2)
2608                         devpriv->adc_control1_bits |= TWO_CHANNEL_4020_BITS;
2609                 devpriv->adc_control1_bits &= ~ADC_LO_CHANNEL_4020_MASK;
2610                 devpriv->adc_control1_bits |=
2611                         adc_lo_chan_4020_bits(CR_CHAN(cmd->chanlist[0]));
2612                 devpriv->adc_control1_bits &= ~ADC_HI_CHANNEL_4020_MASK;
2613                 devpriv->adc_control1_bits |=
2614                         adc_hi_chan_4020_bits(CR_CHAN(cmd->chanlist
2615                                                       [cmd->chanlist_len - 1]));
2616         }
2617         writew(devpriv->adc_control1_bits,
2618                devpriv->main_iobase + ADC_CONTROL1_REG);
2619         spin_unlock_irqrestore(&dev->spinlock, flags);
2620
2621         /*  clear adc buffer */
2622         writew(0, devpriv->main_iobase + ADC_BUFFER_CLEAR_REG);
2623
2624         if ((cmd->flags & CMDF_WAKE_EOS) == 0 ||
2625             board->layout == LAYOUT_4020) {
2626                 devpriv->ai_dma_index = 0;
2627
2628                 /*  set dma transfer size */
2629                 for (i = 0; i < ai_dma_ring_count(board); i++)
2630                         devpriv->ai_dma_desc[i].transfer_size =
2631                                 cpu_to_le32(dma_transfer_size(dev) *
2632                                             sizeof(uint16_t));
2633
2634                 /*  give location of first dma descriptor */
2635                 load_first_dma_descriptor(dev, 1,
2636                                           devpriv->ai_dma_desc_bus_addr |
2637                                           PLX_DMADPR_DESCPCI |
2638                                           PLX_DMADPR_TCINTR |
2639                                           PLX_DMADPR_XFERL2P);
2640
2641                 dma_start_sync(dev, 1);
2642         }
2643
2644         if (board->layout == LAYOUT_4020) {
2645                 /* set source for external triggers */
2646                 bits = 0;
2647                 if (cmd->start_src == TRIG_EXT && CR_CHAN(cmd->start_arg))
2648                         bits |= EXT_START_TRIG_BNC_BIT;
2649                 if (cmd->stop_src == TRIG_EXT && CR_CHAN(cmd->stop_arg))
2650                         bits |= EXT_STOP_TRIG_BNC_BIT;
2651                 writew(bits, devpriv->main_iobase + DAQ_ATRIG_LOW_4020_REG);
2652         }
2653
2654         spin_lock_irqsave(&dev->spinlock, flags);
2655
2656         /* enable pacing, triggering, etc */
2657         bits = ADC_ENABLE_BIT | ADC_SOFT_GATE_BITS | ADC_GATE_LEVEL_BIT;
2658         if (cmd->flags & CMDF_WAKE_EOS)
2659                 bits |= ADC_DMA_DISABLE_BIT;
2660         /*  set start trigger */
2661         if (cmd->start_src == TRIG_EXT) {
2662                 bits |= ADC_START_TRIG_EXT_BITS;
2663                 if (cmd->start_arg & CR_INVERT)
2664                         bits |= ADC_START_TRIG_FALLING_BIT;
2665         } else if (cmd->start_src == TRIG_NOW) {
2666                 bits |= ADC_START_TRIG_SOFT_BITS;
2667         }
2668         if (use_hw_sample_counter(cmd))
2669                 bits |= ADC_SAMPLE_COUNTER_EN_BIT;
2670         writew(bits, devpriv->main_iobase + ADC_CONTROL0_REG);
2671
2672         devpriv->ai_cmd_running = 1;
2673
2674         spin_unlock_irqrestore(&dev->spinlock, flags);
2675
2676         /*  start acquisition */
2677         if (cmd->start_src == TRIG_NOW)
2678                 writew(0, devpriv->main_iobase + ADC_START_REG);
2679
2680         return 0;
2681 }
2682
2683 /* read num_samples from 16 bit wide ai fifo */
2684 static void pio_drain_ai_fifo_16(struct comedi_device *dev)
2685 {
2686         struct pcidas64_private *devpriv = dev->private;
2687         struct comedi_subdevice *s = dev->read_subdev;
2688         unsigned int i;
2689         uint16_t prepost_bits;
2690         int read_segment, read_index, write_segment, write_index;
2691         int num_samples;
2692
2693         do {
2694                 /*  get least significant 15 bits */
2695                 read_index = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2696                              0x7fff;
2697                 write_index = readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) &
2698                               0x7fff;
2699                 /*
2700                  * Get most significant bits (grey code).
2701                  * Different boards use different code so use a scheme
2702                  * that doesn't depend on encoding.  This read must
2703                  * occur after reading least significant 15 bits to avoid race
2704                  * with fifo switching to next segment.
2705                  */
2706                 prepost_bits = readw(devpriv->main_iobase + PREPOST_REG);
2707
2708                 /*
2709                  * if read and write pointers are not on the same fifo segment,
2710                  * read to the end of the read segment
2711                  */
2712                 read_segment = adc_upper_read_ptr_code(prepost_bits);
2713                 write_segment = adc_upper_write_ptr_code(prepost_bits);
2714
2715                 if (read_segment != write_segment)
2716                         num_samples =
2717                                 devpriv->ai_fifo_segment_length - read_index;
2718                 else
2719                         num_samples = write_index - read_index;
2720                 if (num_samples < 0) {
2721                         dev_err(dev->class_dev,
2722                                 "cb_pcidas64: bug! num_samples < 0\n");
2723                         break;
2724                 }
2725
2726                 num_samples = comedi_nsamples_left(s, num_samples);
2727                 if (num_samples == 0)
2728                         break;
2729
2730                 for (i = 0; i < num_samples; i++) {
2731                         unsigned short val;
2732
2733                         val = readw(devpriv->main_iobase + ADC_FIFO_REG);
2734                         comedi_buf_write_samples(s, &val, 1);
2735                 }
2736
2737         } while (read_segment != write_segment);
2738 }
2739
2740 /*
2741  * Read from 32 bit wide ai fifo of 4020 - deal with insane grey coding of
2742  * pointers.  The pci-4020 hardware only supports dma transfers (it only
2743  * supports the use of pio for draining the last remaining points from the
2744  * fifo when a data acquisition operation has completed).
2745  */
2746 static void pio_drain_ai_fifo_32(struct comedi_device *dev)
2747 {
2748         struct pcidas64_private *devpriv = dev->private;
2749         struct comedi_subdevice *s = dev->read_subdev;
2750         unsigned int nsamples;
2751         unsigned int i;
2752         uint32_t fifo_data;
2753         int write_code =
2754                 readw(devpriv->main_iobase + ADC_WRITE_PNTR_REG) & 0x7fff;
2755         int read_code =
2756                 readw(devpriv->main_iobase + ADC_READ_PNTR_REG) & 0x7fff;
2757
2758         nsamples = comedi_nsamples_left(s, 100000);
2759         for (i = 0; read_code != write_code && i < nsamples;) {
2760                 unsigned short val;
2761
2762                 fifo_data = readl(dev->mmio + ADC_FIFO_REG);
2763                 val = fifo_data & 0xffff;
2764                 comedi_buf_write_samples(s, &val, 1);
2765                 i++;
2766                 if (i < nsamples) {
2767                         val = (fifo_data >> 16) & 0xffff;
2768                         comedi_buf_write_samples(s, &val, 1);
2769                         i++;
2770                 }
2771                 read_code = readw(devpriv->main_iobase + ADC_READ_PNTR_REG) &
2772                             0x7fff;
2773         }
2774 }
2775
2776 /* empty fifo */
2777 static void pio_drain_ai_fifo(struct comedi_device *dev)
2778 {
2779         const struct pcidas64_board *board = dev->board_ptr;
2780
2781         if (board->layout == LAYOUT_4020)
2782                 pio_drain_ai_fifo_32(dev);
2783         else
2784                 pio_drain_ai_fifo_16(dev);
2785 }
2786
2787 static void drain_dma_buffers(struct comedi_device *dev, unsigned int channel)
2788 {
2789         const struct pcidas64_board *board = dev->board_ptr;
2790         struct pcidas64_private *devpriv = dev->private;
2791         struct comedi_subdevice *s = dev->read_subdev;
2792         uint32_t next_transfer_addr;
2793         int j;
2794         int num_samples = 0;
2795         void __iomem *pci_addr_reg;
2796
2797         pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR(channel);
2798
2799         /*  loop until we have read all the full buffers */
2800         for (j = 0, next_transfer_addr = readl(pci_addr_reg);
2801              (next_transfer_addr <
2802               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] ||
2803               next_transfer_addr >=
2804               devpriv->ai_buffer_bus_addr[devpriv->ai_dma_index] +
2805               DMA_BUFFER_SIZE) && j < ai_dma_ring_count(board); j++) {
2806                 /*  transfer data from dma buffer to comedi buffer */
2807                 num_samples = comedi_nsamples_left(s, dma_transfer_size(dev));
2808                 comedi_buf_write_samples(s,
2809                                 devpriv->ai_buffer[devpriv->ai_dma_index],
2810                                 num_samples);
2811                 devpriv->ai_dma_index = (devpriv->ai_dma_index + 1) %
2812                                         ai_dma_ring_count(board);
2813         }
2814         /*
2815          * XXX check for dma ring buffer overrun
2816          * (use end-of-chain bit to mark last unused buffer)
2817          */
2818 }
2819
2820 static void handle_ai_interrupt(struct comedi_device *dev,
2821                                 unsigned short status,
2822                                 unsigned int plx_status)
2823 {
2824         const struct pcidas64_board *board = dev->board_ptr;
2825         struct pcidas64_private *devpriv = dev->private;
2826         struct comedi_subdevice *s = dev->read_subdev;
2827         struct comedi_async *async = s->async;
2828         struct comedi_cmd *cmd = &async->cmd;
2829         uint8_t dma1_status;
2830         unsigned long flags;
2831
2832         /*  check for fifo overrun */
2833         if (status & ADC_OVERRUN_BIT) {
2834                 dev_err(dev->class_dev, "fifo overrun\n");
2835                 async->events |= COMEDI_CB_ERROR;
2836         }
2837         /*  spin lock makes sure no one else changes plx dma control reg */
2838         spin_lock_irqsave(&dev->spinlock, flags);
2839         dma1_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2840         if (plx_status & PLX_INTCSR_DMA1IA) {   /*  dma chan 1 interrupt */
2841                 writeb((dma1_status & PLX_DMACSR_ENABLE) | PLX_DMACSR_CLEARINTR,
2842                        devpriv->plx9080_iobase + PLX_REG_DMACSR1);
2843
2844                 if (dma1_status & PLX_DMACSR_ENABLE)
2845                         drain_dma_buffers(dev, 1);
2846         }
2847         spin_unlock_irqrestore(&dev->spinlock, flags);
2848
2849         /*  drain fifo with pio */
2850         if ((status & ADC_DONE_BIT) ||
2851             ((cmd->flags & CMDF_WAKE_EOS) &&
2852              (status & ADC_INTR_PENDING_BIT) &&
2853              (board->layout != LAYOUT_4020))) {
2854                 spin_lock_irqsave(&dev->spinlock, flags);
2855                 if (devpriv->ai_cmd_running) {
2856                         spin_unlock_irqrestore(&dev->spinlock, flags);
2857                         pio_drain_ai_fifo(dev);
2858                 } else {
2859                         spin_unlock_irqrestore(&dev->spinlock, flags);
2860                 }
2861         }
2862         /*  if we are have all the data, then quit */
2863         if ((cmd->stop_src == TRIG_COUNT &&
2864              async->scans_done >= cmd->stop_arg) ||
2865             (cmd->stop_src == TRIG_EXT && (status & ADC_STOP_BIT)))
2866                 async->events |= COMEDI_CB_EOA;
2867
2868         comedi_handle_events(dev, s);
2869 }
2870
2871 static inline unsigned int prev_ao_dma_index(struct comedi_device *dev)
2872 {
2873         struct pcidas64_private *devpriv = dev->private;
2874         unsigned int buffer_index;
2875
2876         if (devpriv->ao_dma_index == 0)
2877                 buffer_index = AO_DMA_RING_COUNT - 1;
2878         else
2879                 buffer_index = devpriv->ao_dma_index - 1;
2880         return buffer_index;
2881 }
2882
2883 static int last_ao_dma_load_completed(struct comedi_device *dev)
2884 {
2885         struct pcidas64_private *devpriv = dev->private;
2886         unsigned int buffer_index;
2887         unsigned int transfer_address;
2888         unsigned short dma_status;
2889
2890         buffer_index = prev_ao_dma_index(dev);
2891         dma_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
2892         if ((dma_status & PLX_DMACSR_DONE) == 0)
2893                 return 0;
2894
2895         transfer_address =
2896                 readl(devpriv->plx9080_iobase + PLX_REG_DMAPADR0);
2897         if (transfer_address != devpriv->ao_buffer_bus_addr[buffer_index])
2898                 return 0;
2899
2900         return 1;
2901 }
2902
2903 static inline int ao_dma_needs_restart(struct comedi_device *dev,
2904                                        unsigned short dma_status)
2905 {
2906         if ((dma_status & PLX_DMACSR_DONE) == 0 ||
2907             (dma_status & PLX_DMACSR_ENABLE) == 0)
2908                 return 0;
2909         if (last_ao_dma_load_completed(dev))
2910                 return 0;
2911
2912         return 1;
2913 }
2914
2915 static void restart_ao_dma(struct comedi_device *dev)
2916 {
2917         struct pcidas64_private *devpriv = dev->private;
2918         unsigned int dma_desc_bits;
2919
2920         dma_desc_bits = readl(devpriv->plx9080_iobase + PLX_REG_DMADPR0);
2921         dma_desc_bits &= ~PLX_DMADPR_CHAINEND;
2922         load_first_dma_descriptor(dev, 0, dma_desc_bits);
2923
2924         dma_start_sync(dev, 0);
2925 }
2926
2927 static unsigned int cb_pcidas64_ao_fill_buffer(struct comedi_device *dev,
2928                                                struct comedi_subdevice *s,
2929                                                unsigned short *dest,
2930                                                unsigned int max_bytes)
2931 {
2932         unsigned int nsamples = comedi_bytes_to_samples(s, max_bytes);
2933         unsigned int actual_bytes;
2934
2935         nsamples = comedi_nsamples_left(s, nsamples);
2936         actual_bytes = comedi_buf_read_samples(s, dest, nsamples);
2937
2938         return comedi_bytes_to_samples(s, actual_bytes);
2939 }
2940
2941 static unsigned int load_ao_dma_buffer(struct comedi_device *dev,
2942                                        const struct comedi_cmd *cmd)
2943 {
2944         struct pcidas64_private *devpriv = dev->private;
2945         struct comedi_subdevice *s = dev->write_subdev;
2946         unsigned int buffer_index = devpriv->ao_dma_index;
2947         unsigned int prev_buffer_index = prev_ao_dma_index(dev);
2948         unsigned int nsamples;
2949         unsigned int nbytes;
2950         unsigned int next_bits;
2951
2952         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
2953                                               devpriv->ao_buffer[buffer_index],
2954                                               DMA_BUFFER_SIZE);
2955         if (nsamples == 0)
2956                 return 0;
2957
2958         nbytes = comedi_samples_to_bytes(s, nsamples);
2959         devpriv->ao_dma_desc[buffer_index].transfer_size = cpu_to_le32(nbytes);
2960         /* set end of chain bit so we catch underruns */
2961         next_bits = le32_to_cpu(devpriv->ao_dma_desc[buffer_index].next);
2962         next_bits |= PLX_DMADPR_CHAINEND;
2963         devpriv->ao_dma_desc[buffer_index].next = cpu_to_le32(next_bits);
2964         /*
2965          * clear end of chain bit on previous buffer now that we have set it
2966          * for the last buffer
2967          */
2968         next_bits = le32_to_cpu(devpriv->ao_dma_desc[prev_buffer_index].next);
2969         next_bits &= ~PLX_DMADPR_CHAINEND;
2970         devpriv->ao_dma_desc[prev_buffer_index].next = cpu_to_le32(next_bits);
2971
2972         devpriv->ao_dma_index = (buffer_index + 1) % AO_DMA_RING_COUNT;
2973
2974         return nbytes;
2975 }
2976
2977 static void load_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
2978 {
2979         struct pcidas64_private *devpriv = dev->private;
2980         unsigned int num_bytes;
2981         unsigned int next_transfer_addr;
2982         void __iomem *pci_addr_reg = devpriv->plx9080_iobase + PLX_REG_DMAPADR0;
2983         unsigned int buffer_index;
2984
2985         do {
2986                 buffer_index = devpriv->ao_dma_index;
2987                 /* don't overwrite data that hasn't been transferred yet */
2988                 next_transfer_addr = readl(pci_addr_reg);
2989                 if (next_transfer_addr >=
2990                     devpriv->ao_buffer_bus_addr[buffer_index] &&
2991                     next_transfer_addr <
2992                     devpriv->ao_buffer_bus_addr[buffer_index] +
2993                     DMA_BUFFER_SIZE)
2994                         return;
2995                 num_bytes = load_ao_dma_buffer(dev, cmd);
2996         } while (num_bytes >= DMA_BUFFER_SIZE);
2997 }
2998
2999 static void handle_ao_interrupt(struct comedi_device *dev,
3000                                 unsigned short status, unsigned int plx_status)
3001 {
3002         struct pcidas64_private *devpriv = dev->private;
3003         struct comedi_subdevice *s = dev->write_subdev;
3004         struct comedi_async *async;
3005         struct comedi_cmd *cmd;
3006         uint8_t dma0_status;
3007         unsigned long flags;
3008
3009         /* board might not support ao, in which case write_subdev is NULL */
3010         if (!s)
3011                 return;
3012         async = s->async;
3013         cmd = &async->cmd;
3014
3015         /*  spin lock makes sure no one else changes plx dma control reg */
3016         spin_lock_irqsave(&dev->spinlock, flags);
3017         dma0_status = readb(devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3018         if (plx_status & PLX_INTCSR_DMA0IA) {   /*  dma chan 0 interrupt */
3019                 if ((dma0_status & PLX_DMACSR_ENABLE) &&
3020                     !(dma0_status & PLX_DMACSR_DONE)) {
3021                         writeb(PLX_DMACSR_ENABLE | PLX_DMACSR_CLEARINTR,
3022                                devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3023                 } else {
3024                         writeb(PLX_DMACSR_CLEARINTR,
3025                                devpriv->plx9080_iobase + PLX_REG_DMACSR0);
3026                 }
3027                 spin_unlock_irqrestore(&dev->spinlock, flags);
3028                 if (dma0_status & PLX_DMACSR_ENABLE) {
3029                         load_ao_dma(dev, cmd);
3030                         /* try to recover from dma end-of-chain event */
3031                         if (ao_dma_needs_restart(dev, dma0_status))
3032                                 restart_ao_dma(dev);
3033                 }
3034         } else {
3035                 spin_unlock_irqrestore(&dev->spinlock, flags);
3036         }
3037
3038         if ((status & DAC_DONE_BIT)) {
3039                 if ((cmd->stop_src == TRIG_COUNT &&
3040                      async->scans_done >= cmd->stop_arg) ||
3041                     last_ao_dma_load_completed(dev))
3042                         async->events |= COMEDI_CB_EOA;
3043                 else
3044                         async->events |= COMEDI_CB_ERROR;
3045         }
3046         comedi_handle_events(dev, s);
3047 }
3048
3049 static irqreturn_t handle_interrupt(int irq, void *d)
3050 {
3051         struct comedi_device *dev = d;
3052         struct pcidas64_private *devpriv = dev->private;
3053         unsigned short status;
3054         uint32_t plx_status;
3055         uint32_t plx_bits;
3056
3057         plx_status = readl(devpriv->plx9080_iobase + PLX_REG_INTCSR);
3058         status = readw(devpriv->main_iobase + HW_STATUS_REG);
3059
3060         /*
3061          * an interrupt before all the postconfig stuff gets done could
3062          * cause a NULL dereference if we continue through the
3063          * interrupt handler
3064          */
3065         if (!dev->attached)
3066                 return IRQ_HANDLED;
3067
3068         handle_ai_interrupt(dev, status, plx_status);
3069         handle_ao_interrupt(dev, status, plx_status);
3070
3071         /* clear possible plx9080 interrupt sources */
3072         if (plx_status & PLX_INTCSR_LDBIA) {
3073                 /* clear local doorbell interrupt */
3074                 plx_bits = readl(devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3075                 writel(plx_bits, devpriv->plx9080_iobase + PLX_REG_L2PDBELL);
3076         }
3077
3078         return IRQ_HANDLED;
3079 }
3080
3081 static int ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3082 {
3083         struct pcidas64_private *devpriv = dev->private;
3084         unsigned long flags;
3085
3086         spin_lock_irqsave(&dev->spinlock, flags);
3087         if (devpriv->ai_cmd_running == 0) {
3088                 spin_unlock_irqrestore(&dev->spinlock, flags);
3089                 return 0;
3090         }
3091         devpriv->ai_cmd_running = 0;
3092         spin_unlock_irqrestore(&dev->spinlock, flags);
3093
3094         disable_ai_pacing(dev);
3095
3096         abort_dma(dev, 1);
3097
3098         return 0;
3099 }
3100
3101 static int ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
3102                     struct comedi_insn *insn, unsigned int *data)
3103 {
3104         const struct pcidas64_board *board = dev->board_ptr;
3105         struct pcidas64_private *devpriv = dev->private;
3106         int chan = CR_CHAN(insn->chanspec);
3107         int range = CR_RANGE(insn->chanspec);
3108
3109         /*  do some initializing */
3110         writew(0, devpriv->main_iobase + DAC_CONTROL0_REG);
3111
3112         /*  set range */
3113         set_dac_range_bits(dev, &devpriv->dac_control1_bits, chan, range);
3114         writew(devpriv->dac_control1_bits,
3115                devpriv->main_iobase + DAC_CONTROL1_REG);
3116
3117         /*  write to channel */
3118         if (board->layout == LAYOUT_4020) {
3119                 writew(data[0] & 0xff,
3120                        devpriv->main_iobase + dac_lsb_4020_reg(chan));
3121                 writew((data[0] >> 8) & 0xf,
3122                        devpriv->main_iobase + dac_msb_4020_reg(chan));
3123         } else {
3124                 writew(data[0], devpriv->main_iobase + dac_convert_reg(chan));
3125         }
3126
3127         /*  remember output value */
3128         s->readback[chan] = data[0];
3129
3130         return 1;
3131 }
3132
3133 static void set_dac_control0_reg(struct comedi_device *dev,
3134                                  const struct comedi_cmd *cmd)
3135 {
3136         struct pcidas64_private *devpriv = dev->private;
3137         unsigned int bits = DAC_ENABLE_BIT | WAVEFORM_GATE_LEVEL_BIT |
3138                             WAVEFORM_GATE_ENABLE_BIT | WAVEFORM_GATE_SELECT_BIT;
3139
3140         if (cmd->start_src == TRIG_EXT) {
3141                 bits |= WAVEFORM_TRIG_EXT_BITS;
3142                 if (cmd->start_arg & CR_INVERT)
3143                         bits |= WAVEFORM_TRIG_FALLING_BIT;
3144         } else {
3145                 bits |= WAVEFORM_TRIG_SOFT_BITS;
3146         }
3147         if (cmd->scan_begin_src == TRIG_EXT) {
3148                 bits |= DAC_EXT_UPDATE_ENABLE_BIT;
3149                 if (cmd->scan_begin_arg & CR_INVERT)
3150                         bits |= DAC_EXT_UPDATE_FALLING_BIT;
3151         }
3152         writew(bits, devpriv->main_iobase + DAC_CONTROL0_REG);
3153 }
3154
3155 static void set_dac_control1_reg(struct comedi_device *dev,
3156                                  const struct comedi_cmd *cmd)
3157 {
3158         struct pcidas64_private *devpriv = dev->private;
3159         int i;
3160
3161         for (i = 0; i < cmd->chanlist_len; i++) {
3162                 int channel, range;
3163
3164                 channel = CR_CHAN(cmd->chanlist[i]);
3165                 range = CR_RANGE(cmd->chanlist[i]);
3166                 set_dac_range_bits(dev, &devpriv->dac_control1_bits, channel,
3167                                    range);
3168         }
3169         devpriv->dac_control1_bits |= DAC_SW_GATE_BIT;
3170         writew(devpriv->dac_control1_bits,
3171                devpriv->main_iobase + DAC_CONTROL1_REG);
3172 }
3173
3174 static void set_dac_select_reg(struct comedi_device *dev,
3175                                const struct comedi_cmd *cmd)
3176 {
3177         struct pcidas64_private *devpriv = dev->private;
3178         uint16_t bits;
3179         unsigned int first_channel, last_channel;
3180
3181         first_channel = CR_CHAN(cmd->chanlist[0]);
3182         last_channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
3183         if (last_channel < first_channel)
3184                 dev_err(dev->class_dev,
3185                         "bug! last ao channel < first ao channel\n");
3186
3187         bits = (first_channel & 0x7) | (last_channel & 0x7) << 3;
3188
3189         writew(bits, devpriv->main_iobase + DAC_SELECT_REG);
3190 }
3191
3192 static unsigned int get_ao_divisor(unsigned int ns, unsigned int flags)
3193 {
3194         return get_divisor(ns, flags) - 2;
3195 }
3196
3197 static void set_dac_interval_regs(struct comedi_device *dev,
3198                                   const struct comedi_cmd *cmd)
3199 {
3200         struct pcidas64_private *devpriv = dev->private;
3201         unsigned int divisor;
3202
3203         if (cmd->scan_begin_src != TRIG_TIMER)
3204                 return;
3205
3206         divisor = get_ao_divisor(cmd->scan_begin_arg, cmd->flags);
3207         if (divisor > max_counter_value) {
3208                 dev_err(dev->class_dev, "bug! ao divisor too big\n");
3209                 divisor = max_counter_value;
3210         }
3211         writew(divisor & 0xffff,
3212                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_LOWER_REG);
3213         writew((divisor >> 16) & 0xff,
3214                devpriv->main_iobase + DAC_SAMPLE_INTERVAL_UPPER_REG);
3215 }
3216
3217 static int prep_ao_dma(struct comedi_device *dev, const struct comedi_cmd *cmd)
3218 {
3219         struct pcidas64_private *devpriv = dev->private;
3220         struct comedi_subdevice *s = dev->write_subdev;
3221         unsigned int nsamples;
3222         unsigned int nbytes;
3223         int i;
3224
3225         /*
3226          * clear queue pointer too, since external queue has
3227          * weird interactions with ao fifo
3228          */
3229         writew(0, devpriv->main_iobase + ADC_QUEUE_CLEAR_REG);
3230         writew(0, devpriv->main_iobase + DAC_BUFFER_CLEAR_REG);
3231
3232         nsamples = cb_pcidas64_ao_fill_buffer(dev, s,
3233                                               devpriv->ao_bounce_buffer,
3234                                               DAC_FIFO_SIZE);
3235         if (nsamples == 0)
3236                 return -1;
3237
3238         for (i = 0; i < nsamples; i++) {
3239                 writew(devpriv->ao_bounce_buffer[i],
3240                        devpriv->main_iobase + DAC_FIFO_REG);
3241         }
3242
3243         if (cmd->stop_src == TRIG_COUNT &&
3244             s->async->scans_done >= cmd->stop_arg)
3245                 return 0;
3246
3247         nbytes = load_ao_dma_buffer(dev, cmd);
3248         if (nbytes == 0)
3249                 return -1;
3250         load_ao_dma(dev, cmd);
3251
3252         dma_start_sync(dev, 0);
3253
3254         return 0;
3255 }
3256
3257 static inline int external_ai_queue_in_use(struct comedi_device *dev,
3258                                            struct comedi_subdevice *s,
3259                                            struct comedi_cmd *cmd)
3260 {
3261         const struct pcidas64_board *board = dev->board_ptr;
3262
3263         if (s->busy)
3264                 return 0;
3265         if (board->layout == LAYOUT_4020)
3266                 return 0;
3267         else if (use_internal_queue_6xxx(cmd))
3268                 return 0;
3269         return 1;
3270 }
3271
3272 static int ao_inttrig(struct comedi_device *dev, struct comedi_subdevice *s,
3273                       unsigned int trig_num)
3274 {
3275         struct pcidas64_private *devpriv = dev->private;
3276         struct comedi_cmd *cmd = &s->async->cmd;
3277         int retval;
3278
3279         if (trig_num != cmd->start_arg)
3280                 return -EINVAL;
3281
3282         retval = prep_ao_dma(dev, cmd);
3283         if (retval < 0)
3284                 return -EPIPE;
3285
3286         set_dac_control0_reg(dev, cmd);
3287
3288         if (cmd->start_src == TRIG_INT)
3289                 writew(0, devpriv->main_iobase + DAC_START_REG);
3290
3291         s->async->inttrig = NULL;
3292
3293         return 0;
3294 }
3295
3296 static int ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3297 {
3298         struct pcidas64_private *devpriv = dev->private;
3299         struct comedi_cmd *cmd = &s->async->cmd;
3300
3301         if (external_ai_queue_in_use(dev, s, cmd)) {
3302                 warn_external_queue(dev);
3303                 return -EBUSY;
3304         }
3305         /* disable analog output system during setup */
3306         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3307
3308         devpriv->ao_dma_index = 0;
3309
3310         set_dac_select_reg(dev, cmd);
3311         set_dac_interval_regs(dev, cmd);
3312         load_first_dma_descriptor(dev, 0, devpriv->ao_dma_desc_bus_addr |
3313                                   PLX_DMADPR_DESCPCI | PLX_DMADPR_TCINTR);
3314
3315         set_dac_control1_reg(dev, cmd);
3316         s->async->inttrig = ao_inttrig;
3317
3318         return 0;
3319 }
3320
3321 static int cb_pcidas64_ao_check_chanlist(struct comedi_device *dev,
3322                                          struct comedi_subdevice *s,
3323                                          struct comedi_cmd *cmd)
3324 {
3325         unsigned int chan0 = CR_CHAN(cmd->chanlist[0]);
3326         int i;
3327
3328         for (i = 1; i < cmd->chanlist_len; i++) {
3329                 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
3330
3331                 if (chan != (chan0 + i)) {
3332                         dev_dbg(dev->class_dev,
3333                                 "chanlist must use consecutive channels\n");
3334                         return -EINVAL;
3335                 }
3336         }
3337
3338         return 0;
3339 }
3340
3341 static int ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
3342                       struct comedi_cmd *cmd)
3343 {
3344         const struct pcidas64_board *board = dev->board_ptr;
3345         int err = 0;
3346         unsigned int tmp_arg;
3347
3348         /* Step 1 : check if triggers are trivially valid */
3349
3350         err |= comedi_check_trigger_src(&cmd->start_src, TRIG_INT | TRIG_EXT);
3351         err |= comedi_check_trigger_src(&cmd->scan_begin_src,
3352                                         TRIG_TIMER | TRIG_EXT);
3353         err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
3354         err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
3355         err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE);
3356
3357         if (err)
3358                 return 1;
3359
3360         /* Step 2a : make sure trigger sources are unique */
3361
3362         err |= comedi_check_trigger_is_unique(cmd->start_src);
3363         err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
3364
3365         /* Step 2b : and mutually compatible */
3366
3367         if (cmd->convert_src == TRIG_EXT && cmd->scan_begin_src == TRIG_TIMER)
3368                 err |= -EINVAL;
3369         if (cmd->stop_src != TRIG_COUNT &&
3370             cmd->stop_src != TRIG_NONE && cmd->stop_src != TRIG_EXT)
3371                 err |= -EINVAL;
3372
3373         if (err)
3374                 return 2;
3375
3376         /* Step 3: check if arguments are trivially valid */
3377
3378         err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
3379
3380         if (cmd->scan_begin_src == TRIG_TIMER) {
3381                 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
3382                                                     board->ao_scan_speed);
3383                 if (get_ao_divisor(cmd->scan_begin_arg, cmd->flags) >
3384                     max_counter_value) {
3385                         cmd->scan_begin_arg = (max_counter_value + 2) *
3386                                               TIMER_BASE;
3387                         err |= -EINVAL;
3388                 }
3389         }
3390
3391         err |= comedi_check_trigger_arg_min(&cmd->chanlist_len, 1);
3392         err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
3393                                            cmd->chanlist_len);
3394
3395         if (err)
3396                 return 3;
3397
3398         /* step 4: fix up any arguments */
3399
3400         if (cmd->scan_begin_src == TRIG_TIMER) {
3401                 tmp_arg = cmd->scan_begin_arg;
3402                 cmd->scan_begin_arg = get_divisor(cmd->scan_begin_arg,
3403                                                   cmd->flags) * TIMER_BASE;
3404                 if (tmp_arg != cmd->scan_begin_arg)
3405                         err++;
3406         }
3407
3408         if (err)
3409                 return 4;
3410
3411         /* Step 5: check channel list if it exists */
3412         if (cmd->chanlist && cmd->chanlist_len > 0)
3413                 err |= cb_pcidas64_ao_check_chanlist(dev, s, cmd);
3414
3415         if (err)
3416                 return 5;
3417
3418         return 0;
3419 }
3420
3421 static int ao_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
3422 {
3423         struct pcidas64_private *devpriv = dev->private;
3424
3425         writew(0x0, devpriv->main_iobase + DAC_CONTROL0_REG);
3426         abort_dma(dev, 0);
3427         return 0;
3428 }
3429
3430 static int dio_callback_4020(struct comedi_device *dev,
3431                              int dir, int port, int data, unsigned long iobase)
3432 {
3433         struct pcidas64_private *devpriv = dev->private;
3434
3435         if (dir) {
3436                 writew(data, devpriv->main_iobase + iobase + 2 * port);
3437                 return 0;
3438         }
3439         return readw(devpriv->main_iobase + iobase + 2 * port);
3440 }
3441
3442 static int di_rbits(struct comedi_device *dev, struct comedi_subdevice *s,
3443                     struct comedi_insn *insn, unsigned int *data)
3444 {
3445         unsigned int bits;
3446
3447         bits = readb(dev->mmio + DI_REG);
3448         bits &= 0xf;
3449         data[1] = bits;
3450         data[0] = 0;
3451
3452         return insn->n;
3453 }
3454
3455 static int do_wbits(struct comedi_device *dev,
3456                     struct comedi_subdevice *s,
3457                     struct comedi_insn *insn,
3458                     unsigned int *data)
3459 {
3460         if (comedi_dio_update_state(s, data))
3461                 writeb(s->state, dev->mmio + DO_REG);
3462
3463         data[1] = s->state;
3464
3465         return insn->n;
3466 }
3467
3468 static int dio_60xx_config_insn(struct comedi_device *dev,
3469                                 struct comedi_subdevice *s,
3470                                 struct comedi_insn *insn,
3471                                 unsigned int *data)
3472 {
3473         int ret;
3474
3475         ret = comedi_dio_insn_config(dev, s, insn, data, 0);
3476         if (ret)
3477                 return ret;
3478
3479         writeb(s->io_bits, dev->mmio + DIO_DIRECTION_60XX_REG);
3480
3481         return insn->n;
3482 }
3483
3484 static int dio_60xx_wbits(struct comedi_device *dev,
3485                           struct comedi_subdevice *s,
3486                           struct comedi_insn *insn,
3487                           unsigned int *data)
3488 {
3489         if (comedi_dio_update_state(s, data))
3490                 writeb(s->state, dev->mmio + DIO_DATA_60XX_REG);
3491
3492         data[1] = readb(dev->mmio + DIO_DATA_60XX_REG);
3493
3494         return insn->n;
3495 }
3496
3497 /*
3498  * pci-6025 8800 caldac:
3499  * address 0 == dac channel 0 offset
3500  * address 1 == dac channel 0 gain
3501  * address 2 == dac channel 1 offset
3502  * address 3 == dac channel 1 gain
3503  * address 4 == fine adc offset
3504  * address 5 == coarse adc offset
3505  * address 6 == coarse adc gain
3506  * address 7 == fine adc gain
3507  */
3508 /*
3509  * pci-6402/16 uses all 8 channels for dac:
3510  * address 0 == dac channel 0 fine gain
3511  * address 1 == dac channel 0 coarse gain
3512  * address 2 == dac channel 0 coarse offset
3513  * address 3 == dac channel 1 coarse offset
3514  * address 4 == dac channel 1 fine gain
3515  * address 5 == dac channel 1 coarse gain
3516  * address 6 == dac channel 0 fine offset
3517  * address 7 == dac channel 1 fine offset
3518  */
3519
3520 static int caldac_8800_write(struct comedi_device *dev, unsigned int address,
3521                              uint8_t value)
3522 {
3523         struct pcidas64_private *devpriv = dev->private;
3524         static const int num_caldac_channels = 8;
3525         static const int bitstream_length = 11;
3526         unsigned int bitstream = ((address & 0x7) << 8) | value;
3527         unsigned int bit, register_bits;
3528         static const int caldac_8800_udelay = 1;
3529
3530         if (address >= num_caldac_channels) {
3531                 dev_err(dev->class_dev, "illegal caldac channel\n");
3532                 return -1;
3533         }
3534         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3535                 register_bits = 0;
3536                 if (bitstream & bit)
3537                         register_bits |= SERIAL_DATA_IN_BIT;
3538                 udelay(caldac_8800_udelay);
3539                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3540                 register_bits |= SERIAL_CLOCK_BIT;
3541                 udelay(caldac_8800_udelay);
3542                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3543         }
3544         udelay(caldac_8800_udelay);
3545         writew(SELECT_8800_BIT, devpriv->main_iobase + CALIBRATION_REG);
3546         udelay(caldac_8800_udelay);
3547         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3548         udelay(caldac_8800_udelay);
3549         return 0;
3550 }
3551
3552 /* 4020 caldacs */
3553 static int caldac_i2c_write(struct comedi_device *dev,
3554                             unsigned int caldac_channel, unsigned int value)
3555 {
3556         uint8_t serial_bytes[3];
3557         uint8_t i2c_addr;
3558         enum pointer_bits {
3559                 /*  manual has gain and offset bits switched */
3560                 OFFSET_0_2 = 0x1,
3561                 GAIN_0_2 = 0x2,
3562                 OFFSET_1_3 = 0x4,
3563                 GAIN_1_3 = 0x8,
3564         };
3565         enum data_bits {
3566                 NOT_CLEAR_REGISTERS = 0x20,
3567         };
3568
3569         switch (caldac_channel) {
3570         case 0:         /*  chan 0 offset */
3571                 i2c_addr = CALDAC0_I2C_ADDR;
3572                 serial_bytes[0] = OFFSET_0_2;
3573                 break;
3574         case 1:         /*  chan 1 offset */
3575                 i2c_addr = CALDAC0_I2C_ADDR;
3576                 serial_bytes[0] = OFFSET_1_3;
3577                 break;
3578         case 2:         /*  chan 2 offset */
3579                 i2c_addr = CALDAC1_I2C_ADDR;
3580                 serial_bytes[0] = OFFSET_0_2;
3581                 break;
3582         case 3:         /*  chan 3 offset */
3583                 i2c_addr = CALDAC1_I2C_ADDR;
3584                 serial_bytes[0] = OFFSET_1_3;
3585                 break;
3586         case 4:         /*  chan 0 gain */
3587                 i2c_addr = CALDAC0_I2C_ADDR;
3588                 serial_bytes[0] = GAIN_0_2;
3589                 break;
3590         case 5:         /*  chan 1 gain */
3591                 i2c_addr = CALDAC0_I2C_ADDR;
3592                 serial_bytes[0] = GAIN_1_3;
3593                 break;
3594         case 6:         /*  chan 2 gain */
3595                 i2c_addr = CALDAC1_I2C_ADDR;
3596                 serial_bytes[0] = GAIN_0_2;
3597                 break;
3598         case 7:         /*  chan 3 gain */
3599                 i2c_addr = CALDAC1_I2C_ADDR;
3600                 serial_bytes[0] = GAIN_1_3;
3601                 break;
3602         default:
3603                 dev_err(dev->class_dev, "invalid caldac channel\n");
3604                 return -1;
3605         }
3606         serial_bytes[1] = NOT_CLEAR_REGISTERS | ((value >> 8) & 0xf);
3607         serial_bytes[2] = value & 0xff;
3608         i2c_write(dev, i2c_addr, serial_bytes, 3);
3609         return 0;
3610 }
3611
3612 static void caldac_write(struct comedi_device *dev, unsigned int channel,
3613                          unsigned int value)
3614 {
3615         const struct pcidas64_board *board = dev->board_ptr;
3616
3617         switch (board->layout) {
3618         case LAYOUT_60XX:
3619         case LAYOUT_64XX:
3620                 caldac_8800_write(dev, channel, value);
3621                 break;
3622         case LAYOUT_4020:
3623                 caldac_i2c_write(dev, channel, value);
3624                 break;
3625         default:
3626                 break;
3627         }
3628 }
3629
3630 static int cb_pcidas64_calib_insn_write(struct comedi_device *dev,
3631                                         struct comedi_subdevice *s,
3632                                         struct comedi_insn *insn,
3633                                         unsigned int *data)
3634 {
3635         unsigned int chan = CR_CHAN(insn->chanspec);
3636
3637         /*
3638          * Programming the calib device is slow. Only write the
3639          * last data value if the value has changed.
3640          */
3641         if (insn->n) {
3642                 unsigned int val = data[insn->n - 1];
3643
3644                 if (s->readback[chan] != val) {
3645                         caldac_write(dev, chan, val);
3646                         s->readback[chan] = val;
3647                 }
3648         }
3649
3650         return insn->n;
3651 }
3652
3653 static void ad8402_write(struct comedi_device *dev, unsigned int channel,
3654                          unsigned int value)
3655 {
3656         struct pcidas64_private *devpriv = dev->private;
3657         static const int bitstream_length = 10;
3658         unsigned int bit, register_bits;
3659         unsigned int bitstream = ((channel & 0x3) << 8) | (value & 0xff);
3660         static const int ad8402_udelay = 1;
3661
3662         register_bits = SELECT_8402_64XX_BIT;
3663         udelay(ad8402_udelay);
3664         writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3665
3666         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3667                 if (bitstream & bit)
3668                         register_bits |= SERIAL_DATA_IN_BIT;
3669                 else
3670                         register_bits &= ~SERIAL_DATA_IN_BIT;
3671                 udelay(ad8402_udelay);
3672                 writew(register_bits, devpriv->main_iobase + CALIBRATION_REG);
3673                 udelay(ad8402_udelay);
3674                 writew(register_bits | SERIAL_CLOCK_BIT,
3675                        devpriv->main_iobase + CALIBRATION_REG);
3676         }
3677
3678         udelay(ad8402_udelay);
3679         writew(0, devpriv->main_iobase + CALIBRATION_REG);
3680 }
3681
3682 /* for pci-das6402/16, channel 0 is analog input gain and channel 1 is offset */
3683 static int cb_pcidas64_ad8402_insn_write(struct comedi_device *dev,
3684                                          struct comedi_subdevice *s,
3685                                          struct comedi_insn *insn,
3686                                          unsigned int *data)
3687 {
3688         unsigned int chan = CR_CHAN(insn->chanspec);
3689
3690         /*
3691          * Programming the calib device is slow. Only write the
3692          * last data value if the value has changed.
3693          */
3694         if (insn->n) {
3695                 unsigned int val = data[insn->n - 1];
3696
3697                 if (s->readback[chan] != val) {
3698                         ad8402_write(dev, chan, val);
3699                         s->readback[chan] = val;
3700                 }
3701         }
3702
3703         return insn->n;
3704 }
3705
3706 static uint16_t read_eeprom(struct comedi_device *dev, uint8_t address)
3707 {
3708         struct pcidas64_private *devpriv = dev->private;
3709         static const int bitstream_length = 11;
3710         static const int read_command = 0x6;
3711         unsigned int bitstream = (read_command << 8) | address;
3712         unsigned int bit;
3713         void __iomem * const plx_control_addr =
3714                 devpriv->plx9080_iobase + PLX_REG_CNTRL;
3715         uint16_t value;
3716         static const int value_length = 16;
3717         static const int eeprom_udelay = 1;
3718
3719         udelay(eeprom_udelay);
3720         devpriv->plx_control_bits &= ~PLX_CNTRL_EESK & ~PLX_CNTRL_EECS;
3721         /*  make sure we don't send anything to the i2c bus on 4020 */
3722         devpriv->plx_control_bits |= PLX_CNTRL_USERO;
3723         writel(devpriv->plx_control_bits, plx_control_addr);
3724         /*  activate serial eeprom */
3725         udelay(eeprom_udelay);
3726         devpriv->plx_control_bits |= PLX_CNTRL_EECS;
3727         writel(devpriv->plx_control_bits, plx_control_addr);
3728
3729         /*  write read command and desired memory address */
3730         for (bit = 1 << (bitstream_length - 1); bit; bit >>= 1) {
3731                 /*  set bit to be written */
3732                 udelay(eeprom_udelay);
3733                 if (bitstream & bit)
3734                         devpriv->plx_control_bits |= PLX_CNTRL_EEWB;
3735                 else
3736                         devpriv->plx_control_bits &= ~PLX_CNTRL_EEWB;
3737                 writel(devpriv->plx_control_bits, plx_control_addr);
3738                 /*  clock in bit */
3739                 udelay(eeprom_udelay);
3740                 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3741                 writel(devpriv->plx_control_bits, plx_control_addr);
3742                 udelay(eeprom_udelay);
3743                 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3744                 writel(devpriv->plx_control_bits, plx_control_addr);
3745         }
3746         /*  read back value from eeprom memory location */
3747         value = 0;
3748         for (bit = 1 << (value_length - 1); bit; bit >>= 1) {
3749                 /*  clock out bit */
3750                 udelay(eeprom_udelay);
3751                 devpriv->plx_control_bits |= PLX_CNTRL_EESK;
3752                 writel(devpriv->plx_control_bits, plx_control_addr);
3753                 udelay(eeprom_udelay);
3754                 devpriv->plx_control_bits &= ~PLX_CNTRL_EESK;
3755                 writel(devpriv->plx_control_bits, plx_control_addr);
3756                 udelay(eeprom_udelay);
3757                 if (readl(plx_control_addr) & PLX_CNTRL_EERB)
3758                         value |= bit;
3759         }
3760
3761         /*  deactivate eeprom serial input */
3762         udelay(eeprom_udelay);
3763         devpriv->plx_control_bits &= ~PLX_CNTRL_EECS;
3764         writel(devpriv->plx_control_bits, plx_control_addr);
3765
3766         return value;
3767 }
3768
3769 static int eeprom_read_insn(struct comedi_device *dev,
3770                             struct comedi_subdevice *s,
3771                             struct comedi_insn *insn, unsigned int *data)
3772 {
3773         data[0] = read_eeprom(dev, CR_CHAN(insn->chanspec));
3774
3775         return 1;
3776 }
3777
3778 /*
3779  * Allocate and initialize the subdevice structures.
3780  */
3781 static int setup_subdevices(struct comedi_device *dev)
3782 {
3783         const struct pcidas64_board *board = dev->board_ptr;
3784         struct pcidas64_private *devpriv = dev->private;
3785         struct comedi_subdevice *s;
3786         int i;
3787         int ret;
3788
3789         ret = comedi_alloc_subdevices(dev, 10);
3790         if (ret)
3791                 return ret;
3792
3793         s = &dev->subdevices[0];
3794         /* analog input subdevice */
3795         dev->read_subdev = s;
3796         s->type = COMEDI_SUBD_AI;
3797         s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DITHER | SDF_CMD_READ;
3798         if (board->layout == LAYOUT_60XX)
3799                 s->subdev_flags |= SDF_COMMON | SDF_DIFF;
3800         else if (board->layout == LAYOUT_64XX)
3801                 s->subdev_flags |= SDF_DIFF;
3802         /* XXX Number of inputs in differential mode is ignored */
3803         s->n_chan = board->ai_se_chans;
3804         s->len_chanlist = 0x2000;
3805         s->maxdata = (1 << board->ai_bits) - 1;
3806         s->range_table = board->ai_range_table;
3807         s->insn_read = ai_rinsn;
3808         s->insn_config = ai_config_insn;
3809         s->do_cmd = ai_cmd;
3810         s->do_cmdtest = ai_cmdtest;
3811         s->cancel = ai_cancel;
3812         if (board->layout == LAYOUT_4020) {
3813                 uint8_t data;
3814                 /*
3815                  * set adc to read from inputs
3816                  * (not internal calibration sources)
3817                  */
3818                 devpriv->i2c_cal_range_bits = adc_src_4020_bits(4);
3819                 /*  set channels to +-5 volt input ranges */
3820                 for (i = 0; i < s->n_chan; i++)
3821                         devpriv->i2c_cal_range_bits |= attenuate_bit(i);
3822                 data = devpriv->i2c_cal_range_bits;
3823                 i2c_write(dev, RANGE_CAL_I2C_ADDR, &data, sizeof(data));
3824         }
3825
3826         /* analog output subdevice */
3827         s = &dev->subdevices[1];
3828         if (board->ao_nchan) {
3829                 s->type = COMEDI_SUBD_AO;
3830                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE |
3831                                   SDF_GROUND | SDF_CMD_WRITE;
3832                 s->n_chan = board->ao_nchan;
3833                 s->maxdata = (1 << board->ao_bits) - 1;
3834                 s->range_table = board->ao_range_table;
3835                 s->insn_write = ao_winsn;
3836
3837                 ret = comedi_alloc_subdev_readback(s);
3838                 if (ret)
3839                         return ret;
3840
3841                 if (ao_cmd_is_supported(board)) {
3842                         dev->write_subdev = s;
3843                         s->do_cmdtest = ao_cmdtest;
3844                         s->do_cmd = ao_cmd;
3845                         s->len_chanlist = board->ao_nchan;
3846                         s->cancel = ao_cancel;
3847                 }
3848         } else {
3849                 s->type = COMEDI_SUBD_UNUSED;
3850         }
3851
3852         /*  digital input */
3853         s = &dev->subdevices[2];
3854         if (board->layout == LAYOUT_64XX) {
3855                 s->type = COMEDI_SUBD_DI;
3856                 s->subdev_flags = SDF_READABLE;
3857                 s->n_chan = 4;
3858                 s->maxdata = 1;
3859                 s->range_table = &range_digital;
3860                 s->insn_bits = di_rbits;
3861         } else {
3862                 s->type = COMEDI_SUBD_UNUSED;
3863         }
3864
3865         /*  digital output */
3866         if (board->layout == LAYOUT_64XX) {
3867                 s = &dev->subdevices[3];
3868                 s->type = COMEDI_SUBD_DO;
3869                 s->subdev_flags = SDF_WRITABLE;
3870                 s->n_chan = 4;
3871                 s->maxdata = 1;
3872                 s->range_table = &range_digital;
3873                 s->insn_bits = do_wbits;
3874         } else {
3875                 s->type = COMEDI_SUBD_UNUSED;
3876         }
3877
3878         /* 8255 */
3879         s = &dev->subdevices[4];
3880         if (board->has_8255) {
3881                 if (board->layout == LAYOUT_4020) {
3882                         ret = subdev_8255_init(dev, s, dio_callback_4020,
3883                                                I8255_4020_REG);
3884                 } else {
3885                         ret = subdev_8255_mm_init(dev, s, NULL,
3886                                                   DIO_8255_OFFSET);
3887                 }
3888                 if (ret)
3889                         return ret;
3890         } else {
3891                 s->type = COMEDI_SUBD_UNUSED;
3892         }
3893
3894         /*  8 channel dio for 60xx */
3895         s = &dev->subdevices[5];
3896         if (board->layout == LAYOUT_60XX) {
3897                 s->type = COMEDI_SUBD_DIO;
3898                 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
3899                 s->n_chan = 8;
3900                 s->maxdata = 1;
3901                 s->range_table = &range_digital;
3902                 s->insn_config = dio_60xx_config_insn;
3903                 s->insn_bits = dio_60xx_wbits;
3904         } else {
3905                 s->type = COMEDI_SUBD_UNUSED;
3906         }
3907
3908         /*  caldac */
3909         s = &dev->subdevices[6];
3910         s->type = COMEDI_SUBD_CALIB;
3911         s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3912         s->n_chan = 8;
3913         if (board->layout == LAYOUT_4020)
3914                 s->maxdata = 0xfff;
3915         else
3916                 s->maxdata = 0xff;
3917         s->insn_write = cb_pcidas64_calib_insn_write;
3918
3919         ret = comedi_alloc_subdev_readback(s);
3920         if (ret)
3921                 return ret;
3922
3923         for (i = 0; i < s->n_chan; i++) {
3924                 caldac_write(dev, i, s->maxdata / 2);
3925                 s->readback[i] = s->maxdata / 2;
3926         }
3927
3928         /*  2 channel ad8402 potentiometer */
3929         s = &dev->subdevices[7];
3930         if (board->layout == LAYOUT_64XX) {
3931                 s->type = COMEDI_SUBD_CALIB;
3932                 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
3933                 s->n_chan = 2;
3934                 s->maxdata = 0xff;
3935                 s->insn_write = cb_pcidas64_ad8402_insn_write;
3936
3937                 ret = comedi_alloc_subdev_readback(s);
3938                 if (ret)
3939                         return ret;
3940
3941                 for (i = 0; i < s->n_chan; i++) {
3942                         ad8402_write(dev, i, s->maxdata / 2);
3943                         s->readback[i] = s->maxdata / 2;
3944                 }
3945         } else {
3946                 s->type = COMEDI_SUBD_UNUSED;
3947         }
3948
3949         /* serial EEPROM, if present */
3950         s = &dev->subdevices[8];
3951         if (readl(devpriv->plx9080_iobase + PLX_REG_CNTRL) &
3952             PLX_CNTRL_EEPRESENT) {
3953                 s->type = COMEDI_SUBD_MEMORY;
3954                 s->subdev_flags = SDF_READABLE | SDF_INTERNAL;
3955                 s->n_chan = 128;
3956                 s->maxdata = 0xffff;
3957                 s->insn_read = eeprom_read_insn;
3958         } else {
3959                 s->type = COMEDI_SUBD_UNUSED;
3960         }
3961
3962         /*  user counter subd XXX */
3963         s = &dev->subdevices[9];
3964         s->type = COMEDI_SUBD_UNUSED;
3965
3966         return 0;
3967 }
3968
3969 static int auto_attach(struct comedi_device *dev,
3970                        unsigned long context)
3971 {
3972         struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3973         const struct pcidas64_board *board = NULL;
3974         struct pcidas64_private *devpriv;
3975         uint32_t local_range, local_decode;
3976         int retval;
3977
3978         if (context < ARRAY_SIZE(pcidas64_boards))
3979                 board = &pcidas64_boards[context];
3980         if (!board)
3981                 return -ENODEV;
3982         dev->board_ptr = board;
3983
3984         devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
3985         if (!devpriv)
3986                 return -ENOMEM;
3987
3988         retval = comedi_pci_enable(dev);
3989         if (retval)
3990                 return retval;
3991         pci_set_master(pcidev);
3992
3993         /* Initialize dev->board_name */
3994         dev->board_name = board->name;
3995
3996         devpriv->main_phys_iobase = pci_resource_start(pcidev, 2);
3997         devpriv->dio_counter_phys_iobase = pci_resource_start(pcidev, 3);
3998
3999         devpriv->plx9080_iobase = pci_ioremap_bar(pcidev, 0);
4000         devpriv->main_iobase = pci_ioremap_bar(pcidev, 2);
4001         dev->mmio = pci_ioremap_bar(pcidev, 3);
4002
4003         if (!devpriv->plx9080_iobase || !devpriv->main_iobase || !dev->mmio) {
4004                 dev_warn(dev->class_dev, "failed to remap io memory\n");
4005                 return -ENOMEM;
4006         }
4007
4008         /*  figure out what local addresses are */
4009         local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS0RR) &
4010                       PLX_LASRR_MEM_MASK;
4011         local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS0BA) &
4012                        local_range & PLX_LASBA_MEM_MASK;
4013         devpriv->local0_iobase = ((uint32_t)devpriv->main_phys_iobase &
4014                                   ~local_range) | local_decode;
4015         local_range = readl(devpriv->plx9080_iobase + PLX_REG_LAS1RR) &
4016                       PLX_LASRR_MEM_MASK;
4017         local_decode = readl(devpriv->plx9080_iobase + PLX_REG_LAS1BA) &
4018                        local_range & PLX_LASBA_MEM_MASK;
4019         devpriv->local1_iobase = ((uint32_t)devpriv->dio_counter_phys_iobase &
4020                                   ~local_range) | local_decode;
4021
4022         retval = alloc_and_init_dma_members(dev);
4023         if (retval < 0)
4024                 return retval;
4025
4026         devpriv->hw_revision =
4027                 hw_revision(dev, readw(devpriv->main_iobase + HW_STATUS_REG));
4028         dev_dbg(dev->class_dev, "stc hardware revision %i\n",
4029                 devpriv->hw_revision);
4030         init_plx9080(dev);
4031         init_stc_registers(dev);
4032
4033         retval = request_irq(pcidev->irq, handle_interrupt, IRQF_SHARED,
4034                              dev->board_name, dev);
4035         if (retval) {
4036                 dev_dbg(dev->class_dev, "unable to allocate irq %u\n",
4037                         pcidev->irq);
4038                 return retval;
4039         }
4040         dev->irq = pcidev->irq;
4041         dev_dbg(dev->class_dev, "irq %u\n", dev->irq);
4042
4043         retval = setup_subdevices(dev);
4044         if (retval < 0)
4045                 return retval;
4046
4047         return 0;
4048 }
4049
4050 static void detach(struct comedi_device *dev)
4051 {
4052         struct pcidas64_private *devpriv = dev->private;
4053
4054         if (dev->irq)
4055                 free_irq(dev->irq, dev);
4056         if (devpriv) {
4057                 if (devpriv->plx9080_iobase) {
4058                         disable_plx_interrupts(dev);
4059                         iounmap(devpriv->plx9080_iobase);
4060                 }
4061                 if (devpriv->main_iobase)
4062                         iounmap(devpriv->main_iobase);
4063                 if (dev->mmio)
4064                         iounmap(dev->mmio);
4065         }
4066         comedi_pci_disable(dev);
4067         cb_pcidas64_free_dma(dev);
4068 }
4069
4070 static struct comedi_driver cb_pcidas64_driver = {
4071         .driver_name    = "cb_pcidas64",
4072         .module         = THIS_MODULE,
4073         .auto_attach    = auto_attach,
4074         .detach         = detach,
4075 };
4076
4077 static int cb_pcidas64_pci_probe(struct pci_dev *dev,
4078                                  const struct pci_device_id *id)
4079 {
4080         return comedi_pci_auto_config(dev, &cb_pcidas64_driver,
4081                                       id->driver_data);
4082 }
4083
4084 static const struct pci_device_id cb_pcidas64_pci_table[] = {
4085         { PCI_VDEVICE(CB, 0x001d), BOARD_PCIDAS6402_16 },
4086         { PCI_VDEVICE(CB, 0x001e), BOARD_PCIDAS6402_12 },
4087         { PCI_VDEVICE(CB, 0x0035), BOARD_PCIDAS64_M1_16 },
4088         { PCI_VDEVICE(CB, 0x0036), BOARD_PCIDAS64_M2_16 },
4089         { PCI_VDEVICE(CB, 0x0037), BOARD_PCIDAS64_M3_16 },
4090         { PCI_VDEVICE(CB, 0x0052), BOARD_PCIDAS4020_12 },
4091         { PCI_VDEVICE(CB, 0x005d), BOARD_PCIDAS6023 },
4092         { PCI_VDEVICE(CB, 0x005e), BOARD_PCIDAS6025 },
4093         { PCI_VDEVICE(CB, 0x005f), BOARD_PCIDAS6030 },
4094         { PCI_VDEVICE(CB, 0x0060), BOARD_PCIDAS6031 },
4095         { PCI_VDEVICE(CB, 0x0061), BOARD_PCIDAS6032 },
4096         { PCI_VDEVICE(CB, 0x0062), BOARD_PCIDAS6033 },
4097         { PCI_VDEVICE(CB, 0x0063), BOARD_PCIDAS6034 },
4098         { PCI_VDEVICE(CB, 0x0064), BOARD_PCIDAS6035 },
4099         { PCI_VDEVICE(CB, 0x0065), BOARD_PCIDAS6040 },
4100         { PCI_VDEVICE(CB, 0x0066), BOARD_PCIDAS6052 },
4101         { PCI_VDEVICE(CB, 0x0067), BOARD_PCIDAS6070 },
4102         { PCI_VDEVICE(CB, 0x0068), BOARD_PCIDAS6071 },
4103         { PCI_VDEVICE(CB, 0x006f), BOARD_PCIDAS6036 },
4104         { PCI_VDEVICE(CB, 0x0078), BOARD_PCIDAS6013 },
4105         { PCI_VDEVICE(CB, 0x0079), BOARD_PCIDAS6014 },
4106         { 0 }
4107 };
4108 MODULE_DEVICE_TABLE(pci, cb_pcidas64_pci_table);
4109
4110 static struct pci_driver cb_pcidas64_pci_driver = {
4111         .name           = "cb_pcidas64",
4112         .id_table       = cb_pcidas64_pci_table,
4113         .probe          = cb_pcidas64_pci_probe,
4114         .remove         = comedi_pci_auto_unconfig,
4115 };
4116 module_comedi_pci_driver(cb_pcidas64_driver, cb_pcidas64_pci_driver);
4117
4118 MODULE_AUTHOR("Comedi http://www.comedi.org");
4119 MODULE_DESCRIPTION("Comedi low-level driver");
4120 MODULE_LICENSE("GPL");