2 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
3 * Caesar Wang <wxt@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
19 #include <linux/module.h>
21 #include <linux/of_address.h>
22 #include <linux/of_irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/reset.h>
26 #include <linux/thermal.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/pinctrl/consumer.h>
31 * If the temperature over a period of time High,
32 * the resulting TSHUT gave CRU module,let it reset the entire chip,
33 * or via GPIO give PMIC.
41 * The system Temperature Sensors tshut(tshut) polarity
42 * the bit 8 is tshut polarity.
43 * 0: low active, 1: high active
51 * The system has two Temperature Sensors.
52 * sensor0 is for CPU, and sensor1 is for GPU.
60 * The conversion table has the adc value and temperature.
61 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
62 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
70 * The max sensors is two in rockchip SoCs.
71 * Two sensors: CPU and GPU sensor.
73 #define SOC_MAX_SENSORS 2
76 * struct chip_tsadc_table - hold information about chip-specific differences
77 * @id: conversion table
78 * @length: size of conversion table
79 * @data_mask: mask to apply on data inputs
80 * @mode: sort mode of this adc variant (incrementing or decrementing)
82 struct chip_tsadc_table {
83 const struct tsadc_table *id;
86 enum adc_sort_mode mode;
90 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
91 * @chn_id[SOC_MAX_SENSORS]: the sensor id of chip correspond to the channel
92 * @chn_num: the channel number of tsadc chip
93 * @tshut_temp: the hardware-controlled shutdown temperature value
94 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
95 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
96 * @initialize: SoC special initialize tsadc controller method
97 * @irq_ack: clear the interrupt
98 * @get_temp: get the temperature
99 * @set_alarm_temp: set the high temperature interrupt
100 * @set_tshut_temp: set the hardware-controlled shutdown temperature
101 * @set_tshut_mode: set the hardware-controlled shutdown mode
102 * @table: the chip-specific conversion table
104 struct rockchip_tsadc_chip {
105 /* The sensor id of chip correspond to the ADC channel */
106 int chn_id[SOC_MAX_SENSORS];
109 /* The hardware-controlled tshut property */
111 enum tshut_mode tshut_mode;
112 enum tshut_polarity tshut_polarity;
114 /* Chip-wide methods */
115 void (*initialize)(struct regmap *grf,
116 void __iomem *reg, enum tshut_polarity p);
117 void (*irq_ack)(void __iomem *reg);
118 void (*control)(void __iomem *reg, bool on);
120 /* Per-sensor methods */
121 int (*get_temp)(struct chip_tsadc_table table,
122 int chn, void __iomem *reg, int *temp);
123 void (*set_alarm_temp)(struct chip_tsadc_table table,
124 int chn, void __iomem *reg, int temp);
125 void (*set_tshut_temp)(struct chip_tsadc_table table,
126 int chn, void __iomem *reg, int temp);
127 void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
129 /* Per-table methods */
130 struct chip_tsadc_table table;
134 * struct rockchip_thermal_sensor - hold the information of thermal sensor
135 * @thermal: pointer to the platform/configuration data
136 * @tzd: pointer to a thermal zone
137 * @id: identifier of the thermal sensor
139 struct rockchip_thermal_sensor {
140 struct rockchip_thermal_data *thermal;
141 struct thermal_zone_device *tzd;
146 * struct rockchip_thermal_data - hold the private data of thermal driver
147 * @chip: pointer to the platform/configuration data
148 * @pdev: platform device of thermal
149 * @reset: the reset controller of tsadc
150 * @sensors[SOC_MAX_SENSORS]: the thermal sensor
151 * @clk: the controller clock is divided by the exteral 24MHz
152 * @pclk: the advanced peripherals bus clock
153 * @grf: the general register file will be used to do static set by software
154 * @regs: the base address of tsadc controller
155 * @tshut_temp: the hardware-controlled shutdown temperature value
156 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
157 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
159 struct rockchip_thermal_data {
160 const struct rockchip_tsadc_chip *chip;
161 struct platform_device *pdev;
162 struct reset_control *reset;
164 struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
173 enum tshut_mode tshut_mode;
174 enum tshut_polarity tshut_polarity;
178 * TSADC Sensor Register description:
180 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
181 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
184 #define TSADCV2_USER_CON 0x00
185 #define TSADCV2_AUTO_CON 0x04
186 #define TSADCV2_INT_EN 0x08
187 #define TSADCV2_INT_PD 0x0c
188 #define TSADCV2_DATA(chn) (0x20 + (chn) * 0x04)
189 #define TSADCV2_COMP_INT(chn) (0x30 + (chn) * 0x04)
190 #define TSADCV2_COMP_SHUT(chn) (0x40 + (chn) * 0x04)
191 #define TSADCV2_HIGHT_INT_DEBOUNCE 0x60
192 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE 0x64
193 #define TSADCV2_AUTO_PERIOD 0x68
194 #define TSADCV2_AUTO_PERIOD_HT 0x6c
196 #define TSADCV2_AUTO_EN BIT(0)
197 #define TSADCV2_AUTO_SRC_EN(chn) BIT(4 + (chn))
198 #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH BIT(8)
200 #define TSADCV3_AUTO_Q_SEL_EN BIT(1)
202 #define TSADCV2_INT_SRC_EN(chn) BIT(chn)
203 #define TSADCV2_SHUT_2GPIO_SRC_EN(chn) BIT(4 + (chn))
204 #define TSADCV2_SHUT_2CRU_SRC_EN(chn) BIT(8 + (chn))
206 #define TSADCV2_INT_PD_CLEAR_MASK ~BIT(8)
207 #define TSADCV3_INT_PD_CLEAR_MASK ~BIT(16)
209 #define TSADCV2_DATA_MASK 0xfff
210 #define TSADCV3_DATA_MASK 0x3ff
212 #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT 4
213 #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT 4
214 #define TSADCV2_AUTO_PERIOD_TIME 250 /* 250ms */
215 #define TSADCV2_AUTO_PERIOD_HT_TIME 50 /* 50ms */
216 #define TSADCV3_AUTO_PERIOD_TIME 1875 /* 2.5ms */
217 #define TSADCV3_AUTO_PERIOD_HT_TIME 1875 /* 2.5ms */
219 #define TSADCV2_USER_INTER_PD_SOC 0x340 /* 13 clocks */
221 #define GRF_SARADC_TESTBIT 0x0e644
222 #define GRF_TSADC_TESTBIT_L 0x0e648
223 #define GRF_TSADC_TESTBIT_H 0x0e64c
225 #define GRF_SARADC_TESTBIT_ON (0x10001 << 2)
226 #define GRF_TSADC_TESTBIT_H_ON (0x10001 << 2)
227 #define GRF_TSADC_VCM_EN_L (0x10001 << 7)
228 #define GRF_TSADC_VCM_EN_H (0x10001 << 7)
231 * struct tsadc_table - code to temperature conversion table
232 * @code: the value of adc channel
233 * @temp: the temperature
235 * code to temperature mapping of the temperature sensor is a piece wise linear
236 * curve.Any temperature, code faling between to 2 give temperatures can be
237 * linearly interpolated.
238 * Code to Temperature mapping should be updated based on manufacturer results.
245 static const struct tsadc_table rk3228_code_table[] = {
281 {TSADCV2_DATA_MASK, 125000},
284 static const struct tsadc_table rk3288_code_table[] = {
285 {TSADCV2_DATA_MASK, -40000},
322 static const struct tsadc_table rk3368_code_table[] = {
358 {TSADCV3_DATA_MASK, 125000},
361 static const struct tsadc_table rk3399_code_table[] = {
397 {TSADCV3_DATA_MASK, 125000},
400 static u32 rk_tsadcv2_temp_to_code(struct chip_tsadc_table table,
407 high = table.length - 1;
408 mid = (high + low) / 2;
410 /* Return mask code data when the temp is over table range */
411 if (temp < table.id[low].temp || temp > table.id[high].temp) {
412 error = table.data_mask;
416 while (low <= high) {
417 if (temp == table.id[mid].temp)
418 return table.id[mid].code;
419 else if (temp < table.id[mid].temp)
423 mid = (low + high) / 2;
427 pr_err("%s: invalid temperature, temp=%d error=%d\n",
428 __func__, temp, error);
432 static int rk_tsadcv2_code_to_temp(struct chip_tsadc_table table, u32 code,
435 unsigned int low = 1;
436 unsigned int high = table.length - 1;
437 unsigned int mid = (low + high) / 2;
441 WARN_ON(table.length < 2);
443 switch (table.mode) {
445 code &= table.data_mask;
446 if (code < table.id[high].code)
447 return -EAGAIN; /* Incorrect reading */
449 while (low <= high) {
450 if (code >= table.id[mid].code &&
451 code < table.id[mid - 1].code)
453 else if (code < table.id[mid].code)
458 mid = (low + high) / 2;
462 code &= table.data_mask;
463 if (code < table.id[low].code)
464 return -EAGAIN; /* Incorrect reading */
466 while (low <= high) {
467 if (code <= table.id[mid].code &&
468 code > table.id[mid - 1].code)
470 else if (code > table.id[mid].code)
475 mid = (low + high) / 2;
479 pr_err("%s: unknown table mode: %d\n", __func__, table.mode);
484 * The 5C granularity provided by the table is too much. Let's
485 * assume that the relationship between sensor readings and
486 * temperature between 2 table entries is linear and interpolate
487 * to produce less granular result.
489 num = table.id[mid].temp - table.id[mid - 1].temp;
490 num *= abs(table.id[mid - 1].code - code);
491 denom = abs(table.id[mid - 1].code - table.id[mid].code);
492 *temp = table.id[mid - 1].temp + (num / denom);
498 * rk_tsadcv2_initialize - initialize TASDC Controller.
500 * (1) Set TSADC_V2_AUTO_PERIOD:
501 * Configure the interleave between every two accessing of
502 * TSADC in normal operation.
504 * (2) Set TSADCV2_AUTO_PERIOD_HT:
505 * Configure the interleave between every two accessing of
506 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
508 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
509 * If the temperature is higher than COMP_INT or COMP_SHUT for
510 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
512 static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
513 enum tshut_polarity tshut_polarity)
515 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
516 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
517 regs + TSADCV2_AUTO_CON);
519 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
520 regs + TSADCV2_AUTO_CON);
522 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
523 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
524 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
525 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
526 regs + TSADCV2_AUTO_PERIOD_HT);
527 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
528 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
532 * rk_tsadcv3_initialize - initialize TASDC Controller.
534 * (1) The tsadc control power sequence.
536 * (2) Set TSADC_V2_AUTO_PERIOD:
537 * Configure the interleave between every two accessing of
538 * TSADC in normal operation.
540 * (2) Set TSADCV2_AUTO_PERIOD_HT:
541 * Configure the interleave between every two accessing of
542 * TSADC after the temperature is higher than COM_SHUT or COM_INT.
544 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
545 * If the temperature is higher than COMP_INT or COMP_SHUT for
546 * "debounce" times, TSADC controller will generate interrupt or TSHUT.
548 static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
549 enum tshut_polarity tshut_polarity)
551 /* The tsadc control power sequence */
553 /* Set interleave value to workround ic time sync issue */
554 writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
557 writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
558 regs + TSADCV2_AUTO_PERIOD);
559 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
560 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
561 writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
562 regs + TSADCV2_AUTO_PERIOD_HT);
563 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
564 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
567 /* Enable the voltage common mode feature */
568 regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
569 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
571 usleep_range(15, 100); /* The spec note says at least 15 us */
572 regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
573 regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
574 usleep_range(90, 200); /* The spec note says at least 90 us */
576 writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
577 regs + TSADCV2_AUTO_PERIOD);
578 writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
579 regs + TSADCV2_HIGHT_INT_DEBOUNCE);
580 writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
581 regs + TSADCV2_AUTO_PERIOD_HT);
582 writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
583 regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
586 if (tshut_polarity == TSHUT_HIGH_ACTIVE)
587 writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
588 regs + TSADCV2_AUTO_CON);
590 writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
591 regs + TSADCV2_AUTO_CON);
594 static void rk_tsadcv2_irq_ack(void __iomem *regs)
598 val = readl_relaxed(regs + TSADCV2_INT_PD);
599 writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
602 static void rk_tsadcv3_irq_ack(void __iomem *regs)
606 val = readl_relaxed(regs + TSADCV2_INT_PD);
607 writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
610 static void rk_tsadcv2_control(void __iomem *regs, bool enable)
614 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
616 val |= TSADCV2_AUTO_EN;
618 val &= ~TSADCV2_AUTO_EN;
620 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
624 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
626 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
627 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
628 * adc value if setting this bit to enable.
630 static void rk_tsadcv3_control(void __iomem *regs, bool enable)
634 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
636 val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
638 val &= ~TSADCV2_AUTO_EN;
640 writel_relaxed(val, regs + TSADCV2_AUTO_CON);
643 static int rk_tsadcv2_get_temp(struct chip_tsadc_table table,
644 int chn, void __iomem *regs, int *temp)
648 val = readl_relaxed(regs + TSADCV2_DATA(chn));
650 return rk_tsadcv2_code_to_temp(table, val, temp);
653 static void rk_tsadcv2_alarm_temp(struct chip_tsadc_table table,
654 int chn, void __iomem *regs, int temp)
656 u32 alarm_value, int_en;
658 /* Make sure the value is valid */
659 alarm_value = rk_tsadcv2_temp_to_code(table, temp);
660 if (alarm_value == table.data_mask)
663 writel_relaxed(alarm_value & table.data_mask,
664 regs + TSADCV2_COMP_INT(chn));
666 int_en = readl_relaxed(regs + TSADCV2_INT_EN);
667 int_en |= TSADCV2_INT_SRC_EN(chn);
668 writel_relaxed(int_en, regs + TSADCV2_INT_EN);
671 static void rk_tsadcv2_tshut_temp(struct chip_tsadc_table table,
672 int chn, void __iomem *regs, int temp)
674 u32 tshut_value, val;
676 /* Make sure the value is valid */
677 tshut_value = rk_tsadcv2_temp_to_code(table, temp);
678 if (tshut_value == table.data_mask)
681 writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
683 /* TSHUT will be valid */
684 val = readl_relaxed(regs + TSADCV2_AUTO_CON);
685 writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
688 static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
689 enum tshut_mode mode)
693 val = readl_relaxed(regs + TSADCV2_INT_EN);
694 if (mode == TSHUT_MODE_GPIO) {
695 val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
696 val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
698 val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
699 val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
702 writel_relaxed(val, regs + TSADCV2_INT_EN);
705 static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
706 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
707 .chn_num = 1, /* one channel for tsadc */
709 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
710 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
713 .initialize = rk_tsadcv2_initialize,
714 .irq_ack = rk_tsadcv3_irq_ack,
715 .control = rk_tsadcv3_control,
716 .get_temp = rk_tsadcv2_get_temp,
717 .set_alarm_temp = rk_tsadcv2_alarm_temp,
718 .set_tshut_temp = rk_tsadcv2_tshut_temp,
719 .set_tshut_mode = rk_tsadcv2_tshut_mode,
722 .id = rk3228_code_table,
723 .length = ARRAY_SIZE(rk3228_code_table),
724 .data_mask = TSADCV3_DATA_MASK,
725 .mode = ADC_INCREMENT,
729 static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
730 .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
731 .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
732 .chn_num = 2, /* two channels for tsadc */
734 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
735 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
738 .initialize = rk_tsadcv2_initialize,
739 .irq_ack = rk_tsadcv2_irq_ack,
740 .control = rk_tsadcv2_control,
741 .get_temp = rk_tsadcv2_get_temp,
742 .set_alarm_temp = rk_tsadcv2_alarm_temp,
743 .set_tshut_temp = rk_tsadcv2_tshut_temp,
744 .set_tshut_mode = rk_tsadcv2_tshut_mode,
747 .id = rk3288_code_table,
748 .length = ARRAY_SIZE(rk3288_code_table),
749 .data_mask = TSADCV2_DATA_MASK,
750 .mode = ADC_DECREMENT,
754 static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
755 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
756 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
757 .chn_num = 2, /* two channels for tsadc */
759 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
760 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
763 .initialize = rk_tsadcv3_initialize,
764 .irq_ack = rk_tsadcv3_irq_ack,
765 .control = rk_tsadcv3_control,
766 .get_temp = rk_tsadcv2_get_temp,
767 .set_alarm_temp = rk_tsadcv2_alarm_temp,
768 .set_tshut_temp = rk_tsadcv2_tshut_temp,
769 .set_tshut_mode = rk_tsadcv2_tshut_mode,
772 .id = rk3228_code_table,
773 .length = ARRAY_SIZE(rk3228_code_table),
774 .data_mask = TSADCV3_DATA_MASK,
775 .mode = ADC_INCREMENT,
779 static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
780 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
781 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
782 .chn_num = 2, /* two channels for tsadc */
784 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
785 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
788 .initialize = rk_tsadcv2_initialize,
789 .irq_ack = rk_tsadcv2_irq_ack,
790 .control = rk_tsadcv2_control,
791 .get_temp = rk_tsadcv2_get_temp,
792 .set_alarm_temp = rk_tsadcv2_alarm_temp,
793 .set_tshut_temp = rk_tsadcv2_tshut_temp,
794 .set_tshut_mode = rk_tsadcv2_tshut_mode,
797 .id = rk3368_code_table,
798 .length = ARRAY_SIZE(rk3368_code_table),
799 .data_mask = TSADCV3_DATA_MASK,
800 .mode = ADC_INCREMENT,
804 static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
805 .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
806 .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
807 .chn_num = 2, /* two channels for tsadc */
809 .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
810 .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
813 .initialize = rk_tsadcv3_initialize,
814 .irq_ack = rk_tsadcv3_irq_ack,
815 .control = rk_tsadcv3_control,
816 .get_temp = rk_tsadcv2_get_temp,
817 .set_alarm_temp = rk_tsadcv2_alarm_temp,
818 .set_tshut_temp = rk_tsadcv2_tshut_temp,
819 .set_tshut_mode = rk_tsadcv2_tshut_mode,
822 .id = rk3399_code_table,
823 .length = ARRAY_SIZE(rk3399_code_table),
824 .data_mask = TSADCV3_DATA_MASK,
825 .mode = ADC_INCREMENT,
829 static const struct of_device_id of_rockchip_thermal_match[] = {
831 .compatible = "rockchip,rk3228-tsadc",
832 .data = (void *)&rk3228_tsadc_data,
835 .compatible = "rockchip,rk3288-tsadc",
836 .data = (void *)&rk3288_tsadc_data,
839 .compatible = "rockchip,rk3366-tsadc",
840 .data = (void *)&rk3366_tsadc_data,
843 .compatible = "rockchip,rk3368-tsadc",
844 .data = (void *)&rk3368_tsadc_data,
847 .compatible = "rockchip,rk3399-tsadc",
848 .data = (void *)&rk3399_tsadc_data,
852 MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
855 rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
857 struct thermal_zone_device *tzd = sensor->tzd;
859 tzd->ops->set_mode(tzd,
860 on ? THERMAL_DEVICE_ENABLED : THERMAL_DEVICE_DISABLED);
863 static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
865 struct rockchip_thermal_data *thermal = dev;
868 dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
870 thermal->chip->irq_ack(thermal->regs);
872 for (i = 0; i < thermal->chip->chn_num; i++)
873 thermal_zone_device_update(thermal->sensors[i].tzd,
874 THERMAL_EVENT_UNSPECIFIED);
879 static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
881 struct rockchip_thermal_sensor *sensor = _sensor;
882 struct rockchip_thermal_data *thermal = sensor->thermal;
883 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
885 dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
886 __func__, sensor->id, low, high);
888 tsadc->set_alarm_temp(tsadc->table,
889 sensor->id, thermal->regs, high);
894 static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
896 struct rockchip_thermal_sensor *sensor = _sensor;
897 struct rockchip_thermal_data *thermal = sensor->thermal;
898 const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
901 retval = tsadc->get_temp(tsadc->table,
902 sensor->id, thermal->regs, out_temp);
903 dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
904 sensor->id, *out_temp, retval);
909 static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
910 .get_temp = rockchip_thermal_get_temp,
911 .set_trips = rockchip_thermal_set_trips,
914 static int rockchip_configure_from_dt(struct device *dev,
915 struct device_node *np,
916 struct rockchip_thermal_data *thermal)
918 u32 shut_temp, tshut_mode, tshut_polarity;
920 if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
922 "Missing tshut temp property, using default %d\n",
923 thermal->chip->tshut_temp);
924 thermal->tshut_temp = thermal->chip->tshut_temp;
926 if (shut_temp > INT_MAX) {
927 dev_err(dev, "Invalid tshut temperature specified: %d\n",
931 thermal->tshut_temp = shut_temp;
934 if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
936 "Missing tshut mode property, using default (%s)\n",
937 thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
939 thermal->tshut_mode = thermal->chip->tshut_mode;
941 thermal->tshut_mode = tshut_mode;
944 if (thermal->tshut_mode > 1) {
945 dev_err(dev, "Invalid tshut mode specified: %d\n",
946 thermal->tshut_mode);
950 if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
953 "Missing tshut-polarity property, using default (%s)\n",
954 thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
956 thermal->tshut_polarity = thermal->chip->tshut_polarity;
958 thermal->tshut_polarity = tshut_polarity;
961 if (thermal->tshut_polarity > 1) {
962 dev_err(dev, "Invalid tshut-polarity specified: %d\n",
963 thermal->tshut_polarity);
967 /* The tsadc wont to handle the error in here since some SoCs didn't
968 * need this property.
970 thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
971 if (IS_ERR(thermal->grf))
972 dev_warn(dev, "Missing rockchip,grf property\n");
978 rockchip_thermal_register_sensor(struct platform_device *pdev,
979 struct rockchip_thermal_data *thermal,
980 struct rockchip_thermal_sensor *sensor,
983 const struct rockchip_tsadc_chip *tsadc = thermal->chip;
986 tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
987 tsadc->set_tshut_temp(tsadc->table, id, thermal->regs,
988 thermal->tshut_temp);
990 sensor->thermal = thermal;
992 sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
993 sensor, &rockchip_of_thermal_ops);
994 if (IS_ERR(sensor->tzd)) {
995 error = PTR_ERR(sensor->tzd);
996 dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1005 * Reset TSADC Controller, reset all tsadc registers.
1007 static void rockchip_thermal_reset_controller(struct reset_control *reset)
1009 reset_control_assert(reset);
1010 usleep_range(10, 20);
1011 reset_control_deassert(reset);
1014 static int rockchip_thermal_probe(struct platform_device *pdev)
1016 struct device_node *np = pdev->dev.of_node;
1017 struct rockchip_thermal_data *thermal;
1018 const struct of_device_id *match;
1019 struct resource *res;
1024 match = of_match_node(of_rockchip_thermal_match, np);
1028 irq = platform_get_irq(pdev, 0);
1030 dev_err(&pdev->dev, "no irq resource?\n");
1034 thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1039 thermal->pdev = pdev;
1041 thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1045 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1046 thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1047 if (IS_ERR(thermal->regs))
1048 return PTR_ERR(thermal->regs);
1050 thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
1051 if (IS_ERR(thermal->reset)) {
1052 error = PTR_ERR(thermal->reset);
1053 dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1057 thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1058 if (IS_ERR(thermal->clk)) {
1059 error = PTR_ERR(thermal->clk);
1060 dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1064 thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1065 if (IS_ERR(thermal->pclk)) {
1066 error = PTR_ERR(thermal->pclk);
1067 dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1072 error = clk_prepare_enable(thermal->clk);
1074 dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1079 error = clk_prepare_enable(thermal->pclk);
1081 dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1082 goto err_disable_clk;
1085 rockchip_thermal_reset_controller(thermal->reset);
1087 error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1089 dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1091 goto err_disable_pclk;
1094 thermal->chip->initialize(thermal->grf, thermal->regs,
1095 thermal->tshut_polarity);
1097 for (i = 0; i < thermal->chip->chn_num; i++) {
1098 error = rockchip_thermal_register_sensor(pdev, thermal,
1099 &thermal->sensors[i],
1100 thermal->chip->chn_id[i]);
1103 "failed to register sensor[%d] : error = %d\n",
1105 goto err_disable_pclk;
1109 error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1110 &rockchip_thermal_alarm_irq_thread,
1112 "rockchip_thermal", thermal);
1115 "failed to request tsadc irq: %d\n", error);
1116 goto err_disable_pclk;
1119 thermal->chip->control(thermal->regs, true);
1121 for (i = 0; i < thermal->chip->chn_num; i++)
1122 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1124 platform_set_drvdata(pdev, thermal);
1129 clk_disable_unprepare(thermal->pclk);
1131 clk_disable_unprepare(thermal->clk);
1136 static int rockchip_thermal_remove(struct platform_device *pdev)
1138 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1141 for (i = 0; i < thermal->chip->chn_num; i++) {
1142 struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1144 rockchip_thermal_toggle_sensor(sensor, false);
1147 thermal->chip->control(thermal->regs, false);
1149 clk_disable_unprepare(thermal->pclk);
1150 clk_disable_unprepare(thermal->clk);
1155 static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1157 struct platform_device *pdev = to_platform_device(dev);
1158 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1161 for (i = 0; i < thermal->chip->chn_num; i++)
1162 rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1164 thermal->chip->control(thermal->regs, false);
1166 clk_disable(thermal->pclk);
1167 clk_disable(thermal->clk);
1169 pinctrl_pm_select_sleep_state(dev);
1174 static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1176 struct platform_device *pdev = to_platform_device(dev);
1177 struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1181 error = clk_enable(thermal->clk);
1185 error = clk_enable(thermal->pclk);
1187 clk_disable(thermal->clk);
1191 rockchip_thermal_reset_controller(thermal->reset);
1193 thermal->chip->initialize(thermal->grf, thermal->regs,
1194 thermal->tshut_polarity);
1196 for (i = 0; i < thermal->chip->chn_num; i++) {
1197 int id = thermal->sensors[i].id;
1199 thermal->chip->set_tshut_mode(id, thermal->regs,
1200 thermal->tshut_mode);
1201 thermal->chip->set_tshut_temp(thermal->chip->table,
1203 thermal->tshut_temp);
1206 thermal->chip->control(thermal->regs, true);
1208 for (i = 0; i < thermal->chip->chn_num; i++)
1209 rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1211 pinctrl_pm_select_default_state(dev);
1216 static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1217 rockchip_thermal_suspend, rockchip_thermal_resume);
1219 static struct platform_driver rockchip_thermal_driver = {
1221 .name = "rockchip-thermal",
1222 .pm = &rockchip_thermal_pm_ops,
1223 .of_match_table = of_rockchip_thermal_match,
1225 .probe = rockchip_thermal_probe,
1226 .remove = rockchip_thermal_remove,
1229 module_platform_driver(rockchip_thermal_driver);
1231 MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1232 MODULE_AUTHOR("Rockchip, Inc.");
1233 MODULE_LICENSE("GPL v2");
1234 MODULE_ALIAS("platform:rockchip-thermal");