drivers/tty/serial/8250/8250_pci.c

   1 /*
   2  *  Probe module for 8250/16550-type PCI serial ports.
   3  *
   4  *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  *  Copyright (C) 2001 Russell King, All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License.
  11  */
  12 #include <linux/module.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/string.h>
  16 #include <linux/kernel.h>
  17 #include <linux/slab.h>
  18 #include <linux/delay.h>
  19 #include <linux/tty.h>
  20 #include <linux/serial_reg.h>
  21 #include <linux/serial_core.h>
  22 #include <linux/8250_pci.h>
  23 #include <linux/bitops.h>
  24
  25 #include <asm/byteorder.h>
  26 #include <asm/io.h>
  27
  28 #include "8250.h"
  29
  30 #undef SERIAL_DEBUG_PCI
  31
  32 /*
  33  * init function returns:
  34  *  > 0 - number of ports
  35  *  = 0 - use board->num_ports
  36  *  < 0 - error
  37  */
  38 struct pci_serial_quirk {
  39         u32     vendor;
  40         u32     device;
  41         u32     subvendor;
  42         u32     subdevice;
  43         int     (*probe)(struct pci_dev *dev);
  44         int     (*init)(struct pci_dev *dev);
  45         int     (*setup)(struct serial_private *,
  46                          const struct pciserial_board *,
  47                          struct uart_8250_port *, int);
  48         void    (*exit)(struct pci_dev *dev);
  49 };
  50
  51 #define PCI_NUM_BAR_RESOURCES   6
  52
  53 struct serial_private {
  54         struct pci_dev          *dev;
  55         unsigned int            nr;
  56         void __iomem            *remapped_bar[PCI_NUM_BAR_RESOURCES];
  57         struct pci_serial_quirk *quirk;
  58         int                     line[0];
  59 };
  60
  61 static int pci_default_setup(struct serial_private*,
  62           const struct pciserial_board*, struct uart_8250_port *, int);
  63
  64 static void moan_device(const char *str, struct pci_dev *dev)
  65 {
  66         printk(KERN_WARNING
  67                "%s: %s\n"
  68                "Please send the output of lspci -vv, this\n"
  69                "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  70                "manufacturer and name of serial board or\n"
  71                "modem board to rmk+serial@arm.linux.org.uk.\n",
  72                pci_name(dev), str, dev->vendor, dev->device,
  73                dev->subsystem_vendor, dev->subsystem_device);
  74 }
  75
  76 static int
  77 setup_port(struct serial_private *priv, struct uart_8250_port *port,
  78            int bar, int offset, int regshift)
  79 {
  80         struct pci_dev *dev = priv->dev;
  81         unsigned long base, len;
  82
  83         if (bar >= PCI_NUM_BAR_RESOURCES)
  84                 return -EINVAL;
  85
  86         base = pci_resource_start(dev, bar);
  87
  88         if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  89                 len =  pci_resource_len(dev, bar);
  90
  91                 if (!priv->remapped_bar[bar])
  92                         priv->remapped_bar[bar] = ioremap_nocache(base, len);
  93                 if (!priv->remapped_bar[bar])
  94                         return -ENOMEM;
  95
  96                 port->port.iotype = UPIO_MEM;
  97                 port->port.iobase = 0;
  98                 port->port.mapbase = base + offset;
  99                 port->port.membase = priv->remapped_bar[bar] + offset;
 100                 port->port.regshift = regshift;
 101         } else {
 102                 port->port.iotype = UPIO_PORT;
 103                 port->port.iobase = base + offset;
 104                 port->port.mapbase = 0;
 105                 port->port.membase = NULL;
 106                 port->port.regshift = 0;
 107         }
 108         return 0;
 109 }
 110
 111 /*
 112  * ADDI-DATA GmbH communication cards <info@addi-data.com>
 113  */
 114 static int addidata_apci7800_setup(struct serial_private *priv,
 115                                 const struct pciserial_board *board,
 116                                 struct uart_8250_port *port, int idx)
 117 {
 118         unsigned int bar = 0, offset = board->first_offset;
 119         bar = FL_GET_BASE(board->flags);
 120
 121         if (idx < 2) {
 122                 offset += idx * board->uart_offset;
 123         } else if ((idx >= 2) && (idx < 4)) {
 124                 bar += 1;
 125                 offset += ((idx - 2) * board->uart_offset);
 126         } else if ((idx >= 4) && (idx < 6)) {
 127                 bar += 2;
 128                 offset += ((idx - 4) * board->uart_offset);
 129         } else if (idx >= 6) {
 130                 bar += 3;
 131                 offset += ((idx - 6) * board->uart_offset);
 132         }
 133
 134         return setup_port(priv, port, bar, offset, board->reg_shift);
 135 }
 136
 137 /*
 138  * AFAVLAB uses a different mixture of BARs and offsets
 139  * Not that ugly ;) -- HW
 140  */
 141 static int
 142 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 143               struct uart_8250_port *port, int idx)
 144 {
 145         unsigned int bar, offset = board->first_offset;
 146
 147         bar = FL_GET_BASE(board->flags);
 148         if (idx < 4)
 149                 bar += idx;
 150         else {
 151                 bar = 4;
 152                 offset += (idx - 4) * board->uart_offset;
 153         }
 154
 155         return setup_port(priv, port, bar, offset, board->reg_shift);
 156 }
 157
 158 /*
 159  * HP's Remote Management Console.  The Diva chip came in several
 160  * different versions.  N-class, L2000 and A500 have two Diva chips, each
 161  * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 162  * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 163  * one Diva chip, but it has been expanded to 5 UARTs.
 164  */
 165 static int pci_hp_diva_init(struct pci_dev *dev)
 166 {
 167         int rc = 0;
 168
 169         switch (dev->subsystem_device) {
 170         case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 171         case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 172         case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 173         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 174                 rc = 3;
 175                 break;
 176         case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 177                 rc = 2;
 178                 break;
 179         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 180                 rc = 4;
 181                 break;
 182         case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 183         case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 184                 rc = 1;
 185                 break;
 186         }
 187
 188         return rc;
 189 }
 190
 191 /*
 192  * HP's Diva chip puts the 4th/5th serial port further out, and
 193  * some serial ports are supposed to be hidden on certain models.
 194  */
 195 static int
 196 pci_hp_diva_setup(struct serial_private *priv,
 197                 const struct pciserial_board *board,
 198                 struct uart_8250_port *port, int idx)
 199 {
 200         unsigned int offset = board->first_offset;
 201         unsigned int bar = FL_GET_BASE(board->flags);
 202
 203         switch (priv->dev->subsystem_device) {
 204         case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 205                 if (idx == 3)
 206                         idx++;
 207                 break;
 208         case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 209                 if (idx > 0)
 210                         idx++;
 211                 if (idx > 2)
 212                         idx++;
 213                 break;
 214         }
 215         if (idx > 2)
 216                 offset = 0x18;
 217
 218         offset += idx * board->uart_offset;
 219
 220         return setup_port(priv, port, bar, offset, board->reg_shift);
 221 }
 222
 223 /*
 224  * Added for EKF Intel i960 serial boards
 225  */
 226 static int pci_inteli960ni_init(struct pci_dev *dev)
 227 {
 228         unsigned long oldval;
 229
 230         if (!(dev->subsystem_device & 0x1000))
 231                 return -ENODEV;
 232
 233         /* is firmware started? */
 234         pci_read_config_dword(dev, 0x44, (void *)&oldval);
 235         if (oldval == 0x00001000L) { /* RESET value */
 236                 printk(KERN_DEBUG "Local i960 firmware missing");
 237                 return -ENODEV;
 238         }
 239         return 0;
 240 }
 241
 242 /*
 243  * Some PCI serial cards using the PLX 9050 PCI interface chip require
 244  * that the card interrupt be explicitly enabled or disabled.  This
 245  * seems to be mainly needed on card using the PLX which also use I/O
 246  * mapped memory.
 247  */
 248 static int pci_plx9050_init(struct pci_dev *dev)
 249 {
 250         u8 irq_config;
 251         void __iomem *p;
 252
 253         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 254                 moan_device("no memory in bar 0", dev);
 255                 return 0;
 256         }
 257
 258         irq_config = 0x41;
 259         if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 260             dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 261                 irq_config = 0x43;
 262
 263         if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 264             (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 265                 /*
 266                  * As the megawolf cards have the int pins active
 267                  * high, and have 2 UART chips, both ints must be
 268                  * enabled on the 9050. Also, the UARTS are set in
 269                  * 16450 mode by default, so we have to enable the
 270                  * 16C950 'enhanced' mode so that we can use the
 271                  * deep FIFOs
 272                  */
 273                 irq_config = 0x5b;
 274         /*
 275          * enable/disable interrupts
 276          */
 277         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 278         if (p == NULL)
 279                 return -ENOMEM;
 280         writel(irq_config, p + 0x4c);
 281
 282         /*
 283          * Read the register back to ensure that it took effect.
 284          */
 285         readl(p + 0x4c);
 286         iounmap(p);
 287
 288         return 0;
 289 }
 290
 291 static void pci_plx9050_exit(struct pci_dev *dev)
 292 {
 293         u8 __iomem *p;
 294
 295         if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 296                 return;
 297
 298         /*
 299          * disable interrupts
 300          */
 301         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 302         if (p != NULL) {
 303                 writel(0, p + 0x4c);
 304
 305                 /*
 306                  * Read the register back to ensure that it took effect.
 307                  */
 308                 readl(p + 0x4c);
 309                 iounmap(p);
 310         }
 311 }
 312
 313 #define NI8420_INT_ENABLE_REG   0x38
 314 #define NI8420_INT_ENABLE_BIT   0x2000
 315
 316 static void pci_ni8420_exit(struct pci_dev *dev)
 317 {
 318         void __iomem *p;
 319         unsigned long base, len;
 320         unsigned int bar = 0;
 321
 322         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 323                 moan_device("no memory in bar", dev);
 324                 return;
 325         }
 326
 327         base = pci_resource_start(dev, bar);
 328         len =  pci_resource_len(dev, bar);
 329         p = ioremap_nocache(base, len);
 330         if (p == NULL)
 331                 return;
 332
 333         /* Disable the CPU Interrupt */
 334         writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 335                p + NI8420_INT_ENABLE_REG);
 336         iounmap(p);
 337 }
 338
 339
 340 /* MITE registers */
 341 #define MITE_IOWBSR1    0xc4
 342 #define MITE_IOWCR1     0xf4
 343 #define MITE_LCIMR1     0x08
 344 #define MITE_LCIMR2     0x10
 345
 346 #define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 347
 348 static void pci_ni8430_exit(struct pci_dev *dev)
 349 {
 350         void __iomem *p;
 351         unsigned long base, len;
 352         unsigned int bar = 0;
 353
 354         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 355                 moan_device("no memory in bar", dev);
 356                 return;
 357         }
 358
 359         base = pci_resource_start(dev, bar);
 360         len =  pci_resource_len(dev, bar);
 361         p = ioremap_nocache(base, len);
 362         if (p == NULL)
 363                 return;
 364
 365         /* Disable the CPU Interrupt */
 366         writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 367         iounmap(p);
 368 }
 369
 370 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 371 static int
 372 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 373                 struct uart_8250_port *port, int idx)
 374 {
 375         unsigned int bar, offset = board->first_offset;
 376
 377         bar = 0;
 378
 379         if (idx < 4) {
 380                 /* first four channels map to 0, 0x100, 0x200, 0x300 */
 381                 offset += idx * board->uart_offset;
 382         } else if (idx < 8) {
 383                 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 384                 offset += idx * board->uart_offset + 0xC00;
 385         } else /* we have only 8 ports on PMC-OCTALPRO */
 386                 return 1;
 387
 388         return setup_port(priv, port, bar, offset, board->reg_shift);
 389 }
 390
 391 /*
 392 * This does initialization for PMC OCTALPRO cards:
 393 * maps the device memory, resets the UARTs (needed, bc
 394 * if the module is removed and inserted again, the card
 395 * is in the sleep mode) and enables global interrupt.
 396 */
 397
 398 /* global control register offset for SBS PMC-OctalPro */
 399 #define OCT_REG_CR_OFF          0x500
 400
 401 static int sbs_init(struct pci_dev *dev)
 402 {
 403         u8 __iomem *p;
 404
 405         p = pci_ioremap_bar(dev, 0);
 406
 407         if (p == NULL)
 408                 return -ENOMEM;
 409         /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 410         writeb(0x10, p + OCT_REG_CR_OFF);
 411         udelay(50);
 412         writeb(0x0, p + OCT_REG_CR_OFF);
 413
 414         /* Set bit-2 (INTENABLE) of Control Register */
 415         writeb(0x4, p + OCT_REG_CR_OFF);
 416         iounmap(p);
 417
 418         return 0;
 419 }
 420
 421 /*
 422  * Disables the global interrupt of PMC-OctalPro
 423  */
 424
 425 static void sbs_exit(struct pci_dev *dev)
 426 {
 427         u8 __iomem *p;
 428
 429         p = pci_ioremap_bar(dev, 0);
 430         /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 431         if (p != NULL)
 432                 writeb(0, p + OCT_REG_CR_OFF);
 433         iounmap(p);
 434 }
 435
 436 /*
 437  * SIIG serial cards have an PCI interface chip which also controls
 438  * the UART clocking frequency. Each UART can be clocked independently
 439  * (except cards equipped with 4 UARTs) and initial clocking settings
 440  * are stored in the EEPROM chip. It can cause problems because this
 441  * version of serial driver doesn't support differently clocked UART's
 442  * on single PCI card. To prevent this, initialization functions set
 443  * high frequency clocking for all UART's on given card. It is safe (I
 444  * hope) because it doesn't touch EEPROM settings to prevent conflicts
 445  * with other OSes (like M$ DOS).
 446  *
 447  *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 448  *
 449  * There is two family of SIIG serial cards with different PCI
 450  * interface chip and different configuration methods:
 451  *     - 10x cards have control registers in IO and/or memory space;
 452  *     - 20x cards have control registers in standard PCI configuration space.
 453  *
 454  * Note: all 10x cards have PCI device ids 0x10..
 455  *       all 20x cards have PCI device ids 0x20..
 456  *
 457  * There are also Quartet Serial cards which use Oxford Semiconductor
 458  * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 459  *
 460  * Note: some SIIG cards are probed by the parport_serial object.
 461  */
 462
 463 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 464 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 465
 466 static int pci_siig10x_init(struct pci_dev *dev)
 467 {
 468         u16 data;
 469         void __iomem *p;
 470
 471         switch (dev->device & 0xfff8) {
 472         case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 473                 data = 0xffdf;
 474                 break;
 475         case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 476                 data = 0xf7ff;
 477                 break;
 478         default:                        /* 1S1P, 4S */
 479                 data = 0xfffb;
 480                 break;
 481         }
 482
 483         p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
 484         if (p == NULL)
 485                 return -ENOMEM;
 486
 487         writew(readw(p + 0x28) & data, p + 0x28);
 488         readw(p + 0x28);
 489         iounmap(p);
 490         return 0;
 491 }
 492
 493 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 494 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 495
 496 static int pci_siig20x_init(struct pci_dev *dev)
 497 {
 498         u8 data;
 499
 500         /* Change clock frequency for the first UART. */
 501         pci_read_config_byte(dev, 0x6f, &data);
 502         pci_write_config_byte(dev, 0x6f, data & 0xef);
 503
 504         /* If this card has 2 UART, we have to do the same with second UART. */
 505         if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 506             ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 507                 pci_read_config_byte(dev, 0x73, &data);
 508                 pci_write_config_byte(dev, 0x73, data & 0xef);
 509         }
 510         return 0;
 511 }
 512
 513 static int pci_siig_init(struct pci_dev *dev)
 514 {
 515         unsigned int type = dev->device & 0xff00;
 516
 517         if (type == 0x1000)
 518                 return pci_siig10x_init(dev);
 519         else if (type == 0x2000)
 520                 return pci_siig20x_init(dev);
 521
 522         moan_device("Unknown SIIG card", dev);
 523         return -ENODEV;
 524 }
 525
 526 static int pci_siig_setup(struct serial_private *priv,
 527                           const struct pciserial_board *board,
 528                           struct uart_8250_port *port, int idx)
 529 {
 530         unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 531
 532         if (idx > 3) {
 533                 bar = 4;
 534                 offset = (idx - 4) * 8;
 535         }
 536
 537         return setup_port(priv, port, bar, offset, 0);
 538 }
 539
 540 /*
 541  * Timedia has an explosion of boards, and to avoid the PCI table from
 542  * growing *huge*, we use this function to collapse some 70 entries
 543  * in the PCI table into one, for sanity's and compactness's sake.
 544  */
 545 static const unsigned short timedia_single_port[] = {
 546         0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 547 };
 548
 549 static const unsigned short timedia_dual_port[] = {
 550         0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 551         0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 552         0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 553         0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 554         0xD079, 0
 555 };
 556
 557 static const unsigned short timedia_quad_port[] = {
 558         0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 559         0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 560         0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 561         0xB157, 0
 562 };
 563
 564 static const unsigned short timedia_eight_port[] = {
 565         0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 566         0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 567 };
 568
 569 static const struct timedia_struct {
 570         int num;
 571         const unsigned short *ids;
 572 } timedia_data[] = {
 573         { 1, timedia_single_port },
 574         { 2, timedia_dual_port },
 575         { 4, timedia_quad_port },
 576         { 8, timedia_eight_port }
 577 };
 578
 579 /*
 580  * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 581  * listing them individually, this driver merely grabs them all with
 582  * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 583  * and should be left free to be claimed by parport_serial instead.
 584  */
 585 static int pci_timedia_probe(struct pci_dev *dev)
 586 {
 587         /*
 588          * Check the third digit of the subdevice ID
 589          * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 590          */
 591         if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 592                 dev_info(&dev->dev,
 593                         "ignoring Timedia subdevice %04x for parport_serial\n",
 594                         dev->subsystem_device);
 595                 return -ENODEV;
 596         }
 597
 598         return 0;
 599 }
 600
 601 static int pci_timedia_init(struct pci_dev *dev)
 602 {
 603         const unsigned short *ids;
 604         int i, j;
 605
 606         for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 607                 ids = timedia_data[i].ids;
 608                 for (j = 0; ids[j]; j++)
 609                         if (dev->subsystem_device == ids[j])
 610                                 return timedia_data[i].num;
 611         }
 612         return 0;
 613 }
 614
 615 /*
 616  * Timedia/SUNIX uses a mixture of BARs and offsets
 617  * Ugh, this is ugly as all hell --- TYT
 618  */
 619 static int
 620 pci_timedia_setup(struct serial_private *priv,
 621                   const struct pciserial_board *board,
 622                   struct uart_8250_port *port, int idx)
 623 {
 624         unsigned int bar = 0, offset = board->first_offset;
 625
 626         switch (idx) {
 627         case 0:
 628                 bar = 0;
 629                 break;
 630         case 1:
 631                 offset = board->uart_offset;
 632                 bar = 0;
 633                 break;
 634         case 2:
 635                 bar = 1;
 636                 break;
 637         case 3:
 638                 offset = board->uart_offset;
 639                 /* FALLTHROUGH */
 640         case 4: /* BAR 2 */
 641         case 5: /* BAR 3 */
 642         case 6: /* BAR 4 */
 643         case 7: /* BAR 5 */
 644                 bar = idx - 2;
 645         }
 646
 647         return setup_port(priv, port, bar, offset, board->reg_shift);
 648 }
 649
 650 /*
 651  * Some Titan cards are also a little weird
 652  */
 653 static int
 654 titan_400l_800l_setup(struct serial_private *priv,
 655                       const struct pciserial_board *board,
 656                       struct uart_8250_port *port, int idx)
 657 {
 658         unsigned int bar, offset = board->first_offset;
 659
 660         switch (idx) {
 661         case 0:
 662                 bar = 1;
 663                 break;
 664         case 1:
 665                 bar = 2;
 666                 break;
 667         default:
 668                 bar = 4;
 669                 offset = (idx - 2) * board->uart_offset;
 670         }
 671
 672         return setup_port(priv, port, bar, offset, board->reg_shift);
 673 }
 674
 675 static int pci_xircom_init(struct pci_dev *dev)
 676 {
 677         msleep(100);
 678         return 0;
 679 }
 680
 681 static int pci_ni8420_init(struct pci_dev *dev)
 682 {
 683         void __iomem *p;
 684         unsigned long base, len;
 685         unsigned int bar = 0;
 686
 687         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 688                 moan_device("no memory in bar", dev);
 689                 return 0;
 690         }
 691
 692         base = pci_resource_start(dev, bar);
 693         len =  pci_resource_len(dev, bar);
 694         p = ioremap_nocache(base, len);
 695         if (p == NULL)
 696                 return -ENOMEM;
 697
 698         /* Enable CPU Interrupt */
 699         writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 700                p + NI8420_INT_ENABLE_REG);
 701
 702         iounmap(p);
 703         return 0;
 704 }
 705
 706 #define MITE_IOWBSR1_WSIZE      0xa
 707 #define MITE_IOWBSR1_WIN_OFFSET 0x800
 708 #define MITE_IOWBSR1_WENAB      (1 << 7)
 709 #define MITE_LCIMR1_IO_IE_0     (1 << 24)
 710 #define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 711 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 712
 713 static int pci_ni8430_init(struct pci_dev *dev)
 714 {
 715         void __iomem *p;
 716         unsigned long base, len;
 717         u32 device_window;
 718         unsigned int bar = 0;
 719
 720         if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 721                 moan_device("no memory in bar", dev);
 722                 return 0;
 723         }
 724
 725         base = pci_resource_start(dev, bar);
 726         len =  pci_resource_len(dev, bar);
 727         p = ioremap_nocache(base, len);
 728         if (p == NULL)
 729                 return -ENOMEM;
 730
 731         /* Set device window address and size in BAR0 */
 732         device_window = ((base + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 733                         | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 734         writel(device_window, p + MITE_IOWBSR1);
 735
 736         /* Set window access to go to RAMSEL IO address space */
 737         writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 738                p + MITE_IOWCR1);
 739
 740         /* Enable IO Bus Interrupt 0 */
 741         writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 742
 743         /* Enable CPU Interrupt */
 744         writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 745
 746         iounmap(p);
 747         return 0;
 748 }
 749
 750 /* UART Port Control Register */
 751 #define NI8430_PORTCON  0x0f
 752 #define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 753
 754 static int
 755 pci_ni8430_setup(struct serial_private *priv,
 756                  const struct pciserial_board *board,
 757                  struct uart_8250_port *port, int idx)
 758 {
 759         void __iomem *p;
 760         unsigned long base, len;
 761         unsigned int bar, offset = board->first_offset;
 762
 763         if (idx >= board->num_ports)
 764                 return 1;
 765
 766         bar = FL_GET_BASE(board->flags);
 767         offset += idx * board->uart_offset;
 768
 769         base = pci_resource_start(priv->dev, bar);
 770         len =  pci_resource_len(priv->dev, bar);
 771         p = ioremap_nocache(base, len);
 772
 773         /* enable the transceiver */
 774         writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 775                p + offset + NI8430_PORTCON);
 776
 777         iounmap(p);
 778
 779         return setup_port(priv, port, bar, offset, board->reg_shift);
 780 }
 781
 782 static int pci_netmos_9900_setup(struct serial_private *priv,
 783                                 const struct pciserial_board *board,
 784                                 struct uart_8250_port *port, int idx)
 785 {
 786         unsigned int bar;
 787
 788         if ((priv->dev->subsystem_device & 0xff00) == 0x3000) {
 789                 /* netmos apparently orders BARs by datasheet layout, so serial
 790                  * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 791                  */
 792                 bar = 3 * idx;
 793
 794                 return setup_port(priv, port, bar, 0, board->reg_shift);
 795         } else {
 796                 return pci_default_setup(priv, board, port, idx);
 797         }
 798 }
 799
 800 /* the 99xx series comes with a range of device IDs and a variety
 801  * of capabilities:
 802  *
 803  * 9900 has varying capabilities and can cascade to sub-controllers
 804  *   (cascading should be purely internal)
 805  * 9904 is hardwired with 4 serial ports
 806  * 9912 and 9922 are hardwired with 2 serial ports
 807  */
 808 static int pci_netmos_9900_numports(struct pci_dev *dev)
 809 {
 810         unsigned int c = dev->class;
 811         unsigned int pi;
 812         unsigned short sub_serports;
 813
 814         pi = (c & 0xff);
 815
 816         if (pi == 2) {
 817                 return 1;
 818         } else if ((pi == 0) &&
 819                            (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 820                 /* two possibilities: 0x30ps encodes number of parallel and
 821                  * serial ports, or 0x1000 indicates *something*. This is not
 822                  * immediately obvious, since the 2s1p+4s configuration seems
 823                  * to offer all functionality on functions 0..2, while still
 824                  * advertising the same function 3 as the 4s+2s1p config.
 825                  */
 826                 sub_serports = dev->subsystem_device & 0xf;
 827                 if (sub_serports > 0) {
 828                         return sub_serports;
 829                 } else {
 830                         printk(KERN_NOTICE "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 831                         return 0;
 832                 }
 833         }
 834
 835         moan_device("unknown NetMos/Mostech program interface", dev);
 836         return 0;
 837 }
 838
 839 static int pci_netmos_init(struct pci_dev *dev)
 840 {
 841         /* subdevice 0x00PS means <P> parallel, <S> serial */
 842         unsigned int num_serial = dev->subsystem_device & 0xf;
 843
 844         if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 845                 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 846                 return 0;
 847
 848         if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 849                         dev->subsystem_device == 0x0299)
 850                 return 0;
 851
 852         switch (dev->device) { /* FALLTHROUGH on all */
 853                 case PCI_DEVICE_ID_NETMOS_9904:
 854                 case PCI_DEVICE_ID_NETMOS_9912:
 855                 case PCI_DEVICE_ID_NETMOS_9922:
 856                 case PCI_DEVICE_ID_NETMOS_9900:
 857                         num_serial = pci_netmos_9900_numports(dev);
 858                         break;
 859
 860                 default:
 861                         if (num_serial == 0 ) {
 862                                 moan_device("unknown NetMos/Mostech device", dev);
 863                         }
 864         }
 865
 866         if (num_serial == 0)
 867                 return -ENODEV;
 868
 869         return num_serial;
 870 }
 871
 872 /*
 873  * These chips are available with optionally one parallel port and up to
 874  * two serial ports. Unfortunately they all have the same product id.
 875  *
 876  * Basic configuration is done over a region of 32 I/O ports. The base
 877  * ioport is called INTA or INTC, depending on docs/other drivers.
 878  *
 879  * The region of the 32 I/O ports is configured in POSIO0R...
 880  */
 881
 882 /* registers */
 883 #define ITE_887x_MISCR          0x9c
 884 #define ITE_887x_INTCBAR        0x78
 885 #define ITE_887x_UARTBAR        0x7c
 886 #define ITE_887x_PS0BAR         0x10
 887 #define ITE_887x_POSIO0         0x60
 888
 889 /* I/O space size */
 890 #define ITE_887x_IOSIZE         32
 891 /* I/O space size (bits 26-24; 8 bytes = 011b) */
 892 #define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 893 /* I/O space size (bits 26-24; 32 bytes = 101b) */
 894 #define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 895 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 896 #define ITE_887x_POSIO_SPEED            (3 << 29)
 897 /* enable IO_Space bit */
 898 #define ITE_887x_POSIO_ENABLE           (1 << 31)
 899
 900 static int pci_ite887x_init(struct pci_dev *dev)
 901 {
 902         /* inta_addr are the configuration addresses of the ITE */
 903         static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 904                                                         0x200, 0x280, 0 };
 905         int ret, i, type;
 906         struct resource *iobase = NULL;
 907         u32 miscr, uartbar, ioport;
 908
 909         /* search for the base-ioport */
 910         i = 0;
 911         while (inta_addr[i] && iobase == NULL) {
 912                 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 913                                                                 "ite887x");
 914                 if (iobase != NULL) {
 915                         /* write POSIO0R - speed | size | ioport */
 916                         pci_write_config_dword(dev, ITE_887x_POSIO0,
 917                                 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 918                                 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 919                         /* write INTCBAR - ioport */
 920                         pci_write_config_dword(dev, ITE_887x_INTCBAR,
 921                                                                 inta_addr[i]);
 922                         ret = inb(inta_addr[i]);
 923                         if (ret != 0xff) {
 924                                 /* ioport connected */
 925                                 break;
 926                         }
 927                         release_region(iobase->start, ITE_887x_IOSIZE);
 928                         iobase = NULL;
 929                 }
 930                 i++;
 931         }
 932
 933         if (!inta_addr[i]) {
 934                 printk(KERN_ERR "ite887x: could not find iobase\n");
 935                 return -ENODEV;
 936         }
 937
 938         /* start of undocumented type checking (see parport_pc.c) */
 939         type = inb(iobase->start + 0x18) & 0x0f;
 940
 941         switch (type) {
 942         case 0x2:       /* ITE8871 (1P) */
 943         case 0xa:       /* ITE8875 (1P) */
 944                 ret = 0;
 945                 break;
 946         case 0xe:       /* ITE8872 (2S1P) */
 947                 ret = 2;
 948                 break;
 949         case 0x6:       /* ITE8873 (1S) */
 950                 ret = 1;
 951                 break;
 952         case 0x8:       /* ITE8874 (2S) */
 953                 ret = 2;
 954                 break;
 955         default:
 956                 moan_device("Unknown ITE887x", dev);
 957                 ret = -ENODEV;
 958         }
 959
 960         /* configure all serial ports */
 961         for (i = 0; i < ret; i++) {
 962                 /* read the I/O port from the device */
 963                 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 964                                                                 &ioport);
 965                 ioport &= 0x0000FF00;   /* the actual base address */
 966                 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 967                         ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 968                         ITE_887x_POSIO_IOSIZE_8 | ioport);
 969
 970                 /* write the ioport to the UARTBAR */
 971                 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 972                 uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 973                 uartbar |= (ioport << (16 * i));        /* set the ioport */
 974                 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 975
 976                 /* get current config */
 977                 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 978                 /* disable interrupts (UARTx_Routing[3:0]) */
 979                 miscr &= ~(0xf << (12 - 4 * i));
 980                 /* activate the UART (UARTx_En) */
 981                 miscr |= 1 << (23 - i);
 982                 /* write new config with activated UART */
 983                 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 984         }
 985
 986         if (ret <= 0) {
 987                 /* the device has no UARTs if we get here */
 988                 release_region(iobase->start, ITE_887x_IOSIZE);
 989         }
 990
 991         return ret;
 992 }
 993
 994 static void pci_ite887x_exit(struct pci_dev *dev)
 995 {
 996         u32 ioport;
 997         /* the ioport is bit 0-15 in POSIO0R */
 998         pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 999         ioport &= 0xffff;
1000         release_region(ioport, ITE_887x_IOSIZE);
1001 }
1002
1003 /*
1004  * Oxford Semiconductor Inc.
1005  * Check that device is part of the Tornado range of devices, then determine
1006  * the number of ports available on the device.
1007  */
1008 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1009 {
1010         u8 __iomem *p;
1011         unsigned long deviceID;
1012         unsigned int  number_uarts = 0;
1013
1014         /* OxSemi Tornado devices are all 0xCxxx */
1015         if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1016             (dev->device & 0xF000) != 0xC000)
1017                 return 0;
1018
1019         p = pci_iomap(dev, 0, 5);
1020         if (p == NULL)
1021                 return -ENOMEM;
1022
1023         deviceID = ioread32(p);
1024         /* Tornado device */
1025         if (deviceID == 0x07000200) {
1026                 number_uarts = ioread8(p + 4);
1027                 printk(KERN_DEBUG
1028                         "%d ports detected on Oxford PCI Express device\n",
1029                                                                 number_uarts);
1030         }
1031         pci_iounmap(dev, p);
1032         return number_uarts;
1033 }
1034
1035 static int pci_asix_setup(struct serial_private *priv,
1036                   const struct pciserial_board *board,
1037                   struct uart_8250_port *port, int idx)
1038 {
1039         port->bugs |= UART_BUG_PARITY;
1040         return pci_default_setup(priv, board, port, idx);
1041 }
1042
1043 /* Quatech devices have their own extra interface features */
1044
1045 struct quatech_feature {
1046         u16 devid;
1047         bool amcc;
1048 };
1049
1050 #define QPCR_TEST_FOR1          0x3F
1051 #define QPCR_TEST_GET1          0x00
1052 #define QPCR_TEST_FOR2          0x40
1053 #define QPCR_TEST_GET2          0x40
1054 #define QPCR_TEST_FOR3          0x80
1055 #define QPCR_TEST_GET3          0x40
1056 #define QPCR_TEST_FOR4          0xC0
1057 #define QPCR_TEST_GET4          0x80
1058
1059 #define QOPR_CLOCK_X1           0x0000
1060 #define QOPR_CLOCK_X2           0x0001
1061 #define QOPR_CLOCK_X4           0x0002
1062 #define QOPR_CLOCK_X8           0x0003
1063 #define QOPR_CLOCK_RATE_MASK    0x0003
1064
1065
1066 static struct quatech_feature quatech_cards[] = {
1067         { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1068         { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1069         { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1070         { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1071         { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1072         { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1073         { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1074         { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1075         { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1076         { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1077         { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1078         { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1079         { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1080         { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1081         { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1082         { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1083         { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1084         { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1085         { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1086         { 0, }
1087 };
1088
1089 static int pci_quatech_amcc(u16 devid)
1090 {
1091         struct quatech_feature *qf = &quatech_cards[0];
1092         while (qf->devid) {
1093                 if (qf->devid == devid)
1094                         return qf->amcc;
1095                 qf++;
1096         }
1097         pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1098         return 0;
1099 };
1100
1101 static int pci_quatech_rqopr(struct uart_8250_port *port)
1102 {
1103         unsigned long base = port->port.iobase;
1104         u8 LCR, val;
1105
1106         LCR = inb(base + UART_LCR);
1107         outb(0xBF, base + UART_LCR);
1108         val = inb(base + UART_SCR);
1109         outb(LCR, base + UART_LCR);
1110         return val;
1111 }
1112
1113 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1114 {
1115         unsigned long base = port->port.iobase;
1116         u8 LCR, val;
1117
1118         LCR = inb(base + UART_LCR);
1119         outb(0xBF, base + UART_LCR);
1120         val = inb(base + UART_SCR);
1121         outb(qopr, base + UART_SCR);
1122         outb(LCR, base + UART_LCR);
1123 }
1124
1125 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1126 {
1127         unsigned long base = port->port.iobase;
1128         u8 LCR, val, qmcr;
1129
1130         LCR = inb(base + UART_LCR);
1131         outb(0xBF, base + UART_LCR);
1132         val = inb(base + UART_SCR);
1133         outb(val | 0x10, base + UART_SCR);
1134         qmcr = inb(base + UART_MCR);
1135         outb(val, base + UART_SCR);
1136         outb(LCR, base + UART_LCR);
1137
1138         return qmcr;
1139 }
1140
1141 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1142 {
1143         unsigned long base = port->port.iobase;
1144         u8 LCR, val;
1145
1146         LCR = inb(base + UART_LCR);
1147         outb(0xBF, base + UART_LCR);
1148         val = inb(base + UART_SCR);
1149         outb(val | 0x10, base + UART_SCR);
1150         outb(qmcr, base + UART_MCR);
1151         outb(val, base + UART_SCR);
1152         outb(LCR, base + UART_LCR);
1153 }
1154
1155 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1156 {
1157         unsigned long base = port->port.iobase;
1158         u8 LCR, val;
1159
1160         LCR = inb(base + UART_LCR);
1161         outb(0xBF, base + UART_LCR);
1162         val = inb(base + UART_SCR);
1163         if (val & 0x20) {
1164                 outb(0x80, UART_LCR);
1165                 if (!(inb(UART_SCR) & 0x20)) {
1166                         outb(LCR, base + UART_LCR);
1167                         return 1;
1168                 }
1169         }
1170         return 0;
1171 }
1172
1173 static int pci_quatech_test(struct uart_8250_port *port)
1174 {
1175         u8 reg;
1176         u8 qopr = pci_quatech_rqopr(port);
1177         pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1178         reg = pci_quatech_rqopr(port) & 0xC0;
1179         if (reg != QPCR_TEST_GET1)
1180                 return -EINVAL;
1181         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1182         reg = pci_quatech_rqopr(port) & 0xC0;
1183         if (reg != QPCR_TEST_GET2)
1184                 return -EINVAL;
1185         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1186         reg = pci_quatech_rqopr(port) & 0xC0;
1187         if (reg != QPCR_TEST_GET3)
1188                 return -EINVAL;
1189         pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1190         reg = pci_quatech_rqopr(port) & 0xC0;
1191         if (reg != QPCR_TEST_GET4)
1192                 return -EINVAL;
1193
1194         pci_quatech_wqopr(port, qopr);
1195         return 0;
1196 }
1197
1198 static int pci_quatech_clock(struct uart_8250_port *port)
1199 {
1200         u8 qopr, reg, set;
1201         unsigned long clock;
1202
1203         if (pci_quatech_test(port) < 0)
1204                 return 1843200;
1205
1206         qopr = pci_quatech_rqopr(port);
1207
1208         pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1209         reg = pci_quatech_rqopr(port);
1210         if (reg & QOPR_CLOCK_X8) {
1211                 clock = 1843200;
1212                 goto out;
1213         }
1214         pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1215         reg = pci_quatech_rqopr(port);
1216         if (!(reg & QOPR_CLOCK_X8)) {
1217                 clock = 1843200;
1218                 goto out;
1219         }
1220         reg &= QOPR_CLOCK_X8;
1221         if (reg == QOPR_CLOCK_X2) {
1222                 clock =  3685400;
1223                 set = QOPR_CLOCK_X2;
1224         } else if (reg == QOPR_CLOCK_X4) {
1225                 clock = 7372800;
1226                 set = QOPR_CLOCK_X4;
1227         } else if (reg == QOPR_CLOCK_X8) {
1228                 clock = 14745600;
1229                 set = QOPR_CLOCK_X8;
1230         } else {
1231                 clock = 1843200;
1232                 set = QOPR_CLOCK_X1;
1233         }
1234         qopr &= ~QOPR_CLOCK_RATE_MASK;
1235         qopr |= set;
1236
1237 out:
1238         pci_quatech_wqopr(port, qopr);
1239         return clock;
1240 }
1241
1242 static int pci_quatech_rs422(struct uart_8250_port *port)
1243 {
1244         u8 qmcr;
1245         int rs422 = 0;
1246
1247         if (!pci_quatech_has_qmcr(port))
1248                 return 0;
1249         qmcr = pci_quatech_rqmcr(port);
1250         pci_quatech_wqmcr(port, 0xFF);
1251         if (pci_quatech_rqmcr(port))
1252                 rs422 = 1;
1253         pci_quatech_wqmcr(port, qmcr);
1254         return rs422;
1255 }
1256
1257 static int pci_quatech_init(struct pci_dev *dev)
1258 {
1259         if (pci_quatech_amcc(dev->device)) {
1260                 unsigned long base = pci_resource_start(dev, 0);
1261                 if (base) {
1262                         u32 tmp;
1263                         outl(inl(base + 0x38), base + 0x38);
1264                         tmp = inl(base + 0x3c);
1265                         outl(tmp | 0x01000000, base + 0x3c);
1266                         outl(tmp, base + 0x3c);
1267                 }
1268         }
1269         return 0;
1270 }
1271
1272 static int pci_quatech_setup(struct serial_private *priv,
1273                   const struct pciserial_board *board,
1274                   struct uart_8250_port *port, int idx)
1275 {
1276         /* Needed by pci_quatech calls below */
1277         port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1278         /* Set up the clocking */
1279         port->port.uartclk = pci_quatech_clock(port);
1280         /* For now just warn about RS422 */
1281         if (pci_quatech_rs422(port))
1282                 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1283         return pci_default_setup(priv, board, port, idx);
1284 }
1285
1286 static void pci_quatech_exit(struct pci_dev *dev)
1287 {
1288 }
1289
1290 static int pci_default_setup(struct serial_private *priv,
1291                   const struct pciserial_board *board,
1292                   struct uart_8250_port *port, int idx)
1293 {
1294         unsigned int bar, offset = board->first_offset, maxnr;
1295
1296         bar = FL_GET_BASE(board->flags);
1297         if (board->flags & FL_BASE_BARS)
1298                 bar += idx;
1299         else
1300                 offset += idx * board->uart_offset;
1301
1302         maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1303                 (board->reg_shift + 3);
1304
1305         if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1306                 return 1;
1307
1308         return setup_port(priv, port, bar, offset, board->reg_shift);
1309 }
1310
1311 static int
1312 ce4100_serial_setup(struct serial_private *priv,
1313                   const struct pciserial_board *board,
1314                   struct uart_8250_port *port, int idx)
1315 {
1316         int ret;
1317
1318         ret = setup_port(priv, port, idx, 0, board->reg_shift);
1319         port->port.iotype = UPIO_MEM32;
1320         port->port.type = PORT_XSCALE;
1321         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1322         port->port.regshift = 2;
1323
1324         return ret;
1325 }
1326
1327 static int
1328 pci_omegapci_setup(struct serial_private *priv,
1329                       const struct pciserial_board *board,
1330                       struct uart_8250_port *port, int idx)
1331 {
1332         return setup_port(priv, port, 2, idx * 8, 0);
1333 }
1334
1335 static int
1336 pci_brcm_trumanage_setup(struct serial_private *priv,
1337                          const struct pciserial_board *board,
1338                          struct uart_8250_port *port, int idx)
1339 {
1340         int ret = pci_default_setup(priv, board, port, idx);
1341
1342         port->port.type = PORT_BRCM_TRUMANAGE;
1343         port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1344         return ret;
1345 }
1346
1347 static int skip_tx_en_setup(struct serial_private *priv,
1348                         const struct pciserial_board *board,
1349                         struct uart_8250_port *port, int idx)
1350 {
1351         port->port.flags |= UPF_NO_TXEN_TEST;
1352         printk(KERN_DEBUG "serial8250: skipping TxEn test for device "
1353                           "[%04x:%04x] subsystem [%04x:%04x]\n",
1354                           priv->dev->vendor,
1355                           priv->dev->device,
1356                           priv->dev->subsystem_vendor,
1357                           priv->dev->subsystem_device);
1358
1359         return pci_default_setup(priv, board, port, idx);
1360 }
1361
1362 static void kt_handle_break(struct uart_port *p)
1363 {
1364         struct uart_8250_port *up =
1365                 container_of(p, struct uart_8250_port, port);
1366         /*
1367          * On receipt of a BI, serial device in Intel ME (Intel
1368          * management engine) needs to have its fifos cleared for sane
1369          * SOL (Serial Over Lan) output.
1370          */
1371         serial8250_clear_and_reinit_fifos(up);
1372 }
1373
1374 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1375 {
1376         struct uart_8250_port *up =
1377                 container_of(p, struct uart_8250_port, port);
1378         unsigned int val;
1379
1380         /*
1381          * When the Intel ME (management engine) gets reset its serial
1382          * port registers could return 0 momentarily.  Functions like
1383          * serial8250_console_write, read and save the IER, perform
1384          * some operation and then restore it.  In order to avoid
1385          * setting IER register inadvertently to 0, if the value read
1386          * is 0, double check with ier value in uart_8250_port and use
1387          * that instead.  up->ier should be the same value as what is
1388          * currently configured.
1389          */
1390         val = inb(p->iobase + offset);
1391         if (offset == UART_IER) {
1392                 if (val == 0)
1393                         val = up->ier;
1394         }
1395         return val;
1396 }
1397
1398 static int kt_serial_setup(struct serial_private *priv,
1399                            const struct pciserial_board *board,
1400                            struct uart_8250_port *port, int idx)
1401 {
1402         port->port.flags |= UPF_BUG_THRE;
1403         port->port.serial_in = kt_serial_in;
1404         port->port.handle_break = kt_handle_break;
1405         return skip_tx_en_setup(priv, board, port, idx);
1406 }
1407
1408 static int pci_eg20t_init(struct pci_dev *dev)
1409 {
1410 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1411         return -ENODEV;
1412 #else
1413         return 0;
1414 #endif
1415 }
1416
1417 static int
1418 pci_xr17c154_setup(struct serial_private *priv,
1419                   const struct pciserial_board *board,
1420                   struct uart_8250_port *port, int idx)
1421 {
1422         port->port.flags |= UPF_EXAR_EFR;
1423         return pci_default_setup(priv, board, port, idx);
1424 }
1425
1426 static int
1427 pci_xr17v35x_setup(struct serial_private *priv,
1428                   const struct pciserial_board *board,
1429                   struct uart_8250_port *port, int idx)
1430 {
1431         u8 __iomem *p;
1432
1433         p = pci_ioremap_bar(priv->dev, 0);
1434         if (p == NULL)
1435                 return -ENOMEM;
1436
1437         port->port.flags |= UPF_EXAR_EFR;
1438
1439         /*
1440          * Setup Multipurpose Input/Output pins.
1441          */
1442         if (idx == 0) {
1443                 writeb(0x00, p + 0x8f); /*MPIOINT[7:0]*/
1444                 writeb(0x00, p + 0x90); /*MPIOLVL[7:0]*/
1445                 writeb(0x00, p + 0x91); /*MPIO3T[7:0]*/
1446                 writeb(0x00, p + 0x92); /*MPIOINV[7:0]*/
1447                 writeb(0x00, p + 0x93); /*MPIOSEL[7:0]*/
1448                 writeb(0x00, p + 0x94); /*MPIOOD[7:0]*/
1449                 writeb(0x00, p + 0x95); /*MPIOINT[15:8]*/
1450                 writeb(0x00, p + 0x96); /*MPIOLVL[15:8]*/
1451                 writeb(0x00, p + 0x97); /*MPIO3T[15:8]*/
1452                 writeb(0x00, p + 0x98); /*MPIOINV[15:8]*/
1453                 writeb(0x00, p + 0x99); /*MPIOSEL[15:8]*/
1454                 writeb(0x00, p + 0x9a); /*MPIOOD[15:8]*/
1455         }
1456         writeb(0x00, p + UART_EXAR_8XMODE);
1457         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1458         writeb(128, p + UART_EXAR_TXTRG);
1459         writeb(128, p + UART_EXAR_RXTRG);
1460         iounmap(p);
1461
1462         return pci_default_setup(priv, board, port, idx);
1463 }
1464
1465 #define PCI_DEVICE_ID_COMMTECH_4222PCI335 0x0004
1466 #define PCI_DEVICE_ID_COMMTECH_4224PCI335 0x0002
1467 #define PCI_DEVICE_ID_COMMTECH_2324PCI335 0x000a
1468 #define PCI_DEVICE_ID_COMMTECH_2328PCI335 0x000b
1469
1470 static int
1471 pci_fastcom335_setup(struct serial_private *priv,
1472                   const struct pciserial_board *board,
1473                   struct uart_8250_port *port, int idx)
1474 {
1475         u8 __iomem *p;
1476
1477         p = pci_ioremap_bar(priv->dev, 0);
1478         if (p == NULL)
1479                 return -ENOMEM;
1480
1481         port->port.flags |= UPF_EXAR_EFR;
1482
1483         /*
1484          * Setup Multipurpose Input/Output pins.
1485          */
1486         if (idx == 0) {
1487                 switch (priv->dev->device) {
1488                 case PCI_DEVICE_ID_COMMTECH_4222PCI335:
1489                 case PCI_DEVICE_ID_COMMTECH_4224PCI335:
1490                         writeb(0x78, p + 0x90); /* MPIOLVL[7:0] */
1491                         writeb(0x00, p + 0x92); /* MPIOINV[7:0] */
1492                         writeb(0x00, p + 0x93); /* MPIOSEL[7:0] */
1493                         break;
1494                 case PCI_DEVICE_ID_COMMTECH_2324PCI335:
1495                 case PCI_DEVICE_ID_COMMTECH_2328PCI335:
1496                         writeb(0x00, p + 0x90); /* MPIOLVL[7:0] */
1497                         writeb(0xc0, p + 0x92); /* MPIOINV[7:0] */
1498                         writeb(0xc0, p + 0x93); /* MPIOSEL[7:0] */
1499                         break;
1500                 }
1501                 writeb(0x00, p + 0x8f); /* MPIOINT[7:0] */
1502                 writeb(0x00, p + 0x91); /* MPIO3T[7:0] */
1503                 writeb(0x00, p + 0x94); /* MPIOOD[7:0] */
1504         }
1505         writeb(0x00, p + UART_EXAR_8XMODE);
1506         writeb(UART_FCTR_EXAR_TRGD, p + UART_EXAR_FCTR);
1507         writeb(32, p + UART_EXAR_TXTRG);
1508         writeb(32, p + UART_EXAR_RXTRG);
1509         iounmap(p);
1510
1511         return pci_default_setup(priv, board, port, idx);
1512 }
1513
1514 static int
1515 pci_wch_ch353_setup(struct serial_private *priv,
1516                     const struct pciserial_board *board,
1517                     struct uart_8250_port *port, int idx)
1518 {
1519         port->port.flags |= UPF_FIXED_TYPE;
1520         port->port.type = PORT_16550A;
1521         return pci_default_setup(priv, board, port, idx);
1522 }
1523
1524 #define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1525 #define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1526 #define PCI_DEVICE_ID_OCTPRO            0x0001
1527 #define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1528 #define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1529 #define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1530 #define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1531 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1532 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1533 #define PCI_VENDOR_ID_ADVANTECH         0x13fe
1534 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1535 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1536 #define PCI_DEVICE_ID_TITAN_200I        0x8028
1537 #define PCI_DEVICE_ID_TITAN_400I        0x8048
1538 #define PCI_DEVICE_ID_TITAN_800I        0x8088
1539 #define PCI_DEVICE_ID_TITAN_800EH       0xA007
1540 #define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1541 #define PCI_DEVICE_ID_TITAN_400EH       0xA009
1542 #define PCI_DEVICE_ID_TITAN_100E        0xA010
1543 #define PCI_DEVICE_ID_TITAN_200E        0xA012
1544 #define PCI_DEVICE_ID_TITAN_400E        0xA013
1545 #define PCI_DEVICE_ID_TITAN_800E        0xA014
1546 #define PCI_DEVICE_ID_TITAN_200EI       0xA016
1547 #define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1548 #define PCI_DEVICE_ID_TITAN_400V3       0xA310
1549 #define PCI_DEVICE_ID_TITAN_410V3       0xA312
1550 #define PCI_DEVICE_ID_TITAN_800V3       0xA314
1551 #define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1552 #define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1553 #define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1554 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1555 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1556 #define PCI_VENDOR_ID_WCH               0x4348
1557 #define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1558 #define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1559 #define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1560 #define PCI_VENDOR_ID_AGESTAR           0x5372
1561 #define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1562 #define PCI_VENDOR_ID_ASIX              0x9710
1563 #define PCI_DEVICE_ID_COMMTECH_4224PCIE 0x0020
1564 #define PCI_DEVICE_ID_COMMTECH_4228PCIE 0x0021
1565 #define PCI_DEVICE_ID_COMMTECH_4222PCIE 0x0022
1566 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1567
1568 #define PCI_VENDOR_ID_SUNIX             0x1fd4
1569 #define PCI_DEVICE_ID_SUNIX_1999        0x1999
1570
1571
1572 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1573 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1574 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1575
1576 /*
1577  * Master list of serial port init/setup/exit quirks.
1578  * This does not describe the general nature of the port.
1579  * (ie, baud base, number and location of ports, etc)
1580  *
1581  * This list is ordered alphabetically by vendor then device.
1582  * Specific entries must come before more generic entries.
1583  */
1584 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1585         /*
1586         * ADDI-DATA GmbH communication cards <info@addi-data.com>
1587         */
1588         {
1589                 .vendor         = PCI_VENDOR_ID_ADDIDATA_OLD,
1590                 .device         = PCI_DEVICE_ID_ADDIDATA_APCI7800,
1591                 .subvendor      = PCI_ANY_ID,
1592                 .subdevice      = PCI_ANY_ID,
1593                 .setup          = addidata_apci7800_setup,
1594         },
1595         /*
1596          * AFAVLAB cards - these may be called via parport_serial
1597          *  It is not clear whether this applies to all products.
1598          */
1599         {
1600                 .vendor         = PCI_VENDOR_ID_AFAVLAB,
1601                 .device         = PCI_ANY_ID,
1602                 .subvendor      = PCI_ANY_ID,
1603                 .subdevice      = PCI_ANY_ID,
1604                 .setup          = afavlab_setup,
1605         },
1606         /*
1607          * HP Diva
1608          */
1609         {
1610                 .vendor         = PCI_VENDOR_ID_HP,
1611                 .device         = PCI_DEVICE_ID_HP_DIVA,
1612                 .subvendor      = PCI_ANY_ID,
1613                 .subdevice      = PCI_ANY_ID,
1614                 .init           = pci_hp_diva_init,
1615                 .setup          = pci_hp_diva_setup,
1616         },
1617         /*
1618          * Intel
1619          */
1620         {
1621                 .vendor         = PCI_VENDOR_ID_INTEL,
1622                 .device         = PCI_DEVICE_ID_INTEL_80960_RP,
1623                 .subvendor      = 0xe4bf,
1624                 .subdevice      = PCI_ANY_ID,
1625                 .init           = pci_inteli960ni_init,
1626                 .setup          = pci_default_setup,
1627         },
1628         {
1629                 .vendor         = PCI_VENDOR_ID_INTEL,
1630                 .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
1631                 .subvendor      = PCI_ANY_ID,
1632                 .subdevice      = PCI_ANY_ID,
1633                 .setup          = skip_tx_en_setup,
1634         },
1635         {
1636                 .vendor         = PCI_VENDOR_ID_INTEL,
1637                 .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
1638                 .subvendor      = PCI_ANY_ID,
1639                 .subdevice      = PCI_ANY_ID,
1640                 .setup          = skip_tx_en_setup,
1641         },
1642         {
1643                 .vendor         = PCI_VENDOR_ID_INTEL,
1644                 .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
1645                 .subvendor      = PCI_ANY_ID,
1646                 .subdevice      = PCI_ANY_ID,
1647                 .setup          = skip_tx_en_setup,
1648         },
1649         {
1650                 .vendor         = PCI_VENDOR_ID_INTEL,
1651                 .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
1652                 .subvendor      = PCI_ANY_ID,
1653                 .subdevice      = PCI_ANY_ID,
1654                 .setup          = ce4100_serial_setup,
1655         },
1656         {
1657                 .vendor         = PCI_VENDOR_ID_INTEL,
1658                 .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1659                 .subvendor      = PCI_ANY_ID,
1660                 .subdevice      = PCI_ANY_ID,
1661                 .setup          = kt_serial_setup,
1662         },
1663         /*
1664          * ITE
1665          */
1666         {
1667                 .vendor         = PCI_VENDOR_ID_ITE,
1668                 .device         = PCI_DEVICE_ID_ITE_8872,
1669                 .subvendor      = PCI_ANY_ID,
1670                 .subdevice      = PCI_ANY_ID,
1671                 .init           = pci_ite887x_init,
1672                 .setup          = pci_default_setup,
1673                 .exit           = pci_ite887x_exit,
1674         },
1675         /*
1676          * National Instruments
1677          */
1678         {
1679                 .vendor         = PCI_VENDOR_ID_NI,
1680                 .device         = PCI_DEVICE_ID_NI_PCI23216,
1681                 .subvendor      = PCI_ANY_ID,
1682                 .subdevice      = PCI_ANY_ID,
1683                 .init           = pci_ni8420_init,
1684                 .setup          = pci_default_setup,
1685                 .exit           = pci_ni8420_exit,
1686         },
1687         {
1688                 .vendor         = PCI_VENDOR_ID_NI,
1689                 .device         = PCI_DEVICE_ID_NI_PCI2328,
1690                 .subvendor      = PCI_ANY_ID,
1691                 .subdevice      = PCI_ANY_ID,
1692                 .init           = pci_ni8420_init,
1693                 .setup          = pci_default_setup,
1694                 .exit           = pci_ni8420_exit,
1695         },
1696         {
1697                 .vendor         = PCI_VENDOR_ID_NI,
1698                 .device         = PCI_DEVICE_ID_NI_PCI2324,
1699                 .subvendor      = PCI_ANY_ID,
1700                 .subdevice      = PCI_ANY_ID,
1701                 .init           = pci_ni8420_init,
1702                 .setup          = pci_default_setup,
1703                 .exit           = pci_ni8420_exit,
1704         },
1705         {
1706                 .vendor         = PCI_VENDOR_ID_NI,
1707                 .device         = PCI_DEVICE_ID_NI_PCI2322,
1708                 .subvendor      = PCI_ANY_ID,
1709                 .subdevice      = PCI_ANY_ID,
1710                 .init           = pci_ni8420_init,
1711                 .setup          = pci_default_setup,
1712                 .exit           = pci_ni8420_exit,
1713         },
1714         {
1715                 .vendor         = PCI_VENDOR_ID_NI,
1716                 .device         = PCI_DEVICE_ID_NI_PCI2324I,
1717                 .subvendor      = PCI_ANY_ID,
1718                 .subdevice      = PCI_ANY_ID,
1719                 .init           = pci_ni8420_init,
1720                 .setup          = pci_default_setup,
1721                 .exit           = pci_ni8420_exit,
1722         },
1723         {
1724                 .vendor         = PCI_VENDOR_ID_NI,
1725                 .device         = PCI_DEVICE_ID_NI_PCI2322I,
1726                 .subvendor      = PCI_ANY_ID,
1727                 .subdevice      = PCI_ANY_ID,
1728                 .init           = pci_ni8420_init,
1729                 .setup          = pci_default_setup,
1730                 .exit           = pci_ni8420_exit,
1731         },
1732         {
1733                 .vendor         = PCI_VENDOR_ID_NI,
1734                 .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
1735                 .subvendor      = PCI_ANY_ID,
1736                 .subdevice      = PCI_ANY_ID,
1737                 .init           = pci_ni8420_init,
1738                 .setup          = pci_default_setup,
1739                 .exit           = pci_ni8420_exit,
1740         },
1741         {
1742                 .vendor         = PCI_VENDOR_ID_NI,
1743                 .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
1744                 .subvendor      = PCI_ANY_ID,
1745                 .subdevice      = PCI_ANY_ID,
1746                 .init           = pci_ni8420_init,
1747                 .setup          = pci_default_setup,
1748                 .exit           = pci_ni8420_exit,
1749         },
1750         {
1751                 .vendor         = PCI_VENDOR_ID_NI,
1752                 .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
1753                 .subvendor      = PCI_ANY_ID,
1754                 .subdevice      = PCI_ANY_ID,
1755                 .init           = pci_ni8420_init,
1756                 .setup          = pci_default_setup,
1757                 .exit           = pci_ni8420_exit,
1758         },
1759         {
1760                 .vendor         = PCI_VENDOR_ID_NI,
1761                 .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
1762                 .subvendor      = PCI_ANY_ID,
1763                 .subdevice      = PCI_ANY_ID,
1764                 .init           = pci_ni8420_init,
1765                 .setup          = pci_default_setup,
1766                 .exit           = pci_ni8420_exit,
1767         },
1768         {
1769                 .vendor         = PCI_VENDOR_ID_NI,
1770                 .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
1771                 .subvendor      = PCI_ANY_ID,
1772                 .subdevice      = PCI_ANY_ID,
1773                 .init           = pci_ni8420_init,
1774                 .setup          = pci_default_setup,
1775                 .exit           = pci_ni8420_exit,
1776         },
1777         {
1778                 .vendor         = PCI_VENDOR_ID_NI,
1779                 .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
1780                 .subvendor      = PCI_ANY_ID,
1781                 .subdevice      = PCI_ANY_ID,
1782                 .init           = pci_ni8420_init,
1783                 .setup          = pci_default_setup,
1784                 .exit           = pci_ni8420_exit,
1785         },
1786         {
1787                 .vendor         = PCI_VENDOR_ID_NI,
1788                 .device         = PCI_ANY_ID,
1789                 .subvendor      = PCI_ANY_ID,
1790                 .subdevice      = PCI_ANY_ID,
1791                 .init           = pci_ni8430_init,
1792                 .setup          = pci_ni8430_setup,
1793                 .exit           = pci_ni8430_exit,
1794         },
1795         /* Quatech */
1796         {
1797                 .vendor         = PCI_VENDOR_ID_QUATECH,
1798                 .device         = PCI_ANY_ID,
1799                 .subvendor      = PCI_ANY_ID,
1800                 .subdevice      = PCI_ANY_ID,
1801                 .init           = pci_quatech_init,
1802                 .setup          = pci_quatech_setup,
1803                 .exit           = pci_quatech_exit,
1804         },
1805         /*
1806          * Panacom
1807          */
1808         {
1809                 .vendor         = PCI_VENDOR_ID_PANACOM,
1810                 .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1811                 .subvendor      = PCI_ANY_ID,
1812                 .subdevice      = PCI_ANY_ID,
1813                 .init           = pci_plx9050_init,
1814                 .setup          = pci_default_setup,
1815                 .exit           = pci_plx9050_exit,
1816         },
1817         {
1818                 .vendor         = PCI_VENDOR_ID_PANACOM,
1819                 .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1820                 .subvendor      = PCI_ANY_ID,
1821                 .subdevice      = PCI_ANY_ID,
1822                 .init           = pci_plx9050_init,
1823                 .setup          = pci_default_setup,
1824                 .exit           = pci_plx9050_exit,
1825         },
1826         /*
1827          * PLX
1828          */
1829         {
1830                 .vendor         = PCI_VENDOR_ID_PLX,
1831                 .device         = PCI_DEVICE_ID_PLX_9030,
1832                 .subvendor      = PCI_SUBVENDOR_ID_PERLE,
1833                 .subdevice      = PCI_ANY_ID,
1834                 .setup          = pci_default_setup,
1835         },
1836         {
1837                 .vendor         = PCI_VENDOR_ID_PLX,
1838                 .device         = PCI_DEVICE_ID_PLX_9050,
1839                 .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
1840                 .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
1841                 .init           = pci_plx9050_init,
1842                 .setup          = pci_default_setup,
1843                 .exit           = pci_plx9050_exit,
1844         },
1845         {
1846                 .vendor         = PCI_VENDOR_ID_PLX,
1847                 .device         = PCI_DEVICE_ID_PLX_9050,
1848                 .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
1849                 .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
1850                 .init           = pci_plx9050_init,
1851                 .setup          = pci_default_setup,
1852                 .exit           = pci_plx9050_exit,
1853         },
1854         {
1855                 .vendor         = PCI_VENDOR_ID_PLX,
1856                 .device         = PCI_DEVICE_ID_PLX_ROMULUS,
1857                 .subvendor      = PCI_VENDOR_ID_PLX,
1858                 .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
1859                 .init           = pci_plx9050_init,
1860                 .setup          = pci_default_setup,
1861                 .exit           = pci_plx9050_exit,
1862         },
1863         /*
1864          * SBS Technologies, Inc., PMC-OCTALPRO 232
1865          */
1866         {
1867                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1868                 .device         = PCI_DEVICE_ID_OCTPRO,
1869                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1870                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
1871                 .init           = sbs_init,
1872                 .setup          = sbs_setup,
1873                 .exit           = sbs_exit,
1874         },
1875         /*
1876          * SBS Technologies, Inc., PMC-OCTALPRO 422
1877          */
1878         {
1879                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1880                 .device         = PCI_DEVICE_ID_OCTPRO,
1881                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1882                 .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
1883                 .init           = sbs_init,
1884                 .setup          = sbs_setup,
1885                 .exit           = sbs_exit,
1886         },
1887         /*
1888          * SBS Technologies, Inc., P-Octal 232
1889          */
1890         {
1891                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1892                 .device         = PCI_DEVICE_ID_OCTPRO,
1893                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1894                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
1895                 .init           = sbs_init,
1896                 .setup          = sbs_setup,
1897                 .exit           = sbs_exit,
1898         },
1899         /*
1900          * SBS Technologies, Inc., P-Octal 422
1901          */
1902         {
1903                 .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
1904                 .device         = PCI_DEVICE_ID_OCTPRO,
1905                 .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
1906                 .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
1907                 .init           = sbs_init,
1908                 .setup          = sbs_setup,
1909                 .exit           = sbs_exit,
1910         },
1911         /*
1912          * SIIG cards - these may be called via parport_serial
1913          */
1914         {
1915                 .vendor         = PCI_VENDOR_ID_SIIG,
1916                 .device         = PCI_ANY_ID,
1917                 .subvendor      = PCI_ANY_ID,
1918                 .subdevice      = PCI_ANY_ID,
1919                 .init           = pci_siig_init,
1920                 .setup          = pci_siig_setup,
1921         },
1922         /*
1923          * Titan cards
1924          */
1925         {
1926                 .vendor         = PCI_VENDOR_ID_TITAN,
1927                 .device         = PCI_DEVICE_ID_TITAN_400L,
1928                 .subvendor      = PCI_ANY_ID,
1929                 .subdevice      = PCI_ANY_ID,
1930                 .setup          = titan_400l_800l_setup,
1931         },
1932         {
1933                 .vendor         = PCI_VENDOR_ID_TITAN,
1934                 .device         = PCI_DEVICE_ID_TITAN_800L,
1935                 .subvendor      = PCI_ANY_ID,
1936                 .subdevice      = PCI_ANY_ID,
1937                 .setup          = titan_400l_800l_setup,
1938         },
1939         /*
1940          * Timedia cards
1941          */
1942         {
1943                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1944                 .device         = PCI_DEVICE_ID_TIMEDIA_1889,
1945                 .subvendor      = PCI_VENDOR_ID_TIMEDIA,
1946                 .subdevice      = PCI_ANY_ID,
1947                 .probe          = pci_timedia_probe,
1948                 .init           = pci_timedia_init,
1949                 .setup          = pci_timedia_setup,
1950         },
1951         {
1952                 .vendor         = PCI_VENDOR_ID_TIMEDIA,
1953                 .device         = PCI_ANY_ID,
1954                 .subvendor      = PCI_ANY_ID,
1955                 .subdevice      = PCI_ANY_ID,
1956                 .setup          = pci_timedia_setup,
1957         },
1958         /*
1959          * SUNIX (Timedia) cards
1960          * Do not "probe" for these cards as there is at least one combination
1961          * card that should be handled by parport_pc that doesn't match the
1962          * rule in pci_timedia_probe.
1963          * It is part number is MIO5079A but its subdevice ID is 0x0102.
1964          * There are some boards with part number SER5037AL that report
1965          * subdevice ID 0x0002.
1966          */
1967         {
1968                 .vendor         = PCI_VENDOR_ID_SUNIX,
1969                 .device         = PCI_DEVICE_ID_SUNIX_1999,
1970                 .subvendor      = PCI_VENDOR_ID_SUNIX,
1971                 .subdevice      = PCI_ANY_ID,
1972                 .init           = pci_timedia_init,
1973                 .setup          = pci_timedia_setup,
1974         },
1975         /*
1976          * Exar cards
1977          */
1978         {
1979                 .vendor = PCI_VENDOR_ID_EXAR,
1980                 .device = PCI_DEVICE_ID_EXAR_XR17C152,
1981                 .subvendor      = PCI_ANY_ID,
1982                 .subdevice      = PCI_ANY_ID,
1983                 .setup          = pci_xr17c154_setup,
1984         },
1985         {
1986                 .vendor = PCI_VENDOR_ID_EXAR,
1987                 .device = PCI_DEVICE_ID_EXAR_XR17C154,
1988                 .subvendor      = PCI_ANY_ID,
1989                 .subdevice      = PCI_ANY_ID,
1990                 .setup          = pci_xr17c154_setup,
1991         },
1992         {
1993                 .vendor = PCI_VENDOR_ID_EXAR,
1994                 .device = PCI_DEVICE_ID_EXAR_XR17C158,
1995                 .subvendor      = PCI_ANY_ID,
1996                 .subdevice      = PCI_ANY_ID,
1997                 .setup          = pci_xr17c154_setup,
1998         },
1999         {
2000                 .vendor = PCI_VENDOR_ID_EXAR,
2001                 .device = PCI_DEVICE_ID_EXAR_XR17V352,
2002                 .subvendor      = PCI_ANY_ID,
2003                 .subdevice      = PCI_ANY_ID,
2004                 .setup          = pci_xr17v35x_setup,
2005         },
2006         {
2007                 .vendor = PCI_VENDOR_ID_EXAR,
2008                 .device = PCI_DEVICE_ID_EXAR_XR17V354,
2009                 .subvendor      = PCI_ANY_ID,
2010                 .subdevice      = PCI_ANY_ID,
2011                 .setup          = pci_xr17v35x_setup,
2012         },
2013         {
2014                 .vendor = PCI_VENDOR_ID_EXAR,
2015                 .device = PCI_DEVICE_ID_EXAR_XR17V358,
2016                 .subvendor      = PCI_ANY_ID,
2017                 .subdevice      = PCI_ANY_ID,
2018                 .setup          = pci_xr17v35x_setup,
2019         },
2020         /*
2021          * Xircom cards
2022          */
2023         {
2024                 .vendor         = PCI_VENDOR_ID_XIRCOM,
2025                 .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2026                 .subvendor      = PCI_ANY_ID,
2027                 .subdevice      = PCI_ANY_ID,
2028                 .init           = pci_xircom_init,
2029                 .setup          = pci_default_setup,
2030         },
2031         /*
2032          * Netmos cards - these may be called via parport_serial
2033          */
2034         {
2035                 .vendor         = PCI_VENDOR_ID_NETMOS,
2036                 .device         = PCI_ANY_ID,
2037                 .subvendor      = PCI_ANY_ID,
2038                 .subdevice      = PCI_ANY_ID,
2039                 .init           = pci_netmos_init,
2040                 .setup          = pci_netmos_9900_setup,
2041         },
2042         /*
2043          * For Oxford Semiconductor Tornado based devices
2044          */
2045         {
2046                 .vendor         = PCI_VENDOR_ID_OXSEMI,
2047                 .device         = PCI_ANY_ID,
2048                 .subvendor      = PCI_ANY_ID,
2049                 .subdevice      = PCI_ANY_ID,
2050                 .init           = pci_oxsemi_tornado_init,
2051                 .setup          = pci_default_setup,
2052         },
2053         {
2054                 .vendor         = PCI_VENDOR_ID_MAINPINE,
2055                 .device         = PCI_ANY_ID,
2056                 .subvendor      = PCI_ANY_ID,
2057                 .subdevice      = PCI_ANY_ID,
2058                 .init           = pci_oxsemi_tornado_init,
2059                 .setup          = pci_default_setup,
2060         },
2061         {
2062                 .vendor         = PCI_VENDOR_ID_DIGI,
2063                 .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2064                 .subvendor              = PCI_SUBVENDOR_ID_IBM,
2065                 .subdevice              = PCI_ANY_ID,
2066                 .init                   = pci_oxsemi_tornado_init,
2067                 .setup          = pci_default_setup,
2068         },
2069         {
2070                 .vendor         = PCI_VENDOR_ID_INTEL,
2071                 .device         = 0x8811,
2072                 .subvendor      = PCI_ANY_ID,
2073                 .subdevice      = PCI_ANY_ID,
2074                 .init           = pci_eg20t_init,
2075                 .setup          = pci_default_setup,
2076         },
2077         {
2078                 .vendor         = PCI_VENDOR_ID_INTEL,
2079                 .device         = 0x8812,
2080                 .subvendor      = PCI_ANY_ID,
2081                 .subdevice      = PCI_ANY_ID,
2082                 .init           = pci_eg20t_init,
2083                 .setup          = pci_default_setup,
2084         },
2085         {
2086                 .vendor         = PCI_VENDOR_ID_INTEL,
2087                 .device         = 0x8813,
2088                 .subvendor      = PCI_ANY_ID,
2089                 .subdevice      = PCI_ANY_ID,
2090                 .init           = pci_eg20t_init,
2091                 .setup          = pci_default_setup,
2092         },
2093         {
2094                 .vendor         = PCI_VENDOR_ID_INTEL,
2095                 .device         = 0x8814,
2096                 .subvendor      = PCI_ANY_ID,
2097                 .subdevice      = PCI_ANY_ID,
2098                 .init           = pci_eg20t_init,
2099                 .setup          = pci_default_setup,
2100         },
2101         {
2102                 .vendor         = 0x10DB,
2103                 .device         = 0x8027,
2104                 .subvendor      = PCI_ANY_ID,
2105                 .subdevice      = PCI_ANY_ID,
2106                 .init           = pci_eg20t_init,
2107                 .setup          = pci_default_setup,
2108         },
2109         {
2110                 .vendor         = 0x10DB,
2111                 .device         = 0x8028,
2112                 .subvendor      = PCI_ANY_ID,
2113                 .subdevice      = PCI_ANY_ID,
2114                 .init           = pci_eg20t_init,
2115                 .setup          = pci_default_setup,
2116         },
2117         {
2118                 .vendor         = 0x10DB,
2119                 .device         = 0x8029,
2120                 .subvendor      = PCI_ANY_ID,
2121                 .subdevice      = PCI_ANY_ID,
2122                 .init           = pci_eg20t_init,
2123                 .setup          = pci_default_setup,
2124         },
2125         {
2126                 .vendor         = 0x10DB,
2127                 .device         = 0x800C,
2128                 .subvendor      = PCI_ANY_ID,
2129                 .subdevice      = PCI_ANY_ID,
2130                 .init           = pci_eg20t_init,
2131                 .setup          = pci_default_setup,
2132         },
2133         {
2134                 .vendor         = 0x10DB,
2135                 .device         = 0x800D,
2136                 .subvendor      = PCI_ANY_ID,
2137                 .subdevice      = PCI_ANY_ID,
2138                 .init           = pci_eg20t_init,
2139                 .setup          = pci_default_setup,
2140         },
2141         /*
2142          * Cronyx Omega PCI (PLX-chip based)
2143          */
2144         {
2145                 .vendor         = PCI_VENDOR_ID_PLX,
2146                 .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2147                 .subvendor      = PCI_ANY_ID,
2148                 .subdevice      = PCI_ANY_ID,
2149                 .setup          = pci_omegapci_setup,
2150         },
2151         /* WCH CH353 2S1P card (16550 clone) */
2152         {
2153                 .vendor         = PCI_VENDOR_ID_WCH,
2154                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2155                 .subvendor      = PCI_ANY_ID,
2156                 .subdevice      = PCI_ANY_ID,
2157                 .setup          = pci_wch_ch353_setup,
2158         },
2159         /* WCH CH353 4S card (16550 clone) */
2160         {
2161                 .vendor         = PCI_VENDOR_ID_WCH,
2162                 .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2163                 .subvendor      = PCI_ANY_ID,
2164                 .subdevice      = PCI_ANY_ID,
2165                 .setup          = pci_wch_ch353_setup,
2166         },
2167         /* WCH CH353 2S1PF card (16550 clone) */
2168         {
2169                 .vendor         = PCI_VENDOR_ID_WCH,
2170                 .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2171                 .subvendor      = PCI_ANY_ID,
2172                 .subdevice      = PCI_ANY_ID,
2173                 .setup          = pci_wch_ch353_setup,
2174         },
2175         /*
2176          * ASIX devices with FIFO bug
2177          */
2178         {
2179                 .vendor         = PCI_VENDOR_ID_ASIX,
2180                 .device         = PCI_ANY_ID,
2181                 .subvendor      = PCI_ANY_ID,
2182                 .subdevice      = PCI_ANY_ID,
2183                 .setup          = pci_asix_setup,
2184         },
2185         /*
2186          * Commtech, Inc. Fastcom adapters
2187          *
2188          */
2189         {
2190                 .vendor = PCI_VENDOR_ID_COMMTECH,
2191                 .device = PCI_DEVICE_ID_COMMTECH_4222PCI335,
2192                 .subvendor      = PCI_ANY_ID,
2193                 .subdevice      = PCI_ANY_ID,
2194                 .setup          = pci_fastcom335_setup,
2195         },
2196         {
2197                 .vendor = PCI_VENDOR_ID_COMMTECH,
2198                 .device = PCI_DEVICE_ID_COMMTECH_4224PCI335,
2199                 .subvendor      = PCI_ANY_ID,
2200                 .subdevice      = PCI_ANY_ID,
2201                 .setup          = pci_fastcom335_setup,
2202         },
2203         {
2204                 .vendor = PCI_VENDOR_ID_COMMTECH,
2205                 .device = PCI_DEVICE_ID_COMMTECH_2324PCI335,
2206                 .subvendor      = PCI_ANY_ID,
2207                 .subdevice      = PCI_ANY_ID,
2208                 .setup          = pci_fastcom335_setup,
2209         },
2210         {
2211                 .vendor = PCI_VENDOR_ID_COMMTECH,
2212                 .device = PCI_DEVICE_ID_COMMTECH_2328PCI335,
2213                 .subvendor      = PCI_ANY_ID,
2214                 .subdevice      = PCI_ANY_ID,
2215                 .setup          = pci_fastcom335_setup,
2216         },
2217         {
2218                 .vendor = PCI_VENDOR_ID_COMMTECH,
2219                 .device = PCI_DEVICE_ID_COMMTECH_4222PCIE,
2220                 .subvendor      = PCI_ANY_ID,
2221                 .subdevice      = PCI_ANY_ID,
2222                 .setup          = pci_xr17v35x_setup,
2223         },
2224         {
2225                 .vendor = PCI_VENDOR_ID_COMMTECH,
2226                 .device = PCI_DEVICE_ID_COMMTECH_4224PCIE,
2227                 .subvendor      = PCI_ANY_ID,
2228                 .subdevice      = PCI_ANY_ID,
2229                 .setup          = pci_xr17v35x_setup,
2230         },
2231         {
2232                 .vendor = PCI_VENDOR_ID_COMMTECH,
2233                 .device = PCI_DEVICE_ID_COMMTECH_4228PCIE,
2234                 .subvendor      = PCI_ANY_ID,
2235                 .subdevice      = PCI_ANY_ID,
2236                 .setup          = pci_xr17v35x_setup,
2237         },
2238         /*
2239          * Broadcom TruManage (NetXtreme)
2240          */
2241         {
2242                 .vendor         = PCI_VENDOR_ID_BROADCOM,
2243                 .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2244                 .subvendor      = PCI_ANY_ID,
2245                 .subdevice      = PCI_ANY_ID,
2246                 .setup          = pci_brcm_trumanage_setup,
2247         },
2248
2249         /*
2250          * Default "match everything" terminator entry
2251          */
2252         {
2253                 .vendor         = PCI_ANY_ID,
2254                 .device         = PCI_ANY_ID,
2255                 .subvendor      = PCI_ANY_ID,
2256                 .subdevice      = PCI_ANY_ID,
2257                 .setup          = pci_default_setup,
2258         }
2259 };
2260
2261 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2262 {
2263         return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2264 }
2265
2266 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2267 {
2268         struct pci_serial_quirk *quirk;
2269
2270         for (quirk = pci_serial_quirks; ; quirk++)
2271                 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2272                     quirk_id_matches(quirk->device, dev->device) &&
2273                     quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2274                     quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2275                         break;
2276         return quirk;
2277 }
2278
2279 static inline int get_pci_irq(struct pci_dev *dev,
2280                                 const struct pciserial_board *board)
2281 {
2282         if (board->flags & FL_NOIRQ)
2283                 return 0;
2284         else
2285                 return dev->irq;
2286 }
2287
2288 /*
2289  * This is the configuration table for all of the PCI serial boards
2290  * which we support.  It is directly indexed by the pci_board_num_t enum
2291  * value, which is encoded in the pci_device_id PCI probe table's
2292  * driver_data member.
2293  *
2294  * The makeup of these names are:
2295  *  pbn_bn{_bt}_n_baud{_offsetinhex}
2296  *
2297  *  bn          = PCI BAR number
2298  *  bt          = Index using PCI BARs
2299  *  n           = number of serial ports
2300  *  baud        = baud rate
2301  *  offsetinhex = offset for each sequential port (in hex)
2302  *
2303  * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2304  *
2305  * Please note: in theory if n = 1, _bt infix should make no difference.
2306  * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2307  */
2308 enum pci_board_num_t {
2309         pbn_default = 0,
2310
2311         pbn_b0_1_115200,
2312         pbn_b0_2_115200,
2313         pbn_b0_4_115200,
2314         pbn_b0_5_115200,
2315         pbn_b0_8_115200,
2316
2317         pbn_b0_1_921600,
2318         pbn_b0_2_921600,
2319         pbn_b0_4_921600,
2320
2321         pbn_b0_2_1130000,
2322
2323         pbn_b0_4_1152000,
2324
2325         pbn_b0_2_1152000_200,
2326         pbn_b0_4_1152000_200,
2327         pbn_b0_8_1152000_200,
2328
2329         pbn_b0_2_1843200,
2330         pbn_b0_4_1843200,
2331
2332         pbn_b0_2_1843200_200,
2333         pbn_b0_4_1843200_200,
2334         pbn_b0_8_1843200_200,
2335
2336         pbn_b0_1_4000000,
2337
2338         pbn_b0_bt_1_115200,
2339         pbn_b0_bt_2_115200,
2340         pbn_b0_bt_4_115200,
2341         pbn_b0_bt_8_115200,
2342
2343         pbn_b0_bt_1_460800,
2344         pbn_b0_bt_2_460800,
2345         pbn_b0_bt_4_460800,
2346
2347         pbn_b0_bt_1_921600,
2348         pbn_b0_bt_2_921600,
2349         pbn_b0_bt_4_921600,
2350         pbn_b0_bt_8_921600,
2351
2352         pbn_b1_1_115200,
2353         pbn_b1_2_115200,
2354         pbn_b1_4_115200,
2355         pbn_b1_8_115200,
2356         pbn_b1_16_115200,
2357
2358         pbn_b1_1_921600,
2359         pbn_b1_2_921600,
2360         pbn_b1_4_921600,
2361         pbn_b1_8_921600,
2362
2363         pbn_b1_2_1250000,
2364
2365         pbn_b1_bt_1_115200,
2366         pbn_b1_bt_2_115200,
2367         pbn_b1_bt_4_115200,
2368
2369         pbn_b1_bt_2_921600,
2370
2371         pbn_b1_1_1382400,
2372         pbn_b1_2_1382400,
2373         pbn_b1_4_1382400,
2374         pbn_b1_8_1382400,
2375
2376         pbn_b2_1_115200,
2377         pbn_b2_2_115200,
2378         pbn_b2_4_115200,
2379         pbn_b2_8_115200,
2380
2381         pbn_b2_1_460800,
2382         pbn_b2_4_460800,
2383         pbn_b2_8_460800,
2384         pbn_b2_16_460800,
2385
2386         pbn_b2_1_921600,
2387         pbn_b2_4_921600,
2388         pbn_b2_8_921600,
2389
2390         pbn_b2_8_1152000,
2391
2392         pbn_b2_bt_1_115200,
2393         pbn_b2_bt_2_115200,
2394         pbn_b2_bt_4_115200,
2395
2396         pbn_b2_bt_2_921600,
2397         pbn_b2_bt_4_921600,
2398
2399         pbn_b3_2_115200,
2400         pbn_b3_4_115200,
2401         pbn_b3_8_115200,
2402
2403         pbn_b4_bt_2_921600,
2404         pbn_b4_bt_4_921600,
2405         pbn_b4_bt_8_921600,
2406
2407         /*
2408          * Board-specific versions.
2409          */
2410         pbn_panacom,
2411         pbn_panacom2,
2412         pbn_panacom4,
2413         pbn_plx_romulus,
2414         pbn_oxsemi,
2415         pbn_oxsemi_1_4000000,
2416         pbn_oxsemi_2_4000000,
2417         pbn_oxsemi_4_4000000,
2418         pbn_oxsemi_8_4000000,
2419         pbn_intel_i960,
2420         pbn_sgi_ioc3,
2421         pbn_computone_4,
2422         pbn_computone_6,
2423         pbn_computone_8,
2424         pbn_sbsxrsio,
2425         pbn_exar_XR17C152,
2426         pbn_exar_XR17C154,
2427         pbn_exar_XR17C158,
2428         pbn_exar_XR17V352,
2429         pbn_exar_XR17V354,
2430         pbn_exar_XR17V358,
2431         pbn_exar_ibm_saturn,
2432         pbn_pasemi_1682M,
2433         pbn_ni8430_2,
2434         pbn_ni8430_4,
2435         pbn_ni8430_8,
2436         pbn_ni8430_16,
2437         pbn_ADDIDATA_PCIe_1_3906250,
2438         pbn_ADDIDATA_PCIe_2_3906250,
2439         pbn_ADDIDATA_PCIe_4_3906250,
2440         pbn_ADDIDATA_PCIe_8_3906250,
2441         pbn_ce4100_1_115200,
2442         pbn_omegapci,
2443         pbn_NETMOS9900_2s_115200,
2444         pbn_brcm_trumanage,
2445 };
2446
2447 /*
2448  * uart_offset - the space between channels
2449  * reg_shift   - describes how the UART registers are mapped
2450  *               to PCI memory by the card.
2451  * For example IER register on SBS, Inc. PMC-OctPro is located at
2452  * offset 0x10 from the UART base, while UART_IER is defined as 1
2453  * in include/linux/serial_reg.h,
2454  * see first lines of serial_in() and serial_out() in 8250.c
2455 */
2456
2457 static struct pciserial_board pci_boards[] = {
2458         [pbn_default] = {
2459                 .flags          = FL_BASE0,
2460                 .num_ports      = 1,
2461                 .base_baud      = 115200,
2462                 .uart_offset    = 8,
2463         },
2464         [pbn_b0_1_115200] = {
2465                 .flags          = FL_BASE0,
2466                 .num_ports      = 1,
2467                 .base_baud      = 115200,
2468                 .uart_offset    = 8,
2469         },
2470         [pbn_b0_2_115200] = {
2471                 .flags          = FL_BASE0,
2472                 .num_ports      = 2,
2473                 .base_baud      = 115200,
2474                 .uart_offset    = 8,
2475         },
2476         [pbn_b0_4_115200] = {
2477                 .flags          = FL_BASE0,
2478                 .num_ports      = 4,
2479                 .base_baud      = 115200,
2480                 .uart_offset    = 8,
2481         },
2482         [pbn_b0_5_115200] = {
2483                 .flags          = FL_BASE0,
2484                 .num_ports      = 5,
2485                 .base_baud      = 115200,
2486                 .uart_offset    = 8,
2487         },
2488         [pbn_b0_8_115200] = {
2489                 .flags          = FL_BASE0,
2490                 .num_ports      = 8,
2491                 .base_baud      = 115200,
2492                 .uart_offset    = 8,
2493         },
2494         [pbn_b0_1_921600] = {
2495                 .flags          = FL_BASE0,
2496                 .num_ports      = 1,
2497                 .base_baud      = 921600,
2498                 .uart_offset    = 8,
2499         },
2500         [pbn_b0_2_921600] = {
2501                 .flags          = FL_BASE0,
2502                 .num_ports      = 2,
2503                 .base_baud      = 921600,
2504                 .uart_offset    = 8,
2505         },
2506         [pbn_b0_4_921600] = {
2507                 .flags          = FL_BASE0,
2508                 .num_ports      = 4,
2509                 .base_baud      = 921600,
2510                 .uart_offset    = 8,
2511         },
2512
2513         [pbn_b0_2_1130000] = {
2514                 .flags          = FL_BASE0,
2515                 .num_ports      = 2,
2516                 .base_baud      = 1130000,
2517                 .uart_offset    = 8,
2518         },
2519
2520         [pbn_b0_4_1152000] = {
2521                 .flags          = FL_BASE0,
2522                 .num_ports      = 4,
2523                 .base_baud      = 1152000,
2524                 .uart_offset    = 8,
2525         },
2526
2527         [pbn_b0_2_1152000_200] = {
2528                 .flags          = FL_BASE0,
2529                 .num_ports      = 2,
2530                 .base_baud      = 1152000,
2531                 .uart_offset    = 0x200,
2532         },
2533
2534         [pbn_b0_4_1152000_200] = {
2535                 .flags          = FL_BASE0,
2536                 .num_ports      = 4,
2537                 .base_baud      = 1152000,
2538                 .uart_offset    = 0x200,
2539         },
2540
2541         [pbn_b0_8_1152000_200] = {
2542                 .flags          = FL_BASE0,
2543                 .num_ports      = 8,
2544                 .base_baud      = 1152000,
2545                 .uart_offset    = 0x200,
2546         },
2547
2548         [pbn_b0_2_1843200] = {
2549                 .flags          = FL_BASE0,
2550                 .num_ports      = 2,
2551                 .base_baud      = 1843200,
2552                 .uart_offset    = 8,
2553         },
2554         [pbn_b0_4_1843200] = {
2555                 .flags          = FL_BASE0,
2556                 .num_ports      = 4,
2557                 .base_baud      = 1843200,
2558                 .uart_offset    = 8,
2559         },
2560
2561         [pbn_b0_2_1843200_200] = {
2562                 .flags          = FL_BASE0,
2563                 .num_ports      = 2,
2564                 .base_baud      = 1843200,
2565                 .uart_offset    = 0x200,
2566         },
2567         [pbn_b0_4_1843200_200] = {
2568                 .flags          = FL_BASE0,
2569                 .num_ports      = 4,
2570                 .base_baud      = 1843200,
2571                 .uart_offset    = 0x200,
2572         },
2573         [pbn_b0_8_1843200_200] = {
2574                 .flags          = FL_BASE0,
2575                 .num_ports      = 8,
2576                 .base_baud      = 1843200,
2577                 .uart_offset    = 0x200,
2578         },
2579         [pbn_b0_1_4000000] = {
2580                 .flags          = FL_BASE0,
2581                 .num_ports      = 1,
2582                 .base_baud      = 4000000,
2583                 .uart_offset    = 8,
2584         },
2585
2586         [pbn_b0_bt_1_115200] = {
2587                 .flags          = FL_BASE0|FL_BASE_BARS,
2588                 .num_ports      = 1,
2589                 .base_baud      = 115200,
2590                 .uart_offset    = 8,
2591         },
2592         [pbn_b0_bt_2_115200] = {
2593                 .flags          = FL_BASE0|FL_BASE_BARS,
2594                 .num_ports      = 2,
2595                 .base_baud      = 115200,
2596                 .uart_offset    = 8,
2597         },
2598         [pbn_b0_bt_4_115200] = {
2599                 .flags          = FL_BASE0|FL_BASE_BARS,
2600                 .num_ports      = 4,
2601                 .base_baud      = 115200,
2602                 .uart_offset    = 8,
2603         },
2604         [pbn_b0_bt_8_115200] = {
2605                 .flags          = FL_BASE0|FL_BASE_BARS,
2606                 .num_ports      = 8,
2607                 .base_baud      = 115200,
2608                 .uart_offset    = 8,
2609         },
2610
2611         [pbn_b0_bt_1_460800] = {
2612                 .flags          = FL_BASE0|FL_BASE_BARS,
2613                 .num_ports      = 1,
2614                 .base_baud      = 460800,
2615                 .uart_offset    = 8,
2616         },
2617         [pbn_b0_bt_2_460800] = {
2618                 .flags          = FL_BASE0|FL_BASE_BARS,
2619                 .num_ports      = 2,
2620                 .base_baud      = 460800,
2621                 .uart_offset    = 8,
2622         },
2623         [pbn_b0_bt_4_460800] = {
2624                 .flags          = FL_BASE0|FL_BASE_BARS,
2625                 .num_ports      = 4,
2626                 .base_baud      = 460800,
2627                 .uart_offset    = 8,
2628         },
2629
2630         [pbn_b0_bt_1_921600] = {
2631                 .flags          = FL_BASE0|FL_BASE_BARS,
2632                 .num_ports      = 1,
2633                 .base_baud      = 921600,
2634                 .uart_offset    = 8,
2635         },
2636         [pbn_b0_bt_2_921600] = {
2637                 .flags          = FL_BASE0|FL_BASE_BARS,
2638                 .num_ports      = 2,
2639                 .base_baud      = 921600,
2640                 .uart_offset    = 8,
2641         },
2642         [pbn_b0_bt_4_921600] = {
2643                 .flags          = FL_BASE0|FL_BASE_BARS,
2644                 .num_ports      = 4,
2645                 .base_baud      = 921600,
2646                 .uart_offset    = 8,
2647         },
2648         [pbn_b0_bt_8_921600] = {
2649                 .flags          = FL_BASE0|FL_BASE_BARS,
2650                 .num_ports      = 8,
2651                 .base_baud      = 921600,
2652                 .uart_offset    = 8,
2653         },
2654
2655         [pbn_b1_1_115200] = {
2656                 .flags          = FL_BASE1,
2657                 .num_ports      = 1,
2658                 .base_baud      = 115200,
2659                 .uart_offset    = 8,
2660         },
2661         [pbn_b1_2_115200] = {
2662                 .flags          = FL_BASE1,
2663                 .num_ports      = 2,
2664                 .base_baud      = 115200,
2665                 .uart_offset    = 8,
2666         },
2667         [pbn_b1_4_115200] = {
2668                 .flags          = FL_BASE1,
2669                 .num_ports      = 4,
2670                 .base_baud      = 115200,
2671                 .uart_offset    = 8,
2672         },
2673         [pbn_b1_8_115200] = {
2674                 .flags          = FL_BASE1,
2675                 .num_ports      = 8,
2676                 .base_baud      = 115200,
2677                 .uart_offset    = 8,
2678         },
2679         [pbn_b1_16_115200] = {
2680                 .flags          = FL_BASE1,
2681                 .num_ports      = 16,
2682                 .base_baud      = 115200,
2683                 .uart_offset    = 8,
2684         },
2685
2686         [pbn_b1_1_921600] = {
2687                 .flags          = FL_BASE1,
2688                 .num_ports      = 1,
2689                 .base_baud      = 921600,
2690                 .uart_offset    = 8,
2691         },
2692         [pbn_b1_2_921600] = {
2693                 .flags          = FL_BASE1,
2694                 .num_ports      = 2,
2695                 .base_baud      = 921600,
2696                 .uart_offset    = 8,
2697         },
2698         [pbn_b1_4_921600] = {
2699                 .flags          = FL_BASE1,
2700                 .num_ports      = 4,
2701                 .base_baud      = 921600,
2702                 .uart_offset    = 8,
2703         },
2704         [pbn_b1_8_921600] = {
2705                 .flags          = FL_BASE1,
2706                 .num_ports      = 8,
2707                 .base_baud      = 921600,
2708                 .uart_offset    = 8,
2709         },
2710         [pbn_b1_2_1250000] = {
2711                 .flags          = FL_BASE1,
2712                 .num_ports      = 2,
2713                 .base_baud      = 1250000,
2714                 .uart_offset    = 8,
2715         },
2716
2717         [pbn_b1_bt_1_115200] = {
2718                 .flags          = FL_BASE1|FL_BASE_BARS,
2719                 .num_ports      = 1,
2720                 .base_baud      = 115200,
2721                 .uart_offset    = 8,
2722         },
2723         [pbn_b1_bt_2_115200] = {
2724                 .flags          = FL_BASE1|FL_BASE_BARS,
2725                 .num_ports      = 2,
2726                 .base_baud      = 115200,
2727                 .uart_offset    = 8,
2728         },
2729         [pbn_b1_bt_4_115200] = {
2730                 .flags          = FL_BASE1|FL_BASE_BARS,
2731                 .num_ports      = 4,
2732                 .base_baud      = 115200,
2733                 .uart_offset    = 8,
2734         },
2735
2736         [pbn_b1_bt_2_921600] = {
2737                 .flags          = FL_BASE1|FL_BASE_BARS,
2738                 .num_ports      = 2,
2739                 .base_baud      = 921600,
2740                 .uart_offset    = 8,
2741         },
2742
2743         [pbn_b1_1_1382400] = {
2744                 .flags          = FL_BASE1,
2745                 .num_ports      = 1,
2746                 .base_baud      = 1382400,
2747                 .uart_offset    = 8,
2748         },
2749         [pbn_b1_2_1382400] = {
2750                 .flags          = FL_BASE1,
2751                 .num_ports      = 2,
2752                 .base_baud      = 1382400,
2753                 .uart_offset    = 8,
2754         },
2755         [pbn_b1_4_1382400] = {
2756                 .flags          = FL_BASE1,
2757                 .num_ports      = 4,
2758                 .base_baud      = 1382400,
2759                 .uart_offset    = 8,
2760         },
2761         [pbn_b1_8_1382400] = {
2762                 .flags          = FL_BASE1,
2763                 .num_ports      = 8,
2764                 .base_baud      = 1382400,
2765                 .uart_offset    = 8,
2766         },
2767
2768         [pbn_b2_1_115200] = {
2769                 .flags          = FL_BASE2,
2770                 .num_ports      = 1,
2771                 .base_baud      = 115200,
2772                 .uart_offset    = 8,
2773         },
2774         [pbn_b2_2_115200] = {
2775                 .flags          = FL_BASE2,
2776                 .num_ports      = 2,
2777                 .base_baud      = 115200,
2778                 .uart_offset    = 8,
2779         },
2780         [pbn_b2_4_115200] = {
2781                 .flags          = FL_BASE2,
2782                 .num_ports      = 4,
2783                 .base_baud      = 115200,
2784                 .uart_offset    = 8,
2785         },
2786         [pbn_b2_8_115200] = {
2787                 .flags          = FL_BASE2,
2788                 .num_ports      = 8,
2789                 .base_baud      = 115200,
2790                 .uart_offset    = 8,
2791         },
2792
2793         [pbn_b2_1_460800] = {
2794                 .flags          = FL_BASE2,
2795                 .num_ports      = 1,
2796                 .base_baud      = 460800,
2797                 .uart_offset    = 8,
2798         },
2799         [pbn_b2_4_460800] = {
2800                 .flags          = FL_BASE2,
2801                 .num_ports      = 4,
2802                 .base_baud      = 460800,
2803                 .uart_offset    = 8,
2804         },
2805         [pbn_b2_8_460800] = {
2806                 .flags          = FL_BASE2,
2807                 .num_ports      = 8,
2808                 .base_baud      = 460800,
2809                 .uart_offset    = 8,
2810         },
2811         [pbn_b2_16_460800] = {
2812                 .flags          = FL_BASE2,
2813                 .num_ports      = 16,
2814                 .base_baud      = 460800,
2815                 .uart_offset    = 8,
2816          },
2817
2818         [pbn_b2_1_921600] = {
2819                 .flags          = FL_BASE2,
2820                 .num_ports      = 1,
2821                 .base_baud      = 921600,
2822                 .uart_offset    = 8,
2823         },
2824         [pbn_b2_4_921600] = {
2825                 .flags          = FL_BASE2,
2826                 .num_ports      = 4,
2827                 .base_baud      = 921600,
2828                 .uart_offset    = 8,
2829         },
2830         [pbn_b2_8_921600] = {
2831                 .flags          = FL_BASE2,
2832                 .num_ports      = 8,
2833                 .base_baud      = 921600,
2834                 .uart_offset    = 8,
2835         },
2836
2837         [pbn_b2_8_1152000] = {
2838                 .flags          = FL_BASE2,
2839                 .num_ports      = 8,
2840                 .base_baud      = 1152000,
2841                 .uart_offset    = 8,
2842         },
2843
2844         [pbn_b2_bt_1_115200] = {
2845                 .flags          = FL_BASE2|FL_BASE_BARS,
2846                 .num_ports      = 1,
2847                 .base_baud      = 115200,
2848                 .uart_offset    = 8,
2849         },
2850         [pbn_b2_bt_2_115200] = {
2851                 .flags          = FL_BASE2|FL_BASE_BARS,
2852                 .num_ports      = 2,
2853                 .base_baud      = 115200,
2854                 .uart_offset    = 8,
2855         },
2856         [pbn_b2_bt_4_115200] = {
2857                 .flags          = FL_BASE2|FL_BASE_BARS,
2858                 .num_ports      = 4,
2859                 .base_baud      = 115200,
2860                 .uart_offset    = 8,
2861         },
2862
2863         [pbn_b2_bt_2_921600] = {
2864                 .flags          = FL_BASE2|FL_BASE_BARS,
2865                 .num_ports      = 2,
2866                 .base_baud      = 921600,
2867                 .uart_offset    = 8,
2868         },
2869         [pbn_b2_bt_4_921600] = {
2870                 .flags          = FL_BASE2|FL_BASE_BARS,
2871                 .num_ports      = 4,
2872                 .base_baud      = 921600,
2873                 .uart_offset    = 8,
2874         },
2875
2876         [pbn_b3_2_115200] = {
2877                 .flags          = FL_BASE3,
2878                 .num_ports      = 2,
2879                 .base_baud      = 115200,
2880                 .uart_offset    = 8,
2881         },
2882         [pbn_b3_4_115200] = {
2883                 .flags          = FL_BASE3,
2884                 .num_ports      = 4,
2885                 .base_baud      = 115200,
2886                 .uart_offset    = 8,
2887         },
2888         [pbn_b3_8_115200] = {
2889                 .flags          = FL_BASE3,
2890                 .num_ports      = 8,
2891                 .base_baud      = 115200,
2892                 .uart_offset    = 8,
2893         },
2894
2895         [pbn_b4_bt_2_921600] = {
2896                 .flags          = FL_BASE4,
2897                 .num_ports      = 2,
2898                 .base_baud      = 921600,
2899                 .uart_offset    = 8,
2900         },
2901         [pbn_b4_bt_4_921600] = {
2902                 .flags          = FL_BASE4,
2903                 .num_ports      = 4,
2904                 .base_baud      = 921600,
2905                 .uart_offset    = 8,
2906         },
2907         [pbn_b4_bt_8_921600] = {
2908                 .flags          = FL_BASE4,
2909                 .num_ports      = 8,
2910                 .base_baud      = 921600,
2911                 .uart_offset    = 8,
2912         },
2913
2914         /*
2915          * Entries following this are board-specific.
2916          */
2917
2918         /*
2919          * Panacom - IOMEM
2920          */
2921         [pbn_panacom] = {
2922                 .flags          = FL_BASE2,
2923                 .num_ports      = 2,
2924                 .base_baud      = 921600,
2925                 .uart_offset    = 0x400,
2926                 .reg_shift      = 7,
2927         },
2928         [pbn_panacom2] = {
2929                 .flags          = FL_BASE2|FL_BASE_BARS,
2930                 .num_ports      = 2,
2931                 .base_baud      = 921600,
2932                 .uart_offset    = 0x400,
2933                 .reg_shift      = 7,
2934         },
2935         [pbn_panacom4] = {
2936                 .flags          = FL_BASE2|FL_BASE_BARS,
2937                 .num_ports      = 4,
2938                 .base_baud      = 921600,
2939                 .uart_offset    = 0x400,
2940                 .reg_shift      = 7,
2941         },
2942
2943         /* I think this entry is broken - the first_offset looks wrong --rmk */
2944         [pbn_plx_romulus] = {
2945                 .flags          = FL_BASE2,
2946                 .num_ports      = 4,
2947                 .base_baud      = 921600,
2948                 .uart_offset    = 8 << 2,
2949                 .reg_shift      = 2,
2950                 .first_offset   = 0x03,
2951         },
2952
2953         /*
2954          * This board uses the size of PCI Base region 0 to
2955          * signal now many ports are available
2956          */
2957         [pbn_oxsemi] = {
2958                 .flags          = FL_BASE0|FL_REGION_SZ_CAP,
2959                 .num_ports      = 32,
2960                 .base_baud      = 115200,
2961                 .uart_offset    = 8,
2962         },
2963         [pbn_oxsemi_1_4000000] = {
2964                 .flags          = FL_BASE0,
2965                 .num_ports      = 1,
2966                 .base_baud      = 4000000,
2967                 .uart_offset    = 0x200,
2968                 .first_offset   = 0x1000,
2969         },
2970         [pbn_oxsemi_2_4000000] = {
2971                 .flags          = FL_BASE0,
2972                 .num_ports      = 2,
2973                 .base_baud      = 4000000,
2974                 .uart_offset    = 0x200,
2975                 .first_offset   = 0x1000,
2976         },
2977         [pbn_oxsemi_4_4000000] = {
2978                 .flags          = FL_BASE0,
2979                 .num_ports      = 4,
2980                 .base_baud      = 4000000,
2981                 .uart_offset    = 0x200,
2982                 .first_offset   = 0x1000,
2983         },
2984         [pbn_oxsemi_8_4000000] = {
2985                 .flags          = FL_BASE0,
2986                 .num_ports      = 8,
2987                 .base_baud      = 4000000,
2988                 .uart_offset    = 0x200,
2989                 .first_offset   = 0x1000,
2990         },
2991
2992
2993         /*
2994          * EKF addition for i960 Boards form EKF with serial port.
2995          * Max 256 ports.
2996          */
2997         [pbn_intel_i960] = {
2998                 .flags          = FL_BASE0,
2999                 .num_ports      = 32,
3000                 .base_baud      = 921600,
3001                 .uart_offset    = 8 << 2,
3002                 .reg_shift      = 2,
3003                 .first_offset   = 0x10000,
3004         },
3005         [pbn_sgi_ioc3] = {
3006                 .flags          = FL_BASE0|FL_NOIRQ,
3007                 .num_ports      = 1,
3008                 .base_baud      = 458333,
3009                 .uart_offset    = 8,
3010                 .reg_shift      = 0,
3011                 .first_offset   = 0x20178,
3012         },
3013
3014         /*
3015          * Computone - uses IOMEM.
3016          */
3017         [pbn_computone_4] = {
3018                 .flags          = FL_BASE0,
3019                 .num_ports      = 4,
3020                 .base_baud      = 921600,
3021                 .uart_offset    = 0x40,
3022                 .reg_shift      = 2,
3023                 .first_offset   = 0x200,
3024         },
3025         [pbn_computone_6] = {
3026                 .flags          = FL_BASE0,
3027                 .num_ports      = 6,
3028                 .base_baud      = 921600,
3029                 .uart_offset    = 0x40,
3030                 .reg_shift      = 2,
3031                 .first_offset   = 0x200,
3032         },
3033         [pbn_computone_8] = {
3034                 .flags          = FL_BASE0,
3035                 .num_ports      = 8,
3036                 .base_baud      = 921600,
3037                 .uart_offset    = 0x40,
3038                 .reg_shift      = 2,
3039                 .first_offset   = 0x200,
3040         },
3041         [pbn_sbsxrsio] = {
3042                 .flags          = FL_BASE0,
3043                 .num_ports      = 8,
3044                 .base_baud      = 460800,
3045                 .uart_offset    = 256,
3046                 .reg_shift      = 4,
3047         },
3048         /*
3049          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
3050          *  Only basic 16550A support.
3051          *  XR17C15[24] are not tested, but they should work.
3052          */
3053         [pbn_exar_XR17C152] = {
3054                 .flags          = FL_BASE0,
3055                 .num_ports      = 2,
3056                 .base_baud      = 921600,
3057                 .uart_offset    = 0x200,
3058         },
3059         [pbn_exar_XR17C154] = {
3060                 .flags          = FL_BASE0,
3061                 .num_ports      = 4,
3062                 .base_baud      = 921600,
3063                 .uart_offset    = 0x200,
3064         },
3065         [pbn_exar_XR17C158] = {
3066                 .flags          = FL_BASE0,
3067                 .num_ports      = 8,
3068                 .base_baud      = 921600,
3069                 .uart_offset    = 0x200,
3070         },
3071         [pbn_exar_XR17V352] = {
3072                 .flags          = FL_BASE0,
3073                 .num_ports      = 2,
3074                 .base_baud      = 7812500,
3075                 .uart_offset    = 0x400,
3076                 .reg_shift      = 0,
3077                 .first_offset   = 0,
3078         },
3079         [pbn_exar_XR17V354] = {
3080                 .flags          = FL_BASE0,
3081                 .num_ports      = 4,
3082                 .base_baud      = 7812500,
3083                 .uart_offset    = 0x400,
3084                 .reg_shift      = 0,
3085                 .first_offset   = 0,
3086         },
3087         [pbn_exar_XR17V358] = {
3088                 .flags          = FL_BASE0,
3089                 .num_ports      = 8,
3090                 .base_baud      = 7812500,
3091                 .uart_offset    = 0x400,
3092                 .reg_shift      = 0,
3093                 .first_offset   = 0,
3094         },
3095         [pbn_exar_ibm_saturn] = {
3096                 .flags          = FL_BASE0,
3097                 .num_ports      = 1,
3098                 .base_baud      = 921600,
3099                 .uart_offset    = 0x200,
3100         },
3101
3102         /*
3103          * PA Semi PWRficient PA6T-1682M on-chip UART
3104          */
3105         [pbn_pasemi_1682M] = {
3106                 .flags          = FL_BASE0,
3107                 .num_ports      = 1,
3108                 .base_baud      = 8333333,
3109         },
3110         /*
3111          * National Instruments 843x
3112          */
3113         [pbn_ni8430_16] = {
3114                 .flags          = FL_BASE0,
3115                 .num_ports      = 16,
3116                 .base_baud      = 3686400,
3117                 .uart_offset    = 0x10,
3118                 .first_offset   = 0x800,
3119         },
3120         [pbn_ni8430_8] = {
3121                 .flags          = FL_BASE0,
3122                 .num_ports      = 8,
3123                 .base_baud      = 3686400,
3124                 .uart_offset    = 0x10,
3125                 .first_offset   = 0x800,
3126         },
3127         [pbn_ni8430_4] = {
3128                 .flags          = FL_BASE0,
3129                 .num_ports      = 4,
3130                 .base_baud      = 3686400,
3131                 .uart_offset    = 0x10,
3132                 .first_offset   = 0x800,
3133         },
3134         [pbn_ni8430_2] = {
3135                 .flags          = FL_BASE0,
3136                 .num_ports      = 2,
3137                 .base_baud      = 3686400,
3138                 .uart_offset    = 0x10,
3139                 .first_offset   = 0x800,
3140         },
3141         /*
3142          * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3143          */
3144         [pbn_ADDIDATA_PCIe_1_3906250] = {
3145                 .flags          = FL_BASE0,
3146                 .num_ports      = 1,
3147                 .base_baud      = 3906250,
3148                 .uart_offset    = 0x200,
3149                 .first_offset   = 0x1000,
3150         },
3151         [pbn_ADDIDATA_PCIe_2_3906250] = {
3152                 .flags          = FL_BASE0,
3153                 .num_ports      = 2,
3154                 .base_baud      = 3906250,
3155                 .uart_offset    = 0x200,
3156                 .first_offset   = 0x1000,
3157         },
3158         [pbn_ADDIDATA_PCIe_4_3906250] = {
3159                 .flags          = FL_BASE0,
3160                 .num_ports      = 4,
3161                 .base_baud      = 3906250,
3162                 .uart_offset    = 0x200,
3163                 .first_offset   = 0x1000,
3164         },
3165         [pbn_ADDIDATA_PCIe_8_3906250] = {
3166                 .flags          = FL_BASE0,
3167                 .num_ports      = 8,
3168                 .base_baud      = 3906250,
3169                 .uart_offset    = 0x200,
3170                 .first_offset   = 0x1000,
3171         },
3172         [pbn_ce4100_1_115200] = {
3173                 .flags          = FL_BASE_BARS,
3174                 .num_ports      = 2,
3175                 .base_baud      = 921600,
3176                 .reg_shift      = 2,
3177         },
3178         [pbn_omegapci] = {
3179                 .flags          = FL_BASE0,
3180                 .num_ports      = 8,
3181                 .base_baud      = 115200,
3182                 .uart_offset    = 0x200,
3183         },
3184         [pbn_NETMOS9900_2s_115200] = {
3185                 .flags          = FL_BASE0,
3186                 .num_ports      = 2,
3187                 .base_baud      = 115200,
3188         },
3189         [pbn_brcm_trumanage] = {
3190                 .flags          = FL_BASE0,
3191                 .num_ports      = 1,
3192                 .reg_shift      = 2,
3193                 .base_baud      = 115200,
3194         },
3195 };
3196
3197 static const struct pci_device_id blacklist[] = {
3198         /* softmodems */
3199         { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3200         { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3201         { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3202
3203         /* multi-io cards handled by parport_serial */
3204         { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3205 };
3206
3207 /*
3208  * Given a complete unknown PCI device, try to use some heuristics to
3209  * guess what the configuration might be, based on the pitiful PCI
3210  * serial specs.  Returns 0 on success, 1 on failure.
3211  */
3212 static int
3213 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3214 {
3215         const struct pci_device_id *bldev;
3216         int num_iomem, num_port, first_port = -1, i;
3217
3218         /*
3219          * If it is not a communications device or the programming
3220          * interface is greater than 6, give up.
3221          *
3222          * (Should we try to make guesses for multiport serial devices
3223          * later?)
3224          */
3225         if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3226              ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3227             (dev->class & 0xff) > 6)
3228                 return -ENODEV;
3229
3230         /*
3231          * Do not access blacklisted devices that are known not to
3232          * feature serial ports or are handled by other modules.
3233          */
3234         for (bldev = blacklist;
3235              bldev < blacklist + ARRAY_SIZE(blacklist);
3236              bldev++) {
3237                 if (dev->vendor == bldev->vendor &&
3238                     dev->device == bldev->device)
3239                         return -ENODEV;
3240         }
3241
3242         num_iomem = num_port = 0;
3243         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3244                 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3245                         num_port++;
3246                         if (first_port == -1)
3247                                 first_port = i;
3248                 }
3249                 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3250                         num_iomem++;
3251         }
3252
3253         /*
3254          * If there is 1 or 0 iomem regions, and exactly one port,
3255          * use it.  We guess the number of ports based on the IO
3256          * region size.
3257          */
3258         if (num_iomem <= 1 && num_port == 1) {
3259                 board->flags = first_port;
3260                 board->num_ports = pci_resource_len(dev, first_port) / 8;
3261                 return 0;
3262         }
3263
3264         /*
3265          * Now guess if we've got a board which indexes by BARs.
3266          * Each IO BAR should be 8 bytes, and they should follow
3267          * consecutively.
3268          */
3269         first_port = -1;
3270         num_port = 0;
3271         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3272                 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3273                     pci_resource_len(dev, i) == 8 &&
3274                     (first_port == -1 || (first_port + num_port) == i)) {
3275                         num_port++;
3276                         if (first_port == -1)
3277                                 first_port = i;
3278                 }
3279         }
3280
3281         if (num_port > 1) {
3282                 board->flags = first_port | FL_BASE_BARS;
3283                 board->num_ports = num_port;
3284                 return 0;
3285         }
3286
3287         return -ENODEV;
3288 }
3289
3290 static inline int
3291 serial_pci_matches(const struct pciserial_board *board,
3292                    const struct pciserial_board *guessed)
3293 {
3294         return
3295             board->num_ports == guessed->num_ports &&
3296             board->base_baud == guessed->base_baud &&
3297             board->uart_offset == guessed->uart_offset &&
3298             board->reg_shift == guessed->reg_shift &&
3299             board->first_offset == guessed->first_offset;
3300 }
3301
3302 struct serial_private *
3303 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3304 {
3305         struct uart_8250_port uart;
3306         struct serial_private *priv;
3307         struct pci_serial_quirk *quirk;
3308         int rc, nr_ports, i;
3309
3310         nr_ports = board->num_ports;
3311
3312         /*
3313          * Find an init and setup quirks.
3314          */
3315         quirk = find_quirk(dev);
3316
3317         /*
3318          * Run the new-style initialization function.
3319          * The initialization function returns:
3320          *  <0  - error
3321          *   0  - use board->num_ports
3322          *  >0  - number of ports
3323          */
3324         if (quirk->init) {
3325                 rc = quirk->init(dev);
3326                 if (rc < 0) {
3327                         priv = ERR_PTR(rc);
3328                         goto err_out;
3329                 }
3330                 if (rc)
3331                         nr_ports = rc;
3332         }
3333
3334         priv = kzalloc(sizeof(struct serial_private) +
3335                        sizeof(unsigned int) * nr_ports,
3336                        GFP_KERNEL);
3337         if (!priv) {
3338                 priv = ERR_PTR(-ENOMEM);
3339                 goto err_deinit;
3340         }
3341
3342         priv->dev = dev;
3343         priv->quirk = quirk;
3344
3345         memset(&uart, 0, sizeof(uart));
3346         uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3347         uart.port.uartclk = board->base_baud * 16;
3348         uart.port.irq = get_pci_irq(dev, board);
3349         uart.port.dev = &dev->dev;
3350
3351         for (i = 0; i < nr_ports; i++) {
3352                 if (quirk->setup(priv, board, &uart, i))
3353                         break;
3354
3355 #ifdef SERIAL_DEBUG_PCI
3356                 printk(KERN_DEBUG "Setup PCI port: port %lx, irq %d, type %d\n",
3357                        uart.port.iobase, uart.port.irq, uart.port.iotype);
3358 #endif
3359
3360                 priv->line[i] = serial8250_register_8250_port(&uart);
3361                 if (priv->line[i] < 0) {
3362                         printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
3363                         break;
3364                 }
3365         }
3366         priv->nr = i;
3367         return priv;
3368
3369 err_deinit:
3370         if (quirk->exit)
3371                 quirk->exit(dev);
3372 err_out:
3373         return priv;
3374 }
3375 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3376
3377 void pciserial_remove_ports(struct serial_private *priv)
3378 {
3379         struct pci_serial_quirk *quirk;
3380         int i;
3381
3382         for (i = 0; i < priv->nr; i++)
3383                 serial8250_unregister_port(priv->line[i]);
3384
3385         for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3386                 if (priv->remapped_bar[i])
3387                         iounmap(priv->remapped_bar[i]);
3388                 priv->remapped_bar[i] = NULL;
3389         }
3390
3391         /*
3392          * Find the exit quirks.
3393          */
3394         quirk = find_quirk(priv->dev);
3395         if (quirk->exit)
3396                 quirk->exit(priv->dev);
3397
3398         kfree(priv);
3399 }
3400 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3401
3402 void pciserial_suspend_ports(struct serial_private *priv)
3403 {
3404         int i;
3405
3406         for (i = 0; i < priv->nr; i++)
3407                 if (priv->line[i] >= 0)
3408                         serial8250_suspend_port(priv->line[i]);
3409
3410         /*
3411          * Ensure that every init quirk is properly torn down
3412          */
3413         if (priv->quirk->exit)
3414                 priv->quirk->exit(priv->dev);
3415 }
3416 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3417
3418 void pciserial_resume_ports(struct serial_private *priv)
3419 {
3420         int i;
3421
3422         /*
3423          * Ensure that the board is correctly configured.
3424          */
3425         if (priv->quirk->init)
3426                 priv->quirk->init(priv->dev);
3427
3428         for (i = 0; i < priv->nr; i++)
3429                 if (priv->line[i] >= 0)
3430                         serial8250_resume_port(priv->line[i]);
3431 }
3432 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3433
3434 /*
3435  * Probe one serial board.  Unfortunately, there is no rhyme nor reason
3436  * to the arrangement of serial ports on a PCI card.
3437  */
3438 static int
3439 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3440 {
3441         struct pci_serial_quirk *quirk;
3442         struct serial_private *priv;
3443         const struct pciserial_board *board;
3444         struct pciserial_board tmp;
3445         int rc;
3446
3447         quirk = find_quirk(dev);
3448         if (quirk->probe) {
3449                 rc = quirk->probe(dev);
3450                 if (rc)
3451                         return rc;
3452         }
3453
3454         if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3455                 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
3456                         ent->driver_data);
3457                 return -EINVAL;
3458         }
3459
3460         board = &pci_boards[ent->driver_data];
3461
3462         rc = pci_enable_device(dev);
3463         pci_save_state(dev);
3464         if (rc)
3465                 return rc;
3466
3467         if (ent->driver_data == pbn_default) {
3468                 /*
3469                  * Use a copy of the pci_board entry for this;
3470                  * avoid changing entries in the table.
3471                  */
3472                 memcpy(&tmp, board, sizeof(struct pciserial_board));
3473                 board = &tmp;
3474
3475                 /*
3476                  * We matched one of our class entries.  Try to
3477                  * determine the parameters of this board.
3478                  */
3479                 rc = serial_pci_guess_board(dev, &tmp);
3480                 if (rc)
3481                         goto disable;
3482         } else {
3483                 /*
3484                  * We matched an explicit entry.  If we are able to
3485                  * detect this boards settings with our heuristic,
3486                  * then we no longer need this entry.
3487                  */
3488                 memcpy(&tmp, &pci_boards[pbn_default],
3489                        sizeof(struct pciserial_board));
3490                 rc = serial_pci_guess_board(dev, &tmp);
3491                 if (rc == 0 && serial_pci_matches(board, &tmp))
3492                         moan_device("Redundant entry in serial pci_table.",
3493                                     dev);
3494         }
3495
3496         priv = pciserial_init_ports(dev, board);
3497         if (!IS_ERR(priv)) {
3498                 pci_set_drvdata(dev, priv);
3499                 return 0;
3500         }
3501
3502         rc = PTR_ERR(priv);
3503
3504  disable:
3505         pci_disable_device(dev);
3506         return rc;
3507 }
3508
3509 static void pciserial_remove_one(struct pci_dev *dev)
3510 {
3511         struct serial_private *priv = pci_get_drvdata(dev);
3512
3513         pci_set_drvdata(dev, NULL);
3514
3515         pciserial_remove_ports(priv);
3516
3517         pci_disable_device(dev);
3518 }
3519
3520 #ifdef CONFIG_PM
3521 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
3522 {
3523         struct serial_private *priv = pci_get_drvdata(dev);
3524
3525         if (priv)
3526                 pciserial_suspend_ports(priv);
3527
3528         pci_save_state(dev);
3529         pci_set_power_state(dev, pci_choose_state(dev, state));
3530         return 0;
3531 }
3532
3533 static int pciserial_resume_one(struct pci_dev *dev)
3534 {
3535         int err;
3536         struct serial_private *priv = pci_get_drvdata(dev);
3537
3538         pci_set_power_state(dev, PCI_D0);
3539         pci_restore_state(dev);
3540
3541         if (priv) {
3542                 /*
3543                  * The device may have been disabled.  Re-enable it.
3544                  */
3545                 err = pci_enable_device(dev);
3546                 /* FIXME: We cannot simply error out here */
3547                 if (err)
3548                         printk(KERN_ERR "pciserial: Unable to re-enable ports, trying to continue.\n");
3549                 pciserial_resume_ports(priv);
3550         }
3551         return 0;
3552 }
3553 #endif
3554
3555 static struct pci_device_id serial_pci_tbl[] = {
3556         /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3557         {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3558                 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3559                 pbn_b2_8_921600 },
3560         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3561                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3562                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3563                 pbn_b1_8_1382400 },
3564         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3565                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3566                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3567                 pbn_b1_4_1382400 },
3568         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3569                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3570                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3571                 pbn_b1_2_1382400 },
3572         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3573                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3574                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3575                 pbn_b1_8_1382400 },
3576         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3577                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3578                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3579                 pbn_b1_4_1382400 },
3580         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3581                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3582                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3583                 pbn_b1_2_1382400 },
3584         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3585                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3586                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3587                 pbn_b1_8_921600 },
3588         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3589                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3590                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3591                 pbn_b1_8_921600 },
3592         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3593                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3594                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3595                 pbn_b1_4_921600 },
3596         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3597                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3598                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3599                 pbn_b1_4_921600 },
3600         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3601                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3602                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3603                 pbn_b1_2_921600 },
3604         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3605                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3606                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3607                 pbn_b1_8_921600 },
3608         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3609                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3610                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3611                 pbn_b1_8_921600 },
3612         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3613                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3614                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3615                 pbn_b1_4_921600 },
3616         {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3617                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3618                 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3619                 pbn_b1_2_1250000 },
3620         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3621                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3622                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3623                 pbn_b0_2_1843200 },
3624         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3625                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3626                 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3627                 pbn_b0_4_1843200 },
3628         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3629                 PCI_VENDOR_ID_AFAVLAB,
3630                 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3631                 pbn_b0_4_1152000 },
3632         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3633                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3634                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_232, 0, 0,
3635                 pbn_b0_2_1843200_200 },
3636         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3637                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3638                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_232, 0, 0,
3639                 pbn_b0_4_1843200_200 },
3640         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3641                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3642                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_232, 0, 0,
3643                 pbn_b0_8_1843200_200 },
3644         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3645                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3646                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_1_1, 0, 0,
3647                 pbn_b0_2_1843200_200 },
3648         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3649                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3650                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_2, 0, 0,
3651                 pbn_b0_4_1843200_200 },
3652         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3653                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3654                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_4, 0, 0,
3655                 pbn_b0_8_1843200_200 },
3656         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3657                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3658                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2, 0, 0,
3659                 pbn_b0_2_1843200_200 },
3660         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3661                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3662                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4, 0, 0,
3663                 pbn_b0_4_1843200_200 },
3664         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3665                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3666                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8, 0, 0,
3667                 pbn_b0_8_1843200_200 },
3668         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3669                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3670                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_2_485, 0, 0,
3671                 pbn_b0_2_1843200_200 },
3672         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
3673                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3674                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_4_485, 0, 0,
3675                 pbn_b0_4_1843200_200 },
3676         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
3677                 PCI_SUBVENDOR_ID_CONNECT_TECH,
3678                 PCI_SUBDEVICE_ID_CONNECT_TECH_PCI_UART_8_485, 0, 0,
3679                 pbn_b0_8_1843200_200 },
3680         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
3681                 PCI_VENDOR_ID_IBM, PCI_SUBDEVICE_ID_IBM_SATURN_SERIAL_ONE_PORT,
3682                 0, 0, pbn_exar_ibm_saturn },
3683
3684         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3685                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3686                 pbn_b2_bt_1_115200 },
3687         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3688                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3689                 pbn_b2_bt_2_115200 },
3690         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3691                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3692                 pbn_b2_bt_4_115200 },
3693         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3694                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3695                 pbn_b2_bt_2_115200 },
3696         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3697                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3698                 pbn_b2_bt_4_115200 },
3699         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3700                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3701                 pbn_b2_8_115200 },
3702         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3703                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3704                 pbn_b2_8_460800 },
3705         {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3706                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3707                 pbn_b2_8_115200 },
3708
3709         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3710                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3711                 pbn_b2_bt_2_115200 },
3712         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3713                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3714                 pbn_b2_bt_2_921600 },
3715         /*
3716          * VScom SPCOM800, from sl@s.pl
3717          */
3718         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3719                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3720                 pbn_b2_8_921600 },
3721         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3722                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3723                 pbn_b2_4_921600 },
3724         /* Unknown card - subdevice 0x1584 */
3725         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3726                 PCI_VENDOR_ID_PLX,
3727                 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3728                 pbn_b2_4_115200 },
3729         /* Unknown card - subdevice 0x1588 */
3730         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3731                 PCI_VENDOR_ID_PLX,
3732                 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3733                 pbn_b2_8_115200 },
3734         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3735                 PCI_SUBVENDOR_ID_KEYSPAN,
3736                 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3737                 pbn_panacom },
3738         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3739                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3740                 pbn_panacom4 },
3741         {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3742                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3743                 pbn_panacom2 },
3744         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3745                 PCI_VENDOR_ID_ESDGMBH,
3746                 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3747                 pbn_b2_4_115200 },
3748         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3749                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3750                 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3751                 pbn_b2_4_460800 },
3752         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3753                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3754                 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3755                 pbn_b2_8_460800 },
3756         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3757                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3758                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
3759                 pbn_b2_16_460800 },
3760         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3761                 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3762                 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
3763                 pbn_b2_16_460800 },
3764         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3765                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3766                 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
3767                 pbn_b2_4_460800 },
3768         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3769                 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
3770                 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
3771                 pbn_b2_8_460800 },
3772         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3773                 PCI_SUBVENDOR_ID_EXSYS,
3774                 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
3775                 pbn_b2_4_115200 },
3776         /*
3777          * Megawolf Romulus PCI Serial Card, from Mike Hudson
3778          * (Exoray@isys.ca)
3779          */
3780         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
3781                 0x10b5, 0x106a, 0, 0,
3782                 pbn_plx_romulus },
3783         /*
3784          * Quatech cards. These actually have configurable clocks but for
3785          * now we just use the default.
3786          *
3787          * 100 series are RS232, 200 series RS422,
3788          */
3789         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
3790                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3791                 pbn_b1_4_115200 },
3792         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
3793                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3794                 pbn_b1_2_115200 },
3795         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
3796                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3797                 pbn_b2_2_115200 },
3798         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
3799                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3800                 pbn_b1_2_115200 },
3801         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
3802                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3803                 pbn_b2_2_115200 },
3804         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
3805                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3806                 pbn_b1_4_115200 },
3807         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
3808                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3809                 pbn_b1_8_115200 },
3810         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
3811                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3812                 pbn_b1_8_115200 },
3813         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
3814                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3815                 pbn_b1_4_115200 },
3816         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
3817                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3818                 pbn_b1_2_115200 },
3819         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
3820                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3821                 pbn_b1_4_115200 },
3822         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
3823                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3824                 pbn_b1_2_115200 },
3825         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
3826                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3827                 pbn_b2_4_115200 },
3828         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
3829                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3830                 pbn_b2_2_115200 },
3831         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
3832                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3833                 pbn_b2_1_115200 },
3834         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
3835                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3836                 pbn_b2_4_115200 },
3837         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
3838                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3839                 pbn_b2_2_115200 },
3840         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
3841                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3842                 pbn_b2_1_115200 },
3843         {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
3844                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3845                 pbn_b0_8_115200 },
3846
3847         {       PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
3848                 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
3849                 0, 0,
3850                 pbn_b0_4_921600 },
3851         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3852                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
3853                 0, 0,
3854                 pbn_b0_4_1152000 },
3855         {       PCI_VENDOR_ID_OXSEMI, 0x9505,
3856                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3857                 pbn_b0_bt_2_921600 },
3858
3859                 /*
3860                  * The below card is a little controversial since it is the
3861                  * subject of a PCI vendor/device ID clash.  (See
3862                  * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
3863                  * For now just used the hex ID 0x950a.
3864                  */
3865         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3866                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
3867                 0, 0, pbn_b0_2_115200 },
3868         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3869                 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
3870                 0, 0, pbn_b0_2_115200 },
3871         {       PCI_VENDOR_ID_OXSEMI, 0x950a,
3872                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3873                 pbn_b0_2_1130000 },
3874         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
3875                 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
3876                 pbn_b0_1_921600 },
3877         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3878                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3879                 pbn_b0_4_115200 },
3880         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
3881                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3882                 pbn_b0_bt_2_921600 },
3883         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
3884                 PCI_ANY_ID , PCI_ANY_ID, 0, 0,
3885                 pbn_b2_8_1152000 },
3886
3887         /*
3888          * Oxford Semiconductor Inc. Tornado PCI express device range.
3889          */
3890         {       PCI_VENDOR_ID_OXSEMI, 0xc101,    /* OXPCIe952 1 Legacy UART */
3891                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3892                 pbn_b0_1_4000000 },
3893         {       PCI_VENDOR_ID_OXSEMI, 0xc105,    /* OXPCIe952 1 Legacy UART */
3894                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3895                 pbn_b0_1_4000000 },
3896         {       PCI_VENDOR_ID_OXSEMI, 0xc11b,    /* OXPCIe952 1 Native UART */
3897                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3898                 pbn_oxsemi_1_4000000 },
3899         {       PCI_VENDOR_ID_OXSEMI, 0xc11f,    /* OXPCIe952 1 Native UART */
3900                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3901                 pbn_oxsemi_1_4000000 },
3902         {       PCI_VENDOR_ID_OXSEMI, 0xc120,    /* OXPCIe952 1 Legacy UART */
3903                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3904                 pbn_b0_1_4000000 },
3905         {       PCI_VENDOR_ID_OXSEMI, 0xc124,    /* OXPCIe952 1 Legacy UART */
3906                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3907                 pbn_b0_1_4000000 },
3908         {       PCI_VENDOR_ID_OXSEMI, 0xc138,    /* OXPCIe952 1 Native UART */
3909                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3910                 pbn_oxsemi_1_4000000 },
3911         {       PCI_VENDOR_ID_OXSEMI, 0xc13d,    /* OXPCIe952 1 Native UART */
3912                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3913                 pbn_oxsemi_1_4000000 },
3914         {       PCI_VENDOR_ID_OXSEMI, 0xc140,    /* OXPCIe952 1 Legacy UART */
3915                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3916                 pbn_b0_1_4000000 },
3917         {       PCI_VENDOR_ID_OXSEMI, 0xc141,    /* OXPCIe952 1 Legacy UART */
3918                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3919                 pbn_b0_1_4000000 },
3920         {       PCI_VENDOR_ID_OXSEMI, 0xc144,    /* OXPCIe952 1 Legacy UART */
3921                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3922                 pbn_b0_1_4000000 },
3923         {       PCI_VENDOR_ID_OXSEMI, 0xc145,    /* OXPCIe952 1 Legacy UART */
3924                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3925                 pbn_b0_1_4000000 },
3926         {       PCI_VENDOR_ID_OXSEMI, 0xc158,    /* OXPCIe952 2 Native UART */
3927                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3928                 pbn_oxsemi_2_4000000 },
3929         {       PCI_VENDOR_ID_OXSEMI, 0xc15d,    /* OXPCIe952 2 Native UART */
3930                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931                 pbn_oxsemi_2_4000000 },
3932         {       PCI_VENDOR_ID_OXSEMI, 0xc208,    /* OXPCIe954 4 Native UART */
3933                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3934                 pbn_oxsemi_4_4000000 },
3935         {       PCI_VENDOR_ID_OXSEMI, 0xc20d,    /* OXPCIe954 4 Native UART */
3936                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937                 pbn_oxsemi_4_4000000 },
3938         {       PCI_VENDOR_ID_OXSEMI, 0xc308,    /* OXPCIe958 8 Native UART */
3939                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3940                 pbn_oxsemi_8_4000000 },
3941         {       PCI_VENDOR_ID_OXSEMI, 0xc30d,    /* OXPCIe958 8 Native UART */
3942                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943                 pbn_oxsemi_8_4000000 },
3944         {       PCI_VENDOR_ID_OXSEMI, 0xc40b,    /* OXPCIe200 1 Native UART */
3945                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946                 pbn_oxsemi_1_4000000 },
3947         {       PCI_VENDOR_ID_OXSEMI, 0xc40f,    /* OXPCIe200 1 Native UART */
3948                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949                 pbn_oxsemi_1_4000000 },
3950         {       PCI_VENDOR_ID_OXSEMI, 0xc41b,    /* OXPCIe200 1 Native UART */
3951                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3952                 pbn_oxsemi_1_4000000 },
3953         {       PCI_VENDOR_ID_OXSEMI, 0xc41f,    /* OXPCIe200 1 Native UART */
3954                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3955                 pbn_oxsemi_1_4000000 },
3956         {       PCI_VENDOR_ID_OXSEMI, 0xc42b,    /* OXPCIe200 1 Native UART */
3957                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3958                 pbn_oxsemi_1_4000000 },
3959         {       PCI_VENDOR_ID_OXSEMI, 0xc42f,    /* OXPCIe200 1 Native UART */
3960                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3961                 pbn_oxsemi_1_4000000 },
3962         {       PCI_VENDOR_ID_OXSEMI, 0xc43b,    /* OXPCIe200 1 Native UART */
3963                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3964                 pbn_oxsemi_1_4000000 },
3965         {       PCI_VENDOR_ID_OXSEMI, 0xc43f,    /* OXPCIe200 1 Native UART */
3966                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3967                 pbn_oxsemi_1_4000000 },
3968         {       PCI_VENDOR_ID_OXSEMI, 0xc44b,    /* OXPCIe200 1 Native UART */
3969                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3970                 pbn_oxsemi_1_4000000 },
3971         {       PCI_VENDOR_ID_OXSEMI, 0xc44f,    /* OXPCIe200 1 Native UART */
3972                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3973                 pbn_oxsemi_1_4000000 },
3974         {       PCI_VENDOR_ID_OXSEMI, 0xc45b,    /* OXPCIe200 1 Native UART */
3975                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3976                 pbn_oxsemi_1_4000000 },
3977         {       PCI_VENDOR_ID_OXSEMI, 0xc45f,    /* OXPCIe200 1 Native UART */
3978                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3979                 pbn_oxsemi_1_4000000 },
3980         {       PCI_VENDOR_ID_OXSEMI, 0xc46b,    /* OXPCIe200 1 Native UART */
3981                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3982                 pbn_oxsemi_1_4000000 },
3983         {       PCI_VENDOR_ID_OXSEMI, 0xc46f,    /* OXPCIe200 1 Native UART */
3984                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3985                 pbn_oxsemi_1_4000000 },
3986         {       PCI_VENDOR_ID_OXSEMI, 0xc47b,    /* OXPCIe200 1 Native UART */
3987                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3988                 pbn_oxsemi_1_4000000 },
3989         {       PCI_VENDOR_ID_OXSEMI, 0xc47f,    /* OXPCIe200 1 Native UART */
3990                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3991                 pbn_oxsemi_1_4000000 },
3992         {       PCI_VENDOR_ID_OXSEMI, 0xc48b,    /* OXPCIe200 1 Native UART */
3993                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3994                 pbn_oxsemi_1_4000000 },
3995         {       PCI_VENDOR_ID_OXSEMI, 0xc48f,    /* OXPCIe200 1 Native UART */
3996                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3997                 pbn_oxsemi_1_4000000 },
3998         {       PCI_VENDOR_ID_OXSEMI, 0xc49b,    /* OXPCIe200 1 Native UART */
3999                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4000                 pbn_oxsemi_1_4000000 },
4001         {       PCI_VENDOR_ID_OXSEMI, 0xc49f,    /* OXPCIe200 1 Native UART */
4002                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4003                 pbn_oxsemi_1_4000000 },
4004         {       PCI_VENDOR_ID_OXSEMI, 0xc4ab,    /* OXPCIe200 1 Native UART */
4005                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4006                 pbn_oxsemi_1_4000000 },
4007         {       PCI_VENDOR_ID_OXSEMI, 0xc4af,    /* OXPCIe200 1 Native UART */
4008                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4009                 pbn_oxsemi_1_4000000 },
4010         {       PCI_VENDOR_ID_OXSEMI, 0xc4bb,    /* OXPCIe200 1 Native UART */
4011                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4012                 pbn_oxsemi_1_4000000 },
4013         {       PCI_VENDOR_ID_OXSEMI, 0xc4bf,    /* OXPCIe200 1 Native UART */
4014                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4015                 pbn_oxsemi_1_4000000 },
4016         {       PCI_VENDOR_ID_OXSEMI, 0xc4cb,    /* OXPCIe200 1 Native UART */
4017                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4018                 pbn_oxsemi_1_4000000 },
4019         {       PCI_VENDOR_ID_OXSEMI, 0xc4cf,    /* OXPCIe200 1 Native UART */
4020                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4021                 pbn_oxsemi_1_4000000 },
4022         /*
4023          * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4024          */
4025         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4026                 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4027                 pbn_oxsemi_1_4000000 },
4028         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4029                 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4030                 pbn_oxsemi_2_4000000 },
4031         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4032                 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4033                 pbn_oxsemi_4_4000000 },
4034         {       PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4035                 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4036                 pbn_oxsemi_8_4000000 },
4037
4038         /*
4039          * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4040          */
4041         {       PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4042                 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4043                 pbn_oxsemi_2_4000000 },
4044
4045         /*
4046          * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4047          * from skokodyn@yahoo.com
4048          */
4049         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4050                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4051                 pbn_sbsxrsio },
4052         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4053                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4054                 pbn_sbsxrsio },
4055         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4056                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4057                 pbn_sbsxrsio },
4058         {       PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4059                 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4060                 pbn_sbsxrsio },
4061
4062         /*
4063          * Digitan DS560-558, from jimd@esoft.com
4064          */
4065         {       PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4066                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4067                 pbn_b1_1_115200 },
4068
4069         /*
4070          * Titan Electronic cards
4071          *  The 400L and 800L have a custom setup quirk.
4072          */
4073         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4074                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4075                 pbn_b0_1_921600 },
4076         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4077                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4078                 pbn_b0_2_921600 },
4079         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4080                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4081                 pbn_b0_4_921600 },
4082         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4083                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4084                 pbn_b0_4_921600 },
4085         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4086                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4087                 pbn_b1_1_921600 },
4088         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4089                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4090                 pbn_b1_bt_2_921600 },
4091         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4092                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4093                 pbn_b0_bt_4_921600 },
4094         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4095                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4096                 pbn_b0_bt_8_921600 },
4097         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4098                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4099                 pbn_b4_bt_2_921600 },
4100         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4101                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4102                 pbn_b4_bt_4_921600 },
4103         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4104                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4105                 pbn_b4_bt_8_921600 },
4106         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4107                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4108                 pbn_b0_4_921600 },
4109         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4110                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4111                 pbn_b0_4_921600 },
4112         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4113                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4114                 pbn_b0_4_921600 },
4115         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4116                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4117                 pbn_oxsemi_1_4000000 },
4118         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4119                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4120                 pbn_oxsemi_2_4000000 },
4121         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4122                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4123                 pbn_oxsemi_4_4000000 },
4124         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4125                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4126                 pbn_oxsemi_8_4000000 },
4127         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4128                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4129                 pbn_oxsemi_2_4000000 },
4130         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4131                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4132                 pbn_oxsemi_2_4000000 },
4133         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4134                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4135                 pbn_b0_4_921600 },
4136         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4137                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4138                 pbn_b0_4_921600 },
4139         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4140                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141                 pbn_b0_4_921600 },
4142         {       PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4143                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144                 pbn_b0_4_921600 },
4145
4146         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4147                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4148                 pbn_b2_1_460800 },
4149         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4150                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4151                 pbn_b2_1_460800 },
4152         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4153                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4154                 pbn_b2_1_460800 },
4155         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4156                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4157                 pbn_b2_bt_2_921600 },
4158         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4159                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4160                 pbn_b2_bt_2_921600 },
4161         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4162                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4163                 pbn_b2_bt_2_921600 },
4164         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4165                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4166                 pbn_b2_bt_4_921600 },
4167         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4168                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4169                 pbn_b2_bt_4_921600 },
4170         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4171                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4172                 pbn_b2_bt_4_921600 },
4173         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4174                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4175                 pbn_b0_1_921600 },
4176         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4177                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4178                 pbn_b0_1_921600 },
4179         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4180                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4181                 pbn_b0_1_921600 },
4182         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4183                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4184                 pbn_b0_bt_2_921600 },
4185         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4186                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4187                 pbn_b0_bt_2_921600 },
4188         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4189                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4190                 pbn_b0_bt_2_921600 },
4191         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4192                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4193                 pbn_b0_bt_4_921600 },
4194         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4195                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4196                 pbn_b0_bt_4_921600 },
4197         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4198                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4199                 pbn_b0_bt_4_921600 },
4200         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4201                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4202                 pbn_b0_bt_8_921600 },
4203         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4204                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4205                 pbn_b0_bt_8_921600 },
4206         {       PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4207                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4208                 pbn_b0_bt_8_921600 },
4209
4210         /*
4211          * Computone devices submitted by Doug McNash dmcnash@computone.com
4212          */
4213         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4214                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4215                 0, 0, pbn_computone_4 },
4216         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4217                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4218                 0, 0, pbn_computone_8 },
4219         {       PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4220                 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4221                 0, 0, pbn_computone_6 },
4222
4223         {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4224                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225                 pbn_oxsemi },
4226         {       PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4227                 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4228                 pbn_b0_bt_1_921600 },
4229
4230         /*
4231          * SUNIX (TIMEDIA)
4232          */
4233         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4234                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4235                 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4236                 pbn_b0_bt_1_921600 },
4237
4238         {       PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4239                 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4240                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4241                 pbn_b0_bt_1_921600 },
4242
4243         /*
4244          * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4245          */
4246         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4247                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4248                 pbn_b0_bt_8_115200 },
4249         {       PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4250                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4251                 pbn_b0_bt_8_115200 },
4252
4253         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4254                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255                 pbn_b0_bt_2_115200 },
4256         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4257                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258                 pbn_b0_bt_2_115200 },
4259         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4260                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261                 pbn_b0_bt_2_115200 },
4262         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4263                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264                 pbn_b0_bt_2_115200 },
4265         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4266                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267                 pbn_b0_bt_2_115200 },
4268         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4269                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270                 pbn_b0_bt_4_460800 },
4271         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4272                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4273                 pbn_b0_bt_4_460800 },
4274         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4275                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4276                 pbn_b0_bt_2_460800 },
4277         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4278                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4279                 pbn_b0_bt_2_460800 },
4280         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4281                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4282                 pbn_b0_bt_2_460800 },
4283         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4284                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4285                 pbn_b0_bt_1_115200 },
4286         {       PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4287                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4288                 pbn_b0_bt_1_460800 },
4289
4290         /*
4291          * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4292          * Cards are identified by their subsystem vendor IDs, which
4293          * (in hex) match the model number.
4294          *
4295          * Note that JC140x are RS422/485 cards which require ox950
4296          * ACR = 0x10, and as such are not currently fully supported.
4297          */
4298         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4299                 0x1204, 0x0004, 0, 0,
4300                 pbn_b0_4_921600 },
4301         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4302                 0x1208, 0x0004, 0, 0,
4303                 pbn_b0_4_921600 },
4304 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4305                 0x1402, 0x0002, 0, 0,
4306                 pbn_b0_2_921600 }, */
4307 /*      {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4308                 0x1404, 0x0004, 0, 0,
4309                 pbn_b0_4_921600 }, */
4310         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4311                 0x1208, 0x0004, 0, 0,
4312                 pbn_b0_4_921600 },
4313
4314         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4315                 0x1204, 0x0004, 0, 0,
4316                 pbn_b0_4_921600 },
4317         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4318                 0x1208, 0x0004, 0, 0,
4319                 pbn_b0_4_921600 },
4320         {       PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4321                 0x1208, 0x0004, 0, 0,
4322                 pbn_b0_4_921600 },
4323         /*
4324          * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4325          */
4326         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4327                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328                 pbn_b1_1_1382400 },
4329
4330         /*
4331          * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4332          */
4333         {       PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4334                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335                 pbn_b1_1_1382400 },
4336
4337         /*
4338          * RAStel 2 port modem, gerg@moreton.com.au
4339          */
4340         {       PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4341                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342                 pbn_b2_bt_2_115200 },
4343
4344         /*
4345          * EKF addition for i960 Boards form EKF with serial port
4346          */
4347         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4348                 0xE4BF, PCI_ANY_ID, 0, 0,
4349                 pbn_intel_i960 },
4350
4351         /*
4352          * Xircom Cardbus/Ethernet combos
4353          */
4354         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4355                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4356                 pbn_b0_1_115200 },
4357         /*
4358          * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4359          */
4360         {       PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4361                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4362                 pbn_b0_1_115200 },
4363
4364         /*
4365          * Untested PCI modems, sent in from various folks...
4366          */
4367
4368         /*
4369          * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4370          */
4371         {       PCI_VENDOR_ID_ROCKWELL, 0x1004,
4372                 0x1048, 0x1500, 0, 0,
4373                 pbn_b1_1_115200 },
4374
4375         {       PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4376                 0xFF00, 0, 0, 0,
4377                 pbn_sgi_ioc3 },
4378
4379         /*
4380          * HP Diva card
4381          */
4382         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4383                 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4384                 pbn_b1_1_115200 },
4385         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4386                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387                 pbn_b0_5_115200 },
4388         {       PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4389                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390                 pbn_b2_1_115200 },
4391
4392         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4393                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4394                 pbn_b3_2_115200 },
4395         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4396                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4397                 pbn_b3_4_115200 },
4398         {       PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4399                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400                 pbn_b3_8_115200 },
4401
4402         /*
4403          * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
4404          */
4405         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
4406                 PCI_ANY_ID, PCI_ANY_ID,
4407                 0,
4408                 0, pbn_exar_XR17C152 },
4409         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
4410                 PCI_ANY_ID, PCI_ANY_ID,
4411                 0,
4412                 0, pbn_exar_XR17C154 },
4413         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
4414                 PCI_ANY_ID, PCI_ANY_ID,
4415                 0,
4416                 0, pbn_exar_XR17C158 },
4417         /*
4418          * Exar Corp. XR17V35[248] Dual/Quad/Octal PCIe UARTs
4419          */
4420         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V352,
4421                 PCI_ANY_ID, PCI_ANY_ID,
4422                 0,
4423                 0, pbn_exar_XR17V352 },
4424         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V354,
4425                 PCI_ANY_ID, PCI_ANY_ID,
4426                 0,
4427                 0, pbn_exar_XR17V354 },
4428         {       PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17V358,
4429                 PCI_ANY_ID, PCI_ANY_ID,
4430                 0,
4431                 0, pbn_exar_XR17V358 },
4432
4433         /*
4434          * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4435          */
4436         {       PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4437                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4438                 pbn_b0_1_115200 },
4439         /*
4440          * ITE
4441          */
4442         {       PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4443                 PCI_ANY_ID, PCI_ANY_ID,
4444                 0, 0,
4445                 pbn_b1_bt_1_115200 },
4446
4447         /*
4448          * IntaShield IS-200
4449          */
4450         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4451                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,   /* 135a.0811 */
4452                 pbn_b2_2_115200 },
4453         /*
4454          * IntaShield IS-400
4455          */
4456         {       PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4457                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,    /* 135a.0dc0 */
4458                 pbn_b2_4_115200 },
4459         /*
4460          * Perle PCI-RAS cards
4461          */
4462         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4463                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4464                 0, 0, pbn_b2_4_921600 },
4465         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4466                 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4467                 0, 0, pbn_b2_8_921600 },
4468
4469         /*
4470          * Mainpine series cards: Fairly standard layout but fools
4471          * parts of the autodetect in some cases and uses otherwise
4472          * unmatched communications subclasses in the PCI Express case
4473          */
4474
4475         {       /* RockForceDUO */
4476                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4477                 PCI_VENDOR_ID_MAINPINE, 0x0200,
4478                 0, 0, pbn_b0_2_115200 },
4479         {       /* RockForceQUATRO */
4480                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4481                 PCI_VENDOR_ID_MAINPINE, 0x0300,
4482                 0, 0, pbn_b0_4_115200 },
4483         {       /* RockForceDUO+ */
4484                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4485                 PCI_VENDOR_ID_MAINPINE, 0x0400,
4486                 0, 0, pbn_b0_2_115200 },
4487         {       /* RockForceQUATRO+ */
4488                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4489                 PCI_VENDOR_ID_MAINPINE, 0x0500,
4490                 0, 0, pbn_b0_4_115200 },
4491         {       /* RockForce+ */
4492                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4493                 PCI_VENDOR_ID_MAINPINE, 0x0600,
4494                 0, 0, pbn_b0_2_115200 },
4495         {       /* RockForce+ */
4496                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4497                 PCI_VENDOR_ID_MAINPINE, 0x0700,
4498                 0, 0, pbn_b0_4_115200 },
4499         {       /* RockForceOCTO+ */
4500                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4501                 PCI_VENDOR_ID_MAINPINE, 0x0800,
4502                 0, 0, pbn_b0_8_115200 },
4503         {       /* RockForceDUO+ */
4504                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4505                 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4506                 0, 0, pbn_b0_2_115200 },
4507         {       /* RockForceQUARTRO+ */
4508                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4509                 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4510                 0, 0, pbn_b0_4_115200 },
4511         {       /* RockForceOCTO+ */
4512                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4513                 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4514                 0, 0, pbn_b0_8_115200 },
4515         {       /* RockForceD1 */
4516                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4517                 PCI_VENDOR_ID_MAINPINE, 0x2000,
4518                 0, 0, pbn_b0_1_115200 },
4519         {       /* RockForceF1 */
4520                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4521                 PCI_VENDOR_ID_MAINPINE, 0x2100,
4522                 0, 0, pbn_b0_1_115200 },
4523         {       /* RockForceD2 */
4524                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4525                 PCI_VENDOR_ID_MAINPINE, 0x2200,
4526                 0, 0, pbn_b0_2_115200 },
4527         {       /* RockForceF2 */
4528                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4529                 PCI_VENDOR_ID_MAINPINE, 0x2300,
4530                 0, 0, pbn_b0_2_115200 },
4531         {       /* RockForceD4 */
4532                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4533                 PCI_VENDOR_ID_MAINPINE, 0x2400,
4534                 0, 0, pbn_b0_4_115200 },
4535         {       /* RockForceF4 */
4536                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4537                 PCI_VENDOR_ID_MAINPINE, 0x2500,
4538                 0, 0, pbn_b0_4_115200 },
4539         {       /* RockForceD8 */
4540                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4541                 PCI_VENDOR_ID_MAINPINE, 0x2600,
4542                 0, 0, pbn_b0_8_115200 },
4543         {       /* RockForceF8 */
4544                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4545                 PCI_VENDOR_ID_MAINPINE, 0x2700,
4546                 0, 0, pbn_b0_8_115200 },
4547         {       /* IQ Express D1 */
4548                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4549                 PCI_VENDOR_ID_MAINPINE, 0x3000,
4550                 0, 0, pbn_b0_1_115200 },
4551         {       /* IQ Express F1 */
4552                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4553                 PCI_VENDOR_ID_MAINPINE, 0x3100,
4554                 0, 0, pbn_b0_1_115200 },
4555         {       /* IQ Express D2 */
4556                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4557                 PCI_VENDOR_ID_MAINPINE, 0x3200,
4558                 0, 0, pbn_b0_2_115200 },
4559         {       /* IQ Express F2 */
4560                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4561                 PCI_VENDOR_ID_MAINPINE, 0x3300,
4562                 0, 0, pbn_b0_2_115200 },
4563         {       /* IQ Express D4 */
4564                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4565                 PCI_VENDOR_ID_MAINPINE, 0x3400,
4566                 0, 0, pbn_b0_4_115200 },
4567         {       /* IQ Express F4 */
4568                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4569                 PCI_VENDOR_ID_MAINPINE, 0x3500,
4570                 0, 0, pbn_b0_4_115200 },
4571         {       /* IQ Express D8 */
4572                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4573                 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4574                 0, 0, pbn_b0_8_115200 },
4575         {       /* IQ Express F8 */
4576                 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4577                 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4578                 0, 0, pbn_b0_8_115200 },
4579
4580
4581         /*
4582          * PA Semi PA6T-1682M on-chip UART
4583          */
4584         {       PCI_VENDOR_ID_PASEMI, 0xa004,
4585                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4586                 pbn_pasemi_1682M },
4587
4588         /*
4589          * National Instruments
4590          */
4591         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4592                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4593                 pbn_b1_16_115200 },
4594         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4595                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4596                 pbn_b1_8_115200 },
4597         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4598                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4599                 pbn_b1_bt_4_115200 },
4600         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4601                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4602                 pbn_b1_bt_2_115200 },
4603         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4604                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4605                 pbn_b1_bt_4_115200 },
4606         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4607                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608                 pbn_b1_bt_2_115200 },
4609         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4610                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4611                 pbn_b1_16_115200 },
4612         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4613                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614                 pbn_b1_8_115200 },
4615         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4616                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4617                 pbn_b1_bt_4_115200 },
4618         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4619                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4620                 pbn_b1_bt_2_115200 },
4621         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4622                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4623                 pbn_b1_bt_4_115200 },
4624         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4625                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4626                 pbn_b1_bt_2_115200 },
4627         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4628                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4629                 pbn_ni8430_2 },
4630         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4631                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4632                 pbn_ni8430_2 },
4633         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4634                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4635                 pbn_ni8430_4 },
4636         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4637                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4638                 pbn_ni8430_4 },
4639         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4640                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4641                 pbn_ni8430_8 },
4642         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4643                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4644                 pbn_ni8430_8 },
4645         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4646                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4647                 pbn_ni8430_16 },
4648         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
4649                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4650                 pbn_ni8430_16 },
4651         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
4652                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4653                 pbn_ni8430_2 },
4654         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
4655                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4656                 pbn_ni8430_2 },
4657         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
4658                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4659                 pbn_ni8430_4 },
4660         {       PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
4661                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4662                 pbn_ni8430_4 },
4663
4664         /*
4665         * ADDI-DATA GmbH communication cards <info@addi-data.com>
4666         */
4667         {       PCI_VENDOR_ID_ADDIDATA,
4668                 PCI_DEVICE_ID_ADDIDATA_APCI7500,
4669                 PCI_ANY_ID,
4670                 PCI_ANY_ID,
4671                 0,
4672                 0,
4673                 pbn_b0_4_115200 },
4674
4675         {       PCI_VENDOR_ID_ADDIDATA,
4676                 PCI_DEVICE_ID_ADDIDATA_APCI7420,
4677                 PCI_ANY_ID,
4678                 PCI_ANY_ID,
4679                 0,
4680                 0,
4681                 pbn_b0_2_115200 },
4682
4683         {       PCI_VENDOR_ID_ADDIDATA,
4684                 PCI_DEVICE_ID_ADDIDATA_APCI7300,
4685                 PCI_ANY_ID,
4686                 PCI_ANY_ID,
4687                 0,
4688                 0,
4689                 pbn_b0_1_115200 },
4690
4691         {       PCI_VENDOR_ID_ADDIDATA_OLD,
4692                 PCI_DEVICE_ID_ADDIDATA_APCI7800,
4693                 PCI_ANY_ID,
4694                 PCI_ANY_ID,
4695                 0,
4696                 0,
4697                 pbn_b1_8_115200 },
4698
4699         {       PCI_VENDOR_ID_ADDIDATA,
4700                 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
4701                 PCI_ANY_ID,
4702                 PCI_ANY_ID,
4703                 0,
4704                 0,
4705                 pbn_b0_4_115200 },
4706
4707         {       PCI_VENDOR_ID_ADDIDATA,
4708                 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
4709                 PCI_ANY_ID,
4710                 PCI_ANY_ID,
4711                 0,
4712                 0,
4713                 pbn_b0_2_115200 },
4714
4715         {       PCI_VENDOR_ID_ADDIDATA,
4716                 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
4717                 PCI_ANY_ID,
4718                 PCI_ANY_ID,
4719                 0,
4720                 0,
4721                 pbn_b0_1_115200 },
4722
4723         {       PCI_VENDOR_ID_ADDIDATA,
4724                 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
4725                 PCI_ANY_ID,
4726                 PCI_ANY_ID,
4727                 0,
4728                 0,
4729                 pbn_b0_4_115200 },
4730
4731         {       PCI_VENDOR_ID_ADDIDATA,
4732                 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
4733                 PCI_ANY_ID,
4734                 PCI_ANY_ID,
4735                 0,
4736                 0,
4737                 pbn_b0_2_115200 },
4738
4739         {       PCI_VENDOR_ID_ADDIDATA,
4740                 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
4741                 PCI_ANY_ID,
4742                 PCI_ANY_ID,
4743                 0,
4744                 0,
4745                 pbn_b0_1_115200 },
4746
4747         {       PCI_VENDOR_ID_ADDIDATA,
4748                 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
4749                 PCI_ANY_ID,
4750                 PCI_ANY_ID,
4751                 0,
4752                 0,
4753                 pbn_b0_8_115200 },
4754
4755         {       PCI_VENDOR_ID_ADDIDATA,
4756                 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
4757                 PCI_ANY_ID,
4758                 PCI_ANY_ID,
4759                 0,
4760                 0,
4761                 pbn_ADDIDATA_PCIe_4_3906250 },
4762
4763         {       PCI_VENDOR_ID_ADDIDATA,
4764                 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
4765                 PCI_ANY_ID,
4766                 PCI_ANY_ID,
4767                 0,
4768                 0,
4769                 pbn_ADDIDATA_PCIe_2_3906250 },
4770
4771         {       PCI_VENDOR_ID_ADDIDATA,
4772                 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
4773                 PCI_ANY_ID,
4774                 PCI_ANY_ID,
4775                 0,
4776                 0,
4777                 pbn_ADDIDATA_PCIe_1_3906250 },
4778
4779         {       PCI_VENDOR_ID_ADDIDATA,
4780                 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
4781                 PCI_ANY_ID,
4782                 PCI_ANY_ID,
4783                 0,
4784                 0,
4785                 pbn_ADDIDATA_PCIe_8_3906250 },
4786
4787         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
4788                 PCI_VENDOR_ID_IBM, 0x0299,
4789                 0, 0, pbn_b0_bt_2_115200 },
4790
4791         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
4792                 0xA000, 0x1000,
4793                 0, 0, pbn_b0_1_115200 },
4794
4795         /* the 9901 is a rebranded 9912 */
4796         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
4797                 0xA000, 0x1000,
4798                 0, 0, pbn_b0_1_115200 },
4799
4800         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
4801                 0xA000, 0x1000,
4802                 0, 0, pbn_b0_1_115200 },
4803
4804         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
4805                 0xA000, 0x1000,
4806                 0, 0, pbn_b0_1_115200 },
4807
4808         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4809                 0xA000, 0x1000,
4810                 0, 0, pbn_b0_1_115200 },
4811
4812         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
4813                 0xA000, 0x3002,
4814                 0, 0, pbn_NETMOS9900_2s_115200 },
4815
4816         /*
4817          * Best Connectivity and Rosewill PCI Multi I/O cards
4818          */
4819
4820         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4821                 0xA000, 0x1000,
4822                 0, 0, pbn_b0_1_115200 },
4823
4824         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4825                 0xA000, 0x3002,
4826                 0, 0, pbn_b0_bt_2_115200 },
4827
4828         {       PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
4829                 0xA000, 0x3004,
4830                 0, 0, pbn_b0_bt_4_115200 },
4831         /* Intel CE4100 */
4832         {       PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
4833                 PCI_ANY_ID,  PCI_ANY_ID, 0, 0,
4834                 pbn_ce4100_1_115200 },
4835
4836         /*
4837          * Cronyx Omega PCI
4838          */
4839         {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
4840                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4841                 pbn_omegapci },
4842
4843         /*
4844          * Broadcom TruManage
4845          */
4846         {       PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
4847                 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4848                 pbn_brcm_trumanage },
4849
4850         /*
4851          * AgeStar as-prs2-009
4852          */
4853         {       PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
4854                 PCI_ANY_ID, PCI_ANY_ID,
4855                 0, 0, pbn_b0_bt_2_115200 },
4856
4857         /*
4858          * WCH CH353 series devices: The 2S1P is handled by parport_serial
4859          * so not listed here.
4860          */
4861         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
4862                 PCI_ANY_ID, PCI_ANY_ID,
4863                 0, 0, pbn_b0_bt_4_115200 },
4864
4865         {       PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
4866                 PCI_ANY_ID, PCI_ANY_ID,
4867                 0, 0, pbn_b0_bt_2_115200 },
4868
4869         /*
4870          * Commtech, Inc. Fastcom adapters
4871          */
4872         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCI335,
4873                 PCI_ANY_ID, PCI_ANY_ID,
4874                 0,
4875                 0, pbn_b0_2_1152000_200 },
4876         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCI335,
4877                 PCI_ANY_ID, PCI_ANY_ID,
4878                 0,
4879                 0, pbn_b0_4_1152000_200 },
4880         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2324PCI335,
4881                 PCI_ANY_ID, PCI_ANY_ID,
4882                 0,
4883                 0, pbn_b0_4_1152000_200 },
4884         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_2328PCI335,
4885                 PCI_ANY_ID, PCI_ANY_ID,
4886                 0,
4887                 0, pbn_b0_8_1152000_200 },
4888         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4222PCIE,
4889                 PCI_ANY_ID, PCI_ANY_ID,
4890                 0,
4891                 0, pbn_exar_XR17V352 },
4892         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4224PCIE,
4893                 PCI_ANY_ID, PCI_ANY_ID,
4894                 0,
4895                 0, pbn_exar_XR17V354 },
4896         {       PCI_VENDOR_ID_COMMTECH, PCI_DEVICE_ID_COMMTECH_4228PCIE,
4897                 PCI_ANY_ID, PCI_ANY_ID,
4898                 0,
4899                 0, pbn_exar_XR17V358 },
4900
4901         /*
4902          * These entries match devices with class COMMUNICATION_SERIAL,
4903          * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
4904          */
4905         {       PCI_ANY_ID, PCI_ANY_ID,
4906                 PCI_ANY_ID, PCI_ANY_ID,
4907                 PCI_CLASS_COMMUNICATION_SERIAL << 8,
4908                 0xffff00, pbn_default },
4909         {       PCI_ANY_ID, PCI_ANY_ID,
4910                 PCI_ANY_ID, PCI_ANY_ID,
4911                 PCI_CLASS_COMMUNICATION_MODEM << 8,
4912                 0xffff00, pbn_default },
4913         {       PCI_ANY_ID, PCI_ANY_ID,
4914                 PCI_ANY_ID, PCI_ANY_ID,
4915                 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
4916                 0xffff00, pbn_default },
4917         { 0, }
4918 };
4919
4920 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
4921                                                 pci_channel_state_t state)
4922 {
4923         struct serial_private *priv = pci_get_drvdata(dev);
4924
4925         if (state == pci_channel_io_perm_failure)
4926                 return PCI_ERS_RESULT_DISCONNECT;
4927
4928         if (priv)
4929                 pciserial_suspend_ports(priv);
4930
4931         pci_disable_device(dev);
4932
4933         return PCI_ERS_RESULT_NEED_RESET;
4934 }
4935
4936 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
4937 {
4938         int rc;
4939
4940         rc = pci_enable_device(dev);
4941
4942         if (rc)
4943                 return PCI_ERS_RESULT_DISCONNECT;
4944
4945         pci_restore_state(dev);
4946         pci_save_state(dev);
4947
4948         return PCI_ERS_RESULT_RECOVERED;
4949 }
4950
4951 static void serial8250_io_resume(struct pci_dev *dev)
4952 {
4953         struct serial_private *priv = pci_get_drvdata(dev);
4954
4955         if (priv)
4956                 pciserial_resume_ports(priv);
4957 }
4958
4959 static const struct pci_error_handlers serial8250_err_handler = {
4960         .error_detected = serial8250_io_error_detected,
4961         .slot_reset = serial8250_io_slot_reset,
4962         .resume = serial8250_io_resume,
4963 };
4964
4965 static struct pci_driver serial_pci_driver = {
4966         .name           = "serial",
4967         .probe          = pciserial_init_one,
4968         .remove         = pciserial_remove_one,
4969 #ifdef CONFIG_PM
4970         .suspend        = pciserial_suspend_one,
4971         .resume         = pciserial_resume_one,
4972 #endif
4973         .id_table       = serial_pci_tbl,
4974         .err_handler    = &serial8250_err_handler,
4975 };
4976
4977 module_pci_driver(serial_pci_driver);
4978
4979 MODULE_LICENSE("GPL");
4980 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
4981 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);