drivers/tty/serial/imx.c

   1 /*
   2  * Driver for Motorola/Freescale IMX serial ports
   3  *
   4  * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   5  *
   6  * Author: Sascha Hauer <sascha@saschahauer.de>
   7  * Copyright (C) 2004 Pengutronix
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  */
  19
  20 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  21 #define SUPPORT_SYSRQ
  22 #endif
  23
  24 #include <linux/module.h>
  25 #include <linux/ioport.h>
  26 #include <linux/init.h>
  27 #include <linux/console.h>
  28 #include <linux/sysrq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/tty.h>
  31 #include <linux/tty_flip.h>
  32 #include <linux/serial_core.h>
  33 #include <linux/serial.h>
  34 #include <linux/clk.h>
  35 #include <linux/delay.h>
  36 #include <linux/rational.h>
  37 #include <linux/slab.h>
  38 #include <linux/of.h>
  39 #include <linux/of_device.h>
  40 #include <linux/io.h>
  41 #include <linux/dma-mapping.h>
  42
  43 #include <asm/irq.h>
  44 #include <linux/platform_data/serial-imx.h>
  45 #include <linux/platform_data/dma-imx.h>
  46
  47 #include "serial_mctrl_gpio.h"
  48
  49 /* Register definitions */
  50 #define URXD0 0x0  /* Receiver Register */
  51 #define URTX0 0x40 /* Transmitter Register */
  52 #define UCR1  0x80 /* Control Register 1 */
  53 #define UCR2  0x84 /* Control Register 2 */
  54 #define UCR3  0x88 /* Control Register 3 */
  55 #define UCR4  0x8c /* Control Register 4 */
  56 #define UFCR  0x90 /* FIFO Control Register */
  57 #define USR1  0x94 /* Status Register 1 */
  58 #define USR2  0x98 /* Status Register 2 */
  59 #define UESC  0x9c /* Escape Character Register */
  60 #define UTIM  0xa0 /* Escape Timer Register */
  61 #define UBIR  0xa4 /* BRM Incremental Register */
  62 #define UBMR  0xa8 /* BRM Modulator Register */
  63 #define UBRC  0xac /* Baud Rate Count Register */
  64 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
  65 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
  66 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
  67
  68 /* UART Control Register Bit Fields.*/
  69 #define URXD_DUMMY_READ (1<<16)
  70 #define URXD_CHARRDY    (1<<15)
  71 #define URXD_ERR        (1<<14)
  72 #define URXD_OVRRUN     (1<<13)
  73 #define URXD_FRMERR     (1<<12)
  74 #define URXD_BRK        (1<<11)
  75 #define URXD_PRERR      (1<<10)
  76 #define URXD_RX_DATA    (0xFF<<0)
  77 #define UCR1_ADEN       (1<<15) /* Auto detect interrupt */
  78 #define UCR1_ADBR       (1<<14) /* Auto detect baud rate */
  79 #define UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
  80 #define UCR1_IDEN       (1<<12) /* Idle condition interrupt */
  81 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
  82 #define UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
  83 #define UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
  84 #define UCR1_IREN       (1<<7)  /* Infrared interface enable */
  85 #define UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
  86 #define UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
  87 #define UCR1_SNDBRK     (1<<4)  /* Send break */
  88 #define UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
  89 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
  90 #define UCR1_ATDMAEN    (1<<2)  /* Aging DMA Timer Enable */
  91 #define UCR1_DOZE       (1<<1)  /* Doze */
  92 #define UCR1_UARTEN     (1<<0)  /* UART enabled */
  93 #define UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
  94 #define UCR2_IRTS       (1<<14) /* Ignore RTS pin */
  95 #define UCR2_CTSC       (1<<13) /* CTS pin control */
  96 #define UCR2_CTS        (1<<12) /* Clear to send */
  97 #define UCR2_ESCEN      (1<<11) /* Escape enable */
  98 #define UCR2_PREN       (1<<8)  /* Parity enable */
  99 #define UCR2_PROE       (1<<7)  /* Parity odd/even */
 100 #define UCR2_STPB       (1<<6)  /* Stop */
 101 #define UCR2_WS         (1<<5)  /* Word size */
 102 #define UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
 103 #define UCR2_ATEN       (1<<3)  /* Aging Timer Enable */
 104 #define UCR2_TXEN       (1<<2)  /* Transmitter enabled */
 105 #define UCR2_RXEN       (1<<1)  /* Receiver enabled */
 106 #define UCR2_SRST       (1<<0)  /* SW reset */
 107 #define UCR3_DTREN      (1<<13) /* DTR interrupt enable */
 108 #define UCR3_PARERREN   (1<<12) /* Parity enable */
 109 #define UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
 110 #define UCR3_DSR        (1<<10) /* Data set ready */
 111 #define UCR3_DCD        (1<<9)  /* Data carrier detect */
 112 #define UCR3_RI         (1<<8)  /* Ring indicator */
 113 #define UCR3_ADNIMP     (1<<7)  /* Autobaud Detection Not Improved */
 114 #define UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
 115 #define UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
 116 #define UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
 117 #define UCR3_DTRDEN     (1<<3)  /* Data Terminal Ready Delta Enable. */
 118 #define IMX21_UCR3_RXDMUXSEL    (1<<2)  /* RXD Muxed Input Select */
 119 #define UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
 120 #define UCR3_BPEN       (1<<0)  /* Preset registers enable */
 121 #define UCR4_CTSTL_SHF  10      /* CTS trigger level shift */
 122 #define UCR4_CTSTL_MASK 0x3F    /* CTS trigger is 6 bits wide */
 123 #define UCR4_INVR       (1<<9)  /* Inverted infrared reception */
 124 #define UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
 125 #define UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
 126 #define UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
 127 #define UCR4_IDDMAEN    (1<<6)  /* DMA IDLE Condition Detected */
 128 #define UCR4_IRSC       (1<<5)  /* IR special case */
 129 #define UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
 130 #define UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
 131 #define UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
 132 #define UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
 133 #define UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
 134 #define UFCR_DCEDTE     (1<<6)  /* DCE/DTE mode select */
 135 #define UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
 136 #define UFCR_RFDIV_REG(x)       (((x) < 7 ? 6 - (x) : 6) << 7)
 137 #define UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
 138 #define USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
 139 #define USR1_RTSS       (1<<14) /* RTS pin status */
 140 #define USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
 141 #define USR1_RTSD       (1<<12) /* RTS delta */
 142 #define USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
 143 #define USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
 144 #define USR1_RRDY       (1<<9)   /* Receiver ready interrupt/dma flag */
 145 #define USR1_AGTIM      (1<<8)   /* Ageing timer interrupt flag */
 146 #define USR1_DTRD       (1<<7)   /* DTR Delta */
 147 #define USR1_RXDS        (1<<6)  /* Receiver idle interrupt flag */
 148 #define USR1_AIRINT      (1<<5)  /* Async IR wake interrupt flag */
 149 #define USR1_AWAKE       (1<<4)  /* Aysnc wake interrupt flag */
 150 #define USR2_ADET        (1<<15) /* Auto baud rate detect complete */
 151 #define USR2_TXFE        (1<<14) /* Transmit buffer FIFO empty */
 152 #define USR2_DTRF        (1<<13) /* DTR edge interrupt flag */
 153 #define USR2_IDLE        (1<<12) /* Idle condition */
 154 #define USR2_RIDELT      (1<<10) /* Ring Interrupt Delta */
 155 #define USR2_RIIN        (1<<9)  /* Ring Indicator Input */
 156 #define USR2_IRINT       (1<<8)  /* Serial infrared interrupt flag */
 157 #define USR2_WAKE        (1<<7)  /* Wake */
 158 #define USR2_DCDIN       (1<<5)  /* Data Carrier Detect Input */
 159 #define USR2_RTSF        (1<<4)  /* RTS edge interrupt flag */
 160 #define USR2_TXDC        (1<<3)  /* Transmitter complete */
 161 #define USR2_BRCD        (1<<2)  /* Break condition */
 162 #define USR2_ORE        (1<<1)   /* Overrun error */
 163 #define USR2_RDR        (1<<0)   /* Recv data ready */
 164 #define UTS_FRCPERR     (1<<13) /* Force parity error */
 165 #define UTS_LOOP        (1<<12)  /* Loop tx and rx */
 166 #define UTS_TXEMPTY      (1<<6)  /* TxFIFO empty */
 167 #define UTS_RXEMPTY      (1<<5)  /* RxFIFO empty */
 168 #define UTS_TXFULL       (1<<4)  /* TxFIFO full */
 169 #define UTS_RXFULL       (1<<3)  /* RxFIFO full */
 170 #define UTS_SOFTRST      (1<<0)  /* Software reset */
 171
 172 /* We've been assigned a range on the "Low-density serial ports" major */
 173 #define SERIAL_IMX_MAJOR        207
 174 #define MINOR_START             16
 175 #define DEV_NAME                "ttymxc"
 176
 177 /*
 178  * This determines how often we check the modem status signals
 179  * for any change.  They generally aren't connected to an IRQ
 180  * so we have to poll them.  We also check immediately before
 181  * filling the TX fifo incase CTS has been dropped.
 182  */
 183 #define MCTRL_TIMEOUT   (250*HZ/1000)
 184
 185 #define DRIVER_NAME "IMX-uart"
 186
 187 #define UART_NR 8
 188
 189 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
 190 enum imx_uart_type {
 191         IMX1_UART,
 192         IMX21_UART,
 193         IMX53_UART,
 194         IMX6Q_UART,
 195 };
 196
 197 /* device type dependent stuff */
 198 struct imx_uart_data {
 199         unsigned uts_reg;
 200         enum imx_uart_type devtype;
 201 };
 202
 203 struct imx_port {
 204         struct uart_port        port;
 205         struct timer_list       timer;
 206         unsigned int            old_status;
 207         unsigned int            have_rtscts:1;
 208         unsigned int            have_rtsgpio:1;
 209         unsigned int            dte_mode:1;
 210         unsigned int            irda_inv_rx:1;
 211         unsigned int            irda_inv_tx:1;
 212         unsigned short          trcv_delay; /* transceiver delay */
 213         struct clk              *clk_ipg;
 214         struct clk              *clk_per;
 215         const struct imx_uart_data *devdata;
 216
 217         struct mctrl_gpios *gpios;
 218
 219         /* DMA fields */
 220         unsigned int            dma_is_inited:1;
 221         unsigned int            dma_is_enabled:1;
 222         unsigned int            dma_is_rxing:1;
 223         unsigned int            dma_is_txing:1;
 224         struct dma_chan         *dma_chan_rx, *dma_chan_tx;
 225         struct scatterlist      rx_sgl, tx_sgl[2];
 226         void                    *rx_buf;
 227         struct circ_buf         rx_ring;
 228         unsigned int            rx_periods;
 229         dma_cookie_t            rx_cookie;
 230         unsigned int            tx_bytes;
 231         unsigned int            dma_tx_nents;
 232         wait_queue_head_t       dma_wait;
 233         unsigned int            saved_reg[10];
 234         bool                    context_saved;
 235 };
 236
 237 struct imx_port_ucrs {
 238         unsigned int    ucr1;
 239         unsigned int    ucr2;
 240         unsigned int    ucr3;
 241 };
 242
 243 static struct imx_uart_data imx_uart_devdata[] = {
 244         [IMX1_UART] = {
 245                 .uts_reg = IMX1_UTS,
 246                 .devtype = IMX1_UART,
 247         },
 248         [IMX21_UART] = {
 249                 .uts_reg = IMX21_UTS,
 250                 .devtype = IMX21_UART,
 251         },
 252         [IMX53_UART] = {
 253                 .uts_reg = IMX21_UTS,
 254                 .devtype = IMX53_UART,
 255         },
 256         [IMX6Q_UART] = {
 257                 .uts_reg = IMX21_UTS,
 258                 .devtype = IMX6Q_UART,
 259         },
 260 };
 261
 262 static const struct platform_device_id imx_uart_devtype[] = {
 263         {
 264                 .name = "imx1-uart",
 265                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
 266         }, {
 267                 .name = "imx21-uart",
 268                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
 269         }, {
 270                 .name = "imx53-uart",
 271                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX53_UART],
 272         }, {
 273                 .name = "imx6q-uart",
 274                 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
 275         }, {
 276                 /* sentinel */
 277         }
 278 };
 279 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
 280
 281 static const struct of_device_id imx_uart_dt_ids[] = {
 282         { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
 283         { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
 284         { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
 285         { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
 286         { /* sentinel */ }
 287 };
 288 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
 289
 290 static inline unsigned uts_reg(struct imx_port *sport)
 291 {
 292         return sport->devdata->uts_reg;
 293 }
 294
 295 static inline int is_imx1_uart(struct imx_port *sport)
 296 {
 297         return sport->devdata->devtype == IMX1_UART;
 298 }
 299
 300 static inline int is_imx21_uart(struct imx_port *sport)
 301 {
 302         return sport->devdata->devtype == IMX21_UART;
 303 }
 304
 305 static inline int is_imx53_uart(struct imx_port *sport)
 306 {
 307         return sport->devdata->devtype == IMX53_UART;
 308 }
 309
 310 static inline int is_imx6q_uart(struct imx_port *sport)
 311 {
 312         return sport->devdata->devtype == IMX6Q_UART;
 313 }
 314 /*
 315  * Save and restore functions for UCR1, UCR2 and UCR3 registers
 316  */
 317 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
 318 static void imx_port_ucrs_save(struct uart_port *port,
 319                                struct imx_port_ucrs *ucr)
 320 {
 321         /* save control registers */
 322         ucr->ucr1 = readl(port->membase + UCR1);
 323         ucr->ucr2 = readl(port->membase + UCR2);
 324         ucr->ucr3 = readl(port->membase + UCR3);
 325 }
 326
 327 static void imx_port_ucrs_restore(struct uart_port *port,
 328                                   struct imx_port_ucrs *ucr)
 329 {
 330         /* restore control registers */
 331         writel(ucr->ucr1, port->membase + UCR1);
 332         writel(ucr->ucr2, port->membase + UCR2);
 333         writel(ucr->ucr3, port->membase + UCR3);
 334 }
 335 #endif
 336
 337 static void imx_port_rts_active(struct imx_port *sport, unsigned long *ucr2)
 338 {
 339         *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
 340
 341         mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
 342 }
 343
 344 static void imx_port_rts_inactive(struct imx_port *sport, unsigned long *ucr2)
 345 {
 346         *ucr2 &= ~UCR2_CTSC;
 347         *ucr2 |= UCR2_CTS;
 348
 349         mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
 350 }
 351
 352 static void imx_port_rts_auto(struct imx_port *sport, unsigned long *ucr2)
 353 {
 354         *ucr2 |= UCR2_CTSC;
 355 }
 356
 357 /*
 358  * interrupts disabled on entry
 359  */
 360 static void imx_stop_tx(struct uart_port *port)
 361 {
 362         struct imx_port *sport = (struct imx_port *)port;
 363         unsigned long temp;
 364
 365         /*
 366          * We are maybe in the SMP context, so if the DMA TX thread is running
 367          * on other cpu, we have to wait for it to finish.
 368          */
 369         if (sport->dma_is_enabled && sport->dma_is_txing)
 370                 return;
 371
 372         temp = readl(port->membase + UCR1);
 373         writel(temp & ~UCR1_TXMPTYEN, port->membase + UCR1);
 374
 375         /* in rs485 mode disable transmitter if shifter is empty */
 376         if (port->rs485.flags & SER_RS485_ENABLED &&
 377             readl(port->membase + USR2) & USR2_TXDC) {
 378                 temp = readl(port->membase + UCR2);
 379                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
 380                         imx_port_rts_active(sport, &temp);
 381                 else
 382                         imx_port_rts_inactive(sport, &temp);
 383                 temp |= UCR2_RXEN;
 384                 writel(temp, port->membase + UCR2);
 385
 386                 temp = readl(port->membase + UCR4);
 387                 temp &= ~UCR4_TCEN;
 388                 writel(temp, port->membase + UCR4);
 389         }
 390 }
 391
 392 /*
 393  * interrupts disabled on entry
 394  */
 395 static void imx_stop_rx(struct uart_port *port)
 396 {
 397         struct imx_port *sport = (struct imx_port *)port;
 398         unsigned long temp;
 399
 400         if (sport->dma_is_enabled && sport->dma_is_rxing) {
 401                 if (sport->port.suspended) {
 402                         dmaengine_terminate_all(sport->dma_chan_rx);
 403                         sport->dma_is_rxing = 0;
 404                 } else {
 405                         return;
 406                 }
 407         }
 408
 409         temp = readl(sport->port.membase + UCR2);
 410         writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
 411
 412         /* disable the `Receiver Ready Interrrupt` */
 413         temp = readl(sport->port.membase + UCR1);
 414         writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
 415 }
 416
 417 /*
 418  * Set the modem control timer to fire immediately.
 419  */
 420 static void imx_enable_ms(struct uart_port *port)
 421 {
 422         struct imx_port *sport = (struct imx_port *)port;
 423
 424         mod_timer(&sport->timer, jiffies);
 425
 426         mctrl_gpio_enable_ms(sport->gpios);
 427 }
 428
 429 static void imx_dma_tx(struct imx_port *sport);
 430 static inline void imx_transmit_buffer(struct imx_port *sport)
 431 {
 432         struct circ_buf *xmit = &sport->port.state->xmit;
 433         unsigned long temp;
 434
 435         if (sport->port.x_char) {
 436                 /* Send next char */
 437                 writel(sport->port.x_char, sport->port.membase + URTX0);
 438                 sport->port.icount.tx++;
 439                 sport->port.x_char = 0;
 440                 return;
 441         }
 442
 443         if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
 444                 imx_stop_tx(&sport->port);
 445                 return;
 446         }
 447
 448         if (sport->dma_is_enabled) {
 449                 /*
 450                  * We've just sent a X-char Ensure the TX DMA is enabled
 451                  * and the TX IRQ is disabled.
 452                  **/
 453                 temp = readl(sport->port.membase + UCR1);
 454                 temp &= ~UCR1_TXMPTYEN;
 455                 if (sport->dma_is_txing) {
 456                         temp |= UCR1_TDMAEN;
 457                         writel(temp, sport->port.membase + UCR1);
 458                 } else {
 459                         writel(temp, sport->port.membase + UCR1);
 460                         imx_dma_tx(sport);
 461                 }
 462         }
 463
 464         while (!uart_circ_empty(xmit) &&
 465                !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
 466                 /* send xmit->buf[xmit->tail]
 467                  * out the port here */
 468                 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
 469                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 470                 sport->port.icount.tx++;
 471         }
 472
 473         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 474                 uart_write_wakeup(&sport->port);
 475
 476         if (uart_circ_empty(xmit))
 477                 imx_stop_tx(&sport->port);
 478 }
 479
 480 static void dma_tx_callback(void *data)
 481 {
 482         struct imx_port *sport = data;
 483         struct scatterlist *sgl = &sport->tx_sgl[0];
 484         struct circ_buf *xmit = &sport->port.state->xmit;
 485         unsigned long flags;
 486         unsigned long temp;
 487
 488         spin_lock_irqsave(&sport->port.lock, flags);
 489
 490         dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 491
 492         temp = readl(sport->port.membase + UCR1);
 493         temp &= ~UCR1_TDMAEN;
 494         writel(temp, sport->port.membase + UCR1);
 495
 496         /* update the stat */
 497         xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
 498         sport->port.icount.tx += sport->tx_bytes;
 499
 500         dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
 501
 502         sport->dma_is_txing = 0;
 503
 504         spin_unlock_irqrestore(&sport->port.lock, flags);
 505
 506         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 507                 uart_write_wakeup(&sport->port);
 508
 509         if (waitqueue_active(&sport->dma_wait)) {
 510                 wake_up(&sport->dma_wait);
 511                 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
 512                 return;
 513         }
 514
 515         spin_lock_irqsave(&sport->port.lock, flags);
 516         if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
 517                 imx_dma_tx(sport);
 518         spin_unlock_irqrestore(&sport->port.lock, flags);
 519 }
 520
 521 static void imx_dma_tx(struct imx_port *sport)
 522 {
 523         struct circ_buf *xmit = &sport->port.state->xmit;
 524         struct scatterlist *sgl = sport->tx_sgl;
 525         struct dma_async_tx_descriptor *desc;
 526         struct dma_chan *chan = sport->dma_chan_tx;
 527         struct device *dev = sport->port.dev;
 528         unsigned long temp;
 529         int ret;
 530
 531         if (sport->dma_is_txing)
 532                 return;
 533
 534         sport->tx_bytes = uart_circ_chars_pending(xmit);
 535
 536         if (xmit->tail < xmit->head) {
 537                 sport->dma_tx_nents = 1;
 538                 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
 539         } else {
 540                 sport->dma_tx_nents = 2;
 541                 sg_init_table(sgl, 2);
 542                 sg_set_buf(sgl, xmit->buf + xmit->tail,
 543                                 UART_XMIT_SIZE - xmit->tail);
 544                 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
 545         }
 546
 547         ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
 548         if (ret == 0) {
 549                 dev_err(dev, "DMA mapping error for TX.\n");
 550                 return;
 551         }
 552         desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
 553                                         DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
 554         if (!desc) {
 555                 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
 556                              DMA_TO_DEVICE);
 557                 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
 558                 return;
 559         }
 560         desc->callback = dma_tx_callback;
 561         desc->callback_param = sport;
 562
 563         dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
 564                         uart_circ_chars_pending(xmit));
 565
 566         temp = readl(sport->port.membase + UCR1);
 567         temp |= UCR1_TDMAEN;
 568         writel(temp, sport->port.membase + UCR1);
 569
 570         /* fire it */
 571         sport->dma_is_txing = 1;
 572         dmaengine_submit(desc);
 573         dma_async_issue_pending(chan);
 574         return;
 575 }
 576
 577 /*
 578  * interrupts disabled on entry
 579  */
 580 static void imx_start_tx(struct uart_port *port)
 581 {
 582         struct imx_port *sport = (struct imx_port *)port;
 583         unsigned long temp;
 584
 585         if (port->rs485.flags & SER_RS485_ENABLED) {
 586                 temp = readl(port->membase + UCR2);
 587                 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
 588                         imx_port_rts_active(sport, &temp);
 589                 else
 590                         imx_port_rts_inactive(sport, &temp);
 591                 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX))
 592                         temp &= ~UCR2_RXEN;
 593                 writel(temp, port->membase + UCR2);
 594
 595                 /* enable transmitter and shifter empty irq */
 596                 temp = readl(port->membase + UCR4);
 597                 temp |= UCR4_TCEN;
 598                 writel(temp, port->membase + UCR4);
 599         }
 600
 601         if (!sport->dma_is_enabled) {
 602                 temp = readl(sport->port.membase + UCR1);
 603                 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
 604         }
 605
 606         if (sport->dma_is_enabled) {
 607                 if (sport->port.x_char) {
 608                         /* We have X-char to send, so enable TX IRQ and
 609                          * disable TX DMA to let TX interrupt to send X-char */
 610                         temp = readl(sport->port.membase + UCR1);
 611                         temp &= ~UCR1_TDMAEN;
 612                         temp |= UCR1_TXMPTYEN;
 613                         writel(temp, sport->port.membase + UCR1);
 614                         return;
 615                 }
 616
 617                 if (!uart_circ_empty(&port->state->xmit) &&
 618                     !uart_tx_stopped(port))
 619                         imx_dma_tx(sport);
 620                 return;
 621         }
 622 }
 623
 624 static irqreturn_t imx_rtsint(int irq, void *dev_id)
 625 {
 626         struct imx_port *sport = dev_id;
 627         unsigned int val;
 628         unsigned long flags;
 629
 630         spin_lock_irqsave(&sport->port.lock, flags);
 631
 632         writel(USR1_RTSD, sport->port.membase + USR1);
 633         val = readl(sport->port.membase + USR1) & USR1_RTSS;
 634         uart_handle_cts_change(&sport->port, !!val);
 635         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 636
 637         spin_unlock_irqrestore(&sport->port.lock, flags);
 638         return IRQ_HANDLED;
 639 }
 640
 641 static irqreturn_t imx_txint(int irq, void *dev_id)
 642 {
 643         struct imx_port *sport = dev_id;
 644         unsigned long flags;
 645
 646         spin_lock_irqsave(&sport->port.lock, flags);
 647         imx_transmit_buffer(sport);
 648         spin_unlock_irqrestore(&sport->port.lock, flags);
 649         return IRQ_HANDLED;
 650 }
 651
 652 static irqreturn_t imx_rxint(int irq, void *dev_id)
 653 {
 654         struct imx_port *sport = dev_id;
 655         unsigned int rx, flg, ignored = 0;
 656         struct tty_port *port = &sport->port.state->port;
 657         unsigned long flags, temp;
 658
 659         spin_lock_irqsave(&sport->port.lock, flags);
 660
 661         while (readl(sport->port.membase + USR2) & USR2_RDR) {
 662                 flg = TTY_NORMAL;
 663                 sport->port.icount.rx++;
 664
 665                 rx = readl(sport->port.membase + URXD0);
 666
 667                 temp = readl(sport->port.membase + USR2);
 668                 if (temp & USR2_BRCD) {
 669                         writel(USR2_BRCD, sport->port.membase + USR2);
 670                         if (uart_handle_break(&sport->port))
 671                                 continue;
 672                 }
 673
 674                 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
 675                         continue;
 676
 677                 if (unlikely(rx & URXD_ERR)) {
 678                         if (rx & URXD_BRK)
 679                                 sport->port.icount.brk++;
 680                         else if (rx & URXD_PRERR)
 681                                 sport->port.icount.parity++;
 682                         else if (rx & URXD_FRMERR)
 683                                 sport->port.icount.frame++;
 684                         if (rx & URXD_OVRRUN)
 685                                 sport->port.icount.overrun++;
 686
 687                         if (rx & sport->port.ignore_status_mask) {
 688                                 if (++ignored > 100)
 689                                         goto out;
 690                                 continue;
 691                         }
 692
 693                         rx &= (sport->port.read_status_mask | 0xFF);
 694
 695                         if (rx & URXD_BRK)
 696                                 flg = TTY_BREAK;
 697                         else if (rx & URXD_PRERR)
 698                                 flg = TTY_PARITY;
 699                         else if (rx & URXD_FRMERR)
 700                                 flg = TTY_FRAME;
 701                         if (rx & URXD_OVRRUN)
 702                                 flg = TTY_OVERRUN;
 703
 704 #ifdef SUPPORT_SYSRQ
 705                         sport->port.sysrq = 0;
 706 #endif
 707                 }
 708
 709                 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
 710                         goto out;
 711
 712                 if (tty_insert_flip_char(port, rx, flg) == 0)
 713                         sport->port.icount.buf_overrun++;
 714         }
 715
 716 out:
 717         spin_unlock_irqrestore(&sport->port.lock, flags);
 718         tty_flip_buffer_push(port);
 719         return IRQ_HANDLED;
 720 }
 721
 722 static void clear_rx_errors(struct imx_port *sport);
 723 static int start_rx_dma(struct imx_port *sport);
 724 /*
 725  * If the RXFIFO is filled with some data, and then we
 726  * arise a DMA operation to receive them.
 727  */
 728 static void imx_dma_rxint(struct imx_port *sport)
 729 {
 730         unsigned long temp;
 731         unsigned long flags;
 732
 733         spin_lock_irqsave(&sport->port.lock, flags);
 734
 735         temp = readl(sport->port.membase + USR2);
 736         if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
 737                 sport->dma_is_rxing = 1;
 738
 739                 /* disable the receiver ready and aging timer interrupts */
 740                 temp = readl(sport->port.membase + UCR1);
 741                 temp &= ~(UCR1_RRDYEN);
 742                 writel(temp, sport->port.membase + UCR1);
 743
 744                 temp = readl(sport->port.membase + UCR2);
 745                 temp &= ~(UCR2_ATEN);
 746                 writel(temp, sport->port.membase + UCR2);
 747
 748                 /* disable the rx errors interrupts */
 749                 temp = readl(sport->port.membase + UCR4);
 750                 temp &= ~UCR4_OREN;
 751                 writel(temp, sport->port.membase + UCR4);
 752
 753                 /* tell the DMA to receive the data. */
 754                 start_rx_dma(sport);
 755         }
 756
 757         spin_unlock_irqrestore(&sport->port.lock, flags);
 758 }
 759
 760 /*
 761  * We have a modem side uart, so the meanings of RTS and CTS are inverted.
 762  */
 763 static unsigned int imx_get_hwmctrl(struct imx_port *sport)
 764 {
 765         unsigned int tmp = TIOCM_DSR;
 766         unsigned usr1 = readl(sport->port.membase + USR1);
 767         unsigned usr2 = readl(sport->port.membase + USR2);
 768
 769         if (usr1 & USR1_RTSS)
 770                 tmp |= TIOCM_CTS;
 771
 772         /* in DCE mode DCDIN is always 0 */
 773         if (!(usr2 & USR2_DCDIN))
 774                 tmp |= TIOCM_CAR;
 775
 776         if (sport->dte_mode)
 777                 if (!(readl(sport->port.membase + USR2) & USR2_RIIN))
 778                         tmp |= TIOCM_RI;
 779
 780         return tmp;
 781 }
 782
 783 /*
 784  * Handle any change of modem status signal since we were last called.
 785  */
 786 static void imx_mctrl_check(struct imx_port *sport)
 787 {
 788         unsigned int status, changed;
 789
 790         status = imx_get_hwmctrl(sport);
 791         changed = status ^ sport->old_status;
 792
 793         if (changed == 0)
 794                 return;
 795
 796         sport->old_status = status;
 797
 798         if (changed & TIOCM_RI && status & TIOCM_RI)
 799                 sport->port.icount.rng++;
 800         if (changed & TIOCM_DSR)
 801                 sport->port.icount.dsr++;
 802         if (changed & TIOCM_CAR)
 803                 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
 804         if (changed & TIOCM_CTS)
 805                 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
 806
 807         wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
 808 }
 809
 810 static irqreturn_t imx_int(int irq, void *dev_id)
 811 {
 812         struct imx_port *sport = dev_id;
 813         unsigned int sts;
 814         unsigned int sts2;
 815         irqreturn_t ret = IRQ_NONE;
 816
 817         sts = readl(sport->port.membase + USR1);
 818         sts2 = readl(sport->port.membase + USR2);
 819
 820         if (sts & (USR1_RRDY | USR1_AGTIM)) {
 821                 if (sport->dma_is_enabled)
 822                         imx_dma_rxint(sport);
 823                 else
 824                         imx_rxint(irq, dev_id);
 825                 ret = IRQ_HANDLED;
 826         }
 827
 828         if ((sts & USR1_TRDY &&
 829              readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) ||
 830             (sts2 & USR2_TXDC &&
 831              readl(sport->port.membase + UCR4) & UCR4_TCEN)) {
 832                 imx_txint(irq, dev_id);
 833                 ret = IRQ_HANDLED;
 834         }
 835
 836         if (sts & USR1_DTRD) {
 837                 unsigned long flags;
 838
 839                 if (sts & USR1_DTRD)
 840                         writel(USR1_DTRD, sport->port.membase + USR1);
 841
 842                 spin_lock_irqsave(&sport->port.lock, flags);
 843                 imx_mctrl_check(sport);
 844                 spin_unlock_irqrestore(&sport->port.lock, flags);
 845
 846                 ret = IRQ_HANDLED;
 847         }
 848
 849         if (sts & USR1_RTSD) {
 850                 imx_rtsint(irq, dev_id);
 851                 ret = IRQ_HANDLED;
 852         }
 853
 854         if (sts & USR1_AWAKE) {
 855                 writel(USR1_AWAKE, sport->port.membase + USR1);
 856                 ret = IRQ_HANDLED;
 857         }
 858
 859         if (sts2 & USR2_ORE) {
 860                 sport->port.icount.overrun++;
 861                 writel(USR2_ORE, sport->port.membase + USR2);
 862                 ret = IRQ_HANDLED;
 863         }
 864
 865         return ret;
 866 }
 867
 868 /*
 869  * Return TIOCSER_TEMT when transmitter is not busy.
 870  */
 871 static unsigned int imx_tx_empty(struct uart_port *port)
 872 {
 873         struct imx_port *sport = (struct imx_port *)port;
 874         unsigned int ret;
 875
 876         ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ?  TIOCSER_TEMT : 0;
 877
 878         /* If the TX DMA is working, return 0. */
 879         if (sport->dma_is_enabled && sport->dma_is_txing)
 880                 ret = 0;
 881
 882         return ret;
 883 }
 884
 885 static unsigned int imx_get_mctrl(struct uart_port *port)
 886 {
 887         struct imx_port *sport = (struct imx_port *)port;
 888         unsigned int ret = imx_get_hwmctrl(sport);
 889
 890         mctrl_gpio_get(sport->gpios, &ret);
 891
 892         return ret;
 893 }
 894
 895 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
 896 {
 897         struct imx_port *sport = (struct imx_port *)port;
 898         unsigned long temp;
 899
 900         if (!(port->rs485.flags & SER_RS485_ENABLED)) {
 901                 temp = readl(sport->port.membase + UCR2);
 902                 temp &= ~(UCR2_CTS | UCR2_CTSC);
 903                 if (mctrl & TIOCM_RTS)
 904                         temp |= UCR2_CTS | UCR2_CTSC;
 905                 writel(temp, sport->port.membase + UCR2);
 906         }
 907
 908         temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR;
 909         if (!(mctrl & TIOCM_DTR))
 910                 temp |= UCR3_DSR;
 911         writel(temp, sport->port.membase + UCR3);
 912
 913         temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
 914         if (mctrl & TIOCM_LOOP)
 915                 temp |= UTS_LOOP;
 916         writel(temp, sport->port.membase + uts_reg(sport));
 917
 918         mctrl_gpio_set(sport->gpios, mctrl);
 919 }
 920
 921 /*
 922  * Interrupts always disabled.
 923  */
 924 static void imx_break_ctl(struct uart_port *port, int break_state)
 925 {
 926         struct imx_port *sport = (struct imx_port *)port;
 927         unsigned long flags, temp;
 928
 929         spin_lock_irqsave(&sport->port.lock, flags);
 930
 931         temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
 932
 933         if (break_state != 0)
 934                 temp |= UCR1_SNDBRK;
 935
 936         writel(temp, sport->port.membase + UCR1);
 937
 938         spin_unlock_irqrestore(&sport->port.lock, flags);
 939 }
 940
 941 /*
 942  * This is our per-port timeout handler, for checking the
 943  * modem status signals.
 944  */
 945 static void imx_timeout(unsigned long data)
 946 {
 947         struct imx_port *sport = (struct imx_port *)data;
 948         unsigned long flags;
 949
 950         if (sport->port.state) {
 951                 spin_lock_irqsave(&sport->port.lock, flags);
 952                 imx_mctrl_check(sport);
 953                 spin_unlock_irqrestore(&sport->port.lock, flags);
 954
 955                 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
 956         }
 957 }
 958
 959 #define RX_BUF_SIZE     (PAGE_SIZE)
 960
 961 /*
 962  * There are two kinds of RX DMA interrupts(such as in the MX6Q):
 963  *   [1] the RX DMA buffer is full.
 964  *   [2] the aging timer expires
 965  *
 966  * Condition [2] is triggered when a character has been sitting in the FIFO
 967  * for at least 8 byte durations.
 968  */
 969 static void dma_rx_callback(void *data)
 970 {
 971         struct imx_port *sport = data;
 972         struct dma_chan *chan = sport->dma_chan_rx;
 973         struct scatterlist *sgl = &sport->rx_sgl;
 974         struct tty_port *port = &sport->port.state->port;
 975         struct dma_tx_state state;
 976         struct circ_buf *rx_ring = &sport->rx_ring;
 977         enum dma_status status;
 978         unsigned int w_bytes = 0;
 979         unsigned int r_bytes;
 980         unsigned int bd_size;
 981
 982         status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
 983
 984         if (status == DMA_ERROR) {
 985                 dev_err(sport->port.dev, "DMA transaction error.\n");
 986                 clear_rx_errors(sport);
 987                 return;
 988         }
 989
 990         if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
 991
 992                 /*
 993                  * The state-residue variable represents the empty space
 994                  * relative to the entire buffer. Taking this in consideration
 995                  * the head is always calculated base on the buffer total
 996                  * length - DMA transaction residue. The UART script from the
 997                  * SDMA firmware will jump to the next buffer descriptor,
 998                  * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
 999                  * Taking this in consideration the tail is always at the
1000                  * beginning of the buffer descriptor that contains the head.
1001                  */
1002
1003                 /* Calculate the head */
1004                 rx_ring->head = sg_dma_len(sgl) - state.residue;
1005
1006                 /* Calculate the tail. */
1007                 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1008                 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1009
1010                 if (rx_ring->head <= sg_dma_len(sgl) &&
1011                     rx_ring->head > rx_ring->tail) {
1012
1013                         /* Move data from tail to head */
1014                         r_bytes = rx_ring->head - rx_ring->tail;
1015
1016                         /* CPU claims ownership of RX DMA buffer */
1017                         dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1018                                 DMA_FROM_DEVICE);
1019
1020                         w_bytes = tty_insert_flip_string(port,
1021                                 sport->rx_buf + rx_ring->tail, r_bytes);
1022
1023                         /* UART retrieves ownership of RX DMA buffer */
1024                         dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1025                                 DMA_FROM_DEVICE);
1026
1027                         if (w_bytes != r_bytes)
1028                                 sport->port.icount.buf_overrun++;
1029
1030                         sport->port.icount.rx += w_bytes;
1031                 } else  {
1032                         WARN_ON(rx_ring->head > sg_dma_len(sgl));
1033                         WARN_ON(rx_ring->head <= rx_ring->tail);
1034                 }
1035         }
1036
1037         if (w_bytes) {
1038                 tty_flip_buffer_push(port);
1039                 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1040         }
1041 }
1042
1043 /* RX DMA buffer periods */
1044 #define RX_DMA_PERIODS 4
1045
1046 static int start_rx_dma(struct imx_port *sport)
1047 {
1048         struct scatterlist *sgl = &sport->rx_sgl;
1049         struct dma_chan *chan = sport->dma_chan_rx;
1050         struct device *dev = sport->port.dev;
1051         struct dma_async_tx_descriptor *desc;
1052         int ret;
1053
1054         sport->rx_ring.head = 0;
1055         sport->rx_ring.tail = 0;
1056         sport->rx_periods = RX_DMA_PERIODS;
1057
1058         sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
1059         ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1060         if (ret == 0) {
1061                 dev_err(dev, "DMA mapping error for RX.\n");
1062                 return -EINVAL;
1063         }
1064
1065         desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1066                 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1067                 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1068
1069         if (!desc) {
1070                 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1071                 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1072                 return -EINVAL;
1073         }
1074         desc->callback = dma_rx_callback;
1075         desc->callback_param = sport;
1076
1077         dev_dbg(dev, "RX: prepare for the DMA.\n");
1078         sport->rx_cookie = dmaengine_submit(desc);
1079         dma_async_issue_pending(chan);
1080         return 0;
1081 }
1082
1083 static void clear_rx_errors(struct imx_port *sport)
1084 {
1085         unsigned int status_usr1, status_usr2;
1086
1087         status_usr1 = readl(sport->port.membase + USR1);
1088         status_usr2 = readl(sport->port.membase + USR2);
1089
1090         if (status_usr2 & USR2_BRCD) {
1091                 sport->port.icount.brk++;
1092                 writel(USR2_BRCD, sport->port.membase + USR2);
1093         } else if (status_usr1 & USR1_FRAMERR) {
1094                 sport->port.icount.frame++;
1095                 writel(USR1_FRAMERR, sport->port.membase + USR1);
1096         } else if (status_usr1 & USR1_PARITYERR) {
1097                 sport->port.icount.parity++;
1098                 writel(USR1_PARITYERR, sport->port.membase + USR1);
1099         }
1100
1101         if (status_usr2 & USR2_ORE) {
1102                 sport->port.icount.overrun++;
1103                 writel(USR2_ORE, sport->port.membase + USR2);
1104         }
1105
1106 }
1107
1108 #define TXTL_DEFAULT 2 /* reset default */
1109 #define RXTL_DEFAULT 1 /* reset default */
1110 #define TXTL_DMA 8 /* DMA burst setting */
1111 #define RXTL_DMA 9 /* DMA burst setting */
1112
1113 static void imx_setup_ufcr(struct imx_port *sport,
1114                           unsigned char txwl, unsigned char rxwl)
1115 {
1116         unsigned int val;
1117
1118         /* set receiver / transmitter trigger level */
1119         val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1120         val |= txwl << UFCR_TXTL_SHF | rxwl;
1121         writel(val, sport->port.membase + UFCR);
1122 }
1123
1124 static void imx_uart_dma_exit(struct imx_port *sport)
1125 {
1126         if (sport->dma_chan_rx) {
1127                 dmaengine_terminate_sync(sport->dma_chan_rx);
1128                 dma_release_channel(sport->dma_chan_rx);
1129                 sport->dma_chan_rx = NULL;
1130                 sport->rx_cookie = -EINVAL;
1131                 kfree(sport->rx_buf);
1132                 sport->rx_buf = NULL;
1133         }
1134
1135         if (sport->dma_chan_tx) {
1136                 dmaengine_terminate_sync(sport->dma_chan_tx);
1137                 dma_release_channel(sport->dma_chan_tx);
1138                 sport->dma_chan_tx = NULL;
1139         }
1140
1141         sport->dma_is_inited = 0;
1142 }
1143
1144 static int imx_uart_dma_init(struct imx_port *sport)
1145 {
1146         struct dma_slave_config slave_config = {};
1147         struct device *dev = sport->port.dev;
1148         int ret;
1149
1150         /* Prepare for RX : */
1151         sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1152         if (!sport->dma_chan_rx) {
1153                 dev_dbg(dev, "cannot get the DMA channel.\n");
1154                 ret = -EINVAL;
1155                 goto err;
1156         }
1157
1158         slave_config.direction = DMA_DEV_TO_MEM;
1159         slave_config.src_addr = sport->port.mapbase + URXD0;
1160         slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1161         /* one byte less than the watermark level to enable the aging timer */
1162         slave_config.src_maxburst = RXTL_DMA - 1;
1163         ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1164         if (ret) {
1165                 dev_err(dev, "error in RX dma configuration.\n");
1166                 goto err;
1167         }
1168
1169         sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1170         if (!sport->rx_buf) {
1171                 ret = -ENOMEM;
1172                 goto err;
1173         }
1174         sport->rx_ring.buf = sport->rx_buf;
1175
1176         /* Prepare for TX : */
1177         sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1178         if (!sport->dma_chan_tx) {
1179                 dev_err(dev, "cannot get the TX DMA channel!\n");
1180                 ret = -EINVAL;
1181                 goto err;
1182         }
1183
1184         slave_config.direction = DMA_MEM_TO_DEV;
1185         slave_config.dst_addr = sport->port.mapbase + URTX0;
1186         slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1187         slave_config.dst_maxburst = TXTL_DMA;
1188         ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1189         if (ret) {
1190                 dev_err(dev, "error in TX dma configuration.");
1191                 goto err;
1192         }
1193
1194         sport->dma_is_inited = 1;
1195
1196         return 0;
1197 err:
1198         imx_uart_dma_exit(sport);
1199         return ret;
1200 }
1201
1202 static void imx_enable_dma(struct imx_port *sport)
1203 {
1204         unsigned long temp;
1205
1206         init_waitqueue_head(&sport->dma_wait);
1207
1208         /* set UCR1 */
1209         temp = readl(sport->port.membase + UCR1);
1210         temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN;
1211         writel(temp, sport->port.membase + UCR1);
1212
1213         temp = readl(sport->port.membase + UCR2);
1214         temp |= UCR2_ATEN;
1215         writel(temp, sport->port.membase + UCR2);
1216
1217         imx_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1218
1219         sport->dma_is_enabled = 1;
1220 }
1221
1222 static void imx_disable_dma(struct imx_port *sport)
1223 {
1224         unsigned long temp;
1225
1226         /* clear UCR1 */
1227         temp = readl(sport->port.membase + UCR1);
1228         temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1229         writel(temp, sport->port.membase + UCR1);
1230
1231         /* clear UCR2 */
1232         temp = readl(sport->port.membase + UCR2);
1233         temp &= ~(UCR2_CTSC | UCR2_CTS | UCR2_ATEN);
1234         writel(temp, sport->port.membase + UCR2);
1235
1236         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1237
1238         sport->dma_is_enabled = 0;
1239 }
1240
1241 /* half the RX buffer size */
1242 #define CTSTL 16
1243
1244 static int imx_startup(struct uart_port *port)
1245 {
1246         struct imx_port *sport = (struct imx_port *)port;
1247         int retval, i;
1248         unsigned long flags, temp;
1249
1250         retval = clk_prepare_enable(sport->clk_per);
1251         if (retval)
1252                 return retval;
1253         retval = clk_prepare_enable(sport->clk_ipg);
1254         if (retval) {
1255                 clk_disable_unprepare(sport->clk_per);
1256                 return retval;
1257         }
1258
1259         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1260
1261         /* disable the DREN bit (Data Ready interrupt enable) before
1262          * requesting IRQs
1263          */
1264         temp = readl(sport->port.membase + UCR4);
1265
1266         /* set the trigger level for CTS */
1267         temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1268         temp |= CTSTL << UCR4_CTSTL_SHF;
1269
1270         writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1271
1272         /* Can we enable the DMA support? */
1273         if (!uart_console(port) && !sport->dma_is_inited)
1274                 imx_uart_dma_init(sport);
1275
1276         spin_lock_irqsave(&sport->port.lock, flags);
1277         /* Reset fifo's and state machines */
1278         i = 100;
1279
1280         temp = readl(sport->port.membase + UCR2);
1281         temp &= ~UCR2_SRST;
1282         writel(temp, sport->port.membase + UCR2);
1283
1284         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1285                 udelay(1);
1286
1287         /*
1288          * Finally, clear and enable interrupts
1289          */
1290         writel(USR1_RTSD | USR1_DTRD, sport->port.membase + USR1);
1291         writel(USR2_ORE, sport->port.membase + USR2);
1292
1293         if (sport->dma_is_inited && !sport->dma_is_enabled)
1294                 imx_enable_dma(sport);
1295
1296         temp = readl(sport->port.membase + UCR1);
1297         temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1298
1299         writel(temp, sport->port.membase + UCR1);
1300
1301         temp = readl(sport->port.membase + UCR4);
1302         temp |= UCR4_OREN;
1303         writel(temp, sport->port.membase + UCR4);
1304
1305         temp = readl(sport->port.membase + UCR2);
1306         temp |= (UCR2_RXEN | UCR2_TXEN);
1307         if (!sport->have_rtscts)
1308                 temp |= UCR2_IRTS;
1309         /*
1310          * make sure the edge sensitive RTS-irq is disabled,
1311          * we're using RTSD instead.
1312          */
1313         if (!is_imx1_uart(sport))
1314                 temp &= ~UCR2_RTSEN;
1315         writel(temp, sport->port.membase + UCR2);
1316
1317         if (!is_imx1_uart(sport)) {
1318                 temp = readl(sport->port.membase + UCR3);
1319
1320                 temp |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1321
1322                 if (sport->dte_mode)
1323                         /* disable broken interrupts */
1324                         temp &= ~(UCR3_RI | UCR3_DCD);
1325
1326                 writel(temp, sport->port.membase + UCR3);
1327         }
1328
1329         /*
1330          * Enable modem status interrupts
1331          */
1332         imx_enable_ms(&sport->port);
1333         spin_unlock_irqrestore(&sport->port.lock, flags);
1334
1335         return 0;
1336 }
1337
1338 static void imx_shutdown(struct uart_port *port)
1339 {
1340         struct imx_port *sport = (struct imx_port *)port;
1341         unsigned long temp;
1342         unsigned long flags;
1343
1344         if (sport->dma_is_enabled) {
1345                 sport->dma_is_rxing = 0;
1346                 sport->dma_is_txing = 0;
1347                 dmaengine_terminate_sync(sport->dma_chan_tx);
1348                 dmaengine_terminate_sync(sport->dma_chan_rx);
1349
1350                 spin_lock_irqsave(&sport->port.lock, flags);
1351                 imx_stop_tx(port);
1352                 imx_stop_rx(port);
1353                 imx_disable_dma(sport);
1354                 spin_unlock_irqrestore(&sport->port.lock, flags);
1355                 imx_uart_dma_exit(sport);
1356         }
1357
1358         mctrl_gpio_disable_ms(sport->gpios);
1359
1360         spin_lock_irqsave(&sport->port.lock, flags);
1361         temp = readl(sport->port.membase + UCR2);
1362         temp &= ~(UCR2_TXEN);
1363         writel(temp, sport->port.membase + UCR2);
1364         spin_unlock_irqrestore(&sport->port.lock, flags);
1365
1366         /*
1367          * Stop our timer.
1368          */
1369         del_timer_sync(&sport->timer);
1370
1371         /*
1372          * Disable all interrupts, port and break condition.
1373          */
1374
1375         spin_lock_irqsave(&sport->port.lock, flags);
1376         temp = readl(sport->port.membase + UCR1);
1377         temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1378
1379         writel(temp, sport->port.membase + UCR1);
1380         spin_unlock_irqrestore(&sport->port.lock, flags);
1381
1382         clk_disable_unprepare(sport->clk_per);
1383         clk_disable_unprepare(sport->clk_ipg);
1384 }
1385
1386 static void imx_flush_buffer(struct uart_port *port)
1387 {
1388         struct imx_port *sport = (struct imx_port *)port;
1389         struct scatterlist *sgl = &sport->tx_sgl[0];
1390         unsigned long temp;
1391         int i = 100, ubir, ubmr, uts;
1392
1393         if (!sport->dma_chan_tx)
1394                 return;
1395
1396         sport->tx_bytes = 0;
1397         dmaengine_terminate_all(sport->dma_chan_tx);
1398         if (sport->dma_is_txing) {
1399                 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1400                              DMA_TO_DEVICE);
1401                 temp = readl(sport->port.membase + UCR1);
1402                 temp &= ~UCR1_TDMAEN;
1403                 writel(temp, sport->port.membase + UCR1);
1404                 sport->dma_is_txing = false;
1405         }
1406
1407         /*
1408          * According to the Reference Manual description of the UART SRST bit:
1409          * "Reset the transmit and receive state machines,
1410          * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
1411          * and UTS[6-3]". As we don't need to restore the old values from
1412          * USR1, USR2, URXD, UTXD, only save/restore the other four registers
1413          */
1414         ubir = readl(sport->port.membase + UBIR);
1415         ubmr = readl(sport->port.membase + UBMR);
1416         uts = readl(sport->port.membase + IMX21_UTS);
1417
1418         temp = readl(sport->port.membase + UCR2);
1419         temp &= ~UCR2_SRST;
1420         writel(temp, sport->port.membase + UCR2);
1421
1422         while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1423                 udelay(1);
1424
1425         /* Restore the registers */
1426         writel(ubir, sport->port.membase + UBIR);
1427         writel(ubmr, sport->port.membase + UBMR);
1428         writel(uts, sport->port.membase + IMX21_UTS);
1429 }
1430
1431 static void
1432 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1433                    struct ktermios *old)
1434 {
1435         struct imx_port *sport = (struct imx_port *)port;
1436         unsigned long flags;
1437         unsigned long ucr2, old_ucr1, old_ucr2;
1438         unsigned int baud, quot;
1439         unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1440         unsigned long div, ufcr;
1441         unsigned long num, denom;
1442         uint64_t tdiv64;
1443
1444         /*
1445          * We only support CS7 and CS8.
1446          */
1447         while ((termios->c_cflag & CSIZE) != CS7 &&
1448                (termios->c_cflag & CSIZE) != CS8) {
1449                 termios->c_cflag &= ~CSIZE;
1450                 termios->c_cflag |= old_csize;
1451                 old_csize = CS8;
1452         }
1453
1454         if ((termios->c_cflag & CSIZE) == CS8)
1455                 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1456         else
1457                 ucr2 = UCR2_SRST | UCR2_IRTS;
1458
1459         if (termios->c_cflag & CRTSCTS) {
1460                 if (sport->have_rtscts) {
1461                         ucr2 &= ~UCR2_IRTS;
1462
1463                         if (port->rs485.flags & SER_RS485_ENABLED) {
1464                                 /*
1465                                  * RTS is mandatory for rs485 operation, so keep
1466                                  * it under manual control and keep transmitter
1467                                  * disabled.
1468                                  */
1469                                 if (port->rs485.flags &
1470                                     SER_RS485_RTS_AFTER_SEND)
1471                                         imx_port_rts_active(sport, &ucr2);
1472                                 else
1473                                         imx_port_rts_inactive(sport, &ucr2);
1474                         } else {
1475                                 imx_port_rts_auto(sport, &ucr2);
1476                         }
1477                 } else {
1478                         termios->c_cflag &= ~CRTSCTS;
1479                 }
1480         } else if (port->rs485.flags & SER_RS485_ENABLED) {
1481                 /* disable transmitter */
1482                 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1483                         imx_port_rts_active(sport, &ucr2);
1484                 else
1485                         imx_port_rts_inactive(sport, &ucr2);
1486         }
1487
1488
1489         if (termios->c_cflag & CSTOPB)
1490                 ucr2 |= UCR2_STPB;
1491         if (termios->c_cflag & PARENB) {
1492                 ucr2 |= UCR2_PREN;
1493                 if (termios->c_cflag & PARODD)
1494                         ucr2 |= UCR2_PROE;
1495         }
1496
1497         del_timer_sync(&sport->timer);
1498
1499         /*
1500          * Ask the core to calculate the divisor for us.
1501          */
1502         baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1503         quot = uart_get_divisor(port, baud);
1504
1505         spin_lock_irqsave(&sport->port.lock, flags);
1506
1507         sport->port.read_status_mask = 0;
1508         if (termios->c_iflag & INPCK)
1509                 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1510         if (termios->c_iflag & (BRKINT | PARMRK))
1511                 sport->port.read_status_mask |= URXD_BRK;
1512
1513         /*
1514          * Characters to ignore
1515          */
1516         sport->port.ignore_status_mask = 0;
1517         if (termios->c_iflag & IGNPAR)
1518                 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1519         if (termios->c_iflag & IGNBRK) {
1520                 sport->port.ignore_status_mask |= URXD_BRK;
1521                 /*
1522                  * If we're ignoring parity and break indicators,
1523                  * ignore overruns too (for real raw support).
1524                  */
1525                 if (termios->c_iflag & IGNPAR)
1526                         sport->port.ignore_status_mask |= URXD_OVRRUN;
1527         }
1528
1529         if ((termios->c_cflag & CREAD) == 0)
1530                 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1531
1532         /*
1533          * Update the per-port timeout.
1534          */
1535         uart_update_timeout(port, termios->c_cflag, baud);
1536
1537         /*
1538          * disable interrupts and drain transmitter
1539          */
1540         old_ucr1 = readl(sport->port.membase + UCR1);
1541         writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1542                         sport->port.membase + UCR1);
1543
1544         while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1545                 barrier();
1546
1547         /* then, disable everything */
1548         old_ucr2 = readl(sport->port.membase + UCR2);
1549         writel(old_ucr2 & ~(UCR2_TXEN | UCR2_RXEN),
1550                         sport->port.membase + UCR2);
1551         old_ucr2 &= (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN);
1552
1553         /* custom-baudrate handling */
1554         div = sport->port.uartclk / (baud * 16);
1555         if (baud == 38400 && quot != div)
1556                 baud = sport->port.uartclk / (quot * 16);
1557
1558         div = sport->port.uartclk / (baud * 16);
1559         if (div > 7)
1560                 div = 7;
1561         if (!div)
1562                 div = 1;
1563
1564         rational_best_approximation(16 * div * baud, sport->port.uartclk,
1565                 1 << 16, 1 << 16, &num, &denom);
1566
1567         tdiv64 = sport->port.uartclk;
1568         tdiv64 *= num;
1569         do_div(tdiv64, denom * 16 * div);
1570         tty_termios_encode_baud_rate(termios,
1571                                 (speed_t)tdiv64, (speed_t)tdiv64);
1572
1573         num -= 1;
1574         denom -= 1;
1575
1576         ufcr = readl(sport->port.membase + UFCR);
1577         ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1578         writel(ufcr, sport->port.membase + UFCR);
1579
1580         writel(num, sport->port.membase + UBIR);
1581         writel(denom, sport->port.membase + UBMR);
1582
1583         if (!is_imx1_uart(sport))
1584                 writel(sport->port.uartclk / div / 1000,
1585                                 sport->port.membase + IMX21_ONEMS);
1586
1587         writel(old_ucr1, sport->port.membase + UCR1);
1588
1589         /* set the parity, stop bits and data size */
1590         writel(ucr2 | old_ucr2, sport->port.membase + UCR2);
1591
1592         if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1593                 imx_enable_ms(&sport->port);
1594
1595         spin_unlock_irqrestore(&sport->port.lock, flags);
1596 }
1597
1598 static const char *imx_type(struct uart_port *port)
1599 {
1600         struct imx_port *sport = (struct imx_port *)port;
1601
1602         return sport->port.type == PORT_IMX ? "IMX" : NULL;
1603 }
1604
1605 /*
1606  * Configure/autoconfigure the port.
1607  */
1608 static void imx_config_port(struct uart_port *port, int flags)
1609 {
1610         struct imx_port *sport = (struct imx_port *)port;
1611
1612         if (flags & UART_CONFIG_TYPE)
1613                 sport->port.type = PORT_IMX;
1614 }
1615
1616 /*
1617  * Verify the new serial_struct (for TIOCSSERIAL).
1618  * The only change we allow are to the flags and type, and
1619  * even then only between PORT_IMX and PORT_UNKNOWN
1620  */
1621 static int
1622 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1623 {
1624         struct imx_port *sport = (struct imx_port *)port;
1625         int ret = 0;
1626
1627         if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1628                 ret = -EINVAL;
1629         if (sport->port.irq != ser->irq)
1630                 ret = -EINVAL;
1631         if (ser->io_type != UPIO_MEM)
1632                 ret = -EINVAL;
1633         if (sport->port.uartclk / 16 != ser->baud_base)
1634                 ret = -EINVAL;
1635         if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1636                 ret = -EINVAL;
1637         if (sport->port.iobase != ser->port)
1638                 ret = -EINVAL;
1639         if (ser->hub6 != 0)
1640                 ret = -EINVAL;
1641         return ret;
1642 }
1643
1644 #if defined(CONFIG_CONSOLE_POLL)
1645
1646 static int imx_poll_init(struct uart_port *port)
1647 {
1648         struct imx_port *sport = (struct imx_port *)port;
1649         unsigned long flags;
1650         unsigned long temp;
1651         int retval;
1652
1653         retval = clk_prepare_enable(sport->clk_ipg);
1654         if (retval)
1655                 return retval;
1656         retval = clk_prepare_enable(sport->clk_per);
1657         if (retval)
1658                 clk_disable_unprepare(sport->clk_ipg);
1659
1660         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1661
1662         spin_lock_irqsave(&sport->port.lock, flags);
1663
1664         temp = readl(sport->port.membase + UCR1);
1665         if (is_imx1_uart(sport))
1666                 temp |= IMX1_UCR1_UARTCLKEN;
1667         temp |= UCR1_UARTEN | UCR1_RRDYEN;
1668         temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1669         writel(temp, sport->port.membase + UCR1);
1670
1671         temp = readl(sport->port.membase + UCR2);
1672         temp |= UCR2_RXEN;
1673         writel(temp, sport->port.membase + UCR2);
1674
1675         spin_unlock_irqrestore(&sport->port.lock, flags);
1676
1677         return 0;
1678 }
1679
1680 static int imx_poll_get_char(struct uart_port *port)
1681 {
1682         if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1683                 return NO_POLL_CHAR;
1684
1685         return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1686 }
1687
1688 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1689 {
1690         unsigned int status;
1691
1692         /* drain */
1693         do {
1694                 status = readl_relaxed(port->membase + USR1);
1695         } while (~status & USR1_TRDY);
1696
1697         /* write */
1698         writel_relaxed(c, port->membase + URTX0);
1699
1700         /* flush */
1701         do {
1702                 status = readl_relaxed(port->membase + USR2);
1703         } while (~status & USR2_TXDC);
1704 }
1705 #endif
1706
1707 static int imx_rs485_config(struct uart_port *port,
1708                             struct serial_rs485 *rs485conf)
1709 {
1710         struct imx_port *sport = (struct imx_port *)port;
1711         unsigned long temp;
1712
1713         /* unimplemented */
1714         rs485conf->delay_rts_before_send = 0;
1715         rs485conf->delay_rts_after_send = 0;
1716
1717         /* RTS is required to control the transmitter */
1718         if (!sport->have_rtscts && !sport->have_rtsgpio)
1719                 rs485conf->flags &= ~SER_RS485_ENABLED;
1720
1721         if (rs485conf->flags & SER_RS485_ENABLED) {
1722                 /* disable transmitter */
1723                 temp = readl(sport->port.membase + UCR2);
1724                 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1725                         imx_port_rts_active(sport, &temp);
1726                 else
1727                         imx_port_rts_inactive(sport, &temp);
1728                 writel(temp, sport->port.membase + UCR2);
1729         }
1730
1731         /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1732         if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1733             rs485conf->flags & SER_RS485_RX_DURING_TX) {
1734                 temp = readl(sport->port.membase + UCR2);
1735                 temp |= UCR2_RXEN;
1736                 writel(temp, sport->port.membase + UCR2);
1737         }
1738
1739         port->rs485 = *rs485conf;
1740
1741         return 0;
1742 }
1743
1744 static const struct uart_ops imx_pops = {
1745         .tx_empty       = imx_tx_empty,
1746         .set_mctrl      = imx_set_mctrl,
1747         .get_mctrl      = imx_get_mctrl,
1748         .stop_tx        = imx_stop_tx,
1749         .start_tx       = imx_start_tx,
1750         .stop_rx        = imx_stop_rx,
1751         .enable_ms      = imx_enable_ms,
1752         .break_ctl      = imx_break_ctl,
1753         .startup        = imx_startup,
1754         .shutdown       = imx_shutdown,
1755         .flush_buffer   = imx_flush_buffer,
1756         .set_termios    = imx_set_termios,
1757         .type           = imx_type,
1758         .config_port    = imx_config_port,
1759         .verify_port    = imx_verify_port,
1760 #if defined(CONFIG_CONSOLE_POLL)
1761         .poll_init      = imx_poll_init,
1762         .poll_get_char  = imx_poll_get_char,
1763         .poll_put_char  = imx_poll_put_char,
1764 #endif
1765 };
1766
1767 static struct imx_port *imx_ports[UART_NR];
1768
1769 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1770 static void imx_console_putchar(struct uart_port *port, int ch)
1771 {
1772         struct imx_port *sport = (struct imx_port *)port;
1773
1774         while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1775                 barrier();
1776
1777         writel(ch, sport->port.membase + URTX0);
1778 }
1779
1780 /*
1781  * Interrupts are disabled on entering
1782  */
1783 static void
1784 imx_console_write(struct console *co, const char *s, unsigned int count)
1785 {
1786         struct imx_port *sport = imx_ports[co->index];
1787         struct imx_port_ucrs old_ucr;
1788         unsigned int ucr1;
1789         unsigned long flags = 0;
1790         int locked = 1;
1791         int retval;
1792
1793         retval = clk_enable(sport->clk_per);
1794         if (retval)
1795                 return;
1796         retval = clk_enable(sport->clk_ipg);
1797         if (retval) {
1798                 clk_disable(sport->clk_per);
1799                 return;
1800         }
1801
1802         if (sport->port.sysrq)
1803                 locked = 0;
1804         else if (oops_in_progress)
1805                 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1806         else
1807                 spin_lock_irqsave(&sport->port.lock, flags);
1808
1809         /*
1810          *      First, save UCR1/2/3 and then disable interrupts
1811          */
1812         imx_port_ucrs_save(&sport->port, &old_ucr);
1813         ucr1 = old_ucr.ucr1;
1814
1815         if (is_imx1_uart(sport))
1816                 ucr1 |= IMX1_UCR1_UARTCLKEN;
1817         ucr1 |= UCR1_UARTEN;
1818         ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1819
1820         writel(ucr1, sport->port.membase + UCR1);
1821
1822         writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1823
1824         uart_console_write(&sport->port, s, count, imx_console_putchar);
1825
1826         /*
1827          *      Finally, wait for transmitter to become empty
1828          *      and restore UCR1/2/3
1829          */
1830         while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1831
1832         imx_port_ucrs_restore(&sport->port, &old_ucr);
1833
1834         if (locked)
1835                 spin_unlock_irqrestore(&sport->port.lock, flags);
1836
1837         clk_disable(sport->clk_ipg);
1838         clk_disable(sport->clk_per);
1839 }
1840
1841 /*
1842  * If the port was already initialised (eg, by a boot loader),
1843  * try to determine the current setup.
1844  */
1845 static void __init
1846 imx_console_get_options(struct imx_port *sport, int *baud,
1847                            int *parity, int *bits)
1848 {
1849
1850         if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1851                 /* ok, the port was enabled */
1852                 unsigned int ucr2, ubir, ubmr, uartclk;
1853                 unsigned int baud_raw;
1854                 unsigned int ucfr_rfdiv;
1855
1856                 ucr2 = readl(sport->port.membase + UCR2);
1857
1858                 *parity = 'n';
1859                 if (ucr2 & UCR2_PREN) {
1860                         if (ucr2 & UCR2_PROE)
1861                                 *parity = 'o';
1862                         else
1863                                 *parity = 'e';
1864                 }
1865
1866                 if (ucr2 & UCR2_WS)
1867                         *bits = 8;
1868                 else
1869                         *bits = 7;
1870
1871                 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1872                 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1873
1874                 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1875                 if (ucfr_rfdiv == 6)
1876                         ucfr_rfdiv = 7;
1877                 else
1878                         ucfr_rfdiv = 6 - ucfr_rfdiv;
1879
1880                 uartclk = clk_get_rate(sport->clk_per);
1881                 uartclk /= ucfr_rfdiv;
1882
1883                 {       /*
1884                          * The next code provides exact computation of
1885                          *   baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1886                          * without need of float support or long long division,
1887                          * which would be required to prevent 32bit arithmetic overflow
1888                          */
1889                         unsigned int mul = ubir + 1;
1890                         unsigned int div = 16 * (ubmr + 1);
1891                         unsigned int rem = uartclk % div;
1892
1893                         baud_raw = (uartclk / div) * mul;
1894                         baud_raw += (rem * mul + div / 2) / div;
1895                         *baud = (baud_raw + 50) / 100 * 100;
1896                 }
1897
1898                 if (*baud != baud_raw)
1899                         pr_info("Console IMX rounded baud rate from %d to %d\n",
1900                                 baud_raw, *baud);
1901         }
1902 }
1903
1904 static int __init
1905 imx_console_setup(struct console *co, char *options)
1906 {
1907         struct imx_port *sport;
1908         int baud = 9600;
1909         int bits = 8;
1910         int parity = 'n';
1911         int flow = 'n';
1912         int retval;
1913
1914         /*
1915          * Check whether an invalid uart number has been specified, and
1916          * if so, search for the first available port that does have
1917          * console support.
1918          */
1919         if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1920                 co->index = 0;
1921         sport = imx_ports[co->index];
1922         if (sport == NULL)
1923                 return -ENODEV;
1924
1925         /* For setting the registers, we only need to enable the ipg clock. */
1926         retval = clk_prepare_enable(sport->clk_ipg);
1927         if (retval)
1928                 goto error_console;
1929
1930         if (options)
1931                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1932         else
1933                 imx_console_get_options(sport, &baud, &parity, &bits);
1934
1935         imx_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1936
1937         retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1938
1939         clk_disable(sport->clk_ipg);
1940         if (retval) {
1941                 clk_unprepare(sport->clk_ipg);
1942                 goto error_console;
1943         }
1944
1945         retval = clk_prepare(sport->clk_per);
1946         if (retval)
1947                 clk_disable_unprepare(sport->clk_ipg);
1948
1949 error_console:
1950         return retval;
1951 }
1952
1953 static struct uart_driver imx_reg;
1954 static struct console imx_console = {
1955         .name           = DEV_NAME,
1956         .write          = imx_console_write,
1957         .device         = uart_console_device,
1958         .setup          = imx_console_setup,
1959         .flags          = CON_PRINTBUFFER,
1960         .index          = -1,
1961         .data           = &imx_reg,
1962 };
1963
1964 #define IMX_CONSOLE     &imx_console
1965
1966 #ifdef CONFIG_OF
1967 static void imx_console_early_putchar(struct uart_port *port, int ch)
1968 {
1969         while (readl_relaxed(port->membase + IMX21_UTS) & UTS_TXFULL)
1970                 cpu_relax();
1971
1972         writel_relaxed(ch, port->membase + URTX0);
1973 }
1974
1975 static void imx_console_early_write(struct console *con, const char *s,
1976                                     unsigned count)
1977 {
1978         struct earlycon_device *dev = con->data;
1979
1980         uart_console_write(&dev->port, s, count, imx_console_early_putchar);
1981 }
1982
1983 static int __init
1984 imx_console_early_setup(struct earlycon_device *dev, const char *opt)
1985 {
1986         if (!dev->port.membase)
1987                 return -ENODEV;
1988
1989         dev->con->write = imx_console_early_write;
1990
1991         return 0;
1992 }
1993 OF_EARLYCON_DECLARE(ec_imx6q, "fsl,imx6q-uart", imx_console_early_setup);
1994 OF_EARLYCON_DECLARE(ec_imx21, "fsl,imx21-uart", imx_console_early_setup);
1995 #endif
1996
1997 #else
1998 #define IMX_CONSOLE     NULL
1999 #endif
2000
2001 static struct uart_driver imx_reg = {
2002         .owner          = THIS_MODULE,
2003         .driver_name    = DRIVER_NAME,
2004         .dev_name       = DEV_NAME,
2005         .major          = SERIAL_IMX_MAJOR,
2006         .minor          = MINOR_START,
2007         .nr             = ARRAY_SIZE(imx_ports),
2008         .cons           = IMX_CONSOLE,
2009 };
2010
2011 #ifdef CONFIG_OF
2012 /*
2013  * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
2014  * could successfully get all information from dt or a negative errno.
2015  */
2016 static int serial_imx_probe_dt(struct imx_port *sport,
2017                 struct platform_device *pdev)
2018 {
2019         struct device_node *np = pdev->dev.of_node;
2020         int ret;
2021
2022         sport->devdata = of_device_get_match_data(&pdev->dev);
2023         if (!sport->devdata)
2024                 /* no device tree device */
2025                 return 1;
2026
2027         ret = of_alias_get_id(np, "serial");
2028         if (ret < 0) {
2029                 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2030                 return ret;
2031         }
2032         sport->port.line = ret;
2033
2034         if (of_get_property(np, "uart-has-rtscts", NULL) ||
2035             of_get_property(np, "fsl,uart-has-rtscts", NULL) /* deprecated */)
2036                 sport->have_rtscts = 1;
2037
2038         if (of_get_property(np, "fsl,dte-mode", NULL))
2039                 sport->dte_mode = 1;
2040
2041         if (of_get_property(np, "rts-gpios", NULL))
2042                 sport->have_rtsgpio = 1;
2043
2044         return 0;
2045 }
2046 #else
2047 static inline int serial_imx_probe_dt(struct imx_port *sport,
2048                 struct platform_device *pdev)
2049 {
2050         return 1;
2051 }
2052 #endif
2053
2054 static void serial_imx_probe_pdata(struct imx_port *sport,
2055                 struct platform_device *pdev)
2056 {
2057         struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
2058
2059         sport->port.line = pdev->id;
2060         sport->devdata = (struct imx_uart_data  *) pdev->id_entry->driver_data;
2061
2062         if (!pdata)
2063                 return;
2064
2065         if (pdata->flags & IMXUART_HAVE_RTSCTS)
2066                 sport->have_rtscts = 1;
2067 }
2068
2069 static int serial_imx_probe(struct platform_device *pdev)
2070 {
2071         struct imx_port *sport;
2072         void __iomem *base;
2073         int ret = 0, reg;
2074         struct resource *res;
2075         int txirq, rxirq, rtsirq;
2076
2077         sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2078         if (!sport)
2079                 return -ENOMEM;
2080
2081         ret = serial_imx_probe_dt(sport, pdev);
2082         if (ret > 0)
2083                 serial_imx_probe_pdata(sport, pdev);
2084         else if (ret < 0)
2085                 return ret;
2086
2087         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2088         base = devm_ioremap_resource(&pdev->dev, res);
2089         if (IS_ERR(base))
2090                 return PTR_ERR(base);
2091
2092         rxirq = platform_get_irq(pdev, 0);
2093         txirq = platform_get_irq(pdev, 1);
2094         rtsirq = platform_get_irq(pdev, 2);
2095
2096         sport->port.dev = &pdev->dev;
2097         sport->port.mapbase = res->start;
2098         sport->port.membase = base;
2099         sport->port.type = PORT_IMX,
2100         sport->port.iotype = UPIO_MEM;
2101         sport->port.irq = rxirq;
2102         sport->port.fifosize = 32;
2103         sport->port.ops = &imx_pops;
2104         sport->port.rs485_config = imx_rs485_config;
2105         sport->port.rs485.flags =
2106                 SER_RS485_RTS_ON_SEND | SER_RS485_RX_DURING_TX;
2107         sport->port.flags = UPF_BOOT_AUTOCONF;
2108         init_timer(&sport->timer);
2109         sport->timer.function = imx_timeout;
2110         sport->timer.data     = (unsigned long)sport;
2111
2112         sport->gpios = mctrl_gpio_init(&sport->port, 0);
2113         if (IS_ERR(sport->gpios))
2114                 return PTR_ERR(sport->gpios);
2115
2116         sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2117         if (IS_ERR(sport->clk_ipg)) {
2118                 ret = PTR_ERR(sport->clk_ipg);
2119                 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2120                 return ret;
2121         }
2122
2123         sport->clk_per = devm_clk_get(&pdev->dev, "per");
2124         if (IS_ERR(sport->clk_per)) {
2125                 ret = PTR_ERR(sport->clk_per);
2126                 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2127                 return ret;
2128         }
2129
2130         sport->port.uartclk = clk_get_rate(sport->clk_per);
2131
2132         /* For register access, we only need to enable the ipg clock. */
2133         ret = clk_prepare_enable(sport->clk_ipg);
2134         if (ret) {
2135                 dev_err(&pdev->dev, "failed to enable per clk: %d\n", ret);
2136                 return ret;
2137         }
2138
2139         /* Disable interrupts before requesting them */
2140         reg = readl_relaxed(sport->port.membase + UCR1);
2141         reg &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN |
2142                  UCR1_TXMPTYEN | UCR1_RTSDEN);
2143         writel_relaxed(reg, sport->port.membase + UCR1);
2144
2145         if (!is_imx1_uart(sport) && sport->dte_mode) {
2146                 /*
2147                  * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2148                  * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2149                  * and DCD (when they are outputs) or enables the respective
2150                  * irqs. So set this bit early, i.e. before requesting irqs.
2151                  */
2152                 writel(UFCR_DCEDTE, sport->port.membase + UFCR);
2153
2154                 /*
2155                  * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2156                  * enabled later because they cannot be cleared
2157                  * (confirmed on i.MX25) which makes them unusable.
2158                  */
2159                 writel(IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2160                        sport->port.membase + UCR3);
2161
2162         } else {
2163                 writel(0, sport->port.membase + UFCR);
2164         }
2165
2166         clk_disable_unprepare(sport->clk_ipg);
2167
2168         /*
2169          * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2170          * chips only have one interrupt.
2171          */
2172         if (txirq > 0) {
2173                 ret = devm_request_irq(&pdev->dev, rxirq, imx_rxint, 0,
2174                                        dev_name(&pdev->dev), sport);
2175                 if (ret) {
2176                         dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2177                                 ret);
2178                         return ret;
2179                 }
2180
2181                 ret = devm_request_irq(&pdev->dev, txirq, imx_txint, 0,
2182                                        dev_name(&pdev->dev), sport);
2183                 if (ret) {
2184                         dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2185                                 ret);
2186                         return ret;
2187                 }
2188         } else {
2189                 ret = devm_request_irq(&pdev->dev, rxirq, imx_int, 0,
2190                                        dev_name(&pdev->dev), sport);
2191                 if (ret) {
2192                         dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2193                         return ret;
2194                 }
2195         }
2196
2197         imx_ports[sport->port.line] = sport;
2198
2199         platform_set_drvdata(pdev, sport);
2200
2201         return uart_add_one_port(&imx_reg, &sport->port);
2202 }
2203
2204 static int serial_imx_remove(struct platform_device *pdev)
2205 {
2206         struct imx_port *sport = platform_get_drvdata(pdev);
2207
2208         return uart_remove_one_port(&imx_reg, &sport->port);
2209 }
2210
2211 static void serial_imx_restore_context(struct imx_port *sport)
2212 {
2213         if (!sport->context_saved)
2214                 return;
2215
2216         writel(sport->saved_reg[4], sport->port.membase + UFCR);
2217         writel(sport->saved_reg[5], sport->port.membase + UESC);
2218         writel(sport->saved_reg[6], sport->port.membase + UTIM);
2219         writel(sport->saved_reg[7], sport->port.membase + UBIR);
2220         writel(sport->saved_reg[8], sport->port.membase + UBMR);
2221         writel(sport->saved_reg[9], sport->port.membase + IMX21_UTS);
2222         writel(sport->saved_reg[0], sport->port.membase + UCR1);
2223         writel(sport->saved_reg[1] | UCR2_SRST, sport->port.membase + UCR2);
2224         writel(sport->saved_reg[2], sport->port.membase + UCR3);
2225         writel(sport->saved_reg[3], sport->port.membase + UCR4);
2226         sport->context_saved = false;
2227 }
2228
2229 static void serial_imx_save_context(struct imx_port *sport)
2230 {
2231         /* Save necessary regs */
2232         sport->saved_reg[0] = readl(sport->port.membase + UCR1);
2233         sport->saved_reg[1] = readl(sport->port.membase + UCR2);
2234         sport->saved_reg[2] = readl(sport->port.membase + UCR3);
2235         sport->saved_reg[3] = readl(sport->port.membase + UCR4);
2236         sport->saved_reg[4] = readl(sport->port.membase + UFCR);
2237         sport->saved_reg[5] = readl(sport->port.membase + UESC);
2238         sport->saved_reg[6] = readl(sport->port.membase + UTIM);
2239         sport->saved_reg[7] = readl(sport->port.membase + UBIR);
2240         sport->saved_reg[8] = readl(sport->port.membase + UBMR);
2241         sport->saved_reg[9] = readl(sport->port.membase + IMX21_UTS);
2242         sport->context_saved = true;
2243 }
2244
2245 static void serial_imx_enable_wakeup(struct imx_port *sport, bool on)
2246 {
2247         unsigned int val;
2248
2249         val = readl(sport->port.membase + UCR3);
2250         if (on)
2251                 val |= UCR3_AWAKEN;
2252         else
2253                 val &= ~UCR3_AWAKEN;
2254         writel(val, sport->port.membase + UCR3);
2255
2256         val = readl(sport->port.membase + UCR1);
2257         if (on)
2258                 val |= UCR1_RTSDEN;
2259         else
2260                 val &= ~UCR1_RTSDEN;
2261         writel(val, sport->port.membase + UCR1);
2262 }
2263
2264 static int imx_serial_port_suspend_noirq(struct device *dev)
2265 {
2266         struct platform_device *pdev = to_platform_device(dev);
2267         struct imx_port *sport = platform_get_drvdata(pdev);
2268         int ret;
2269
2270         ret = clk_enable(sport->clk_ipg);
2271         if (ret)
2272                 return ret;
2273
2274         serial_imx_save_context(sport);
2275
2276         clk_disable(sport->clk_ipg);
2277
2278         return 0;
2279 }
2280
2281 static int imx_serial_port_resume_noirq(struct device *dev)
2282 {
2283         struct platform_device *pdev = to_platform_device(dev);
2284         struct imx_port *sport = platform_get_drvdata(pdev);
2285         int ret;
2286
2287         ret = clk_enable(sport->clk_ipg);
2288         if (ret)
2289                 return ret;
2290
2291         serial_imx_restore_context(sport);
2292
2293         clk_disable(sport->clk_ipg);
2294
2295         return 0;
2296 }
2297
2298 static int imx_serial_port_suspend(struct device *dev)
2299 {
2300         struct platform_device *pdev = to_platform_device(dev);
2301         struct imx_port *sport = platform_get_drvdata(pdev);
2302
2303         /* enable wakeup from i.MX UART */
2304         serial_imx_enable_wakeup(sport, true);
2305
2306         uart_suspend_port(&imx_reg, &sport->port);
2307
2308         /* Needed to enable clock in suspend_noirq */
2309         return clk_prepare(sport->clk_ipg);
2310 }
2311
2312 static int imx_serial_port_resume(struct device *dev)
2313 {
2314         struct platform_device *pdev = to_platform_device(dev);
2315         struct imx_port *sport = platform_get_drvdata(pdev);
2316
2317         /* disable wakeup from i.MX UART */
2318         serial_imx_enable_wakeup(sport, false);
2319
2320         uart_resume_port(&imx_reg, &sport->port);
2321
2322         clk_unprepare(sport->clk_ipg);
2323
2324         return 0;
2325 }
2326
2327 static const struct dev_pm_ops imx_serial_port_pm_ops = {
2328         .suspend_noirq = imx_serial_port_suspend_noirq,
2329         .resume_noirq = imx_serial_port_resume_noirq,
2330         .suspend = imx_serial_port_suspend,
2331         .resume = imx_serial_port_resume,
2332 };
2333
2334 static struct platform_driver serial_imx_driver = {
2335         .probe          = serial_imx_probe,
2336         .remove         = serial_imx_remove,
2337
2338         .id_table       = imx_uart_devtype,
2339         .driver         = {
2340                 .name   = "imx-uart",
2341                 .of_match_table = imx_uart_dt_ids,
2342                 .pm     = &imx_serial_port_pm_ops,
2343         },
2344 };
2345
2346 static int __init imx_serial_init(void)
2347 {
2348         int ret = uart_register_driver(&imx_reg);
2349
2350         if (ret)
2351                 return ret;
2352
2353         ret = platform_driver_register(&serial_imx_driver);
2354         if (ret != 0)
2355                 uart_unregister_driver(&imx_reg);
2356
2357         return ret;
2358 }
2359
2360 static void __exit imx_serial_exit(void)
2361 {
2362         platform_driver_unregister(&serial_imx_driver);
2363         uart_unregister_driver(&imx_reg);
2364 }
2365
2366 module_init(imx_serial_init);
2367 module_exit(imx_serial_exit);
2368
2369 MODULE_AUTHOR("Sascha Hauer");
2370 MODULE_DESCRIPTION("IMX generic serial port driver");
2371 MODULE_LICENSE("GPL");
2372 MODULE_ALIAS("platform:imx-uart");