drivers/usb/host/ohci-hcd.c

   1 /*
   2  * Open Host Controller Interface (OHCI) driver for USB.
   3  *
   4  * Maintainer: Alan Stern <stern@rowland.harvard.edu>
   5  *
   6  * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
   7  * (C) Copyright 2000-2004 David Brownell <dbrownell@users.sourceforge.net>
   8  *
   9  * [ Initialisation is based on Linus'  ]
  10  * [ uhci code and gregs ohci fragments ]
  11  * [ (C) Copyright 1999 Linus Torvalds  ]
  12  * [ (C) Copyright 1999 Gregory P. Smith]
  13  *
  14  *
  15  * OHCI is the main "non-Intel/VIA" standard for USB 1.1 host controller
  16  * interfaces (though some non-x86 Intel chips use it).  It supports
  17  * smarter hardware than UHCI.  A download link for the spec available
  18  * through the http://www.usb.org website.
  19  *
  20  * This file is licenced under the GPL.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/pci.h>
  26 #include <linux/kernel.h>
  27 #include <linux/delay.h>
  28 #include <linux/ioport.h>
  29 #include <linux/sched.h>
  30 #include <linux/slab.h>
  31 #include <linux/errno.h>
  32 #include <linux/init.h>
  33 #include <linux/timer.h>
  34 #include <linux/list.h>
  35 #include <linux/usb.h>
  36 #include <linux/usb/otg.h>
  37 #include <linux/usb/hcd.h>
  38 #include <linux/dma-mapping.h>
  39 #include <linux/dmapool.h>
  40 #include <linux/workqueue.h>
  41 #include <linux/debugfs.h>
  42
  43 #include <asm/io.h>
  44 #include <asm/irq.h>
  45 #include <asm/unaligned.h>
  46 #include <asm/byteorder.h>
  47
  48
  49 #define DRIVER_AUTHOR "Roman Weissgaerber, David Brownell"
  50 #define DRIVER_DESC "USB 1.1 'Open' Host Controller (OHCI) Driver"
  51
  52 /*-------------------------------------------------------------------------*/
  53
  54 /* For initializing controller (mask in an HCFS mode too) */
  55 #define OHCI_CONTROL_INIT       OHCI_CTRL_CBSR
  56 #define OHCI_INTR_INIT \
  57                 (OHCI_INTR_MIE | OHCI_INTR_RHSC | OHCI_INTR_UE \
  58                 | OHCI_INTR_RD | OHCI_INTR_WDH)
  59
  60 #ifdef __hppa__
  61 /* On PA-RISC, PDC can leave IR set incorrectly; ignore it there. */
  62 #define IR_DISABLE
  63 #endif
  64
  65 #ifdef CONFIG_ARCH_OMAP
  66 /* OMAP doesn't support IR (no SMM; not needed) */
  67 #define IR_DISABLE
  68 #endif
  69
  70 /*-------------------------------------------------------------------------*/
  71
  72 static const char       hcd_name [] = "ohci_hcd";
  73
  74 #define STATECHANGE_DELAY       msecs_to_jiffies(300)
  75
  76 #include "ohci.h"
  77 #include "pci-quirks.h"
  78
  79 static void ohci_dump(struct ohci_hcd *ohci);
  80 static void ohci_stop(struct usb_hcd *hcd);
  81
  82 #include "ohci-hub.c"
  83 #include "ohci-dbg.c"
  84 #include "ohci-mem.c"
  85 #include "ohci-q.c"
  86
  87
  88 /*
  89  * On architectures with edge-triggered interrupts we must never return
  90  * IRQ_NONE.
  91  */
  92 #if defined(CONFIG_SA1111)  /* ... or other edge-triggered systems */
  93 #define IRQ_NOTMINE     IRQ_HANDLED
  94 #else
  95 #define IRQ_NOTMINE     IRQ_NONE
  96 #endif
  97
  98
  99 /* Some boards misreport power switching/overcurrent */
 100 static bool distrust_firmware = 1;
 101 module_param (distrust_firmware, bool, 0);
 102 MODULE_PARM_DESC (distrust_firmware,
 103         "true to distrust firmware power/overcurrent setup");
 104
 105 /* Some boards leave IR set wrongly, since they fail BIOS/SMM handshakes */
 106 static bool no_handshake = 0;
 107 module_param (no_handshake, bool, 0);
 108 MODULE_PARM_DESC (no_handshake, "true (not default) disables BIOS handshake");
 109
 110 /*-------------------------------------------------------------------------*/
 111
 112 static int number_of_tds(struct urb *urb)
 113 {
 114         int                     len, i, num, this_sg_len;
 115         struct scatterlist      *sg;
 116
 117         len = urb->transfer_buffer_length;
 118         i = urb->num_mapped_sgs;
 119
 120         if (len > 0 && i > 0) {         /* Scatter-gather transfer */
 121                 num = 0;
 122                 sg = urb->sg;
 123                 for (;;) {
 124                         this_sg_len = min_t(int, sg_dma_len(sg), len);
 125                         num += DIV_ROUND_UP(this_sg_len, 4096);
 126                         len -= this_sg_len;
 127                         if (--i <= 0 || len <= 0)
 128                                 break;
 129                         sg = sg_next(sg);
 130                 }
 131
 132         } else {                        /* Non-SG transfer */
 133                 /* one TD for every 4096 Bytes (could be up to 8K) */
 134                 num = DIV_ROUND_UP(len, 4096);
 135         }
 136         return num;
 137 }
 138
 139 /*
 140  * queue up an urb for anything except the root hub
 141  */
 142 static int ohci_urb_enqueue (
 143         struct usb_hcd  *hcd,
 144         struct urb      *urb,
 145         gfp_t           mem_flags
 146 ) {
 147         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 148         struct ed       *ed;
 149         urb_priv_t      *urb_priv;
 150         unsigned int    pipe = urb->pipe;
 151         int             i, size = 0;
 152         unsigned long   flags;
 153         int             retval = 0;
 154
 155         /* every endpoint has a ed, locate and maybe (re)initialize it */
 156         if (! (ed = ed_get (ohci, urb->ep, urb->dev, pipe, urb->interval)))
 157                 return -ENOMEM;
 158
 159         /* for the private part of the URB we need the number of TDs (size) */
 160         switch (ed->type) {
 161                 case PIPE_CONTROL:
 162                         /* td_submit_urb() doesn't yet handle these */
 163                         if (urb->transfer_buffer_length > 4096)
 164                                 return -EMSGSIZE;
 165
 166                         /* 1 TD for setup, 1 for ACK, plus ... */
 167                         size = 2;
 168                         /* FALLTHROUGH */
 169                 // case PIPE_INTERRUPT:
 170                 // case PIPE_BULK:
 171                 default:
 172                         size += number_of_tds(urb);
 173                         /* maybe a zero-length packet to wrap it up */
 174                         if (size == 0)
 175                                 size++;
 176                         else if ((urb->transfer_flags & URB_ZERO_PACKET) != 0
 177                                 && (urb->transfer_buffer_length
 178                                         % usb_maxpacket (urb->dev, pipe,
 179                                                 usb_pipeout (pipe))) == 0)
 180                                 size++;
 181                         break;
 182                 case PIPE_ISOCHRONOUS: /* number of packets from URB */
 183                         size = urb->number_of_packets;
 184                         break;
 185         }
 186
 187         /* allocate the private part of the URB */
 188         urb_priv = kzalloc (sizeof (urb_priv_t) + size * sizeof (struct td *),
 189                         mem_flags);
 190         if (!urb_priv)
 191                 return -ENOMEM;
 192         INIT_LIST_HEAD (&urb_priv->pending);
 193         urb_priv->length = size;
 194         urb_priv->ed = ed;
 195
 196         /* allocate the TDs (deferring hash chain updates) */
 197         for (i = 0; i < size; i++) {
 198                 urb_priv->td [i] = td_alloc (ohci, mem_flags);
 199                 if (!urb_priv->td [i]) {
 200                         urb_priv->length = i;
 201                         urb_free_priv (ohci, urb_priv);
 202                         return -ENOMEM;
 203                 }
 204         }
 205
 206         spin_lock_irqsave (&ohci->lock, flags);
 207
 208         /* don't submit to a dead HC */
 209         if (!HCD_HW_ACCESSIBLE(hcd)) {
 210                 retval = -ENODEV;
 211                 goto fail;
 212         }
 213         if (ohci->rh_state != OHCI_RH_RUNNING) {
 214                 retval = -ENODEV;
 215                 goto fail;
 216         }
 217         retval = usb_hcd_link_urb_to_ep(hcd, urb);
 218         if (retval)
 219                 goto fail;
 220
 221         /* schedule the ed if needed */
 222         if (ed->state == ED_IDLE) {
 223                 retval = ed_schedule (ohci, ed);
 224                 if (retval < 0) {
 225                         usb_hcd_unlink_urb_from_ep(hcd, urb);
 226                         goto fail;
 227                 }
 228                 if (ed->type == PIPE_ISOCHRONOUS) {
 229                         u16     frame = ohci_frame_no(ohci);
 230
 231                         /* delay a few frames before the first TD */
 232                         frame += max_t (u16, 8, ed->interval);
 233                         frame &= ~(ed->interval - 1);
 234                         frame |= ed->branch;
 235                         urb->start_frame = frame;
 236                         ed->last_iso = frame + ed->interval * (size - 1);
 237                 }
 238         } else if (ed->type == PIPE_ISOCHRONOUS) {
 239                 u16     next = ohci_frame_no(ohci) + 1;
 240                 u16     frame = ed->last_iso + ed->interval;
 241                 u16     length = ed->interval * (size - 1);
 242
 243                 /* Behind the scheduling threshold? */
 244                 if (unlikely(tick_before(frame, next))) {
 245
 246                         /* URB_ISO_ASAP: Round up to the first available slot */
 247                         if (urb->transfer_flags & URB_ISO_ASAP) {
 248                                 frame += (next - frame + ed->interval - 1) &
 249                                                 -ed->interval;
 250
 251                         /*
 252                          * Not ASAP: Use the next slot in the stream,
 253                          * no matter what.
 254                          */
 255                         } else {
 256                                 /*
 257                                  * Some OHCI hardware doesn't handle late TDs
 258                                  * correctly.  After retiring them it proceeds
 259                                  * to the next ED instead of the next TD.
 260                                  * Therefore we have to omit the late TDs
 261                                  * entirely.
 262                                  */
 263                                 urb_priv->td_cnt = DIV_ROUND_UP(
 264                                                 (u16) (next - frame),
 265                                                 ed->interval);
 266                                 if (urb_priv->td_cnt >= urb_priv->length) {
 267                                         ++urb_priv->td_cnt;     /* Mark it */
 268                                         ohci_dbg(ohci, "iso underrun %p (%u+%u < %u)\n",
 269                                                         urb, frame, length,
 270                                                         next);
 271                                 }
 272                         }
 273                 }
 274                 urb->start_frame = frame;
 275                 ed->last_iso = frame + length;
 276         }
 277
 278         /* fill the TDs and link them to the ed; and
 279          * enable that part of the schedule, if needed
 280          * and update count of queued periodic urbs
 281          */
 282         urb->hcpriv = urb_priv;
 283         td_submit_urb (ohci, urb);
 284
 285 fail:
 286         if (retval)
 287                 urb_free_priv (ohci, urb_priv);
 288         spin_unlock_irqrestore (&ohci->lock, flags);
 289         return retval;
 290 }
 291
 292 /*
 293  * decouple the URB from the HC queues (TDs, urb_priv).
 294  * reporting is always done
 295  * asynchronously, and we might be dealing with an urb that's
 296  * partially transferred, or an ED with other urbs being unlinked.
 297  */
 298 static int ohci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
 299 {
 300         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 301         unsigned long           flags;
 302         int                     rc;
 303
 304         spin_lock_irqsave (&ohci->lock, flags);
 305         rc = usb_hcd_check_unlink_urb(hcd, urb, status);
 306         if (rc) {
 307                 ;       /* Do nothing */
 308         } else if (ohci->rh_state == OHCI_RH_RUNNING) {
 309                 urb_priv_t  *urb_priv;
 310
 311                 /* Unless an IRQ completed the unlink while it was being
 312                  * handed to us, flag it for unlink and giveback, and force
 313                  * some upcoming INTR_SF to call finish_unlinks()
 314                  */
 315                 urb_priv = urb->hcpriv;
 316                 if (urb_priv) {
 317                         if (urb_priv->ed->state == ED_OPER)
 318                                 start_ed_unlink (ohci, urb_priv->ed);
 319                 }
 320         } else {
 321                 /*
 322                  * with HC dead, we won't respect hc queue pointers
 323                  * any more ... just clean up every urb's memory.
 324                  */
 325                 if (urb->hcpriv)
 326                         finish_urb(ohci, urb, status);
 327         }
 328         spin_unlock_irqrestore (&ohci->lock, flags);
 329         return rc;
 330 }
 331
 332 /*-------------------------------------------------------------------------*/
 333
 334 /* frees config/altsetting state for endpoints,
 335  * including ED memory, dummy TD, and bulk/intr data toggle
 336  */
 337
 338 static void
 339 ohci_endpoint_disable (struct usb_hcd *hcd, struct usb_host_endpoint *ep)
 340 {
 341         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 342         unsigned long           flags;
 343         struct ed               *ed = ep->hcpriv;
 344         unsigned                limit = 1000;
 345
 346         /* ASSERT:  any requests/urbs are being unlinked */
 347         /* ASSERT:  nobody can be submitting urbs for this any more */
 348
 349         if (!ed)
 350                 return;
 351
 352 rescan:
 353         spin_lock_irqsave (&ohci->lock, flags);
 354
 355         if (ohci->rh_state != OHCI_RH_RUNNING) {
 356 sanitize:
 357                 ed->state = ED_IDLE;
 358                 finish_unlinks (ohci, 0);
 359         }
 360
 361         switch (ed->state) {
 362         case ED_UNLINK:         /* wait for hw to finish? */
 363                 /* major IRQ delivery trouble loses INTR_SF too... */
 364                 if (limit-- == 0) {
 365                         ohci_warn(ohci, "ED unlink timeout\n");
 366                         goto sanitize;
 367                 }
 368                 spin_unlock_irqrestore (&ohci->lock, flags);
 369                 schedule_timeout_uninterruptible(1);
 370                 goto rescan;
 371         case ED_IDLE:           /* fully unlinked */
 372                 if (list_empty (&ed->td_list)) {
 373                         td_free (ohci, ed->dummy);
 374                         ed_free (ohci, ed);
 375                         break;
 376                 }
 377                 /* else FALL THROUGH */
 378         default:
 379                 /* caller was supposed to have unlinked any requests;
 380                  * that's not our job.  can't recover; must leak ed.
 381                  */
 382                 ohci_err (ohci, "leak ed %p (#%02x) state %d%s\n",
 383                         ed, ep->desc.bEndpointAddress, ed->state,
 384                         list_empty (&ed->td_list) ? "" : " (has tds)");
 385                 td_free (ohci, ed->dummy);
 386                 break;
 387         }
 388         ep->hcpriv = NULL;
 389         spin_unlock_irqrestore (&ohci->lock, flags);
 390 }
 391
 392 static int ohci_get_frame (struct usb_hcd *hcd)
 393 {
 394         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 395
 396         return ohci_frame_no(ohci);
 397 }
 398
 399 static void ohci_usb_reset (struct ohci_hcd *ohci)
 400 {
 401         ohci->hc_control = ohci_readl (ohci, &ohci->regs->control);
 402         ohci->hc_control &= OHCI_CTRL_RWC;
 403         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 404         ohci->rh_state = OHCI_RH_HALTED;
 405 }
 406
 407 /* ohci_shutdown forcibly disables IRQs and DMA, helping kexec and
 408  * other cases where the next software may expect clean state from the
 409  * "firmware".  this is bus-neutral, unlike shutdown() methods.
 410  */
 411 static void
 412 ohci_shutdown (struct usb_hcd *hcd)
 413 {
 414         struct ohci_hcd *ohci;
 415
 416         ohci = hcd_to_ohci (hcd);
 417         ohci_writel(ohci, (u32) ~0, &ohci->regs->intrdisable);
 418
 419         /* Software reset, after which the controller goes into SUSPEND */
 420         ohci_writel(ohci, OHCI_HCR, &ohci->regs->cmdstatus);
 421         ohci_readl(ohci, &ohci->regs->cmdstatus);       /* flush the writes */
 422         udelay(10);
 423
 424         ohci_writel(ohci, ohci->fminterval, &ohci->regs->fminterval);
 425 }
 426
 427 /*-------------------------------------------------------------------------*
 428  * HC functions
 429  *-------------------------------------------------------------------------*/
 430
 431 /* init memory, and kick BIOS/SMM off */
 432
 433 static int ohci_init (struct ohci_hcd *ohci)
 434 {
 435         int ret;
 436         struct usb_hcd *hcd = ohci_to_hcd(ohci);
 437
 438         /* Accept arbitrarily long scatter-gather lists */
 439         hcd->self.sg_tablesize = ~0;
 440
 441         if (distrust_firmware)
 442                 ohci->flags |= OHCI_QUIRK_HUB_POWER;
 443
 444         ohci->rh_state = OHCI_RH_HALTED;
 445         ohci->regs = hcd->regs;
 446
 447         /* REVISIT this BIOS handshake is now moved into PCI "quirks", and
 448          * was never needed for most non-PCI systems ... remove the code?
 449          */
 450
 451 #ifndef IR_DISABLE
 452         /* SMM owns the HC?  not for long! */
 453         if (!no_handshake && ohci_readl (ohci,
 454                                         &ohci->regs->control) & OHCI_CTRL_IR) {
 455                 u32 temp;
 456
 457                 ohci_dbg (ohci, "USB HC TakeOver from BIOS/SMM\n");
 458
 459                 /* this timeout is arbitrary.  we make it long, so systems
 460                  * depending on usb keyboards may be usable even if the
 461                  * BIOS/SMM code seems pretty broken.
 462                  */
 463                 temp = 500;     /* arbitrary: five seconds */
 464
 465                 ohci_writel (ohci, OHCI_INTR_OC, &ohci->regs->intrenable);
 466                 ohci_writel (ohci, OHCI_OCR, &ohci->regs->cmdstatus);
 467                 while (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_IR) {
 468                         msleep (10);
 469                         if (--temp == 0) {
 470                                 ohci_err (ohci, "USB HC takeover failed!"
 471                                         "  (BIOS/SMM bug)\n");
 472                                 return -EBUSY;
 473                         }
 474                 }
 475                 ohci_usb_reset (ohci);
 476         }
 477 #endif
 478
 479         /* Disable HC interrupts */
 480         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 481
 482         /* flush the writes, and save key bits like RWC */
 483         if (ohci_readl (ohci, &ohci->regs->control) & OHCI_CTRL_RWC)
 484                 ohci->hc_control |= OHCI_CTRL_RWC;
 485
 486         /* Read the number of ports unless overridden */
 487         if (ohci->num_ports == 0)
 488                 ohci->num_ports = roothub_a(ohci) & RH_A_NDP;
 489
 490         if (ohci->hcca)
 491                 return 0;
 492
 493         ohci->hcca = dma_alloc_coherent (hcd->self.controller,
 494                         sizeof(*ohci->hcca), &ohci->hcca_dma, GFP_KERNEL);
 495         if (!ohci->hcca)
 496                 return -ENOMEM;
 497
 498         if ((ret = ohci_mem_init (ohci)) < 0)
 499                 ohci_stop (hcd);
 500         else {
 501                 create_debug_files (ohci);
 502         }
 503
 504         return ret;
 505 }
 506
 507 /*-------------------------------------------------------------------------*/
 508
 509 /* Start an OHCI controller, set the BUS operational
 510  * resets USB and controller
 511  * enable interrupts
 512  */
 513 static int ohci_run (struct ohci_hcd *ohci)
 514 {
 515         u32                     mask, val;
 516         int                     first = ohci->fminterval == 0;
 517         struct usb_hcd          *hcd = ohci_to_hcd(ohci);
 518
 519         ohci->rh_state = OHCI_RH_HALTED;
 520
 521         /* boot firmware should have set this up (5.1.1.3.1) */
 522         if (first) {
 523
 524                 val = ohci_readl (ohci, &ohci->regs->fminterval);
 525                 ohci->fminterval = val & 0x3fff;
 526                 if (ohci->fminterval != FI)
 527                         ohci_dbg (ohci, "fminterval delta %d\n",
 528                                 ohci->fminterval - FI);
 529                 ohci->fminterval |= FSMP (ohci->fminterval) << 16;
 530                 /* also: power/overcurrent flags in roothub.a */
 531         }
 532
 533         /* Reset USB nearly "by the book".  RemoteWakeupConnected has
 534          * to be checked in case boot firmware (BIOS/SMM/...) has set up
 535          * wakeup in a way the bus isn't aware of (e.g., legacy PCI PM).
 536          * If the bus glue detected wakeup capability then it should
 537          * already be enabled; if so we'll just enable it again.
 538          */
 539         if ((ohci->hc_control & OHCI_CTRL_RWC) != 0)
 540                 device_set_wakeup_capable(hcd->self.controller, 1);
 541
 542         switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 543         case OHCI_USB_OPER:
 544                 val = 0;
 545                 break;
 546         case OHCI_USB_SUSPEND:
 547         case OHCI_USB_RESUME:
 548                 ohci->hc_control &= OHCI_CTRL_RWC;
 549                 ohci->hc_control |= OHCI_USB_RESUME;
 550                 val = 10 /* msec wait */;
 551                 break;
 552         // case OHCI_USB_RESET:
 553         default:
 554                 ohci->hc_control &= OHCI_CTRL_RWC;
 555                 ohci->hc_control |= OHCI_USB_RESET;
 556                 val = 50 /* msec wait */;
 557                 break;
 558         }
 559         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 560         // flush the writes
 561         (void) ohci_readl (ohci, &ohci->regs->control);
 562         msleep(val);
 563
 564         memset (ohci->hcca, 0, sizeof (struct ohci_hcca));
 565
 566         /* 2msec timelimit here means no irqs/preempt */
 567         spin_lock_irq (&ohci->lock);
 568
 569 retry:
 570         /* HC Reset requires max 10 us delay */
 571         ohci_writel (ohci, OHCI_HCR,  &ohci->regs->cmdstatus);
 572         val = 30;       /* ... allow extra time */
 573         while ((ohci_readl (ohci, &ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
 574                 if (--val == 0) {
 575                         spin_unlock_irq (&ohci->lock);
 576                         ohci_err (ohci, "USB HC reset timed out!\n");
 577                         return -1;
 578                 }
 579                 udelay (1);
 580         }
 581
 582         /* now we're in the SUSPEND state ... must go OPERATIONAL
 583          * within 2msec else HC enters RESUME
 584          *
 585          * ... but some hardware won't init fmInterval "by the book"
 586          * (SiS, OPTi ...), so reset again instead.  SiS doesn't need
 587          * this if we write fmInterval after we're OPERATIONAL.
 588          * Unclear about ALi, ServerWorks, and others ... this could
 589          * easily be a longstanding bug in chip init on Linux.
 590          */
 591         if (ohci->flags & OHCI_QUIRK_INITRESET) {
 592                 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 593                 // flush those writes
 594                 (void) ohci_readl (ohci, &ohci->regs->control);
 595         }
 596
 597         /* Tell the controller where the control and bulk lists are
 598          * The lists are empty now. */
 599         ohci_writel (ohci, 0, &ohci->regs->ed_controlhead);
 600         ohci_writel (ohci, 0, &ohci->regs->ed_bulkhead);
 601
 602         /* a reset clears this */
 603         ohci_writel (ohci, (u32) ohci->hcca_dma, &ohci->regs->hcca);
 604
 605         periodic_reinit (ohci);
 606
 607         /* some OHCI implementations are finicky about how they init.
 608          * bogus values here mean not even enumeration could work.
 609          */
 610         if ((ohci_readl (ohci, &ohci->regs->fminterval) & 0x3fff0000) == 0
 611                         || !ohci_readl (ohci, &ohci->regs->periodicstart)) {
 612                 if (!(ohci->flags & OHCI_QUIRK_INITRESET)) {
 613                         ohci->flags |= OHCI_QUIRK_INITRESET;
 614                         ohci_dbg (ohci, "enabling initreset quirk\n");
 615                         goto retry;
 616                 }
 617                 spin_unlock_irq (&ohci->lock);
 618                 ohci_err (ohci, "init err (%08x %04x)\n",
 619                         ohci_readl (ohci, &ohci->regs->fminterval),
 620                         ohci_readl (ohci, &ohci->regs->periodicstart));
 621                 return -EOVERFLOW;
 622         }
 623
 624         /* use rhsc irqs after khubd is fully initialized */
 625         set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 626         hcd->uses_new_polling = 1;
 627
 628         /* start controller operations */
 629         ohci->hc_control &= OHCI_CTRL_RWC;
 630         ohci->hc_control |= OHCI_CONTROL_INIT | OHCI_USB_OPER;
 631         ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
 632         ohci->rh_state = OHCI_RH_RUNNING;
 633
 634         /* wake on ConnectStatusChange, matching external hubs */
 635         ohci_writel (ohci, RH_HS_DRWE, &ohci->regs->roothub.status);
 636
 637         /* Choose the interrupts we care about now, others later on demand */
 638         mask = OHCI_INTR_INIT;
 639         ohci_writel (ohci, ~0, &ohci->regs->intrstatus);
 640         ohci_writel (ohci, mask, &ohci->regs->intrenable);
 641
 642         /* handle root hub init quirks ... */
 643         val = roothub_a (ohci);
 644         val &= ~(RH_A_PSM | RH_A_OCPM);
 645         if (ohci->flags & OHCI_QUIRK_SUPERIO) {
 646                 /* NSC 87560 and maybe others */
 647                 val |= RH_A_NOCP;
 648                 val &= ~(RH_A_POTPGT | RH_A_NPS);
 649                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 650         } else if ((ohci->flags & OHCI_QUIRK_AMD756) ||
 651                         (ohci->flags & OHCI_QUIRK_HUB_POWER)) {
 652                 /* hub power always on; required for AMD-756 and some
 653                  * Mac platforms.  ganged overcurrent reporting, if any.
 654                  */
 655                 val |= RH_A_NPS;
 656                 ohci_writel (ohci, val, &ohci->regs->roothub.a);
 657         }
 658         ohci_writel (ohci, RH_HS_LPSC, &ohci->regs->roothub.status);
 659         ohci_writel (ohci, (val & RH_A_NPS) ? 0 : RH_B_PPCM,
 660                                                 &ohci->regs->roothub.b);
 661         // flush those writes
 662         (void) ohci_readl (ohci, &ohci->regs->control);
 663
 664         ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 665         spin_unlock_irq (&ohci->lock);
 666
 667         // POTPGT delay is bits 24-31, in 2 ms units.
 668         mdelay ((val >> 23) & 0x1fe);
 669
 670         ohci_dump(ohci);
 671
 672         return 0;
 673 }
 674
 675 /* ohci_setup routine for generic controller initialization */
 676
 677 int ohci_setup(struct usb_hcd *hcd)
 678 {
 679         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 680
 681         ohci_hcd_init(ohci);
 682
 683         return ohci_init(ohci);
 684 }
 685 EXPORT_SYMBOL_GPL(ohci_setup);
 686
 687 /* ohci_start routine for generic controller start of all OHCI bus glue */
 688 static int ohci_start(struct usb_hcd *hcd)
 689 {
 690         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 691         int     ret;
 692
 693         ret = ohci_run(ohci);
 694         if (ret < 0) {
 695                 ohci_err(ohci, "can't start\n");
 696                 ohci_stop(hcd);
 697         }
 698         return ret;
 699 }
 700
 701 /*-------------------------------------------------------------------------*/
 702
 703 /* an interrupt happens */
 704
 705 static irqreturn_t ohci_irq (struct usb_hcd *hcd)
 706 {
 707         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 708         struct ohci_regs __iomem *regs = ohci->regs;
 709         int                     ints;
 710
 711         /* Read interrupt status (and flush pending writes).  We ignore the
 712          * optimization of checking the LSB of hcca->done_head; it doesn't
 713          * work on all systems (edge triggering for OHCI can be a factor).
 714          */
 715         ints = ohci_readl(ohci, &regs->intrstatus);
 716
 717         /* Check for an all 1's result which is a typical consequence
 718          * of dead, unclocked, or unplugged (CardBus...) devices
 719          */
 720         if (ints == ~(u32)0) {
 721                 ohci->rh_state = OHCI_RH_HALTED;
 722                 ohci_dbg (ohci, "device removed!\n");
 723                 usb_hc_died(hcd);
 724                 return IRQ_HANDLED;
 725         }
 726
 727         /* We only care about interrupts that are enabled */
 728         ints &= ohci_readl(ohci, &regs->intrenable);
 729
 730         /* interrupt for some other device? */
 731         if (ints == 0 || unlikely(ohci->rh_state == OHCI_RH_HALTED))
 732                 return IRQ_NOTMINE;
 733
 734         if (ints & OHCI_INTR_UE) {
 735                 // e.g. due to PCI Master/Target Abort
 736                 if (quirk_nec(ohci)) {
 737                         /* Workaround for a silicon bug in some NEC chips used
 738                          * in Apple's PowerBooks. Adapted from Darwin code.
 739                          */
 740                         ohci_err (ohci, "OHCI Unrecoverable Error, scheduling NEC chip restart\n");
 741
 742                         ohci_writel (ohci, OHCI_INTR_UE, &regs->intrdisable);
 743
 744                         schedule_work (&ohci->nec_work);
 745                 } else {
 746                         ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
 747                         ohci->rh_state = OHCI_RH_HALTED;
 748                         usb_hc_died(hcd);
 749                 }
 750
 751                 ohci_dump(ohci);
 752                 ohci_usb_reset (ohci);
 753         }
 754
 755         if (ints & OHCI_INTR_RHSC) {
 756                 ohci_dbg(ohci, "rhsc\n");
 757                 ohci->next_statechange = jiffies + STATECHANGE_DELAY;
 758                 ohci_writel(ohci, OHCI_INTR_RD | OHCI_INTR_RHSC,
 759                                 &regs->intrstatus);
 760
 761                 /* NOTE: Vendors didn't always make the same implementation
 762                  * choices for RHSC.  Many followed the spec; RHSC triggers
 763                  * on an edge, like setting and maybe clearing a port status
 764                  * change bit.  With others it's level-triggered, active
 765                  * until khubd clears all the port status change bits.  We'll
 766                  * always disable it here and rely on polling until khubd
 767                  * re-enables it.
 768                  */
 769                 ohci_writel(ohci, OHCI_INTR_RHSC, &regs->intrdisable);
 770                 usb_hcd_poll_rh_status(hcd);
 771         }
 772
 773         /* For connect and disconnect events, we expect the controller
 774          * to turn on RHSC along with RD.  But for remote wakeup events
 775          * this might not happen.
 776          */
 777         else if (ints & OHCI_INTR_RD) {
 778                 ohci_dbg(ohci, "resume detect\n");
 779                 ohci_writel(ohci, OHCI_INTR_RD, &regs->intrstatus);
 780                 set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
 781                 if (ohci->autostop) {
 782                         spin_lock (&ohci->lock);
 783                         ohci_rh_resume (ohci);
 784                         spin_unlock (&ohci->lock);
 785                 } else
 786                         usb_hcd_resume_root_hub(hcd);
 787         }
 788
 789         if (ints & OHCI_INTR_WDH) {
 790                 spin_lock (&ohci->lock);
 791                 dl_done_list (ohci);
 792                 spin_unlock (&ohci->lock);
 793         }
 794
 795         /* could track INTR_SO to reduce available PCI/... bandwidth */
 796
 797         /* handle any pending URB/ED unlinks, leaving INTR_SF enabled
 798          * when there's still unlinking to be done (next frame).
 799          */
 800         spin_lock (&ohci->lock);
 801         if (ohci->ed_rm_list)
 802                 finish_unlinks (ohci, ohci_frame_no(ohci));
 803         if ((ints & OHCI_INTR_SF) != 0 && !ohci->ed_rm_list
 804                         && ohci->rh_state == OHCI_RH_RUNNING)
 805                 ohci_writel (ohci, OHCI_INTR_SF, &regs->intrdisable);
 806         spin_unlock (&ohci->lock);
 807
 808         if (ohci->rh_state == OHCI_RH_RUNNING) {
 809                 ohci_writel (ohci, ints, &regs->intrstatus);
 810                 ohci_writel (ohci, OHCI_INTR_MIE, &regs->intrenable);
 811                 // flush those writes
 812                 (void) ohci_readl (ohci, &ohci->regs->control);
 813         }
 814
 815         return IRQ_HANDLED;
 816 }
 817
 818 /*-------------------------------------------------------------------------*/
 819
 820 static void ohci_stop (struct usb_hcd *hcd)
 821 {
 822         struct ohci_hcd         *ohci = hcd_to_ohci (hcd);
 823
 824         ohci_dump(ohci);
 825
 826         if (quirk_nec(ohci))
 827                 flush_work(&ohci->nec_work);
 828
 829         ohci_writel (ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 830         ohci_usb_reset(ohci);
 831         free_irq(hcd->irq, hcd);
 832         hcd->irq = 0;
 833
 834         if (quirk_amdiso(ohci))
 835                 usb_amd_dev_put();
 836
 837         remove_debug_files (ohci);
 838         ohci_mem_cleanup (ohci);
 839         if (ohci->hcca) {
 840                 dma_free_coherent (hcd->self.controller,
 841                                 sizeof *ohci->hcca,
 842                                 ohci->hcca, ohci->hcca_dma);
 843                 ohci->hcca = NULL;
 844                 ohci->hcca_dma = 0;
 845         }
 846 }
 847
 848 /*-------------------------------------------------------------------------*/
 849
 850 #if defined(CONFIG_PM) || defined(CONFIG_PCI)
 851
 852 /* must not be called from interrupt context */
 853 int ohci_restart(struct ohci_hcd *ohci)
 854 {
 855         int temp;
 856         int i;
 857         struct urb_priv *priv;
 858
 859         ohci_init(ohci);
 860         spin_lock_irq(&ohci->lock);
 861         ohci->rh_state = OHCI_RH_HALTED;
 862
 863         /* Recycle any "live" eds/tds (and urbs). */
 864         if (!list_empty (&ohci->pending))
 865                 ohci_dbg(ohci, "abort schedule...\n");
 866         list_for_each_entry (priv, &ohci->pending, pending) {
 867                 struct urb      *urb = priv->td[0]->urb;
 868                 struct ed       *ed = priv->ed;
 869
 870                 switch (ed->state) {
 871                 case ED_OPER:
 872                         ed->state = ED_UNLINK;
 873                         ed->hwINFO |= cpu_to_hc32(ohci, ED_DEQUEUE);
 874                         ed_deschedule (ohci, ed);
 875
 876                         ed->ed_next = ohci->ed_rm_list;
 877                         ed->ed_prev = NULL;
 878                         ohci->ed_rm_list = ed;
 879                         /* FALLTHROUGH */
 880                 case ED_UNLINK:
 881                         break;
 882                 default:
 883                         ohci_dbg(ohci, "bogus ed %p state %d\n",
 884                                         ed, ed->state);
 885                 }
 886
 887                 if (!urb->unlinked)
 888                         urb->unlinked = -ESHUTDOWN;
 889         }
 890         finish_unlinks (ohci, 0);
 891         spin_unlock_irq(&ohci->lock);
 892
 893         /* paranoia, in case that didn't work: */
 894
 895         /* empty the interrupt branches */
 896         for (i = 0; i < NUM_INTS; i++) ohci->load [i] = 0;
 897         for (i = 0; i < NUM_INTS; i++) ohci->hcca->int_table [i] = 0;
 898
 899         /* no EDs to remove */
 900         ohci->ed_rm_list = NULL;
 901
 902         /* empty control and bulk lists */
 903         ohci->ed_controltail = NULL;
 904         ohci->ed_bulktail    = NULL;
 905
 906         if ((temp = ohci_run (ohci)) < 0) {
 907                 ohci_err (ohci, "can't restart, %d\n", temp);
 908                 return temp;
 909         }
 910         ohci_dbg(ohci, "restart complete\n");
 911         return 0;
 912 }
 913 EXPORT_SYMBOL_GPL(ohci_restart);
 914
 915 #endif
 916
 917 #ifdef CONFIG_PM
 918
 919 int ohci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 920 {
 921         struct ohci_hcd *ohci = hcd_to_ohci (hcd);
 922         unsigned long   flags;
 923         int             rc = 0;
 924
 925         /* Disable irq emission and mark HW unaccessible. Use
 926          * the spinlock to properly synchronize with possible pending
 927          * RH suspend or resume activity.
 928          */
 929         spin_lock_irqsave (&ohci->lock, flags);
 930         ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrdisable);
 931         (void)ohci_readl(ohci, &ohci->regs->intrdisable);
 932
 933         clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 934         spin_unlock_irqrestore (&ohci->lock, flags);
 935
 936         synchronize_irq(hcd->irq);
 937
 938         if (do_wakeup && HCD_WAKEUP_PENDING(hcd)) {
 939                 ohci_resume(hcd, false);
 940                 rc = -EBUSY;
 941         }
 942         return rc;
 943 }
 944 EXPORT_SYMBOL_GPL(ohci_suspend);
 945
 946
 947 int ohci_resume(struct usb_hcd *hcd, bool hibernated)
 948 {
 949         struct ohci_hcd         *ohci = hcd_to_ohci(hcd);
 950         int                     port;
 951         bool                    need_reinit = false;
 952
 953         set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 954
 955         /* Make sure resume from hibernation re-enumerates everything */
 956         if (hibernated)
 957                 ohci_usb_reset(ohci);
 958
 959         /* See if the controller is already running or has been reset */
 960         ohci->hc_control = ohci_readl(ohci, &ohci->regs->control);
 961         if (ohci->hc_control & (OHCI_CTRL_IR | OHCI_SCHED_ENABLES)) {
 962                 need_reinit = true;
 963         } else {
 964                 switch (ohci->hc_control & OHCI_CTRL_HCFS) {
 965                 case OHCI_USB_OPER:
 966                 case OHCI_USB_RESET:
 967                         need_reinit = true;
 968                 }
 969         }
 970
 971         /* If needed, reinitialize and suspend the root hub */
 972         if (need_reinit) {
 973                 spin_lock_irq(&ohci->lock);
 974                 ohci_rh_resume(ohci);
 975                 ohci_rh_suspend(ohci, 0);
 976                 spin_unlock_irq(&ohci->lock);
 977         }
 978
 979         /* Normally just turn on port power and enable interrupts */
 980         else {
 981                 ohci_dbg(ohci, "powerup ports\n");
 982                 for (port = 0; port < ohci->num_ports; port++)
 983                         ohci_writel(ohci, RH_PS_PPS,
 984                                         &ohci->regs->roothub.portstatus[port]);
 985
 986                 ohci_writel(ohci, OHCI_INTR_MIE, &ohci->regs->intrenable);
 987                 ohci_readl(ohci, &ohci->regs->intrenable);
 988                 msleep(20);
 989         }
 990
 991         usb_hcd_resume_root_hub(hcd);
 992
 993         return 0;
 994 }
 995 EXPORT_SYMBOL_GPL(ohci_resume);
 996
 997 #endif
 998
 999 /*-------------------------------------------------------------------------*/
1000
1001 /*
1002  * Generic structure: This gets copied for platform drivers so that
1003  * individual entries can be overridden as needed.
1004  */
1005
1006 static const struct hc_driver ohci_hc_driver = {
1007         .description =          hcd_name,
1008         .product_desc =         "OHCI Host Controller",
1009         .hcd_priv_size =        sizeof(struct ohci_hcd),
1010
1011         /*
1012          * generic hardware linkage
1013         */
1014         .irq =                  ohci_irq,
1015         .flags =                HCD_MEMORY | HCD_USB11,
1016
1017         /*
1018         * basic lifecycle operations
1019         */
1020         .reset =                ohci_setup,
1021         .start =                ohci_start,
1022         .stop =                 ohci_stop,
1023         .shutdown =             ohci_shutdown,
1024
1025         /*
1026          * managing i/o requests and associated device resources
1027         */
1028         .urb_enqueue =          ohci_urb_enqueue,
1029         .urb_dequeue =          ohci_urb_dequeue,
1030         .endpoint_disable =     ohci_endpoint_disable,
1031
1032         /*
1033         * scheduling support
1034         */
1035         .get_frame_number =     ohci_get_frame,
1036
1037         /*
1038         * root hub support
1039         */
1040         .hub_status_data =      ohci_hub_status_data,
1041         .hub_control =          ohci_hub_control,
1042 #ifdef CONFIG_PM
1043         .bus_suspend =          ohci_bus_suspend,
1044         .bus_resume =           ohci_bus_resume,
1045 #endif
1046         .start_port_reset =     ohci_start_port_reset,
1047 };
1048
1049 void ohci_init_driver(struct hc_driver *drv,
1050                 const struct ohci_driver_overrides *over)
1051 {
1052         /* Copy the generic table to drv and then apply the overrides */
1053         *drv = ohci_hc_driver;
1054
1055         if (over) {
1056                 drv->product_desc = over->product_desc;
1057                 drv->hcd_priv_size += over->extra_priv_size;
1058                 if (over->reset)
1059                         drv->reset = over->reset;
1060         }
1061 }
1062 EXPORT_SYMBOL_GPL(ohci_init_driver);
1063
1064 /*-------------------------------------------------------------------------*/
1065
1066 MODULE_AUTHOR (DRIVER_AUTHOR);
1067 MODULE_DESCRIPTION(DRIVER_DESC);
1068 MODULE_LICENSE ("GPL");
1069
1070 #if defined(CONFIG_ARCH_SA1100) && defined(CONFIG_SA1111)
1071 #include "ohci-sa1111.c"
1072 #define SA1111_DRIVER           ohci_hcd_sa1111_driver
1073 #endif
1074
1075 #ifdef CONFIG_USB_OHCI_HCD_DAVINCI
1076 #include "ohci-da8xx.c"
1077 #define DAVINCI_PLATFORM_DRIVER ohci_hcd_da8xx_driver
1078 #endif
1079
1080 #ifdef CONFIG_USB_OHCI_HCD_PPC_OF
1081 #include "ohci-ppc-of.c"
1082 #define OF_PLATFORM_DRIVER      ohci_hcd_ppc_of_driver
1083 #endif
1084
1085 #ifdef CONFIG_PPC_PS3
1086 #include "ohci-ps3.c"
1087 #define PS3_SYSTEM_BUS_DRIVER   ps3_ohci_driver
1088 #endif
1089
1090 #ifdef CONFIG_MFD_SM501
1091 #include "ohci-sm501.c"
1092 #define SM501_OHCI_DRIVER       ohci_hcd_sm501_driver
1093 #endif
1094
1095 #ifdef CONFIG_MFD_TC6393XB
1096 #include "ohci-tmio.c"
1097 #define TMIO_OHCI_DRIVER        ohci_hcd_tmio_driver
1098 #endif
1099
1100 #ifdef CONFIG_MACH_JZ4740
1101 #include "ohci-jz4740.c"
1102 #define PLATFORM_DRIVER ohci_hcd_jz4740_driver
1103 #endif
1104
1105 #ifdef CONFIG_USB_OCTEON_OHCI
1106 #include "ohci-octeon.c"
1107 #define PLATFORM_DRIVER         ohci_octeon_driver
1108 #endif
1109
1110 #ifdef CONFIG_TILE_USB
1111 #include "ohci-tilegx.c"
1112 #define PLATFORM_DRIVER         ohci_hcd_tilegx_driver
1113 #endif
1114
1115 static int __init ohci_hcd_mod_init(void)
1116 {
1117         int retval = 0;
1118
1119         if (usb_disabled())
1120                 return -ENODEV;
1121
1122         printk(KERN_INFO "%s: " DRIVER_DESC "\n", hcd_name);
1123         pr_debug ("%s: block sizes: ed %Zd td %Zd\n", hcd_name,
1124                 sizeof (struct ed), sizeof (struct td));
1125         set_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1126
1127         ohci_debug_root = debugfs_create_dir("ohci", usb_debug_root);
1128         if (!ohci_debug_root) {
1129                 retval = -ENOENT;
1130                 goto error_debug;
1131         }
1132
1133 #ifdef PS3_SYSTEM_BUS_DRIVER
1134         retval = ps3_ohci_driver_register(&PS3_SYSTEM_BUS_DRIVER);
1135         if (retval < 0)
1136                 goto error_ps3;
1137 #endif
1138
1139 #ifdef PLATFORM_DRIVER
1140         retval = platform_driver_register(&PLATFORM_DRIVER);
1141         if (retval < 0)
1142                 goto error_platform;
1143 #endif
1144
1145 #ifdef OF_PLATFORM_DRIVER
1146         retval = platform_driver_register(&OF_PLATFORM_DRIVER);
1147         if (retval < 0)
1148                 goto error_of_platform;
1149 #endif
1150
1151 #ifdef SA1111_DRIVER
1152         retval = sa1111_driver_register(&SA1111_DRIVER);
1153         if (retval < 0)
1154                 goto error_sa1111;
1155 #endif
1156
1157 #ifdef SM501_OHCI_DRIVER
1158         retval = platform_driver_register(&SM501_OHCI_DRIVER);
1159         if (retval < 0)
1160                 goto error_sm501;
1161 #endif
1162
1163 #ifdef TMIO_OHCI_DRIVER
1164         retval = platform_driver_register(&TMIO_OHCI_DRIVER);
1165         if (retval < 0)
1166                 goto error_tmio;
1167 #endif
1168
1169 #ifdef DAVINCI_PLATFORM_DRIVER
1170         retval = platform_driver_register(&DAVINCI_PLATFORM_DRIVER);
1171         if (retval < 0)
1172                 goto error_davinci;
1173 #endif
1174
1175         return retval;
1176
1177         /* Error path */
1178 #ifdef DAVINCI_PLATFORM_DRIVER
1179         platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1180  error_davinci:
1181 #endif
1182 #ifdef TMIO_OHCI_DRIVER
1183         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1184  error_tmio:
1185 #endif
1186 #ifdef SM501_OHCI_DRIVER
1187         platform_driver_unregister(&SM501_OHCI_DRIVER);
1188  error_sm501:
1189 #endif
1190 #ifdef SA1111_DRIVER
1191         sa1111_driver_unregister(&SA1111_DRIVER);
1192  error_sa1111:
1193 #endif
1194 #ifdef OF_PLATFORM_DRIVER
1195         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1196  error_of_platform:
1197 #endif
1198 #ifdef PLATFORM_DRIVER
1199         platform_driver_unregister(&PLATFORM_DRIVER);
1200  error_platform:
1201 #endif
1202 #ifdef PS3_SYSTEM_BUS_DRIVER
1203         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1204  error_ps3:
1205 #endif
1206         debugfs_remove(ohci_debug_root);
1207         ohci_debug_root = NULL;
1208  error_debug:
1209
1210         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1211         return retval;
1212 }
1213 module_init(ohci_hcd_mod_init);
1214
1215 static void __exit ohci_hcd_mod_exit(void)
1216 {
1217 #ifdef DAVINCI_PLATFORM_DRIVER
1218         platform_driver_unregister(&DAVINCI_PLATFORM_DRIVER);
1219 #endif
1220 #ifdef TMIO_OHCI_DRIVER
1221         platform_driver_unregister(&TMIO_OHCI_DRIVER);
1222 #endif
1223 #ifdef SM501_OHCI_DRIVER
1224         platform_driver_unregister(&SM501_OHCI_DRIVER);
1225 #endif
1226 #ifdef SA1111_DRIVER
1227         sa1111_driver_unregister(&SA1111_DRIVER);
1228 #endif
1229 #ifdef OF_PLATFORM_DRIVER
1230         platform_driver_unregister(&OF_PLATFORM_DRIVER);
1231 #endif
1232 #ifdef PLATFORM_DRIVER
1233         platform_driver_unregister(&PLATFORM_DRIVER);
1234 #endif
1235 #ifdef PS3_SYSTEM_BUS_DRIVER
1236         ps3_ohci_driver_unregister(&PS3_SYSTEM_BUS_DRIVER);
1237 #endif
1238         debugfs_remove(ohci_debug_root);
1239         clear_bit(USB_OHCI_LOADED, &usb_hcds_loaded);
1240 }
1241 module_exit(ohci_hcd_mod_exit);
1242