2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev;
31 /* Scan and identify a NAND device */
32 int nand_scan(struct mtd_info *mtd, int max_chips);
34 * Separate phases of nand_scan(), allowing board driver to intervene
35 * and override command or ECC setup according to flash type.
37 int nand_scan_ident(struct mtd_info *mtd, int max_chips,
38 struct nand_flash_dev *table);
39 int nand_scan_tail(struct mtd_info *mtd);
41 /* Unregister the MTD device and free resources held by the NAND device */
42 void nand_release(struct mtd_info *mtd);
44 /* Internal helper for board drivers which need to override command function */
45 void nand_wait_ready(struct mtd_info *mtd);
47 /* locks all blocks present in the device */
48 int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50 /* unlocks specified locked blocks */
51 int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
53 /* The maximum number of NAND chips in an array */
54 #define NAND_MAX_CHIPS 8
57 * Constants for hardware specific CLE/ALE/NCE function
59 * These are bits which can be or'ed to set/clear multiple
62 /* Select the chip by setting nCE to low */
64 /* Select the command latch by setting CLE to high */
66 /* Select the address latch by setting ALE to high */
69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71 #define NAND_CTRL_CHANGE 0x80
74 * Standard NAND flash commands
76 #define NAND_CMD_READ0 0
77 #define NAND_CMD_READ1 1
78 #define NAND_CMD_RNDOUT 5
79 #define NAND_CMD_PAGEPROG 0x10
80 #define NAND_CMD_READOOB 0x50
81 #define NAND_CMD_ERASE1 0x60
82 #define NAND_CMD_STATUS 0x70
83 #define NAND_CMD_SEQIN 0x80
84 #define NAND_CMD_RNDIN 0x85
85 #define NAND_CMD_READID 0x90
86 #define NAND_CMD_ERASE2 0xd0
87 #define NAND_CMD_PARAM 0xec
88 #define NAND_CMD_GET_FEATURES 0xee
89 #define NAND_CMD_SET_FEATURES 0xef
90 #define NAND_CMD_RESET 0xff
92 #define NAND_CMD_LOCK 0x2a
93 #define NAND_CMD_UNLOCK1 0x23
94 #define NAND_CMD_UNLOCK2 0x24
96 /* Extended commands for large page devices */
97 #define NAND_CMD_READSTART 0x30
98 #define NAND_CMD_RNDOUTSTART 0xE0
99 #define NAND_CMD_CACHEDPROG 0x15
101 #define NAND_CMD_NONE -1
104 #define NAND_STATUS_FAIL 0x01
105 #define NAND_STATUS_FAIL_N1 0x02
106 #define NAND_STATUS_TRUE_READY 0x20
107 #define NAND_STATUS_READY 0x40
108 #define NAND_STATUS_WP 0x80
111 * Constants for ECC_MODES
117 NAND_ECC_HW_SYNDROME,
118 NAND_ECC_HW_OOB_FIRST,
129 * Constants for Hardware ECC
131 /* Reset Hardware ECC for read */
132 #define NAND_ECC_READ 0
133 /* Reset Hardware ECC for write */
134 #define NAND_ECC_WRITE 1
135 /* Enable Hardware ECC before syndrome is read back from flash */
136 #define NAND_ECC_READSYN 2
139 * Enable generic NAND 'page erased' check. This check is only done when
140 * ecc.correct() returns -EBADMSG.
141 * Set this flag if your implementation does not fix bitflips in erased
142 * pages and you want to rely on the default implementation.
144 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
145 #define NAND_ECC_MAXIMIZE BIT(1)
147 * If your controller already sends the required NAND commands when
148 * reading or writing a page, then the framework is not supposed to
149 * send READ0 and SEQIN/PAGEPROG respectively.
151 #define NAND_ECC_CUSTOM_PAGE_ACCESS BIT(2)
153 /* Bit mask for flags passed to do_nand_read_ecc */
154 #define NAND_GET_DEVICE 0x80
158 * Option constants for bizarre disfunctionality and real
161 /* Buswidth is 16 bit */
162 #define NAND_BUSWIDTH_16 0x00000002
163 /* Chip has cache program function */
164 #define NAND_CACHEPRG 0x00000008
166 * Chip requires ready check on read (for auto-incremented sequential read).
167 * True only for small page devices; large page devices do not support
170 #define NAND_NEED_READRDY 0x00000100
172 /* Chip does not allow subpage writes */
173 #define NAND_NO_SUBPAGE_WRITE 0x00000200
175 /* Device is one of 'new' xD cards that expose fake nand command set */
176 #define NAND_BROKEN_XD 0x00000400
178 /* Device behaves just like nand, but is readonly */
179 #define NAND_ROM 0x00000800
181 /* Device supports subpage reads */
182 #define NAND_SUBPAGE_READ 0x00001000
185 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
188 #define NAND_NEED_SCRAMBLING 0x00002000
190 /* Options valid for Samsung large page devices */
191 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
193 /* Macros to identify the above */
194 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
195 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
196 #define NAND_HAS_SUBPAGE_WRITE(chip) !((chip)->options & NAND_NO_SUBPAGE_WRITE)
198 /* Non chip related options */
199 /* This option skips the bbt scan during initialization. */
200 #define NAND_SKIP_BBTSCAN 0x00010000
202 * This option is defined if the board driver allocates its own buffers
203 * (e.g. because it needs them DMA-coherent).
205 #define NAND_OWN_BUFFERS 0x00020000
206 /* Chip may not exist, so silence any errors in scan */
207 #define NAND_SCAN_SILENT_NODEV 0x00040000
209 * Autodetect nand buswidth with readid/onfi.
210 * This suppose the driver will configure the hardware in 8 bits mode
211 * when calling nand_scan_ident, and update its configuration
212 * before calling nand_scan_tail.
214 #define NAND_BUSWIDTH_AUTO 0x00080000
216 * This option could be defined by controller drivers to protect against
217 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
219 #define NAND_USE_BOUNCE_BUFFER 0x00100000
222 * In case your controller is implementing ->cmd_ctrl() and is relying on the
223 * default ->cmdfunc() implementation, you may want to let the core handle the
224 * tCCS delay which is required when a column change (RNDIN or RNDOUT) is
226 * If your controller already takes care of this delay, you don't need to set
229 #define NAND_WAIT_TCCS 0x00200000
231 /* Options set by nand scan */
232 /* Nand scan has allocated controller struct */
233 #define NAND_CONTROLLER_ALLOC 0x80000000
235 /* Cell info constants */
236 #define NAND_CI_CHIPNR_MSK 0x03
237 #define NAND_CI_CELLTYPE_MSK 0x0C
238 #define NAND_CI_CELLTYPE_SHIFT 2
244 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
245 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
247 /* ONFI timing mode, used in both asynchronous and synchronous mode */
248 #define ONFI_TIMING_MODE_0 (1 << 0)
249 #define ONFI_TIMING_MODE_1 (1 << 1)
250 #define ONFI_TIMING_MODE_2 (1 << 2)
251 #define ONFI_TIMING_MODE_3 (1 << 3)
252 #define ONFI_TIMING_MODE_4 (1 << 4)
253 #define ONFI_TIMING_MODE_5 (1 << 5)
254 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
256 /* ONFI feature address */
257 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
259 /* Vendor-specific feature address (Micron) */
260 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
261 #define ONFI_FEATURE_ON_DIE_ECC 0x90
262 #define ONFI_FEATURE_ON_DIE_ECC_EN BIT(3)
264 /* ONFI subfeature parameters length */
265 #define ONFI_SUBFEATURE_PARAM_LEN 4
267 /* ONFI optional commands SET/GET FEATURES supported? */
268 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
270 struct nand_onfi_params {
271 /* rev info and features block */
272 /* 'O' 'N' 'F' 'I' */
278 __le16 ext_param_page_length; /* since ONFI 2.1 */
279 u8 num_of_param_pages; /* since ONFI 2.1 */
282 /* manufacturer information block */
283 char manufacturer[12];
289 /* memory organization block */
290 __le32 byte_per_page;
291 __le16 spare_bytes_per_page;
292 __le32 data_bytes_per_ppage;
293 __le16 spare_bytes_per_ppage;
294 __le32 pages_per_block;
295 __le32 blocks_per_lun;
300 __le16 block_endurance;
301 u8 guaranteed_good_blocks;
302 __le16 guaranteed_block_endurance;
303 u8 programs_per_page;
310 /* electrical parameter block */
311 u8 io_pin_capacitance_max;
312 __le16 async_timing_mode;
313 __le16 program_cache_timing_mode;
318 __le16 src_sync_timing_mode;
319 u8 src_ssync_features;
320 __le16 clk_pin_capacitance_typ;
321 __le16 io_pin_capacitance_typ;
322 __le16 input_pin_capacitance_typ;
323 u8 input_pin_capacitance_max;
324 u8 driver_strength_support;
330 __le16 vendor_revision;
336 #define ONFI_CRC_BASE 0x4F4E
338 /* Extended ECC information Block Definition (since ONFI 2.1) */
339 struct onfi_ext_ecc_info {
343 __le16 block_endurance;
347 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
348 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
349 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
350 struct onfi_ext_section {
355 #define ONFI_EXT_SECTION_MAX 8
357 /* Extended Parameter Page Definition (since ONFI 2.1) */
358 struct onfi_ext_param_page {
360 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
362 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
365 * The actual size of the Extended Parameter Page is in
366 * @ext_param_page_length of nand_onfi_params{}.
367 * The following are the variable length sections.
368 * So we do not add any fields below. Please see the ONFI spec.
372 struct jedec_ecc_info {
376 __le16 block_endurance;
381 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
383 struct nand_jedec_params {
384 /* rev info and features block */
385 /* 'J' 'E' 'S' 'D' */
391 u8 num_of_param_pages;
394 /* manufacturer information block */
395 char manufacturer[12];
400 /* memory organization block */
401 __le32 byte_per_page;
402 __le16 spare_bytes_per_page;
404 __le32 pages_per_block;
405 __le32 blocks_per_lun;
409 u8 programs_per_page;
411 u8 multi_plane_op_attr;
414 /* electrical parameter block */
415 __le16 async_sdr_speed_grade;
416 __le16 toggle_ddr_speed_grade;
417 __le16 sync_ddr_speed_grade;
418 u8 async_sdr_features;
419 u8 toggle_ddr_features;
420 u8 sync_ddr_features;
424 __le16 t_r_multi_plane;
426 __le16 io_pin_capacitance_typ;
427 __le16 input_pin_capacitance_typ;
428 __le16 clk_pin_capacitance_typ;
429 u8 driver_strength_support;
433 /* ECC and endurance block */
434 u8 guaranteed_good_blocks;
435 __le16 guaranteed_block_endurance;
436 struct jedec_ecc_info ecc_info[4];
443 __le16 vendor_rev_num;
446 /* CRC for Parameter Page */
451 * struct nand_id - NAND id structure
452 * @data: buffer containing the id bytes. Currently 8 bytes large, but can
453 * be extended if required.
462 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
463 * @lock: protection lock
464 * @active: the mtd device which holds the controller currently
465 * @wq: wait queue to sleep on if a NAND operation is in
466 * progress used instead of the per chip wait queue
467 * when a hw controller is available.
469 struct nand_hw_control {
471 struct nand_chip *active;
472 wait_queue_head_t wq;
475 static inline void nand_hw_control_init(struct nand_hw_control *nfc)
478 spin_lock_init(&nfc->lock);
479 init_waitqueue_head(&nfc->wq);
483 * struct nand_ecc_ctrl - Control structure for ECC
485 * @algo: ECC algorithm
486 * @steps: number of ECC steps per page
487 * @size: data bytes per ECC step
488 * @bytes: ECC bytes per step
489 * @strength: max number of correctible bits per ECC step
490 * @total: total number of ECC bytes per page
491 * @prepad: padding information for syndrome based ECC generators
492 * @postpad: padding information for syndrome based ECC generators
493 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
494 * @priv: pointer to private ECC control data
495 * @hwctl: function to control hardware ECC generator. Must only
496 * be provided if an hardware ECC is available
497 * @calculate: function for ECC calculation or readback from ECC hardware
498 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
499 * Should return a positive number representing the number of
500 * corrected bitflips, -EBADMSG if the number of bitflips exceed
501 * ECC strength, or any other error code if the error is not
502 * directly related to correction.
503 * If -EBADMSG is returned the input buffers should be left
505 * @read_page_raw: function to read a raw page without ECC. This function
506 * should hide the specific layout used by the ECC
507 * controller and always return contiguous in-band and
508 * out-of-band data even if they're not stored
509 * contiguously on the NAND chip (e.g.
510 * NAND_ECC_HW_SYNDROME interleaves in-band and
512 * @write_page_raw: function to write a raw page without ECC. This function
513 * should hide the specific layout used by the ECC
514 * controller and consider the passed data as contiguous
515 * in-band and out-of-band data. ECC controller is
516 * responsible for doing the appropriate transformations
517 * to adapt to its specific layout (e.g.
518 * NAND_ECC_HW_SYNDROME interleaves in-band and
520 * @read_page: function to read a page according to the ECC generator
521 * requirements; returns maximum number of bitflips corrected in
522 * any single ECC step, -EIO hw error
523 * @read_subpage: function to read parts of the page covered by ECC;
524 * returns same as read_page()
525 * @write_subpage: function to write parts of the page covered by ECC.
526 * @write_page: function to write a page according to the ECC generator
528 * @write_oob_raw: function to write chip OOB data without ECC
529 * @read_oob_raw: function to read chip OOB data without ECC
530 * @read_oob: function to read chip OOB data
531 * @write_oob: function to write chip OOB data
533 struct nand_ecc_ctrl {
534 nand_ecc_modes_t mode;
535 enum nand_ecc_algo algo;
543 unsigned int options;
545 void (*hwctl)(struct mtd_info *mtd, int mode);
546 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
548 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
550 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
551 uint8_t *buf, int oob_required, int page);
552 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
553 const uint8_t *buf, int oob_required, int page);
554 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
555 uint8_t *buf, int oob_required, int page);
556 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
557 uint32_t offs, uint32_t len, uint8_t *buf, int page);
558 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
559 uint32_t offset, uint32_t data_len,
560 const uint8_t *data_buf, int oob_required, int page);
561 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
562 const uint8_t *buf, int oob_required, int page);
563 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
565 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
567 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
568 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
572 static inline int nand_standard_page_accessors(struct nand_ecc_ctrl *ecc)
574 return !(ecc->options & NAND_ECC_CUSTOM_PAGE_ACCESS);
578 * struct nand_buffers - buffer structure for read/write
579 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
580 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
581 * @databuf: buffer pointer for data, size is (page size + oobsize).
583 * Do not change the order of buffers. databuf and oobrbuf must be in
586 struct nand_buffers {
593 * struct nand_sdr_timings - SDR NAND chip timings
595 * This struct defines the timing requirements of a SDR NAND chip.
596 * These information can be found in every NAND datasheets and the timings
597 * meaning are described in the ONFI specifications:
598 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
601 * All these timings are expressed in picoseconds.
603 * @tBERS_max: Block erase time
604 * @tCCS_min: Change column setup time
605 * @tPROG_max: Page program time
606 * @tR_max: Page read time
607 * @tALH_min: ALE hold time
608 * @tADL_min: ALE to data loading time
609 * @tALS_min: ALE setup time
610 * @tAR_min: ALE to RE# delay
611 * @tCEA_max: CE# access time
612 * @tCEH_min: CE# high hold time
613 * @tCH_min: CE# hold time
614 * @tCHZ_max: CE# high to output hi-Z
615 * @tCLH_min: CLE hold time
616 * @tCLR_min: CLE to RE# delay
617 * @tCLS_min: CLE setup time
618 * @tCOH_min: CE# high to output hold
619 * @tCS_min: CE# setup time
620 * @tDH_min: Data hold time
621 * @tDS_min: Data setup time
622 * @tFEAT_max: Busy time for Set Features and Get Features
623 * @tIR_min: Output hi-Z to RE# low
624 * @tITC_max: Interface and Timing Mode Change time
625 * @tRC_min: RE# cycle time
626 * @tREA_max: RE# access time
627 * @tREH_min: RE# high hold time
628 * @tRHOH_min: RE# high to output hold
629 * @tRHW_min: RE# high to WE# low
630 * @tRHZ_max: RE# high to output hi-Z
631 * @tRLOH_min: RE# low to output hold
632 * @tRP_min: RE# pulse width
633 * @tRR_min: Ready to RE# low (data only)
634 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
635 * rising edge of R/B#.
636 * @tWB_max: WE# high to SR[6] low
637 * @tWC_min: WE# cycle time
638 * @tWH_min: WE# high hold time
639 * @tWHR_min: WE# high to RE# low
640 * @tWP_min: WE# pulse width
641 * @tWW_min: WP# transition to WE# low
643 struct nand_sdr_timings {
685 * enum nand_data_interface_type - NAND interface timing type
686 * @NAND_SDR_IFACE: Single Data Rate interface
688 enum nand_data_interface_type {
693 * struct nand_data_interface - NAND interface timing
694 * @type: type of the timing
695 * @timings: The timing, type according to @type
697 struct nand_data_interface {
698 enum nand_data_interface_type type;
700 struct nand_sdr_timings sdr;
705 * nand_get_sdr_timings - get SDR timing from data interface
706 * @conf: The data interface
708 static inline const struct nand_sdr_timings *
709 nand_get_sdr_timings(const struct nand_data_interface *conf)
711 if (conf->type != NAND_SDR_IFACE)
712 return ERR_PTR(-EINVAL);
714 return &conf->timings.sdr;
718 * struct nand_manufacturer_ops - NAND Manufacturer operations
719 * @detect: detect the NAND memory organization and capabilities
720 * @init: initialize all vendor specific fields (like the ->read_retry()
721 * implementation) if any.
722 * @cleanup: the ->init() function may have allocated resources, ->cleanup()
723 * is here to let vendor specific code release those resources.
725 struct nand_manufacturer_ops {
726 void (*detect)(struct nand_chip *chip);
727 int (*init)(struct nand_chip *chip);
728 void (*cleanup)(struct nand_chip *chip);
732 * struct nand_chip - NAND Private Flash Chip Data
733 * @mtd: MTD device registered to the MTD framework
734 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
736 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
738 * @read_byte: [REPLACEABLE] read one byte from the chip
739 * @read_word: [REPLACEABLE] read one word from the chip
740 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
742 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
743 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
744 * @select_chip: [REPLACEABLE] select chip nr
745 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
746 * @block_markbad: [REPLACEABLE] mark a block bad
747 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
748 * ALE/CLE/nCE. Also used to write command and address
749 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
750 * device ready/busy line. If set to NULL no access to
751 * ready/busy is available and the ready/busy information
752 * is read from the chip status register.
753 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
754 * commands to the chip.
755 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
757 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
758 * setting the read-retry mode. Mostly needed for MLC NAND.
759 * @ecc: [BOARDSPECIFIC] ECC control structure
760 * @buffers: buffer structure for read/write
761 * @buf_align: minimum buffer alignment required by a platform
762 * @hwcontrol: platform-specific hardware control structure
763 * @erase: [REPLACEABLE] erase function
764 * @scan_bbt: [REPLACEABLE] function to scan bad block table
765 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
766 * data from array to read regs (tR).
767 * @state: [INTERN] the current state of the NAND device
768 * @oob_poi: "poison value buffer," used for laying out OOB data
770 * @page_shift: [INTERN] number of address bits in a page (column
772 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
773 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
774 * @chip_shift: [INTERN] number of address bits in one chip
775 * @options: [BOARDSPECIFIC] various chip options. They can partly
776 * be set to inform nand_scan about special functionality.
777 * See the defines for further explanation.
778 * @bbt_options: [INTERN] bad block specific options. All options used
779 * here must come from bbm.h. By default, these options
780 * will be copied to the appropriate nand_bbt_descr's.
781 * @badblockpos: [INTERN] position of the bad block marker in the oob
783 * @badblockbits: [INTERN] minimum number of set bits in a good block's
784 * bad block marker position; i.e., BBM == 11110111b is
785 * not bad when badblockbits == 7
786 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
787 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
788 * Minimum amount of bit errors per @ecc_step_ds guaranteed
789 * to be correctable. If unknown, set to zero.
790 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
791 * also from the datasheet. It is the recommended ECC step
792 * size, if known; if unknown, set to zero.
793 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
794 * set to the actually used ONFI mode if the chip is
795 * ONFI compliant or deduced from the datasheet if
796 * the NAND chip is not ONFI compliant.
797 * @numchips: [INTERN] number of physical chips
798 * @chipsize: [INTERN] the size of one chip for multichip arrays
799 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
800 * @pagebuf: [INTERN] holds the pagenumber which is currently in
802 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
803 * currently in data_buf.
804 * @subpagesize: [INTERN] holds the subpagesize
805 * @id: [INTERN] holds NAND ID
806 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
807 * non 0 if ONFI supported.
808 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
809 * non 0 if JEDEC supported.
810 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
811 * supported, 0 otherwise.
812 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
813 * supported, 0 otherwise.
814 * @max_bb_per_die: [INTERN] the max number of bad blocks each die of a
815 * this nand device will encounter their life times.
816 * @blocks_per_die: [INTERN] The number of PEBs in a die
817 * @data_interface: [INTERN] NAND interface timing information
818 * @read_retries: [INTERN] the number of read retry modes supported
819 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
820 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
821 * @setup_data_interface: [OPTIONAL] setup the data interface and timing
822 * @bbt: [INTERN] bad block table pointer
823 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
825 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
826 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
828 * @controller: [REPLACEABLE] a pointer to a hardware controller
829 * structure which is shared among multiple independent
831 * @priv: [OPTIONAL] pointer to private chip data
832 * @errstat: [OPTIONAL] hardware specific function to perform
833 * additional error status checks (determine if errors are
835 * @manufacturer: [INTERN] Contains manufacturer information
840 void __iomem *IO_ADDR_R;
841 void __iomem *IO_ADDR_W;
843 uint8_t (*read_byte)(struct mtd_info *mtd);
844 u16 (*read_word)(struct mtd_info *mtd);
845 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
846 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
847 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
848 void (*select_chip)(struct mtd_info *mtd, int chip);
849 int (*block_bad)(struct mtd_info *mtd, loff_t ofs);
850 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
851 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
852 int (*dev_ready)(struct mtd_info *mtd);
853 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
855 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
856 int (*erase)(struct mtd_info *mtd, int page);
857 int (*scan_bbt)(struct mtd_info *mtd);
858 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
859 int status, int page);
860 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
861 int feature_addr, uint8_t *subfeature_para);
862 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
863 int feature_addr, uint8_t *subfeature_para);
864 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
865 int (*setup_data_interface)(struct mtd_info *mtd,
866 const struct nand_data_interface *conf,
871 unsigned int options;
872 unsigned int bbt_options;
875 int phys_erase_shift;
882 unsigned int pagebuf_bitflips;
884 uint8_t bits_per_cell;
885 uint16_t ecc_strength_ds;
886 uint16_t ecc_step_ds;
887 int onfi_timing_mode_default;
895 struct nand_onfi_params onfi_params;
896 struct nand_jedec_params jedec_params;
901 struct nand_data_interface *data_interface;
908 struct nand_hw_control *controller;
910 struct nand_ecc_ctrl ecc;
911 struct nand_buffers *buffers;
912 unsigned long buf_align;
913 struct nand_hw_control hwcontrol;
916 struct nand_bbt_descr *bbt_td;
917 struct nand_bbt_descr *bbt_md;
919 struct nand_bbt_descr *badblock_pattern;
924 const struct nand_manufacturer *desc;
929 extern const struct mtd_ooblayout_ops nand_ooblayout_sp_ops;
930 extern const struct mtd_ooblayout_ops nand_ooblayout_lp_ops;
932 static inline void nand_set_flash_node(struct nand_chip *chip,
933 struct device_node *np)
935 mtd_set_of_node(&chip->mtd, np);
938 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
940 return mtd_get_of_node(&chip->mtd);
943 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
945 return container_of(mtd, struct nand_chip, mtd);
948 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
953 static inline void *nand_get_controller_data(struct nand_chip *chip)
958 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
963 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
966 chip->manufacturer.priv = priv;
969 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
971 return chip->manufacturer.priv;
975 * NAND Flash Manufacturer ID Codes
977 #define NAND_MFR_TOSHIBA 0x98
978 #define NAND_MFR_ESMT 0xc8
979 #define NAND_MFR_SAMSUNG 0xec
980 #define NAND_MFR_FUJITSU 0x04
981 #define NAND_MFR_NATIONAL 0x8f
982 #define NAND_MFR_RENESAS 0x07
983 #define NAND_MFR_STMICRO 0x20
984 #define NAND_MFR_HYNIX 0xad
985 #define NAND_MFR_MICRON 0x2c
986 #define NAND_MFR_AMD 0x01
987 #define NAND_MFR_MACRONIX 0xc2
988 #define NAND_MFR_EON 0x92
989 #define NAND_MFR_SANDISK 0x45
990 #define NAND_MFR_INTEL 0x89
991 #define NAND_MFR_ATO 0x9b
992 #define NAND_MFR_WINBOND 0xef
994 /* The maximum expected count of bytes in the NAND ID sequence */
995 #define NAND_MAX_ID_LEN 8
998 * A helper for defining older NAND chips where the second ID byte fully
999 * defined the chip, including the geometry (chip size, eraseblock size, page
1000 * size). All these chips have 512 bytes NAND page size.
1002 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1003 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1004 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1007 * A helper for defining newer chips which report their page size and
1008 * eraseblock size via the extended ID bytes.
1010 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1011 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1012 * device ID now only represented a particular total chip size (and voltage,
1013 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1014 * using the same device ID.
1016 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1017 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1020 #define NAND_ECC_INFO(_strength, _step) \
1021 { .strength_ds = (_strength), .step_ds = (_step) }
1022 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1023 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1026 * struct nand_flash_dev - NAND Flash Device ID Structure
1027 * @name: a human-readable name of the NAND chip
1028 * @dev_id: the device ID (the second byte of the full chip ID array)
1029 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
1030 * memory address as @id[0])
1031 * @dev_id: device ID part of the full chip ID array (refers the same memory
1032 * address as @id[1])
1033 * @id: full device ID array
1034 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1035 * well as the eraseblock size) is determined from the extended NAND
1037 * @chipsize: total chip size in MiB
1038 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1039 * @options: stores various chip bit options
1040 * @id_len: The valid length of the @id.
1041 * @oobsize: OOB size
1042 * @ecc: ECC correctability and step information from the datasheet.
1043 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1044 * @ecc_strength_ds in nand_chip{}.
1045 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1046 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1047 * For example, the "4bit ECC for each 512Byte" can be set with
1048 * NAND_ECC_INFO(4, 512).
1049 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
1050 * reset. Should be deduced from timings described
1054 struct nand_flash_dev {
1061 uint8_t id[NAND_MAX_ID_LEN];
1063 unsigned int pagesize;
1064 unsigned int chipsize;
1065 unsigned int erasesize;
1066 unsigned int options;
1070 uint16_t strength_ds;
1073 int onfi_timing_mode_default;
1077 * struct nand_manufacturer - NAND Flash Manufacturer structure
1078 * @name: Manufacturer name
1079 * @id: manufacturer ID code of device.
1080 * @ops: manufacturer operations
1082 struct nand_manufacturer {
1085 const struct nand_manufacturer_ops *ops;
1088 const struct nand_manufacturer *nand_get_manufacturer(u8 id);
1090 static inline const char *
1091 nand_manufacturer_name(const struct nand_manufacturer *manufacturer)
1093 return manufacturer ? manufacturer->name : "Unknown";
1096 extern struct nand_flash_dev nand_flash_ids[];
1098 extern const struct nand_manufacturer_ops toshiba_nand_manuf_ops;
1099 extern const struct nand_manufacturer_ops samsung_nand_manuf_ops;
1100 extern const struct nand_manufacturer_ops hynix_nand_manuf_ops;
1101 extern const struct nand_manufacturer_ops micron_nand_manuf_ops;
1102 extern const struct nand_manufacturer_ops amd_nand_manuf_ops;
1103 extern const struct nand_manufacturer_ops macronix_nand_manuf_ops;
1105 int nand_default_bbt(struct mtd_info *mtd);
1106 int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
1107 int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
1108 int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
1109 int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
1111 int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
1112 size_t *retlen, uint8_t *buf);
1115 * struct platform_nand_chip - chip level device structure
1116 * @nr_chips: max. number of chips to scan for
1117 * @chip_offset: chip number offset
1118 * @nr_partitions: number of partitions pointed to by partitions (or zero)
1119 * @partitions: mtd partition list
1120 * @chip_delay: R/B delay value in us
1121 * @options: Option flags, e.g. 16bit buswidth
1122 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
1123 * @part_probe_types: NULL-terminated array of probe types
1125 struct platform_nand_chip {
1129 struct mtd_partition *partitions;
1131 unsigned int options;
1132 unsigned int bbt_options;
1133 const char **part_probe_types;
1136 /* Keep gcc happy */
1137 struct platform_device;
1140 * struct platform_nand_ctrl - controller level device structure
1141 * @probe: platform specific function to probe/setup hardware
1142 * @remove: platform specific function to remove/teardown hardware
1143 * @hwcontrol: platform specific hardware control structure
1144 * @dev_ready: platform specific function to read ready/busy pin
1145 * @select_chip: platform specific chip select function
1146 * @cmd_ctrl: platform specific function for controlling
1147 * ALE/CLE/nCE. Also used to write command and address
1148 * @write_buf: platform specific function for write buffer
1149 * @read_buf: platform specific function for read buffer
1150 * @read_byte: platform specific function to read one byte from chip
1151 * @priv: private data to transport driver specific settings
1153 * All fields are optional and depend on the hardware driver requirements
1155 struct platform_nand_ctrl {
1156 int (*probe)(struct platform_device *pdev);
1157 void (*remove)(struct platform_device *pdev);
1158 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
1159 int (*dev_ready)(struct mtd_info *mtd);
1160 void (*select_chip)(struct mtd_info *mtd, int chip);
1161 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
1162 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
1163 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
1164 unsigned char (*read_byte)(struct mtd_info *mtd);
1169 * struct platform_nand_data - container structure for platform-specific data
1170 * @chip: chip level chip structure
1171 * @ctrl: controller level device structure
1173 struct platform_nand_data {
1174 struct platform_nand_chip chip;
1175 struct platform_nand_ctrl ctrl;
1178 /* return the supported features. */
1179 static inline int onfi_feature(struct nand_chip *chip)
1181 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
1184 /* return the supported asynchronous timing mode. */
1185 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
1187 if (!chip->onfi_version)
1188 return ONFI_TIMING_MODE_UNKNOWN;
1189 return le16_to_cpu(chip->onfi_params.async_timing_mode);
1192 /* return the supported synchronous timing mode. */
1193 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
1195 if (!chip->onfi_version)
1196 return ONFI_TIMING_MODE_UNKNOWN;
1197 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
1200 int onfi_init_data_interface(struct nand_chip *chip,
1201 struct nand_data_interface *iface,
1202 enum nand_data_interface_type type,
1206 * Check if it is a SLC nand.
1207 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1208 * We do not distinguish the MLC and TLC now.
1210 static inline bool nand_is_slc(struct nand_chip *chip)
1212 return chip->bits_per_cell == 1;
1216 * Check if the opcode's address should be sent only on the lower 8 bits
1217 * @command: opcode to check
1219 static inline int nand_opcode_8bits(unsigned int command)
1222 case NAND_CMD_READID:
1223 case NAND_CMD_PARAM:
1224 case NAND_CMD_GET_FEATURES:
1225 case NAND_CMD_SET_FEATURES:
1233 /* return the supported JEDEC features. */
1234 static inline int jedec_feature(struct nand_chip *chip)
1236 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
1240 /* get timing characteristics from ONFI timing mode. */
1241 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1242 /* get data interface from ONFI timing mode 0, used after reset. */
1243 const struct nand_data_interface *nand_get_default_data_interface(void);
1245 int nand_check_erased_ecc_chunk(void *data, int datalen,
1246 void *ecc, int ecclen,
1247 void *extraoob, int extraooblen,
1250 /* Default write_oob implementation */
1251 int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1253 /* Default write_oob syndrome implementation */
1254 int nand_write_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1257 /* Default read_oob implementation */
1258 int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip, int page);
1260 /* Default read_oob syndrome implementation */
1261 int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
1264 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1265 int nand_onfi_get_set_features_notsupp(struct mtd_info *mtd,
1266 struct nand_chip *chip, int addr,
1267 u8 *subfeature_param);
1269 /* Default read_page_raw implementation */
1270 int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1271 uint8_t *buf, int oob_required, int page);
1273 /* Default write_page_raw implementation */
1274 int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
1275 const uint8_t *buf, int oob_required, int page);
1277 /* Reset and initialize a NAND device */
1278 int nand_reset(struct nand_chip *chip, int chipnr);
1280 /* Free resources held by the NAND device */
1281 void nand_cleanup(struct nand_chip *chip);
1283 /* Default extended ID decoding function */
1284 void nand_decode_ext_id(struct nand_chip *chip);
1285 #endif /* __LINUX_MTD_NAND_H */