4 * PCI defines and function prototypes
5 * Copyright 1994, Drew Eckhardt
6 * Copyright 1997--1999 Martin Mares <mj@ucw.cz>
8 * For more information, please consult the following manuals (look at
9 * http://www.pcisig.com/ for how to get them):
11 * PCI BIOS Specification
12 * PCI Local Bus Specification
13 * PCI to PCI Bridge Specification
14 * PCI System Design Guide
20 #include <linux/mod_devicetable.h>
22 #include <linux/types.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/list.h>
26 #include <linux/compiler.h>
27 #include <linux/errno.h>
28 #include <linux/kobject.h>
29 #include <linux/atomic.h>
30 #include <linux/device.h>
31 #include <linux/interrupt.h>
33 #include <linux/resource_ext.h>
34 #include <uapi/linux/pci.h>
36 #include <linux/pci_ids.h>
39 * The PCI interface treats multi-function devices as independent
40 * devices. The slot/function address of each device is encoded
41 * in a single byte as follows:
46 * PCI_DEVFN(), PCI_SLOT(), and PCI_FUNC() are defined in uapi/linux/pci.h.
47 * In the interest of not exposing interfaces to user-space unnecessarily,
48 * the following kernel-only defines are being added here.
50 #define PCI_DEVID(bus, devfn) ((((u16)(bus)) << 8) | (devfn))
51 /* return bus from PCI devid = ((u16)bus_number) << 8) | devfn */
52 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
54 /* pci_slot represents a physical slot */
56 struct pci_bus *bus; /* The bus this slot is on */
57 struct list_head list; /* node in list of slots on this bus */
58 struct hotplug_slot *hotplug; /* Hotplug info (migrate over time) */
59 unsigned char number; /* PCI_SLOT(pci_dev->devfn) */
63 static inline const char *pci_slot_name(const struct pci_slot *slot)
65 return kobject_name(&slot->kobj);
68 /* File state for mmap()s on /proc/bus/pci/X/Y */
75 * For PCI devices, the region numbers are assigned this way:
78 /* #0-5: standard PCI resources */
80 PCI_STD_RESOURCE_END = 5,
82 /* #6: expansion ROM resource */
85 /* device specific resources */
88 PCI_IOV_RESOURCE_END = PCI_IOV_RESOURCES + PCI_SRIOV_NUM_BARS - 1,
91 /* resources assigned to buses behind the bridge */
92 #define PCI_BRIDGE_RESOURCE_NUM 4
95 PCI_BRIDGE_RESOURCE_END = PCI_BRIDGE_RESOURCES +
96 PCI_BRIDGE_RESOURCE_NUM - 1,
98 /* total resources associated with a PCI device */
101 /* preserve this for compatibility */
102 DEVICE_COUNT_RESOURCE = PCI_NUM_RESOURCES,
106 * pci_power_t values must match the bits in the Capabilities PME_Support
107 * and Control/Status PowerState fields in the Power Management capability.
109 typedef int __bitwise pci_power_t;
111 #define PCI_D0 ((pci_power_t __force) 0)
112 #define PCI_D1 ((pci_power_t __force) 1)
113 #define PCI_D2 ((pci_power_t __force) 2)
114 #define PCI_D3hot ((pci_power_t __force) 3)
115 #define PCI_D3cold ((pci_power_t __force) 4)
116 #define PCI_UNKNOWN ((pci_power_t __force) 5)
117 #define PCI_POWER_ERROR ((pci_power_t __force) -1)
119 /* Remember to update this when the list above changes! */
120 extern const char *pci_power_names[];
122 static inline const char *pci_power_name(pci_power_t state)
124 return pci_power_names[1 + (__force int) state];
127 #define PCI_PM_D2_DELAY 200
128 #define PCI_PM_D3_WAIT 10
129 #define PCI_PM_D3COLD_WAIT 100
130 #define PCI_PM_BUS_WAIT 50
132 /** The pci_channel state describes connectivity between the CPU and
133 * the pci device. If some PCI bus between here and the pci device
134 * has crashed or locked up, this info is reflected here.
136 typedef unsigned int __bitwise pci_channel_state_t;
138 enum pci_channel_state {
139 /* I/O channel is in normal state */
140 pci_channel_io_normal = (__force pci_channel_state_t) 1,
142 /* I/O to channel is blocked */
143 pci_channel_io_frozen = (__force pci_channel_state_t) 2,
145 /* PCI card is dead */
146 pci_channel_io_perm_failure = (__force pci_channel_state_t) 3,
149 typedef unsigned int __bitwise pcie_reset_state_t;
151 enum pcie_reset_state {
152 /* Reset is NOT asserted (Use to deassert reset) */
153 pcie_deassert_reset = (__force pcie_reset_state_t) 1,
155 /* Use #PERST to reset PCIe device */
156 pcie_warm_reset = (__force pcie_reset_state_t) 2,
158 /* Use PCIe Hot Reset to reset device */
159 pcie_hot_reset = (__force pcie_reset_state_t) 3
162 typedef unsigned short __bitwise pci_dev_flags_t;
164 /* INTX_DISABLE in PCI_COMMAND register disables MSI
167 PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG = (__force pci_dev_flags_t) (1 << 0),
168 /* Device configuration is irrevocably lost if disabled into D3 */
169 PCI_DEV_FLAGS_NO_D3 = (__force pci_dev_flags_t) (1 << 1),
170 /* Provide indication device is assigned by a Virtual Machine Manager */
171 PCI_DEV_FLAGS_ASSIGNED = (__force pci_dev_flags_t) (1 << 2),
172 /* Flag for quirk use to store if quirk-specific ACS is enabled */
173 PCI_DEV_FLAGS_ACS_ENABLED_QUIRK = (__force pci_dev_flags_t) (1 << 3),
174 /* Use a PCIe-to-PCI bridge alias even if !pci_is_pcie */
175 PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS = (__force pci_dev_flags_t) (1 << 5),
176 /* Do not use bus resets for device */
177 PCI_DEV_FLAGS_NO_BUS_RESET = (__force pci_dev_flags_t) (1 << 6),
178 /* Do not use PM reset even if device advertises NoSoftRst- */
179 PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
180 /* Get VPD from function 0 VPD */
181 PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
182 /* a non-root bridge where translation occurs, stop alias search here */
183 PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT = (__force pci_dev_flags_t) (1 << 9),
184 /* Do not use FLR even if device advertises PCI_AF_CAP */
185 PCI_DEV_FLAGS_NO_FLR_RESET = (__force pci_dev_flags_t) (1 << 10),
187 * Resume before calling the driver's system suspend hooks, disabling
188 * the direct_complete optimization.
190 PCI_DEV_FLAGS_NEEDS_RESUME = (__force pci_dev_flags_t) (1 << 11),
191 /* Don't use Relaxed Ordering for TLPs directed at this device */
192 PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 12),
195 enum pci_irq_reroute_variant {
196 INTEL_IRQ_REROUTE_VARIANT = 1,
197 MAX_IRQ_REROUTE_VARIANTS = 3
200 typedef unsigned short __bitwise pci_bus_flags_t;
202 PCI_BUS_FLAGS_NO_MSI = (__force pci_bus_flags_t) 1,
203 PCI_BUS_FLAGS_NO_MMRBC = (__force pci_bus_flags_t) 2,
204 PCI_BUS_FLAGS_NO_AERSID = (__force pci_bus_flags_t) 4,
207 /* These values come from the PCI Express Spec */
208 enum pcie_link_width {
209 PCIE_LNK_WIDTH_RESRV = 0x00,
217 PCIE_LNK_WIDTH_UNKNOWN = 0xFF,
220 /* Based on the PCI Hotplug Spec, but some values are made up by us */
222 PCI_SPEED_33MHz = 0x00,
223 PCI_SPEED_66MHz = 0x01,
224 PCI_SPEED_66MHz_PCIX = 0x02,
225 PCI_SPEED_100MHz_PCIX = 0x03,
226 PCI_SPEED_133MHz_PCIX = 0x04,
227 PCI_SPEED_66MHz_PCIX_ECC = 0x05,
228 PCI_SPEED_100MHz_PCIX_ECC = 0x06,
229 PCI_SPEED_133MHz_PCIX_ECC = 0x07,
230 PCI_SPEED_66MHz_PCIX_266 = 0x09,
231 PCI_SPEED_100MHz_PCIX_266 = 0x0a,
232 PCI_SPEED_133MHz_PCIX_266 = 0x0b,
238 PCI_SPEED_66MHz_PCIX_533 = 0x11,
239 PCI_SPEED_100MHz_PCIX_533 = 0x12,
240 PCI_SPEED_133MHz_PCIX_533 = 0x13,
241 PCIE_SPEED_2_5GT = 0x14,
242 PCIE_SPEED_5_0GT = 0x15,
243 PCIE_SPEED_8_0GT = 0x16,
244 PCI_SPEED_UNKNOWN = 0xff,
247 struct pci_cap_saved_data {
254 struct pci_cap_saved_state {
255 struct hlist_node next;
256 struct pci_cap_saved_data cap;
260 struct pcie_link_state;
266 * The pci_dev structure is used to describe PCI devices.
269 struct list_head bus_list; /* node in per-bus list */
270 struct pci_bus *bus; /* bus this device is on */
271 struct pci_bus *subordinate; /* bus this device bridges to */
273 void *sysdata; /* hook for sys-specific extension */
274 struct proc_dir_entry *procent; /* device entry in /proc/bus/pci */
275 struct pci_slot *slot; /* Physical slot this device is in */
277 unsigned int devfn; /* encoded device & function index */
278 unsigned short vendor;
279 unsigned short device;
280 unsigned short subsystem_vendor;
281 unsigned short subsystem_device;
282 unsigned int class; /* 3 bytes: (base,sub,prog-if) */
283 u8 revision; /* PCI revision, low byte of class word */
284 u8 hdr_type; /* PCI header type (`multi' flag masked out) */
285 #ifdef CONFIG_PCIEAER
286 u16 aer_cap; /* AER capability offset */
288 u8 pcie_cap; /* PCIe capability offset */
289 u8 msi_cap; /* MSI capability offset */
290 u8 msix_cap; /* MSI-X capability offset */
291 u8 pcie_mpss:3; /* PCIe Max Payload Size Supported */
292 u8 rom_base_reg; /* which config register controls the ROM */
293 u8 pin; /* which interrupt pin this device uses */
294 u16 pcie_flags_reg; /* cached PCIe Capabilities Register */
295 unsigned long *dma_alias_mask;/* mask of enabled devfn aliases */
297 struct pci_driver *driver; /* which driver has allocated this device */
298 u64 dma_mask; /* Mask of the bits of bus address this
299 device implements. Normally this is
300 0xffffffff. You only need to change
301 this if your device has broken DMA
302 or supports 64-bit transfers. */
304 struct device_dma_parameters dma_parms;
306 pci_power_t current_state; /* Current operating state. In ACPI-speak,
307 this is D0-D3, D0 being fully functional,
309 u8 pm_cap; /* PM capability offset */
310 unsigned int pme_support:5; /* Bitmask of states from which PME#
312 unsigned int pme_poll:1; /* Poll device's PME status bit */
313 unsigned int d1_support:1; /* Low power state D1 is supported */
314 unsigned int d2_support:1; /* Low power state D2 is supported */
315 unsigned int no_d1d2:1; /* D1 and D2 are forbidden */
316 unsigned int no_d3cold:1; /* D3cold is forbidden */
317 unsigned int bridge_d3:1; /* Allow D3 for bridge */
318 unsigned int d3cold_allowed:1; /* D3cold is allowed by user */
319 unsigned int mmio_always_on:1; /* disallow turning off io/mem
320 decoding during bar sizing */
321 unsigned int wakeup_prepared:1;
322 unsigned int runtime_d3cold:1; /* whether go through runtime
323 D3cold, not set for devices
324 powered on/off by the
325 corresponding bridge */
326 unsigned int ignore_hotplug:1; /* Ignore hotplug events */
327 unsigned int hotplug_user_indicators:1; /* SlotCtl indicators
328 controlled exclusively by
330 unsigned int d3_delay; /* D3->D0 transition time in ms */
331 unsigned int d3cold_delay; /* D3cold->D0 transition time in ms */
333 #ifdef CONFIG_PCIEASPM
334 struct pcie_link_state *link_state; /* ASPM link state */
337 pci_channel_state_t error_state; /* current connectivity state */
338 struct device dev; /* Generic device interface */
340 int cfg_size; /* Size of configuration space */
343 * Instead of touching interrupt line and base address registers
344 * directly, use the values stored here. They might be different!
347 struct resource resource[DEVICE_COUNT_RESOURCE]; /* I/O and memory regions + expansion ROMs */
349 bool match_driver; /* Skip attaching driver */
350 /* These fields are used by common fixups */
351 unsigned int transparent:1; /* Subtractive decode PCI bridge */
352 unsigned int multifunction:1;/* Part of multi-function device */
353 /* keep track of device state */
354 unsigned int is_added:1;
355 unsigned int is_busmaster:1; /* device is busmaster */
356 unsigned int no_msi:1; /* device may not use msi */
357 unsigned int no_64bit_msi:1; /* device may only use 32-bit MSIs */
358 unsigned int block_cfg_access:1; /* config space access is blocked */
359 unsigned int broken_parity_status:1; /* Device generates false positive parity */
360 unsigned int irq_reroute_variant:2; /* device needs IRQ rerouting variant */
361 unsigned int msi_enabled:1;
362 unsigned int msix_enabled:1;
363 unsigned int ari_enabled:1; /* ARI forwarding */
364 unsigned int ats_enabled:1; /* Address Translation Service */
365 unsigned int pasid_enabled:1; /* Process Address Space ID */
366 unsigned int pri_enabled:1; /* Page Request Interface */
367 unsigned int is_managed:1;
368 unsigned int needs_freset:1; /* Dev requires fundamental reset */
369 unsigned int state_saved:1;
370 unsigned int is_physfn:1;
371 unsigned int is_virtfn:1;
372 unsigned int reset_fn:1;
373 unsigned int is_hotplug_bridge:1;
374 unsigned int is_thunderbolt:1; /* Thunderbolt controller */
375 unsigned int __aer_firmware_first_valid:1;
376 unsigned int __aer_firmware_first:1;
377 unsigned int broken_intx_masking:1; /* INTx masking can't be used */
378 unsigned int io_window_1k:1; /* Intel P2P bridge 1K I/O windows */
379 unsigned int irq_managed:1;
380 unsigned int has_secondary_link:1;
381 unsigned int non_compliant_bars:1; /* broken BARs; ignore them */
382 unsigned int is_probed:1; /* device probing in progress */
383 pci_dev_flags_t dev_flags;
384 atomic_t enable_cnt; /* pci_enable_device has been called */
386 u32 saved_config_space[16]; /* config space saved at suspend time */
387 struct hlist_head saved_cap_space;
388 struct bin_attribute *rom_attr; /* attribute descriptor for sysfs ROM entry */
389 int rom_attr_enabled; /* has display of the rom attribute been enabled? */
390 struct bin_attribute *res_attr[DEVICE_COUNT_RESOURCE]; /* sysfs file for resources */
391 struct bin_attribute *res_attr_wc[DEVICE_COUNT_RESOURCE]; /* sysfs file for WC mapping of resources */
393 #ifdef CONFIG_PCIE_PTM
394 unsigned int ptm_root:1;
395 unsigned int ptm_enabled:1;
398 #ifdef CONFIG_PCI_MSI
399 const struct attribute_group **msi_irq_groups;
402 #ifdef CONFIG_PCI_ATS
404 struct pci_sriov *sriov; /* SR-IOV capability related */
405 struct pci_dev *physfn; /* the PF this VF is associated with */
407 u16 ats_cap; /* ATS Capability offset */
408 u8 ats_stu; /* ATS Smallest Translation Unit */
409 atomic_t ats_ref_cnt; /* number of VFs with ATS enabled */
411 #ifdef CONFIG_PCI_PRI
412 u32 pri_reqs_alloc; /* Number of PRI requests allocated */
414 #ifdef CONFIG_PCI_PASID
417 phys_addr_t rom; /* Physical address of ROM if it's not from the BAR */
418 size_t romlen; /* Length of ROM if it's not from the BAR */
419 char *driver_override; /* Driver name to force a match */
421 unsigned long priv_flags; /* Private flags for the pci driver */
424 static inline struct pci_dev *pci_physfn(struct pci_dev *dev)
426 #ifdef CONFIG_PCI_IOV
433 struct pci_dev *pci_alloc_dev(struct pci_bus *bus);
435 #define to_pci_dev(n) container_of(n, struct pci_dev, dev)
436 #define for_each_pci_dev(d) while ((d = pci_get_device(PCI_ANY_ID, PCI_ANY_ID, d)) != NULL)
438 static inline int pci_channel_offline(struct pci_dev *pdev)
440 return (pdev->error_state != pci_channel_io_normal);
443 struct pci_host_bridge {
445 struct pci_bus *bus; /* root bus */
449 struct list_head windows; /* resource_entry */
450 u8 (*swizzle_irq)(struct pci_dev *, u8 *); /* platform IRQ swizzler */
451 int (*map_irq)(const struct pci_dev *, u8, u8);
452 void (*release_fn)(struct pci_host_bridge *);
454 struct msi_controller *msi;
455 unsigned int ignore_reset_delay:1; /* for entire hierarchy */
456 /* Resource alignment requirements */
457 resource_size_t (*align_resource)(struct pci_dev *dev,
458 const struct resource *res,
459 resource_size_t start,
460 resource_size_t size,
461 resource_size_t align);
462 unsigned long private[0] ____cacheline_aligned;
465 #define to_pci_host_bridge(n) container_of(n, struct pci_host_bridge, dev)
467 static inline void *pci_host_bridge_priv(struct pci_host_bridge *bridge)
469 return (void *)bridge->private;
472 static inline struct pci_host_bridge *pci_host_bridge_from_priv(void *priv)
474 return container_of(priv, struct pci_host_bridge, private);
477 struct pci_host_bridge *pci_alloc_host_bridge(size_t priv);
478 struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev,
480 void pci_free_host_bridge(struct pci_host_bridge *bridge);
481 struct pci_host_bridge *pci_find_host_bridge(struct pci_bus *bus);
483 void pci_set_host_bridge_release(struct pci_host_bridge *bridge,
484 void (*release_fn)(struct pci_host_bridge *),
487 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge);
490 * The first PCI_BRIDGE_RESOURCE_NUM PCI bus resources (those that correspond
491 * to P2P or CardBus bridge windows) go in a table. Additional ones (for
492 * buses below host bridges or subtractive decode bridges) go in the list.
493 * Use pci_bus_for_each_resource() to iterate through all the resources.
497 * PCI_SUBTRACTIVE_DECODE means the bridge forwards the window implicitly
498 * and there's no way to program the bridge with the details of the window.
499 * This does not apply to ACPI _CRS windows, even with the _DEC subtractive-
500 * decode bit set, because they are explicit and can be programmed with _SRS.
502 #define PCI_SUBTRACTIVE_DECODE 0x1
504 struct pci_bus_resource {
505 struct list_head list;
506 struct resource *res;
510 #define PCI_REGION_FLAG_MASK 0x0fU /* These bits of resource flags tell us the PCI region flags */
513 struct list_head node; /* node in list of buses */
514 struct pci_bus *parent; /* parent bus this bridge is on */
515 struct list_head children; /* list of child buses */
516 struct list_head devices; /* list of devices on this bus */
517 struct pci_dev *self; /* bridge device as seen by parent */
518 struct list_head slots; /* list of slots on this bus;
519 protected by pci_slot_mutex */
520 struct resource *resource[PCI_BRIDGE_RESOURCE_NUM];
521 struct list_head resources; /* address space routed to this bus */
522 struct resource busn_res; /* bus numbers routed to this bus */
524 struct pci_ops *ops; /* configuration access functions */
525 struct msi_controller *msi; /* MSI controller */
526 void *sysdata; /* hook for sys-specific extension */
527 struct proc_dir_entry *procdir; /* directory entry in /proc/bus/pci */
529 unsigned char number; /* bus number */
530 unsigned char primary; /* number of primary bridge */
531 unsigned char max_bus_speed; /* enum pci_bus_speed */
532 unsigned char cur_bus_speed; /* enum pci_bus_speed */
533 #ifdef CONFIG_PCI_DOMAINS_GENERIC
539 unsigned short bridge_ctl; /* manage NO_ISA/FBB/et al behaviors */
540 pci_bus_flags_t bus_flags; /* inherited by child buses */
541 struct device *bridge;
543 struct bin_attribute *legacy_io; /* legacy I/O for this bus */
544 struct bin_attribute *legacy_mem; /* legacy mem */
545 unsigned int is_added:1;
548 #define to_pci_bus(n) container_of(n, struct pci_bus, dev)
551 * Returns true if the PCI bus is root (behind host-PCI bridge),
554 * Some code assumes that "bus->self == NULL" means that bus is a root bus.
555 * This is incorrect because "virtual" buses added for SR-IOV (via
556 * virtfn_add_bus()) have "bus->self == NULL" but are not root buses.
558 static inline bool pci_is_root_bus(struct pci_bus *pbus)
560 return !(pbus->parent);
564 * pci_is_bridge - check if the PCI device is a bridge
567 * Return true if the PCI device is bridge whether it has subordinate
570 static inline bool pci_is_bridge(struct pci_dev *dev)
572 return dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
573 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS;
576 static inline struct pci_dev *pci_upstream_bridge(struct pci_dev *dev)
578 dev = pci_physfn(dev);
579 if (pci_is_root_bus(dev->bus))
582 return dev->bus->self;
585 struct device *pci_get_host_bridge_device(struct pci_dev *dev);
586 void pci_put_host_bridge_device(struct device *dev);
588 #ifdef CONFIG_PCI_MSI
589 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev)
591 return pci_dev->msi_enabled || pci_dev->msix_enabled;
594 static inline bool pci_dev_msi_enabled(struct pci_dev *pci_dev) { return false; }
598 * Error values that may be returned by PCI functions.
600 #define PCIBIOS_SUCCESSFUL 0x00
601 #define PCIBIOS_FUNC_NOT_SUPPORTED 0x81
602 #define PCIBIOS_BAD_VENDOR_ID 0x83
603 #define PCIBIOS_DEVICE_NOT_FOUND 0x86
604 #define PCIBIOS_BAD_REGISTER_NUMBER 0x87
605 #define PCIBIOS_SET_FAILED 0x88
606 #define PCIBIOS_BUFFER_TOO_SMALL 0x89
609 * Translate above to generic errno for passing back through non-PCI code.
611 static inline int pcibios_err_to_errno(int err)
613 if (err <= PCIBIOS_SUCCESSFUL)
614 return err; /* Assume already errno */
617 case PCIBIOS_FUNC_NOT_SUPPORTED:
619 case PCIBIOS_BAD_VENDOR_ID:
621 case PCIBIOS_DEVICE_NOT_FOUND:
623 case PCIBIOS_BAD_REGISTER_NUMBER:
625 case PCIBIOS_SET_FAILED:
627 case PCIBIOS_BUFFER_TOO_SMALL:
634 /* Low-level architecture-dependent routines */
637 int (*add_bus)(struct pci_bus *bus);
638 void (*remove_bus)(struct pci_bus *bus);
639 void __iomem *(*map_bus)(struct pci_bus *bus, unsigned int devfn, int where);
640 int (*read)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 *val);
641 int (*write)(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val);
645 * ACPI needs to be able to access PCI config space before we've done a
646 * PCI bus scan and created pci_bus structures.
648 int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn,
649 int reg, int len, u32 *val);
650 int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn,
651 int reg, int len, u32 val);
653 #ifdef CONFIG_PCI_BUS_ADDR_T_64BIT
654 typedef u64 pci_bus_addr_t;
656 typedef u32 pci_bus_addr_t;
659 struct pci_bus_region {
660 pci_bus_addr_t start;
665 spinlock_t lock; /* protects list, index */
666 struct list_head list; /* for IDs added at runtime */
671 * PCI Error Recovery System (PCI-ERS). If a PCI device driver provides
672 * a set of callbacks in struct pci_error_handlers, that device driver
673 * will be notified of PCI bus errors, and will be driven to recovery
674 * when an error occurs.
677 typedef unsigned int __bitwise pci_ers_result_t;
679 enum pci_ers_result {
680 /* no result/none/not supported in device driver */
681 PCI_ERS_RESULT_NONE = (__force pci_ers_result_t) 1,
683 /* Device driver can recover without slot reset */
684 PCI_ERS_RESULT_CAN_RECOVER = (__force pci_ers_result_t) 2,
686 /* Device driver wants slot to be reset. */
687 PCI_ERS_RESULT_NEED_RESET = (__force pci_ers_result_t) 3,
689 /* Device has completely failed, is unrecoverable */
690 PCI_ERS_RESULT_DISCONNECT = (__force pci_ers_result_t) 4,
692 /* Device driver is fully recovered and operational */
693 PCI_ERS_RESULT_RECOVERED = (__force pci_ers_result_t) 5,
695 /* No AER capabilities registered for the driver */
696 PCI_ERS_RESULT_NO_AER_DRIVER = (__force pci_ers_result_t) 6,
699 /* PCI bus error event callbacks */
700 struct pci_error_handlers {
701 /* PCI bus error detected on this device */
702 pci_ers_result_t (*error_detected)(struct pci_dev *dev,
703 enum pci_channel_state error);
705 /* MMIO has been re-enabled, but not DMA */
706 pci_ers_result_t (*mmio_enabled)(struct pci_dev *dev);
708 /* PCI slot has been reset */
709 pci_ers_result_t (*slot_reset)(struct pci_dev *dev);
711 /* PCI function reset prepare or completed */
712 void (*reset_prepare)(struct pci_dev *dev);
713 void (*reset_done)(struct pci_dev *dev);
715 /* Device driver may resume normal operations */
716 void (*resume)(struct pci_dev *dev);
722 struct list_head node;
724 const struct pci_device_id *id_table; /* must be non-NULL for probe to be called */
725 int (*probe) (struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
726 void (*remove) (struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
727 int (*suspend) (struct pci_dev *dev, pm_message_t state); /* Device suspended */
728 int (*suspend_late) (struct pci_dev *dev, pm_message_t state);
729 int (*resume_early) (struct pci_dev *dev);
730 int (*resume) (struct pci_dev *dev); /* Device woken up */
731 void (*shutdown) (struct pci_dev *dev);
732 int (*sriov_configure) (struct pci_dev *dev, int num_vfs); /* PF pdev */
733 const struct pci_error_handlers *err_handler;
734 struct device_driver driver;
735 struct pci_dynids dynids;
738 #define to_pci_driver(drv) container_of(drv, struct pci_driver, driver)
741 * PCI_DEVICE - macro used to describe a specific pci device
742 * @vend: the 16 bit PCI Vendor ID
743 * @dev: the 16 bit PCI Device ID
745 * This macro is used to create a struct pci_device_id that matches a
746 * specific device. The subvendor and subdevice fields will be set to
749 #define PCI_DEVICE(vend,dev) \
750 .vendor = (vend), .device = (dev), \
751 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
754 * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
755 * @vend: the 16 bit PCI Vendor ID
756 * @dev: the 16 bit PCI Device ID
757 * @subvend: the 16 bit PCI Subvendor ID
758 * @subdev: the 16 bit PCI Subdevice ID
760 * This macro is used to create a struct pci_device_id that matches a
761 * specific device with subsystem information.
763 #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
764 .vendor = (vend), .device = (dev), \
765 .subvendor = (subvend), .subdevice = (subdev)
768 * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
769 * @dev_class: the class, subclass, prog-if triple for this device
770 * @dev_class_mask: the class mask for this device
772 * This macro is used to create a struct pci_device_id that matches a
773 * specific PCI class. The vendor, device, subvendor, and subdevice
774 * fields will be set to PCI_ANY_ID.
776 #define PCI_DEVICE_CLASS(dev_class,dev_class_mask) \
777 .class = (dev_class), .class_mask = (dev_class_mask), \
778 .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
779 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
782 * PCI_VDEVICE - macro used to describe a specific pci device in short form
783 * @vend: the vendor name
784 * @dev: the 16 bit PCI Device ID
786 * This macro is used to create a struct pci_device_id that matches a
787 * specific PCI device. The subvendor, and subdevice fields will be set
788 * to PCI_ANY_ID. The macro allows the next field to follow as the device
792 #define PCI_VDEVICE(vend, dev) \
793 .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
794 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
797 PCI_REASSIGN_ALL_RSRC = 0x00000001, /* ignore firmware setup */
798 PCI_REASSIGN_ALL_BUS = 0x00000002, /* reassign all bus numbers */
799 PCI_PROBE_ONLY = 0x00000004, /* use existing setup */
800 PCI_CAN_SKIP_ISA_ALIGN = 0x00000008, /* don't do ISA alignment */
801 PCI_ENABLE_PROC_DOMAINS = 0x00000010, /* enable domains in /proc */
802 PCI_COMPAT_DOMAIN_0 = 0x00000020, /* ... except domain 0 */
803 PCI_SCAN_ALL_PCIE_DEVS = 0x00000040, /* scan all, not just dev 0 */
806 /* these external functions are only available when PCI support is enabled */
809 extern unsigned int pci_flags;
811 static inline void pci_set_flags(int flags) { pci_flags = flags; }
812 static inline void pci_add_flags(int flags) { pci_flags |= flags; }
813 static inline void pci_clear_flags(int flags) { pci_flags &= ~flags; }
814 static inline int pci_has_flag(int flag) { return pci_flags & flag; }
816 void pcie_bus_configure_settings(struct pci_bus *bus);
818 enum pcie_bus_config_types {
819 PCIE_BUS_TUNE_OFF, /* don't touch MPS at all */
820 PCIE_BUS_DEFAULT, /* ensure MPS matches upstream bridge */
821 PCIE_BUS_SAFE, /* use largest MPS boot-time devices support */
822 PCIE_BUS_PERFORMANCE, /* use MPS and MRRS for best performance */
823 PCIE_BUS_PEER2PEER, /* set MPS = 128 for all devices */
826 extern enum pcie_bus_config_types pcie_bus_config;
828 extern struct bus_type pci_bus_type;
830 /* Do NOT directly access these two variables, unless you are arch-specific PCI
831 * code, or PCI core code. */
832 extern struct list_head pci_root_buses; /* list of all known PCI buses */
833 /* Some device drivers need know if PCI is initiated */
834 int no_pci_devices(void);
836 void pcibios_resource_survey_bus(struct pci_bus *bus);
837 void pcibios_bus_add_device(struct pci_dev *pdev);
838 void pcibios_add_bus(struct pci_bus *bus);
839 void pcibios_remove_bus(struct pci_bus *bus);
840 void pcibios_fixup_bus(struct pci_bus *);
841 int __must_check pcibios_enable_device(struct pci_dev *, int mask);
842 /* Architecture-specific versions may override this (weak) */
843 char *pcibios_setup(char *str);
845 /* Used only when drivers/pci/setup.c is used */
846 resource_size_t pcibios_align_resource(void *, const struct resource *,
849 void pcibios_update_irq(struct pci_dev *, int irq);
851 /* Weak but can be overriden by arch */
852 void pci_fixup_cardbus(struct pci_bus *);
854 /* Generic PCI functions used internally */
856 void pcibios_resource_to_bus(struct pci_bus *bus, struct pci_bus_region *region,
857 struct resource *res);
858 void pcibios_bus_to_resource(struct pci_bus *bus, struct resource *res,
859 struct pci_bus_region *region);
860 void pcibios_scan_specific_bus(int busn);
861 struct pci_bus *pci_find_bus(int domain, int busnr);
862 void pci_bus_add_devices(const struct pci_bus *bus);
863 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, void *sysdata);
864 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
865 struct pci_ops *ops, void *sysdata,
866 struct list_head *resources);
867 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int busmax);
868 int pci_bus_update_busn_res_end(struct pci_bus *b, int busmax);
869 void pci_bus_release_busn_res(struct pci_bus *b);
870 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
871 struct pci_ops *ops, void *sysdata,
872 struct list_head *resources);
873 int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge);
874 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
876 void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
877 struct pci_slot *pci_create_slot(struct pci_bus *parent, int slot_nr,
879 struct hotplug_slot *hotplug);
880 void pci_destroy_slot(struct pci_slot *slot);
882 void pci_dev_assign_slot(struct pci_dev *dev);
884 static inline void pci_dev_assign_slot(struct pci_dev *dev) { }
886 int pci_scan_slot(struct pci_bus *bus, int devfn);
887 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn);
888 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus);
889 unsigned int pci_scan_child_bus(struct pci_bus *bus);
890 void pci_bus_add_device(struct pci_dev *dev);
891 void pci_read_bridge_bases(struct pci_bus *child);
892 struct resource *pci_find_parent_resource(const struct pci_dev *dev,
893 struct resource *res);
894 struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev);
895 u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin);
896 int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge);
897 u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp);
898 struct pci_dev *pci_dev_get(struct pci_dev *dev);
899 void pci_dev_put(struct pci_dev *dev);
900 void pci_remove_bus(struct pci_bus *b);
901 void pci_stop_and_remove_bus_device(struct pci_dev *dev);
902 void pci_stop_and_remove_bus_device_locked(struct pci_dev *dev);
903 void pci_stop_root_bus(struct pci_bus *bus);
904 void pci_remove_root_bus(struct pci_bus *bus);
905 void pci_setup_cardbus(struct pci_bus *bus);
906 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type);
907 void pci_sort_breadthfirst(void);
908 #define dev_is_pci(d) ((d)->bus == &pci_bus_type)
909 #define dev_is_pf(d) ((dev_is_pci(d) ? to_pci_dev(d)->is_physfn : false))
911 /* Generic PCI functions exported to card drivers */
913 enum pci_lost_interrupt_reason {
914 PCI_LOST_IRQ_NO_INFORMATION = 0,
915 PCI_LOST_IRQ_DISABLE_MSI,
916 PCI_LOST_IRQ_DISABLE_MSIX,
917 PCI_LOST_IRQ_DISABLE_ACPI,
919 enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
920 int pci_find_capability(struct pci_dev *dev, int cap);
921 int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
922 int pci_find_ext_capability(struct pci_dev *dev, int cap);
923 int pci_find_next_ext_capability(struct pci_dev *dev, int pos, int cap);
924 int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
925 int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
926 struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
928 struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
929 struct pci_dev *from);
930 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
931 unsigned int ss_vendor, unsigned int ss_device,
932 struct pci_dev *from);
933 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
934 struct pci_dev *pci_get_domain_bus_and_slot(int domain, unsigned int bus,
936 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
939 return pci_get_domain_bus_and_slot(0, bus, devfn);
941 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
942 int pci_dev_present(const struct pci_device_id *ids);
944 int pci_bus_read_config_byte(struct pci_bus *bus, unsigned int devfn,
946 int pci_bus_read_config_word(struct pci_bus *bus, unsigned int devfn,
947 int where, u16 *val);
948 int pci_bus_read_config_dword(struct pci_bus *bus, unsigned int devfn,
949 int where, u32 *val);
950 int pci_bus_write_config_byte(struct pci_bus *bus, unsigned int devfn,
952 int pci_bus_write_config_word(struct pci_bus *bus, unsigned int devfn,
954 int pci_bus_write_config_dword(struct pci_bus *bus, unsigned int devfn,
957 int pci_generic_config_read(struct pci_bus *bus, unsigned int devfn,
958 int where, int size, u32 *val);
959 int pci_generic_config_write(struct pci_bus *bus, unsigned int devfn,
960 int where, int size, u32 val);
961 int pci_generic_config_read32(struct pci_bus *bus, unsigned int devfn,
962 int where, int size, u32 *val);
963 int pci_generic_config_write32(struct pci_bus *bus, unsigned int devfn,
964 int where, int size, u32 val);
966 struct pci_ops *pci_bus_set_ops(struct pci_bus *bus, struct pci_ops *ops);
968 int pci_read_config_byte(const struct pci_dev *dev, int where, u8 *val);
969 int pci_read_config_word(const struct pci_dev *dev, int where, u16 *val);
970 int pci_read_config_dword(const struct pci_dev *dev, int where, u32 *val);
971 int pci_write_config_byte(const struct pci_dev *dev, int where, u8 val);
972 int pci_write_config_word(const struct pci_dev *dev, int where, u16 val);
973 int pci_write_config_dword(const struct pci_dev *dev, int where, u32 val);
975 int pcie_capability_read_word(struct pci_dev *dev, int pos, u16 *val);
976 int pcie_capability_read_dword(struct pci_dev *dev, int pos, u32 *val);
977 int pcie_capability_write_word(struct pci_dev *dev, int pos, u16 val);
978 int pcie_capability_write_dword(struct pci_dev *dev, int pos, u32 val);
979 int pcie_capability_clear_and_set_word(struct pci_dev *dev, int pos,
981 int pcie_capability_clear_and_set_dword(struct pci_dev *dev, int pos,
984 static inline int pcie_capability_set_word(struct pci_dev *dev, int pos,
987 return pcie_capability_clear_and_set_word(dev, pos, 0, set);
990 static inline int pcie_capability_set_dword(struct pci_dev *dev, int pos,
993 return pcie_capability_clear_and_set_dword(dev, pos, 0, set);
996 static inline int pcie_capability_clear_word(struct pci_dev *dev, int pos,
999 return pcie_capability_clear_and_set_word(dev, pos, clear, 0);
1002 static inline int pcie_capability_clear_dword(struct pci_dev *dev, int pos,
1005 return pcie_capability_clear_and_set_dword(dev, pos, clear, 0);
1008 /* user-space driven config access */
1009 int pci_user_read_config_byte(struct pci_dev *dev, int where, u8 *val);
1010 int pci_user_read_config_word(struct pci_dev *dev, int where, u16 *val);
1011 int pci_user_read_config_dword(struct pci_dev *dev, int where, u32 *val);
1012 int pci_user_write_config_byte(struct pci_dev *dev, int where, u8 val);
1013 int pci_user_write_config_word(struct pci_dev *dev, int where, u16 val);
1014 int pci_user_write_config_dword(struct pci_dev *dev, int where, u32 val);
1016 int __must_check pci_enable_device(struct pci_dev *dev);
1017 int __must_check pci_enable_device_io(struct pci_dev *dev);
1018 int __must_check pci_enable_device_mem(struct pci_dev *dev);
1019 int __must_check pci_reenable_device(struct pci_dev *);
1020 int __must_check pcim_enable_device(struct pci_dev *pdev);
1021 void pcim_pin_device(struct pci_dev *pdev);
1023 static inline bool pci_intx_mask_supported(struct pci_dev *pdev)
1026 * INTx masking is supported if PCI_COMMAND_INTX_DISABLE is
1027 * writable and no quirk has marked the feature broken.
1029 return !pdev->broken_intx_masking;
1032 static inline int pci_is_enabled(struct pci_dev *pdev)
1034 return (atomic_read(&pdev->enable_cnt) > 0);
1037 static inline int pci_is_managed(struct pci_dev *pdev)
1039 return pdev->is_managed;
1042 void pci_disable_device(struct pci_dev *dev);
1044 extern unsigned int pcibios_max_latency;
1045 void pci_set_master(struct pci_dev *dev);
1046 void pci_clear_master(struct pci_dev *dev);
1048 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state);
1049 int pci_set_cacheline_size(struct pci_dev *dev);
1050 #define HAVE_PCI_SET_MWI
1051 int __must_check pci_set_mwi(struct pci_dev *dev);
1052 int pci_try_set_mwi(struct pci_dev *dev);
1053 void pci_clear_mwi(struct pci_dev *dev);
1054 void pci_intx(struct pci_dev *dev, int enable);
1055 bool pci_check_and_mask_intx(struct pci_dev *dev);
1056 bool pci_check_and_unmask_intx(struct pci_dev *dev);
1057 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask);
1058 int pci_wait_for_pending_transaction(struct pci_dev *dev);
1059 int pcix_get_max_mmrbc(struct pci_dev *dev);
1060 int pcix_get_mmrbc(struct pci_dev *dev);
1061 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc);
1062 int pcie_get_readrq(struct pci_dev *dev);
1063 int pcie_set_readrq(struct pci_dev *dev, int rq);
1064 int pcie_get_mps(struct pci_dev *dev);
1065 int pcie_set_mps(struct pci_dev *dev, int mps);
1066 int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
1067 enum pcie_link_width *width);
1068 void pcie_flr(struct pci_dev *dev);
1069 int __pci_reset_function(struct pci_dev *dev);
1070 int __pci_reset_function_locked(struct pci_dev *dev);
1071 int pci_reset_function(struct pci_dev *dev);
1072 int pci_try_reset_function(struct pci_dev *dev);
1073 int pci_probe_reset_slot(struct pci_slot *slot);
1074 int pci_reset_slot(struct pci_slot *slot);
1075 int pci_try_reset_slot(struct pci_slot *slot);
1076 int pci_probe_reset_bus(struct pci_bus *bus);
1077 int pci_reset_bus(struct pci_bus *bus);
1078 int pci_try_reset_bus(struct pci_bus *bus);
1079 void pci_reset_secondary_bus(struct pci_dev *dev);
1080 void pcibios_reset_secondary_bus(struct pci_dev *dev);
1081 void pci_reset_bridge_secondary_bus(struct pci_dev *dev);
1082 void pci_update_resource(struct pci_dev *dev, int resno);
1083 int __must_check pci_assign_resource(struct pci_dev *dev, int i);
1084 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align);
1085 int pci_select_bars(struct pci_dev *dev, unsigned long flags);
1086 bool pci_device_is_present(struct pci_dev *pdev);
1087 void pci_ignore_hotplug(struct pci_dev *dev);
1089 int __printf(6, 7) pci_request_irq(struct pci_dev *dev, unsigned int nr,
1090 irq_handler_t handler, irq_handler_t thread_fn, void *dev_id,
1091 const char *fmt, ...);
1092 void pci_free_irq(struct pci_dev *dev, unsigned int nr, void *dev_id);
1094 /* ROM control related routines */
1095 int pci_enable_rom(struct pci_dev *pdev);
1096 void pci_disable_rom(struct pci_dev *pdev);
1097 void __iomem __must_check *pci_map_rom(struct pci_dev *pdev, size_t *size);
1098 void pci_unmap_rom(struct pci_dev *pdev, void __iomem *rom);
1099 size_t pci_get_rom_size(struct pci_dev *pdev, void __iomem *rom, size_t size);
1100 void __iomem __must_check *pci_platform_rom(struct pci_dev *pdev, size_t *size);
1102 /* Power management related routines */
1103 int pci_save_state(struct pci_dev *dev);
1104 void pci_restore_state(struct pci_dev *dev);
1105 struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
1106 int pci_load_saved_state(struct pci_dev *dev,
1107 struct pci_saved_state *state);
1108 int pci_load_and_free_saved_state(struct pci_dev *dev,
1109 struct pci_saved_state **state);
1110 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap);
1111 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev,
1113 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size);
1114 int pci_add_ext_cap_save_buffer(struct pci_dev *dev,
1115 u16 cap, unsigned int size);
1116 int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
1117 int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
1118 pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
1119 bool pci_pme_capable(struct pci_dev *dev, pci_power_t state);
1120 void pci_pme_active(struct pci_dev *dev, bool enable);
1121 int pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable);
1122 int pci_wake_from_d3(struct pci_dev *dev, bool enable);
1123 int pci_prepare_to_sleep(struct pci_dev *dev);
1124 int pci_back_from_sleep(struct pci_dev *dev);
1125 bool pci_dev_run_wake(struct pci_dev *dev);
1126 bool pci_check_pme_status(struct pci_dev *dev);
1127 void pci_pme_wakeup_bus(struct pci_bus *bus);
1128 void pci_d3cold_enable(struct pci_dev *dev);
1129 void pci_d3cold_disable(struct pci_dev *dev);
1130 bool pcie_relaxed_ordering_enabled(struct pci_dev *dev);
1132 /* PCI Virtual Channel */
1133 int pci_save_vc_state(struct pci_dev *dev);
1134 void pci_restore_vc_state(struct pci_dev *dev);
1135 void pci_allocate_vc_save_buffers(struct pci_dev *dev);
1137 /* For use by arch with custom probe code */
1138 void set_pcie_port_type(struct pci_dev *pdev);
1139 void set_pcie_hotplug_bridge(struct pci_dev *pdev);
1141 /* Functions for PCI Hotplug drivers to use */
1142 int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap);
1143 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge);
1144 unsigned int pci_rescan_bus(struct pci_bus *bus);
1145 void pci_lock_rescan_remove(void);
1146 void pci_unlock_rescan_remove(void);
1148 /* Vital product data routines */
1149 ssize_t pci_read_vpd(struct pci_dev *dev, loff_t pos, size_t count, void *buf);
1150 ssize_t pci_write_vpd(struct pci_dev *dev, loff_t pos, size_t count, const void *buf);
1151 int pci_set_vpd_size(struct pci_dev *dev, size_t len);
1153 /* Helper functions for low-level code (drivers/pci/setup-[bus,res].c) */
1154 resource_size_t pcibios_retrieve_fw_addr(struct pci_dev *dev, int idx);
1155 void pci_bus_assign_resources(const struct pci_bus *bus);
1156 void pci_bus_claim_resources(struct pci_bus *bus);
1157 void pci_bus_size_bridges(struct pci_bus *bus);
1158 int pci_claim_resource(struct pci_dev *, int);
1159 int pci_claim_bridge_resource(struct pci_dev *bridge, int i);
1160 void pci_assign_unassigned_resources(void);
1161 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge);
1162 void pci_assign_unassigned_bus_resources(struct pci_bus *bus);
1163 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus);
1164 void pdev_enable_device(struct pci_dev *);
1165 int pci_enable_resources(struct pci_dev *, int mask);
1166 void pci_fixup_irqs(u8 (*)(struct pci_dev *, u8 *),
1167 int (*)(const struct pci_dev *, u8, u8));
1168 void pci_assign_irq(struct pci_dev *dev);
1169 struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res);
1170 #define HAVE_PCI_REQ_REGIONS 2
1171 int __must_check pci_request_regions(struct pci_dev *, const char *);
1172 int __must_check pci_request_regions_exclusive(struct pci_dev *, const char *);
1173 void pci_release_regions(struct pci_dev *);
1174 int __must_check pci_request_region(struct pci_dev *, int, const char *);
1175 int __must_check pci_request_region_exclusive(struct pci_dev *, int, const char *);
1176 void pci_release_region(struct pci_dev *, int);
1177 int pci_request_selected_regions(struct pci_dev *, int, const char *);
1178 int pci_request_selected_regions_exclusive(struct pci_dev *, int, const char *);
1179 void pci_release_selected_regions(struct pci_dev *, int);
1181 /* drivers/pci/bus.c */
1182 struct pci_bus *pci_bus_get(struct pci_bus *bus);
1183 void pci_bus_put(struct pci_bus *bus);
1184 void pci_add_resource(struct list_head *resources, struct resource *res);
1185 void pci_add_resource_offset(struct list_head *resources, struct resource *res,
1186 resource_size_t offset);
1187 void pci_free_resource_list(struct list_head *resources);
1188 void pci_bus_add_resource(struct pci_bus *bus, struct resource *res,
1189 unsigned int flags);
1190 struct resource *pci_bus_resource_n(const struct pci_bus *bus, int n);
1191 void pci_bus_remove_resources(struct pci_bus *bus);
1192 int devm_request_pci_bus_resources(struct device *dev,
1193 struct list_head *resources);
1195 #define pci_bus_for_each_resource(bus, res, i) \
1197 (res = pci_bus_resource_n(bus, i)) || i < PCI_BRIDGE_RESOURCE_NUM; \
1200 int __must_check pci_bus_alloc_resource(struct pci_bus *bus,
1201 struct resource *res, resource_size_t size,
1202 resource_size_t align, resource_size_t min,
1203 unsigned long type_mask,
1204 resource_size_t (*alignf)(void *,
1205 const struct resource *,
1211 int pci_register_io_range(phys_addr_t addr, resource_size_t size);
1212 unsigned long pci_address_to_pio(phys_addr_t addr);
1213 phys_addr_t pci_pio_to_address(unsigned long pio);
1214 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr);
1215 void pci_unmap_iospace(struct resource *res);
1216 void __iomem *devm_pci_remap_cfgspace(struct device *dev,
1217 resource_size_t offset,
1218 resource_size_t size);
1219 void __iomem *devm_pci_remap_cfg_resource(struct device *dev,
1220 struct resource *res);
1222 static inline pci_bus_addr_t pci_bus_address(struct pci_dev *pdev, int bar)
1224 struct pci_bus_region region;
1226 pcibios_resource_to_bus(pdev->bus, ®ion, &pdev->resource[bar]);
1227 return region.start;
1230 /* Proper probing supporting hot-pluggable devices */
1231 int __must_check __pci_register_driver(struct pci_driver *, struct module *,
1232 const char *mod_name);
1235 * pci_register_driver must be a macro so that KBUILD_MODNAME can be expanded
1237 #define pci_register_driver(driver) \
1238 __pci_register_driver(driver, THIS_MODULE, KBUILD_MODNAME)
1240 void pci_unregister_driver(struct pci_driver *dev);
1243 * module_pci_driver() - Helper macro for registering a PCI driver
1244 * @__pci_driver: pci_driver struct
1246 * Helper macro for PCI drivers which do not do anything special in module
1247 * init/exit. This eliminates a lot of boilerplate. Each module may only
1248 * use this macro once, and calling it replaces module_init() and module_exit()
1250 #define module_pci_driver(__pci_driver) \
1251 module_driver(__pci_driver, pci_register_driver, \
1252 pci_unregister_driver)
1255 * builtin_pci_driver() - Helper macro for registering a PCI driver
1256 * @__pci_driver: pci_driver struct
1258 * Helper macro for PCI drivers which do not do anything special in their
1259 * init code. This eliminates a lot of boilerplate. Each driver may only
1260 * use this macro once, and calling it replaces device_initcall(...)
1262 #define builtin_pci_driver(__pci_driver) \
1263 builtin_driver(__pci_driver, pci_register_driver)
1265 struct pci_driver *pci_dev_driver(const struct pci_dev *dev);
1266 int pci_add_dynid(struct pci_driver *drv,
1267 unsigned int vendor, unsigned int device,
1268 unsigned int subvendor, unsigned int subdevice,
1269 unsigned int class, unsigned int class_mask,
1270 unsigned long driver_data);
1271 const struct pci_device_id *pci_match_id(const struct pci_device_id *ids,
1272 struct pci_dev *dev);
1273 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max,
1276 void pci_walk_bus(struct pci_bus *top, int (*cb)(struct pci_dev *, void *),
1278 int pci_cfg_space_size(struct pci_dev *dev);
1279 unsigned char pci_bus_max_busnr(struct pci_bus *bus);
1280 void pci_setup_bridge(struct pci_bus *bus);
1281 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
1282 unsigned long type);
1283 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *dev, int resno);
1285 #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
1286 #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
1288 int pci_set_vga_state(struct pci_dev *pdev, bool decode,
1289 unsigned int command_bits, u32 flags);
1291 #define PCI_IRQ_LEGACY (1 << 0) /* allow legacy interrupts */
1292 #define PCI_IRQ_MSI (1 << 1) /* allow MSI interrupts */
1293 #define PCI_IRQ_MSIX (1 << 2) /* allow MSI-X interrupts */
1294 #define PCI_IRQ_AFFINITY (1 << 3) /* auto-assign affinity */
1295 #define PCI_IRQ_ALL_TYPES \
1296 (PCI_IRQ_LEGACY | PCI_IRQ_MSI | PCI_IRQ_MSIX)
1298 /* kmem_cache style wrapper around pci_alloc_consistent() */
1300 #include <linux/pci-dma.h>
1301 #include <linux/dmapool.h>
1303 #define pci_pool dma_pool
1304 #define pci_pool_create(name, pdev, size, align, allocation) \
1305 dma_pool_create(name, &pdev->dev, size, align, allocation)
1306 #define pci_pool_destroy(pool) dma_pool_destroy(pool)
1307 #define pci_pool_alloc(pool, flags, handle) dma_pool_alloc(pool, flags, handle)
1308 #define pci_pool_zalloc(pool, flags, handle) \
1309 dma_pool_zalloc(pool, flags, handle)
1310 #define pci_pool_free(pool, vaddr, addr) dma_pool_free(pool, vaddr, addr)
1313 u32 vector; /* kernel uses to write allocated vector */
1314 u16 entry; /* driver uses to specify entry, OS writes */
1317 #ifdef CONFIG_PCI_MSI
1318 int pci_msi_vec_count(struct pci_dev *dev);
1319 void pci_disable_msi(struct pci_dev *dev);
1320 int pci_msix_vec_count(struct pci_dev *dev);
1321 void pci_disable_msix(struct pci_dev *dev);
1322 void pci_restore_msi_state(struct pci_dev *dev);
1323 int pci_msi_enabled(void);
1324 int pci_enable_msi(struct pci_dev *dev);
1325 int pci_enable_msix_range(struct pci_dev *dev, struct msix_entry *entries,
1326 int minvec, int maxvec);
1327 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1328 struct msix_entry *entries, int nvec)
1330 int rc = pci_enable_msix_range(dev, entries, nvec, nvec);
1335 int pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1336 unsigned int max_vecs, unsigned int flags,
1337 const struct irq_affinity *affd);
1339 void pci_free_irq_vectors(struct pci_dev *dev);
1340 int pci_irq_vector(struct pci_dev *dev, unsigned int nr);
1341 const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev, int vec);
1342 int pci_irq_get_node(struct pci_dev *pdev, int vec);
1345 static inline int pci_msi_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1346 static inline void pci_disable_msi(struct pci_dev *dev) { }
1347 static inline int pci_msix_vec_count(struct pci_dev *dev) { return -ENOSYS; }
1348 static inline void pci_disable_msix(struct pci_dev *dev) { }
1349 static inline void pci_restore_msi_state(struct pci_dev *dev) { }
1350 static inline int pci_msi_enabled(void) { return 0; }
1351 static inline int pci_enable_msi(struct pci_dev *dev)
1353 static inline int pci_enable_msix_range(struct pci_dev *dev,
1354 struct msix_entry *entries, int minvec, int maxvec)
1356 static inline int pci_enable_msix_exact(struct pci_dev *dev,
1357 struct msix_entry *entries, int nvec)
1361 pci_alloc_irq_vectors_affinity(struct pci_dev *dev, unsigned int min_vecs,
1362 unsigned int max_vecs, unsigned int flags,
1363 const struct irq_affinity *aff_desc)
1365 if ((flags & PCI_IRQ_LEGACY) && min_vecs == 1 && dev->irq)
1370 static inline void pci_free_irq_vectors(struct pci_dev *dev)
1374 static inline int pci_irq_vector(struct pci_dev *dev, unsigned int nr)
1376 if (WARN_ON_ONCE(nr > 0))
1380 static inline const struct cpumask *pci_irq_get_affinity(struct pci_dev *pdev,
1383 return cpu_possible_mask;
1386 static inline int pci_irq_get_node(struct pci_dev *pdev, int vec)
1388 return first_online_node;
1393 pci_alloc_irq_vectors(struct pci_dev *dev, unsigned int min_vecs,
1394 unsigned int max_vecs, unsigned int flags)
1396 return pci_alloc_irq_vectors_affinity(dev, min_vecs, max_vecs, flags,
1400 #ifdef CONFIG_PCIEPORTBUS
1401 extern bool pcie_ports_disabled;
1402 extern bool pcie_ports_auto;
1404 #define pcie_ports_disabled true
1405 #define pcie_ports_auto false
1408 #ifdef CONFIG_PCIEASPM
1409 bool pcie_aspm_support_enabled(void);
1411 static inline bool pcie_aspm_support_enabled(void) { return false; }
1414 #ifdef CONFIG_PCIEAER
1415 void pci_no_aer(void);
1416 bool pci_aer_available(void);
1417 int pci_aer_init(struct pci_dev *dev);
1419 static inline void pci_no_aer(void) { }
1420 static inline bool pci_aer_available(void) { return false; }
1421 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
1424 #ifdef CONFIG_PCIE_ECRC
1425 void pcie_set_ecrc_checking(struct pci_dev *dev);
1426 void pcie_ecrc_get_policy(char *str);
1428 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
1429 static inline void pcie_ecrc_get_policy(char *str) { }
1432 #ifdef CONFIG_HT_IRQ
1433 /* The functions a driver should call */
1434 int ht_create_irq(struct pci_dev *dev, int idx);
1435 void ht_destroy_irq(unsigned int irq);
1436 #endif /* CONFIG_HT_IRQ */
1438 #ifdef CONFIG_PCI_ATS
1439 /* Address Translation Service */
1440 void pci_ats_init(struct pci_dev *dev);
1441 int pci_enable_ats(struct pci_dev *dev, int ps);
1442 void pci_disable_ats(struct pci_dev *dev);
1443 int pci_ats_queue_depth(struct pci_dev *dev);
1445 static inline void pci_ats_init(struct pci_dev *d) { }
1446 static inline int pci_enable_ats(struct pci_dev *d, int ps) { return -ENODEV; }
1447 static inline void pci_disable_ats(struct pci_dev *d) { }
1448 static inline int pci_ats_queue_depth(struct pci_dev *d) { return -ENODEV; }
1451 #ifdef CONFIG_PCIE_PTM
1452 int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
1454 static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
1458 void pci_cfg_access_lock(struct pci_dev *dev);
1459 bool pci_cfg_access_trylock(struct pci_dev *dev);
1460 void pci_cfg_access_unlock(struct pci_dev *dev);
1463 * PCI domain support. Sometimes called PCI segment (eg by ACPI),
1464 * a PCI domain is defined to be a set of PCI buses which share
1465 * configuration space.
1467 #ifdef CONFIG_PCI_DOMAINS
1468 extern int pci_domains_supported;
1469 int pci_get_new_domain_nr(void);
1471 enum { pci_domains_supported = 0 };
1472 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1473 static inline int pci_proc_domain(struct pci_bus *bus) { return 0; }
1474 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1475 #endif /* CONFIG_PCI_DOMAINS */
1478 * Generic implementation for PCI domain support. If your
1479 * architecture does not need custom management of PCI
1480 * domains then this implementation will be used
1482 #ifdef CONFIG_PCI_DOMAINS_GENERIC
1483 static inline int pci_domain_nr(struct pci_bus *bus)
1485 return bus->domain_nr;
1488 int acpi_pci_bus_find_domain_nr(struct pci_bus *bus);
1490 static inline int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1493 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent);
1496 /* some architectures require additional setup to direct VGA traffic */
1497 typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
1498 unsigned int command_bits, u32 flags);
1499 void pci_register_set_vga_state(arch_set_vga_state_t func);
1502 pci_request_io_regions(struct pci_dev *pdev, const char *name)
1504 return pci_request_selected_regions(pdev,
1505 pci_select_bars(pdev, IORESOURCE_IO), name);
1509 pci_release_io_regions(struct pci_dev *pdev)
1511 return pci_release_selected_regions(pdev,
1512 pci_select_bars(pdev, IORESOURCE_IO));
1516 pci_request_mem_regions(struct pci_dev *pdev, const char *name)
1518 return pci_request_selected_regions(pdev,
1519 pci_select_bars(pdev, IORESOURCE_MEM), name);
1523 pci_release_mem_regions(struct pci_dev *pdev)
1525 return pci_release_selected_regions(pdev,
1526 pci_select_bars(pdev, IORESOURCE_MEM));
1529 #else /* CONFIG_PCI is not enabled */
1531 static inline void pci_set_flags(int flags) { }
1532 static inline void pci_add_flags(int flags) { }
1533 static inline void pci_clear_flags(int flags) { }
1534 static inline int pci_has_flag(int flag) { return 0; }
1537 * If the system does not have PCI, clearly these return errors. Define
1538 * these as simple inline functions to avoid hair in drivers.
1541 #define _PCI_NOP(o, s, t) \
1542 static inline int pci_##o##_config_##s(struct pci_dev *dev, \
1544 { return PCIBIOS_FUNC_NOT_SUPPORTED; }
1546 #define _PCI_NOP_ALL(o, x) _PCI_NOP(o, byte, u8 x) \
1547 _PCI_NOP(o, word, u16 x) \
1548 _PCI_NOP(o, dword, u32 x)
1549 _PCI_NOP_ALL(read, *)
1550 _PCI_NOP_ALL(write,)
1552 static inline struct pci_dev *pci_get_device(unsigned int vendor,
1553 unsigned int device,
1554 struct pci_dev *from)
1557 static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
1558 unsigned int device,
1559 unsigned int ss_vendor,
1560 unsigned int ss_device,
1561 struct pci_dev *from)
1564 static inline struct pci_dev *pci_get_class(unsigned int class,
1565 struct pci_dev *from)
1568 #define pci_dev_present(ids) (0)
1569 #define no_pci_devices() (1)
1570 #define pci_dev_put(dev) do { } while (0)
1572 static inline void pci_set_master(struct pci_dev *dev) { }
1573 static inline int pci_enable_device(struct pci_dev *dev) { return -EIO; }
1574 static inline void pci_disable_device(struct pci_dev *dev) { }
1575 static inline int pci_assign_resource(struct pci_dev *dev, int i)
1577 static inline int __pci_register_driver(struct pci_driver *drv,
1578 struct module *owner)
1580 static inline int pci_register_driver(struct pci_driver *drv)
1582 static inline void pci_unregister_driver(struct pci_driver *drv) { }
1583 static inline int pci_find_capability(struct pci_dev *dev, int cap)
1585 static inline int pci_find_next_capability(struct pci_dev *dev, u8 post,
1588 static inline int pci_find_ext_capability(struct pci_dev *dev, int cap)
1591 /* Power management related routines */
1592 static inline int pci_save_state(struct pci_dev *dev) { return 0; }
1593 static inline void pci_restore_state(struct pci_dev *dev) { }
1594 static inline int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1596 static inline int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1598 static inline pci_power_t pci_choose_state(struct pci_dev *dev,
1601 static inline int pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1605 static inline struct resource *pci_find_resource(struct pci_dev *dev,
1606 struct resource *res)
1608 static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
1610 static inline void pci_release_regions(struct pci_dev *dev) { }
1612 static inline unsigned long pci_address_to_pio(phys_addr_t addr) { return -1; }
1614 static inline void pci_block_cfg_access(struct pci_dev *dev) { }
1615 static inline int pci_block_cfg_access_in_atomic(struct pci_dev *dev)
1617 static inline void pci_unblock_cfg_access(struct pci_dev *dev) { }
1619 static inline struct pci_bus *pci_find_next_bus(const struct pci_bus *from)
1621 static inline struct pci_dev *pci_get_slot(struct pci_bus *bus,
1624 static inline struct pci_dev *pci_get_bus_and_slot(unsigned int bus,
1628 static inline int pci_domain_nr(struct pci_bus *bus) { return 0; }
1629 static inline struct pci_dev *pci_dev_get(struct pci_dev *dev) { return NULL; }
1630 static inline int pci_get_new_domain_nr(void) { return -ENOSYS; }
1632 #define dev_is_pci(d) (false)
1633 #define dev_is_pf(d) (false)
1634 #endif /* CONFIG_PCI */
1636 /* Include architecture-dependent settings and functions */
1638 #include <asm/pci.h>
1640 /* These two functions provide almost identical functionality. Depennding
1641 * on the architecture, one will be implemented as a wrapper around the
1642 * other (in drivers/pci/mmap.c).
1644 * pci_mmap_resource_range() maps a specific BAR, and vm->vm_pgoff
1645 * is expected to be an offset within that region.
1647 * pci_mmap_page_range() is the legacy architecture-specific interface,
1648 * which accepts a "user visible" resource address converted by
1649 * pci_resource_to_user(), as used in the legacy mmap() interface in
1652 int pci_mmap_resource_range(struct pci_dev *dev, int bar,
1653 struct vm_area_struct *vma,
1654 enum pci_mmap_state mmap_state, int write_combine);
1655 int pci_mmap_page_range(struct pci_dev *pdev, int bar,
1656 struct vm_area_struct *vma,
1657 enum pci_mmap_state mmap_state, int write_combine);
1659 #ifndef arch_can_pci_mmap_wc
1660 #define arch_can_pci_mmap_wc() 0
1663 #ifndef arch_can_pci_mmap_io
1664 #define arch_can_pci_mmap_io() 0
1665 #define pci_iobar_pfn(pdev, bar, vma) (-EINVAL)
1667 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma);
1670 #ifndef pci_root_bus_fwnode
1671 #define pci_root_bus_fwnode(bus) NULL
1674 /* these helpers provide future and backwards compatibility
1675 * for accessing popular PCI BAR info */
1676 #define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
1677 #define pci_resource_end(dev, bar) ((dev)->resource[(bar)].end)
1678 #define pci_resource_flags(dev, bar) ((dev)->resource[(bar)].flags)
1679 #define pci_resource_len(dev,bar) \
1680 ((pci_resource_start((dev), (bar)) == 0 && \
1681 pci_resource_end((dev), (bar)) == \
1682 pci_resource_start((dev), (bar))) ? 0 : \
1684 (pci_resource_end((dev), (bar)) - \
1685 pci_resource_start((dev), (bar)) + 1))
1687 /* Similar to the helpers above, these manipulate per-pci_dev
1688 * driver-specific data. They are really just a wrapper around
1689 * the generic device structure functions of these calls.
1691 static inline void *pci_get_drvdata(struct pci_dev *pdev)
1693 return dev_get_drvdata(&pdev->dev);
1696 static inline void pci_set_drvdata(struct pci_dev *pdev, void *data)
1698 dev_set_drvdata(&pdev->dev, data);
1701 /* If you want to know what to call your pci_dev, ask this function.
1702 * Again, it's a wrapper around the generic device.
1704 static inline const char *pci_name(const struct pci_dev *pdev)
1706 return dev_name(&pdev->dev);
1710 /* Some archs don't want to expose struct resource to userland as-is
1711 * in sysfs and /proc
1713 #ifdef HAVE_ARCH_PCI_RESOURCE_TO_USER
1714 void pci_resource_to_user(const struct pci_dev *dev, int bar,
1715 const struct resource *rsrc,
1716 resource_size_t *start, resource_size_t *end);
1718 static inline void pci_resource_to_user(const struct pci_dev *dev, int bar,
1719 const struct resource *rsrc, resource_size_t *start,
1720 resource_size_t *end)
1722 *start = rsrc->start;
1725 #endif /* HAVE_ARCH_PCI_RESOURCE_TO_USER */
1729 * The world is not perfect and supplies us with broken PCI devices.
1730 * For at least a part of these bugs we need a work-around, so both
1731 * generic (drivers/pci/quirks.c) and per-architecture code can define
1732 * fixup hooks to be called for particular buggy devices.
1736 u16 vendor; /* You can use PCI_ANY_ID here of course */
1737 u16 device; /* You can use PCI_ANY_ID here of course */
1738 u32 class; /* You can use PCI_ANY_ID here too */
1739 unsigned int class_shift; /* should be 0, 8, 16 */
1740 void (*hook)(struct pci_dev *dev);
1743 enum pci_fixup_pass {
1744 pci_fixup_early, /* Before probing BARs */
1745 pci_fixup_header, /* After reading configuration header */
1746 pci_fixup_final, /* Final phase of device fixups */
1747 pci_fixup_enable, /* pci_enable_device() time */
1748 pci_fixup_resume, /* pci_device_resume() */
1749 pci_fixup_suspend, /* pci_device_suspend() */
1750 pci_fixup_resume_early, /* pci_device_resume_early() */
1751 pci_fixup_suspend_late, /* pci_device_suspend_late() */
1754 /* Anonymous variables would be nice... */
1755 #define DECLARE_PCI_FIXUP_SECTION(section, name, vendor, device, class, \
1756 class_shift, hook) \
1757 static const struct pci_fixup __PASTE(__pci_fixup_##name,__LINE__) __used \
1758 __attribute__((__section__(#section), aligned((sizeof(void *))))) \
1759 = { vendor, device, class, class_shift, hook };
1761 #define DECLARE_PCI_FIXUP_CLASS_EARLY(vendor, device, class, \
1762 class_shift, hook) \
1763 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1764 hook, vendor, device, class, class_shift, hook)
1765 #define DECLARE_PCI_FIXUP_CLASS_HEADER(vendor, device, class, \
1766 class_shift, hook) \
1767 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1768 hook, vendor, device, class, class_shift, hook)
1769 #define DECLARE_PCI_FIXUP_CLASS_FINAL(vendor, device, class, \
1770 class_shift, hook) \
1771 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1772 hook, vendor, device, class, class_shift, hook)
1773 #define DECLARE_PCI_FIXUP_CLASS_ENABLE(vendor, device, class, \
1774 class_shift, hook) \
1775 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1776 hook, vendor, device, class, class_shift, hook)
1777 #define DECLARE_PCI_FIXUP_CLASS_RESUME(vendor, device, class, \
1778 class_shift, hook) \
1779 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1780 resume##hook, vendor, device, class, \
1782 #define DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(vendor, device, class, \
1783 class_shift, hook) \
1784 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1785 resume_early##hook, vendor, device, \
1786 class, class_shift, hook)
1787 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND(vendor, device, class, \
1788 class_shift, hook) \
1789 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1790 suspend##hook, vendor, device, class, \
1792 #define DECLARE_PCI_FIXUP_CLASS_SUSPEND_LATE(vendor, device, class, \
1793 class_shift, hook) \
1794 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1795 suspend_late##hook, vendor, device, \
1796 class, class_shift, hook)
1798 #define DECLARE_PCI_FIXUP_EARLY(vendor, device, hook) \
1799 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_early, \
1800 hook, vendor, device, PCI_ANY_ID, 0, hook)
1801 #define DECLARE_PCI_FIXUP_HEADER(vendor, device, hook) \
1802 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_header, \
1803 hook, vendor, device, PCI_ANY_ID, 0, hook)
1804 #define DECLARE_PCI_FIXUP_FINAL(vendor, device, hook) \
1805 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_final, \
1806 hook, vendor, device, PCI_ANY_ID, 0, hook)
1807 #define DECLARE_PCI_FIXUP_ENABLE(vendor, device, hook) \
1808 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_enable, \
1809 hook, vendor, device, PCI_ANY_ID, 0, hook)
1810 #define DECLARE_PCI_FIXUP_RESUME(vendor, device, hook) \
1811 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume, \
1812 resume##hook, vendor, device, \
1813 PCI_ANY_ID, 0, hook)
1814 #define DECLARE_PCI_FIXUP_RESUME_EARLY(vendor, device, hook) \
1815 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_resume_early, \
1816 resume_early##hook, vendor, device, \
1817 PCI_ANY_ID, 0, hook)
1818 #define DECLARE_PCI_FIXUP_SUSPEND(vendor, device, hook) \
1819 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend, \
1820 suspend##hook, vendor, device, \
1821 PCI_ANY_ID, 0, hook)
1822 #define DECLARE_PCI_FIXUP_SUSPEND_LATE(vendor, device, hook) \
1823 DECLARE_PCI_FIXUP_SECTION(.pci_fixup_suspend_late, \
1824 suspend_late##hook, vendor, device, \
1825 PCI_ANY_ID, 0, hook)
1827 #ifdef CONFIG_PCI_QUIRKS
1828 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev);
1829 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
1830 int pci_dev_specific_enable_acs(struct pci_dev *dev);
1832 static inline void pci_fixup_device(enum pci_fixup_pass pass,
1833 struct pci_dev *dev) { }
1834 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
1839 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
1845 void __iomem *pcim_iomap(struct pci_dev *pdev, int bar, unsigned long maxlen);
1846 void pcim_iounmap(struct pci_dev *pdev, void __iomem *addr);
1847 void __iomem * const *pcim_iomap_table(struct pci_dev *pdev);
1848 int pcim_iomap_regions(struct pci_dev *pdev, int mask, const char *name);
1849 int pcim_iomap_regions_request_all(struct pci_dev *pdev, int mask,
1851 void pcim_iounmap_regions(struct pci_dev *pdev, int mask);
1853 extern int pci_pci_problems;
1854 #define PCIPCI_FAIL 1 /* No PCI PCI DMA */
1855 #define PCIPCI_TRITON 2
1856 #define PCIPCI_NATOMA 4
1857 #define PCIPCI_VIAETBF 8
1858 #define PCIPCI_VSFX 16
1859 #define PCIPCI_ALIMAGIK 32 /* Need low latency setting */
1860 #define PCIAGP_FAIL 64 /* No PCI to AGP DMA */
1862 extern unsigned long pci_cardbus_io_size;
1863 extern unsigned long pci_cardbus_mem_size;
1864 extern u8 pci_dfl_cache_line_size;
1865 extern u8 pci_cache_line_size;
1867 extern unsigned long pci_hotplug_io_size;
1868 extern unsigned long pci_hotplug_mem_size;
1869 extern unsigned long pci_hotplug_bus_size;
1871 /* Architecture-specific versions may override these (weak) */
1872 void pcibios_disable_device(struct pci_dev *dev);
1873 void pcibios_set_master(struct pci_dev *dev);
1874 int pcibios_set_pcie_reset_state(struct pci_dev *dev,
1875 enum pcie_reset_state state);
1876 int pcibios_add_device(struct pci_dev *dev);
1877 void pcibios_release_device(struct pci_dev *dev);
1878 void pcibios_penalize_isa_irq(int irq, int active);
1879 int pcibios_alloc_irq(struct pci_dev *dev);
1880 void pcibios_free_irq(struct pci_dev *dev);
1882 #ifdef CONFIG_HIBERNATE_CALLBACKS
1883 extern struct dev_pm_ops pcibios_pm_ops;
1886 #if defined(CONFIG_PCI_MMCONFIG) || defined(CONFIG_ACPI_MCFG)
1887 void __init pci_mmcfg_early_init(void);
1888 void __init pci_mmcfg_late_init(void);
1890 static inline void pci_mmcfg_early_init(void) { }
1891 static inline void pci_mmcfg_late_init(void) { }
1894 int pci_ext_cfg_avail(void);
1896 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar);
1897 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar);
1899 #ifdef CONFIG_PCI_IOV
1900 int pci_iov_virtfn_bus(struct pci_dev *dev, int id);
1901 int pci_iov_virtfn_devfn(struct pci_dev *dev, int id);
1903 int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn);
1904 void pci_disable_sriov(struct pci_dev *dev);
1905 int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset);
1906 void pci_iov_remove_virtfn(struct pci_dev *dev, int id, int reset);
1907 int pci_num_vf(struct pci_dev *dev);
1908 int pci_vfs_assigned(struct pci_dev *dev);
1909 int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs);
1910 int pci_sriov_get_totalvfs(struct pci_dev *dev);
1911 resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno);
1913 static inline int pci_iov_virtfn_bus(struct pci_dev *dev, int id)
1917 static inline int pci_iov_virtfn_devfn(struct pci_dev *dev, int id)
1921 static inline int pci_enable_sriov(struct pci_dev *dev, int nr_virtfn)
1923 static inline int pci_iov_add_virtfn(struct pci_dev *dev, int id, int reset)
1927 static inline void pci_iov_remove_virtfn(struct pci_dev *dev,
1928 int id, int reset) { }
1929 static inline void pci_disable_sriov(struct pci_dev *dev) { }
1930 static inline int pci_num_vf(struct pci_dev *dev) { return 0; }
1931 static inline int pci_vfs_assigned(struct pci_dev *dev)
1933 static inline int pci_sriov_set_totalvfs(struct pci_dev *dev, u16 numvfs)
1935 static inline int pci_sriov_get_totalvfs(struct pci_dev *dev)
1937 static inline resource_size_t pci_iov_resource_size(struct pci_dev *dev, int resno)
1941 #if defined(CONFIG_HOTPLUG_PCI) || defined(CONFIG_HOTPLUG_PCI_MODULE)
1942 void pci_hp_create_module_link(struct pci_slot *pci_slot);
1943 void pci_hp_remove_module_link(struct pci_slot *pci_slot);
1947 * pci_pcie_cap - get the saved PCIe capability offset
1950 * PCIe capability offset is calculated at PCI device initialization
1951 * time and saved in the data structure. This function returns saved
1952 * PCIe capability offset. Using this instead of pci_find_capability()
1953 * reduces unnecessary search in the PCI configuration space. If you
1954 * need to calculate PCIe capability offset from raw device for some
1955 * reasons, please use pci_find_capability() instead.
1957 static inline int pci_pcie_cap(struct pci_dev *dev)
1959 return dev->pcie_cap;
1963 * pci_is_pcie - check if the PCI device is PCI Express capable
1966 * Returns: true if the PCI device is PCI Express capable, false otherwise.
1968 static inline bool pci_is_pcie(struct pci_dev *dev)
1970 return pci_pcie_cap(dev);
1974 * pcie_caps_reg - get the PCIe Capabilities Register
1977 static inline u16 pcie_caps_reg(const struct pci_dev *dev)
1979 return dev->pcie_flags_reg;
1983 * pci_pcie_type - get the PCIe device/port type
1986 static inline int pci_pcie_type(const struct pci_dev *dev)
1988 return (pcie_caps_reg(dev) & PCI_EXP_FLAGS_TYPE) >> 4;
1991 static inline struct pci_dev *pcie_find_root_port(struct pci_dev *dev)
1994 if (!pci_is_pcie(dev))
1996 if (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT)
1998 if (!dev->bus->self)
2000 dev = dev->bus->self;
2005 void pci_request_acs(void);
2006 bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags);
2007 bool pci_acs_path_enabled(struct pci_dev *start,
2008 struct pci_dev *end, u16 acs_flags);
2010 #define PCI_VPD_LRDT 0x80 /* Large Resource Data Type */
2011 #define PCI_VPD_LRDT_ID(x) ((x) | PCI_VPD_LRDT)
2013 /* Large Resource Data Type Tag Item Names */
2014 #define PCI_VPD_LTIN_ID_STRING 0x02 /* Identifier String */
2015 #define PCI_VPD_LTIN_RO_DATA 0x10 /* Read-Only Data */
2016 #define PCI_VPD_LTIN_RW_DATA 0x11 /* Read-Write Data */
2018 #define PCI_VPD_LRDT_ID_STRING PCI_VPD_LRDT_ID(PCI_VPD_LTIN_ID_STRING)
2019 #define PCI_VPD_LRDT_RO_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RO_DATA)
2020 #define PCI_VPD_LRDT_RW_DATA PCI_VPD_LRDT_ID(PCI_VPD_LTIN_RW_DATA)
2022 /* Small Resource Data Type Tag Item Names */
2023 #define PCI_VPD_STIN_END 0x0f /* End */
2025 #define PCI_VPD_SRDT_END (PCI_VPD_STIN_END << 3)
2027 #define PCI_VPD_SRDT_TIN_MASK 0x78
2028 #define PCI_VPD_SRDT_LEN_MASK 0x07
2029 #define PCI_VPD_LRDT_TIN_MASK 0x7f
2031 #define PCI_VPD_LRDT_TAG_SIZE 3
2032 #define PCI_VPD_SRDT_TAG_SIZE 1
2034 #define PCI_VPD_INFO_FLD_HDR_SIZE 3
2036 #define PCI_VPD_RO_KEYWORD_PARTNO "PN"
2037 #define PCI_VPD_RO_KEYWORD_MFR_ID "MN"
2038 #define PCI_VPD_RO_KEYWORD_VENDOR0 "V0"
2039 #define PCI_VPD_RO_KEYWORD_CHKSUM "RV"
2042 * pci_vpd_lrdt_size - Extracts the Large Resource Data Type length
2043 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2045 * Returns the extracted Large Resource Data Type length.
2047 static inline u16 pci_vpd_lrdt_size(const u8 *lrdt)
2049 return (u16)lrdt[1] + ((u16)lrdt[2] << 8);
2053 * pci_vpd_lrdt_tag - Extracts the Large Resource Data Type Tag Item
2054 * @lrdt: Pointer to the beginning of the Large Resource Data Type tag
2056 * Returns the extracted Large Resource Data Type Tag item.
2058 static inline u16 pci_vpd_lrdt_tag(const u8 *lrdt)
2060 return (u16)(lrdt[0] & PCI_VPD_LRDT_TIN_MASK);
2064 * pci_vpd_srdt_size - Extracts the Small Resource Data Type length
2065 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2067 * Returns the extracted Small Resource Data Type length.
2069 static inline u8 pci_vpd_srdt_size(const u8 *srdt)
2071 return (*srdt) & PCI_VPD_SRDT_LEN_MASK;
2075 * pci_vpd_srdt_tag - Extracts the Small Resource Data Type Tag Item
2076 * @lrdt: Pointer to the beginning of the Small Resource Data Type tag
2078 * Returns the extracted Small Resource Data Type Tag Item.
2080 static inline u8 pci_vpd_srdt_tag(const u8 *srdt)
2082 return ((*srdt) & PCI_VPD_SRDT_TIN_MASK) >> 3;
2086 * pci_vpd_info_field_size - Extracts the information field length
2087 * @lrdt: Pointer to the beginning of an information field header
2089 * Returns the extracted information field length.
2091 static inline u8 pci_vpd_info_field_size(const u8 *info_field)
2093 return info_field[2];
2097 * pci_vpd_find_tag - Locates the Resource Data Type tag provided
2098 * @buf: Pointer to buffered vpd data
2099 * @off: The offset into the buffer at which to begin the search
2100 * @len: The length of the vpd buffer
2101 * @rdt: The Resource Data Type to search for
2103 * Returns the index where the Resource Data Type was found or
2104 * -ENOENT otherwise.
2106 int pci_vpd_find_tag(const u8 *buf, unsigned int off, unsigned int len, u8 rdt);
2109 * pci_vpd_find_info_keyword - Locates an information field keyword in the VPD
2110 * @buf: Pointer to buffered vpd data
2111 * @off: The offset into the buffer at which to begin the search
2112 * @len: The length of the buffer area, relative to off, in which to search
2113 * @kw: The keyword to search for
2115 * Returns the index where the information field keyword was found or
2116 * -ENOENT otherwise.
2118 int pci_vpd_find_info_keyword(const u8 *buf, unsigned int off,
2119 unsigned int len, const char *kw);
2121 /* PCI <-> OF binding helpers */
2125 void pci_set_of_node(struct pci_dev *dev);
2126 void pci_release_of_node(struct pci_dev *dev);
2127 void pci_set_bus_of_node(struct pci_bus *bus);
2128 void pci_release_bus_of_node(struct pci_bus *bus);
2129 struct irq_domain *pci_host_bridge_of_msi_domain(struct pci_bus *bus);
2131 /* Arch may override this (weak) */
2132 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus);
2134 static inline struct device_node *
2135 pci_device_to_OF_node(const struct pci_dev *pdev)
2137 return pdev ? pdev->dev.of_node : NULL;
2140 static inline struct device_node *pci_bus_to_OF_node(struct pci_bus *bus)
2142 return bus ? bus->dev.of_node : NULL;
2145 #else /* CONFIG_OF */
2146 static inline void pci_set_of_node(struct pci_dev *dev) { }
2147 static inline void pci_release_of_node(struct pci_dev *dev) { }
2148 static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
2149 static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
2150 static inline struct device_node *
2151 pci_device_to_OF_node(const struct pci_dev *pdev) { return NULL; }
2152 static inline struct irq_domain *
2153 pci_host_bridge_of_msi_domain(struct pci_bus *bus) { return NULL; }
2154 #endif /* CONFIG_OF */
2157 struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus);
2160 pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *));
2162 static inline struct irq_domain *
2163 pci_host_bridge_acpi_msi_domain(struct pci_bus *bus) { return NULL; }
2167 static inline struct eeh_dev *pci_dev_to_eeh_dev(struct pci_dev *pdev)
2169 return pdev->dev.archdata.edev;
2173 void pci_add_dma_alias(struct pci_dev *dev, u8 devfn);
2174 bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2);
2175 int pci_for_each_dma_alias(struct pci_dev *pdev,
2176 int (*fn)(struct pci_dev *pdev,
2177 u16 alias, void *data), void *data);
2179 /* helper functions for operation of device flag */
2180 static inline void pci_set_dev_assigned(struct pci_dev *pdev)
2182 pdev->dev_flags |= PCI_DEV_FLAGS_ASSIGNED;
2184 static inline void pci_clear_dev_assigned(struct pci_dev *pdev)
2186 pdev->dev_flags &= ~PCI_DEV_FLAGS_ASSIGNED;
2188 static inline bool pci_is_dev_assigned(struct pci_dev *pdev)
2190 return (pdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED) == PCI_DEV_FLAGS_ASSIGNED;
2194 * pci_ari_enabled - query ARI forwarding status
2197 * Returns true if ARI forwarding is enabled.
2199 static inline bool pci_ari_enabled(struct pci_bus *bus)
2201 return bus->self && bus->self->ari_enabled;
2205 * pci_is_thunderbolt_attached - whether device is on a Thunderbolt daisy chain
2206 * @pdev: PCI device to check
2208 * Walk upwards from @pdev and check for each encountered bridge if it's part
2209 * of a Thunderbolt controller. Reaching the host bridge means @pdev is not
2210 * Thunderbolt-attached. (But rather soldered to the mainboard usually.)
2212 static inline bool pci_is_thunderbolt_attached(struct pci_dev *pdev)
2214 struct pci_dev *parent = pdev;
2216 if (pdev->is_thunderbolt)
2219 while ((parent = pci_upstream_bridge(parent)))
2220 if (parent->is_thunderbolt)
2226 /* provide the legacy pci_dma_* API */
2227 #include <linux/pci-dma-compat.h>
2229 #endif /* LINUX_PCI_H */