/* * Copyright 2015 Lothar Waßmann * */ #include #include #include #include / { aliases { can0 = &can2; can1 = &can1; display = &display; i2c0 = &i2c_gpio; i2c1 = &i2c2; lcdif_23bit_pins_a = &pinctrl_disp0_1; lcdif_24bit_pins_a = &pinctrl_disp0_2; pwm0 = &pwm5; reg_can_xcvr = ®_can_xcvr; serial2 = &uart5; // spi0 = &ecspi2; spi0 = &spi_gpio; stk5led = &user_led; usbh1 = &usbotg2; usbotg = &usbotg1; }; chosen { stdout-path = &uart1; }; memory { reg = <0 0>; /* will be filled by U-Boot */ }; clocks { #address-cells = <1>; #size-cells = <0>; mclk: clock@0 { compatible = "fixed-clock"; reg = <0>; #clock-cells = <0>; clock-frequency = <27000000>; }; }; backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm5 0 500000 PWM_POLARITY_INVERTED>; power-supply = <®_3v3>; /* * a poor man's way to create a 1:1 relationship between * the PWM value and the actual duty cycle */ brightness-levels = < 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100>; default-brightness-level = <50>; }; gpio-keys { compatible = "gpio-keys"; }; i2c_gpio: i2c-gpio { compatible = "i2c-gpio"; #address-cells = <1>; #size-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c_gpio>; gpios = < &gpio5 1 GPIO_ACTIVE_HIGH /* SDA */ &gpio5 0 GPIO_ACTIVE_HIGH /* SCL */ >; clock-frequency = <400000>; status = "okay"; ds1339: rtc@68 { compatible = "dallas,ds1339"; reg = <0x68>; status = "disabled"; }; }; leds { compatible = "gpio-leds"; user_led: user { label = "Heartbeat"; gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_3v3_etn: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "3V3_ETN"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_etnphy_power>; gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_2v5: regulator@1 { compatible = "regulator-fixed"; reg = <1>; regulator-name = "2V5"; regulator-min-microvolt = <2500000>; regulator-max-microvolt = <2500000>; regulator-always-on; }; reg_3v3: regulator@2 { compatible = "regulator-fixed"; reg = <2>; regulator-name = "3V3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; reg_can_xcvr: regulator@3 { compatible = "regulator-fixed"; reg = <3>; regulator-name = "CAN XCVR"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan_xcvr>; gpio = <&gpio3 5 GPIO_ACTIVE_HIGH>; enable-active-low; }; reg_lcd_pwr: regulator@5 { compatible = "regulator-fixed"; reg = <5>; regulator-name = "LCD POWER"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lcd1_pwr>; gpio = <&gpio5 4 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-boot-on; regulator-always-on; }; reg_usbh1_vbus: regulator@6 { compatible = "regulator-fixed"; reg = <6>; regulator-name = "usbh1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbh1_vbus &pinctrl_usbh1_oc>; gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_usbotg_vbus: regulator@7 { compatible = "regulator-fixed"; reg = <7>; regulator-name = "usbotg_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg_vbus &pinctrl_usbotg_oc>; gpio = <&gpio1 26 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; spi_gpio: spi-gpio { #address-cells = <1>; #size-cells = <0>; compatible = "spi-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi_gpio>; gpio-mosi = <&gpio1 30 GPIO_ACTIVE_HIGH>; gpio-miso = <&gpio1 31 GPIO_ACTIVE_HIGH>; gpio-sck = <&gpio1 28 GPIO_ACTIVE_HIGH>; num-chipselects = <2>; cs-gpios = < &gpio1 29 GPIO_ACTIVE_HIGH &gpio1 10 GPIO_ACTIVE_HIGH >; status = "okay"; spidev0: spi@0 { compatible = "spidev"; reg = <0>; spi-max-frequency = <54000000>; }; spidev1: spi@1 { compatible = "spidev"; reg = <1>; spi-max-frequency = <54000000>; }; }; }; &can1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan1>; xceiver-supply = <®_can_xcvr>; status = "okay"; }; &can2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexcan2>; xceiver-supply = <®_can_xcvr>; status = "okay"; }; #if 0 &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; fsl,spi-num-chipselects = <2>; cs-gpios = < &gpio1 29 GPIO_ACTIVE_HIGH &gpio1 10 GPIO_ACTIVE_HIGH >; status = "okay"; spidev0: spi@0 { compatible = "spidev"; reg = <0>; spi-max-frequency = <54000000>; }; spidev1: spi@1 { compatible = "spidev"; reg = <1>; spi-max-frequency = <54000000>; }; }; #endif &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet_mdio>; phy-mode = "rmii"; phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>; phy-supply = <®_3v3_etn>; phy-handle = <&etnphy0>; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; etnphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; interrupt-parent = <&gpio5>; interrupts = <5>; status = "okay"; }; etnphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; status = "okay"; }; }; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_enet2>; phy-mode = "rmii"; phy-supply = <®_3v3_etn>; phy-handle = <&etnphy1>; status = "okay"; }; &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; nand-on-flash-bbt; fsl,no-blockmark-swap; status = "okay"; }; &i2c2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; clock-frequency = <400000>; status = "okay"; sgtl5000: sgtl5000@0a { compatible = "fsl,sgtl5000"; reg = <0x0a>; VDDA-supply = <®_2v5>; VDDIO-supply = <®_3v3>; clocks = <&mclk>; }; polytouch: edt-ft5x06@38 { compatible = "edt,edt-ft5x06"; reg = <0x38>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_edt_ft5x06>; interrupt-parent = <&gpio5>; interrupts = <2 IRQ_TYPE_EDGE_FALLING>; reset-gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; wake-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; linux,wakeup; }; touchscreen: tsc2007@48 { compatible = "ti,tsc2007"; reg = <0x48>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tsc2007>; interrupt-parent = <&gpio3>; interrupts = <26 0>; gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; ti,x-plate-ohms = <660>; linux,wakeup; }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; imx6qdl-tx6 { pinctrl_hog: hoggrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x0b0b0 /* LED */ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0 /* ETN PHY RESET */ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0 /* ETN PHY INT */ >; }; pinctrl_disp0_1: disp0grp-1 { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ /* PAD DISP0_DAT0 is used for the Flexcan transceiver control */ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 >; }; pinctrl_disp0_2: disp0grp-2 { fsl,pins = < MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x10 /* LSCLK */ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x10 /* OE_ACD */ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x10 /* HSYNC */ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x10 /* VSYNC */ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x10 MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x10 MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x10 MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x10 MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x10 MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x10 MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x10 MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x10 MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x10 MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x10 MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x10 MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x10 MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x10 MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x10 MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x10 MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x10 MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x10 MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x10 MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x10 MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x10 MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x10 MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x10 MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x10 MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x10 >; }; pinctrl_ecspi2: ecspi2grp { fsl,pins = < MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ MX6UL_PAD_UART5_TX_DATA__ECSPI2_MOSI 0x0b0b0 /* CSPI_MOSI */ MX6UL_PAD_UART5_RX_DATA__ECSPI2_MISO 0x0b0b0 /* CSPI_MISO */ MX6UL_PAD_UART4_TX_DATA__ECSPI2_SCLK 0x0b0b0 /* CSPI_SCLK */ >; }; pinctrl_edt_ft5x06: edt-ft5x06grp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x1b0b0 /* Interrupt */ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x1b0b0 /* Reset */ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x1b0b0 /* Wake */ >; }; pinctrl_enet1: enet1grp { fsl,pins = < MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x0b0b0 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x0b0b0 MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x0b0b0 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x0b0b0 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x0b0b0 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x0b0b0 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x0b0b0 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x40000031 >; }; pinctrl_enet2: enet2grp { fsl,pins = < MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x0b0b0 MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x0b0b0 MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x0b0b0 MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x0b0b0 MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x0b0b0 MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x0b0b0 MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x0b0b0 MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x40000031 >; }; pinctrl_enet_mdio: enet-mdiogrp { fsl,pins = < MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x0b0b0 MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 >; }; pinctrl_etnphy_power: etnphy-pwrgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0 /* ETN PHY POWER */ >; }; pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b0b0 MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b0b0 >; }; pinctrl_flexcan2: flexcan2grp { fsl,pins = < MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b0b0 MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b0b0 >; }; pinctrl_flexcan_xcvr: flexcan-xcvrgrp { fsl,pins = < MX6UL_PAD_LCD_DATA00__GPIO3_IO05 0x0b0b0 /* Flexcan XCVR enable */ >; }; pinctrl_gpmi_nand: gpminandgrp { fsl,pins = < MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0x0b0b1 MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0x0b0b1 MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0x0b0b1 MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0x0b000 MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0b0b1 MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0x0b0b1 MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0x0b0b1 MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0x0b0b1 MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0x0b0b1 MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0x0b0b1 MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0x0b0b1 MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0x0b0b1 MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0x0b0b1 MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0x0b0b1 MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0x0b0b1 >; }; pinctrl_i2c_gpio: i2c-gpiogrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x4001b8b1 /* I2C SCL */ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x4001b8b1 /* I2C SDA */ >; }; pinctrl_i2c2: i2c2grp { fsl,pins = < MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b1 MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b1 >; }; pinctrl_kpp: kppgrp { fsl,pins = < MX6UL_PAD_ENET2_RX_DATA1__KPP_COL04 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA0__KPP_COL05 0x1b0b0 MX6UL_PAD_ENET2_TX_EN__KPP_COL06 0x1b0b0 MX6UL_PAD_ENET2_RX_ER__KPP_COL07 0x1b0b0 MX6UL_PAD_ENET2_RX_DATA0__KPP_ROW04 0x1b0b0 MX6UL_PAD_ENET2_RX_EN__KPP_ROW05 0x1b0b0 MX6UL_PAD_ENET2_TX_DATA1__KPP_ROW06 0x1b0b0 MX6UL_PAD_ENET2_TX_CLK__KPP_ROW07 0x1b0b0 >; }; pinctrl_lcd1_pwr: lcd1-pwrgrp { fsl,pins = < MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0 /* LCD Power Enable */ >; }; pinctrl_pwm5: pwm5grp { fsl,pins = < MX6UL_PAD_NAND_DQS__PWM5_OUT 0x0b0b0 >; }; pinctrl_sai2: sai2grp { fsl,pins = < MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x0b0b0 /* SSI1_RXD */ MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x0b0b0 /* SSI1_TXD */ MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x0b0b0 /* SSI1_CLK */ MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x0b0b0 /* SSI1_FS */ >; }; pinctrl_spi_gpio: spi-gpiogrp { fsl,pins = < MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x0b0b0 /* CSPI_SS */ MX6UL_PAD_JTAG_MOD__GPIO1_IO10 0x0b0b0 /* CSPI_SS */ MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x0b0b0 /* CSPI_MOSI */ MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x0b0b0 /* CSPI_MISO */ MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x0b0b0 /* CSPI_SCLK */ >; }; pinctrl_tsc2007: tsc2007grp { fsl,pins = < MX6UL_PAD_JTAG_TMS__GPIO1_IO11 0x1b0b0 /* Interrupt */ >; }; pinctrl_uart1: uart1grp { fsl,pins = < MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x0b0b0 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x0b0b0 >; }; pinctrl_uart1_rtscts: uart1_rtsctsgrp { fsl,pins = < MX6UL_PAD_UART1_RTS_B__UART1_DCE_RTS 0x0b0b0 MX6UL_PAD_UART1_CTS_B__UART1_DCE_CTS 0x0b0b0 >; }; pinctrl_uart2: uart2grp { fsl,pins = < MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x0b0b0 MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x0b0b0 >; }; pinctrl_uart2_rtscts: uart2_rtsctsgrp { fsl,pins = < MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x0b0b0 MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x0b0b0 >; }; pinctrl_uart5: uart5grp { fsl,pins = < MX6UL_PAD_GPIO1_IO04__UART5_DCE_TX 0x0b0b0 MX6UL_PAD_GPIO1_IO05__UART5_DCE_RX 0x0b0b0 >; }; pinctrl_uart5_rtscts: uart5_rtsctsgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO08__UART5_DCE_RTS 0x0b0b0 MX6UL_PAD_GPIO1_IO09__UART5_DCE_CTS 0x0b0b0 >; }; pinctrl_usbh1_oc: usbh1-ocgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0x17059 /* USBH1_OC */ >; }; pinctrl_usbh1_vbus: usbh1-vbusgrp { fsl,pins = < MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0x0b0b0 /* USBH1_VBUSEN */ >; }; pinctrl_usbotg_oc: usbotg-ocgrp { fsl,pins = < MX6UL_PAD_UART3_RTS_B__GPIO1_IO27 0x17059 /* USBOTG_OC */ >; }; pinctrl_usbotg_vbus: usbotg-vbusgrp { fsl,pins = < MX6UL_PAD_UART3_CTS_B__GPIO1_IO26 0x1b0b0 /* USBOTG_VBUSEN */ >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x070b1 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x07099 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x070b1 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x070b1 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x070b1 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x070b1 /* SD1 CD */ MX6UL_PAD_NAND_CE1_B__GPIO4_IO14 0x170b0 /* SD1 CD */ >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x070b1 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x070b1 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x070b1 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x070b1 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x070b1 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x070b1 /* eMMC RESET */ MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x170b0 >; }; }; }; &kpp { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp>; /* sample keymap */ /* row/col 0,1 are mapped to KPP row/col 6,7 */ linux,keymap = < MATRIX_KEY(6, 6, KEY_POWER) /* 0x06060074 */ MATRIX_KEY(6, 7, KEY_KP0) /* 0x06070052 */ MATRIX_KEY(6, 2, KEY_KP1) /* 0x0602004f */ MATRIX_KEY(6, 3, KEY_KP2) /* 0x06030050 */ MATRIX_KEY(7, 6, KEY_KP3) /* 0x07060051 */ MATRIX_KEY(7, 7, KEY_KP4) /* 0x0707004b */ MATRIX_KEY(7, 2, KEY_KP5) /* 0x0702004c */ MATRIX_KEY(7, 3, KEY_KP6) /* 0x0703004d */ MATRIX_KEY(2, 6, KEY_KP7) /* 0x02060047 */ MATRIX_KEY(2, 7, KEY_KP8) /* 0x02070048 */ MATRIX_KEY(2, 2, KEY_KP9) /* 0x02020049 */ >; status = "okay"; }; &lcdif { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_disp0_1>; lcd-supply = <®_lcd_pwr>; display = <&display>; status = "okay"; display: display@di0 { bits-per-pixel = <32>; bus-width = <24>; status = "okay"; display-timings { VGA { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; hback-porch = <48>; hsync-len = <96>; hfront-porch = <16>; vback-porch = <31>; vsync-len = <2>; vfront-porch = <12>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ETV570 { clock-frequency = <25200000>; hactive = <640>; vactive = <480>; hback-porch = <114>; hsync-len = <30>; hfront-porch = <16>; vback-porch = <32>; vsync-len = <3>; vfront-porch = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ET0350 { clock-frequency = <6413760>; hactive = <320>; vactive = <240>; hback-porch = <34>; hsync-len = <34>; hfront-porch = <20>; vback-porch = <15>; vsync-len = <3>; vfront-porch = <4>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ET0430 { clock-frequency = <9009000>; hactive = <480>; vactive = <272>; hback-porch = <2>; hsync-len = <41>; hfront-porch = <2>; vback-porch = <2>; vsync-len = <10>; vfront-porch = <2>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <1>; }; ET0500 { clock-frequency = <33264000>; hactive = <800>; vactive = <480>; hback-porch = <88>; hsync-len = <128>; hfront-porch = <40>; vback-porch = <33>; vsync-len = <2>; vfront-porch = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ET0700 { /* same as ET0500 */ clock-frequency = <33264000>; hactive = <800>; vactive = <480>; hback-porch = <88>; hsync-len = <128>; hfront-porch = <40>; vback-porch = <33>; vsync-len = <2>; vfront-porch = <10>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; ETQ570 { clock-frequency = <6596040>; hactive = <320>; vactive = <240>; hback-porch = <38>; hsync-len = <30>; hfront-porch = <30>; vback-porch = <16>; vsync-len = <3>; vfront-porch = <4>; hsync-active = <0>; vsync-active = <0>; de-active = <1>; pixelclk-active = <0>; }; }; }; }; &pwm5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pwm5>; #pwm-cells = <3>; status = "okay"; }; &sai2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai2>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1 &pinctrl_uart1_rtscts>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart2 &pinctrl_uart2_rtscts>; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart5 &pinctrl_uart5_rtscts>; status = "okay"; }; &usbotg2 { vbus-supply = <®_usbh1_vbus>; dr_mode = "host"; disable-over-current; status = "okay"; }; &usbotg1 { vbus-supply = <®_usbotg_vbus>; dr_mode = "peripheral"; disable-over-current; status = "okay"; }; &usdhc1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc1>; bus-width = <4>; no-1-8-v; cd-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>; fsl,wp-controller; status = "okay"; };