memory: omap-gpmc: Implement IRQ domain for NAND IRQs

[karo-tx-linux.git] / Documentation / devicetree / bindings / bus / ti-gpmc.txt

diff --git a/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 01683707060bfdc60f2e4d2ebd9a6534c50d9658..13f13786f9927d768990f144d94d78f65cabce12 100644 (file)
--- a/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -32,6 +32,12 @@ Required properties:
                        bootloader) are used for the physical address decoding.
                        As this will change in the future, filling correct
                        values here is a requirement.
+ - interrupt-controller: The GPMC driver implements and interrupt controller for
+                       the NAND events "fifoevent" and "termcount".
+                       The interrupt number mapping is as follows
+                       0 - NAND_fifoevent
+                       1 - NAND_termcount
+ - interrupt-cells:    Must be set to 2
 
 Timing properties for child nodes. All are optional and default to 0.
 
@@ -130,6 +136,8 @@ Example for an AM33xx board:
                #address-cells = <2>;
                #size-cells = <1>;
                ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
+               interrupt-controller;
+               #interrupt-cells = <2>;
 
                /* child nodes go here */
        };