ARM: 8114/1: LPAE: load upper bits of early TTBR0/TTBR1

[karo-tx-linux.git] / arch / arm / mm / proc-v7-3level.S

diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 22e3ad63500c0e79f4eaf54555ca6c7aa13c57ff..1a24e9232ec8653b70dc163dd524cf1b6f85b951 100644 (file)
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -19,6 +19,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  */
+#include <asm/assembler.h>
 
 #define TTB_IRGN_NC    (0 << 8)
 #define TTB_IRGN_WBWA  (1 << 8)
@@ -61,7 +62,7 @@ ENTRY(cpu_v7_switch_mm)
        mcrr    p15, 0, rpgdl, rpgdh, c2                @ set TTB 0
        isb
 #endif
-       mov     pc, lr
+       ret     lr
 ENDPROC(cpu_v7_switch_mm)
 
 #ifdef __ARMEB__
@@ -86,13 +87,18 @@ ENTRY(cpu_v7_set_pte_ext)
        tst     rh, #1 << (57 - 32)             @ L_PTE_NONE
        bicne   rl, #L_PTE_VALID
        bne     1f
-       tst     rh, #1 << (55 - 32)             @ L_PTE_DIRTY
-       orreq   rl, #L_PTE_RDONLY
+
+       eor     ip, rh, #1 << (55 - 32) @ toggle L_PTE_DIRTY in temp reg to
+                                       @ test for !L_PTE_DIRTY || L_PTE_RDONLY
+       tst     ip, #1 << (55 - 32) | 1 << (58 - 32)
+       orrne   rl, #PTE_AP2
+       biceq   rl, #PTE_AP2
+
 1:     strd    r2, r3, [r0]
        ALT_SMP(W(nop))
        ALT_UP (mcr     p15, 0, r0, c7, c10, 1)         @ flush_pte
 #endif
-       mov     pc, lr
+       ret     lr
 ENDPROC(cpu_v7_set_pte_ext)
 
        /*
@@ -140,12 +146,11 @@ ENDPROC(cpu_v7_set_pte_ext)
        mov     \tmp, \ttbr1, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
        mov     \ttbr1, \ttbr1, lsl #ARCH_PGD_SHIFT             @ lower bits
        addls   \ttbr1, \ttbr1, #TTBR1_OFFSET
-       mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
+       adcls   \tmp, \tmp, #0
+       mcrr    p15, 1, \ttbr1, \tmp, c2                        @ load TTBR1
        mov     \tmp, \ttbr0, lsr #(32 - ARCH_PGD_SHIFT)        @ upper bits
        mov     \ttbr0, \ttbr0, lsl #ARCH_PGD_SHIFT             @ lower bits
-       mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
-       mcrr    p15, 1, \ttbr1, \zero, c2                       @ load TTBR1
-       mcrr    p15, 0, \ttbr0, \zero, c2                       @ load TTBR0
+       mcrr    p15, 0, \ttbr0, \tmp, c2                        @ load TTBR0
        .endm
 
        /*