Merge branch 'for-4.8/core' of git://git.kernel.dk/linux-block

[karo-tx-linux.git] / drivers / gpu / drm / amd / amdgpu / sdma_v2_4.c

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 6e0a86a563f3e8d35e7bf907bdaaa845aca5d55c..b556bd0a8797edce702d3c26ce78ff331ea82945 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -105,6 +105,15 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
        }
 }
 
+static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
+{
+       int i;
+       for (i = 0; i < adev->sdma.num_instances; i++) {
+               release_firmware(adev->sdma.instance[i].fw);
+               adev->sdma.instance[i].fw = NULL;
+       }
+}
+
 /**
  * sdma_v2_4_init_microcode - load ucode images from disk
  *
@@ -242,9 +251,10 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  * Schedule an IB in the DMA ring (VI).
  */
 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
-                                  struct amdgpu_ib *ib)
+                                  struct amdgpu_ib *ib,
+                                  unsigned vm_id, bool ctx_switch)
 {
-       u32 vmid = ib->vm_id & 0xf;
+       u32 vmid = vm_id & 0xf;
        u32 next_rptr = ring->wptr + 5;
 
        while ((next_rptr & 7) != 2)
@@ -460,6 +470,8 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
                /* Initialize the ring buffer's read and write pointers */
                WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
                WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
+               WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
+               WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 
                /* set the wb address whether it's enabled or not */
                WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
@@ -488,7 +500,11 @@ static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
                WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 
                ring->ready = true;
+       }
 
+       sdma_v2_4_enable(adev, true);
+       for (i = 0; i < adev->sdma.num_instances; i++) {
+               ring = &adev->sdma.instance[i].ring;
                r = amdgpu_ring_test_ring(ring);
                if (r) {
                        ring->ready = false;
@@ -579,8 +595,8 @@ static int sdma_v2_4_start(struct amdgpu_device *adev)
                        return -EINVAL;
        }
 
-       /* unhalt the MEs */
-       sdma_v2_4_enable(adev, true);
+       /* halt the engine before programing */
+       sdma_v2_4_enable(adev, false);
 
        /* start the gfx rings and rlc compute queues */
        r = sdma_v2_4_gfx_resume(adev);
@@ -701,7 +717,7 @@ static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring)
        ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
        ib.length_dw = 8;
 
-       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
        if (r)
                goto err1;
 
@@ -990,7 +1006,7 @@ static int sdma_v2_4_sw_init(void *handle)
                ring->ring_obj = NULL;
                ring->use_doorbell = false;
                sprintf(ring->name, "sdma%d", i);
-               r = amdgpu_ring_init(adev, ring, 256 * 1024,
+               r = amdgpu_ring_init(adev, ring, 1024,
                                     SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP), 0xf,
                                     &adev->sdma.trap_irq,
                                     (i == 0) ?
@@ -1011,6 +1027,7 @@ static int sdma_v2_4_sw_fini(void *handle)
        for (i = 0; i < adev->sdma.num_instances; i++)
                amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 
+       sdma_v2_4_free_microcode(adev);
        return 0;
 }
 
@@ -1080,55 +1097,6 @@ static int sdma_v2_4_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static void sdma_v2_4_print_status(void *handle)
-{
-       int i, j;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-
-       dev_info(adev->dev, "VI SDMA registers\n");
-       dev_info(adev->dev, "  SRBM_STATUS2=0x%08X\n",
-                RREG32(mmSRBM_STATUS2));
-       for (i = 0; i < adev->sdma.num_instances; i++) {
-               dev_info(adev->dev, "  SDMA%d_STATUS_REG=0x%08X\n",
-                        i, RREG32(mmSDMA0_STATUS_REG + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_F32_CNTL=0x%08X\n",
-                        i, RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_CNTL=0x%08X\n",
-                        i, RREG32(mmSDMA0_CNTL + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_SEM_WAIT_FAIL_TIMER_CNTL=0x%08X\n",
-                        i, RREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_IB_CNTL=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_RB_CNTL=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_RB_WPTR=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_HI=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_RB_RPTR_ADDR_LO=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_GFX_RB_BASE_HI=0x%08X\n",
-                        i, RREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i]));
-               dev_info(adev->dev, "  SDMA%d_TILING_CONFIG=0x%08X\n",
-                        i, RREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i]));
-               mutex_lock(&adev->srbm_mutex);
-               for (j = 0; j < 16; j++) {
-                       vi_srbm_select(adev, 0, 0, 0, j);
-                       dev_info(adev->dev, "  VM %d:\n", j);
-                       dev_info(adev->dev, "  SDMA%d_GFX_VIRTUAL_ADDR=0x%08X\n",
-                                i, RREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i]));
-                       dev_info(adev->dev, "  SDMA%d_GFX_APE1_CNTL=0x%08X\n",
-                                i, RREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i]));
-               }
-               vi_srbm_select(adev, 0, 0, 0, 0);
-               mutex_unlock(&adev->srbm_mutex);
-       }
-}
-
 static int sdma_v2_4_soft_reset(void *handle)
 {
        u32 srbm_soft_reset = 0;
@@ -1151,8 +1119,6 @@ static int sdma_v2_4_soft_reset(void *handle)
        }
 
        if (srbm_soft_reset) {
-               sdma_v2_4_print_status((void *)adev);
-
                tmp = RREG32(mmSRBM_SOFT_RESET);
                tmp |= srbm_soft_reset;
                dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
@@ -1167,8 +1133,6 @@ static int sdma_v2_4_soft_reset(void *handle)
 
                /* Wait a little for things to settle down */
                udelay(50);
-
-               sdma_v2_4_print_status((void *)adev);
        }
 
        return 0;
@@ -1283,6 +1247,7 @@ static int sdma_v2_4_set_powergating_state(void *handle,
 }
 
 const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
+       .name = "sdma_v2_4",
        .early_init = sdma_v2_4_early_init,
        .late_init = NULL,
        .sw_init = sdma_v2_4_sw_init,
@@ -1294,7 +1259,6 @@ const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
        .is_idle = sdma_v2_4_is_idle,
        .wait_for_idle = sdma_v2_4_wait_for_idle,
        .soft_reset = sdma_v2_4_soft_reset,
-       .print_status = sdma_v2_4_print_status,
        .set_clockgating_state = sdma_v2_4_set_clockgating_state,
        .set_powergating_state = sdma_v2_4_set_powergating_state,
 };