i2c: exynos5: simplify clock frequency handling

[karo-tx-linux.git] / drivers / i2c / busses / i2c-exynos5.c

diff --git a/drivers/i2c/busses/i2c-exynos5.c b/drivers/i2c/busses/i2c-exynos5.c
index 736a82472101733d7ada08b360c9f159c35371cb..3d21bc280927945a4f4aacf493a46ffcd20f0615 100644 (file)
--- a/drivers/i2c/busses/i2c-exynos5.c
+++ b/drivers/i2c/busses/i2c-exynos5.c
@@ -168,8 +168,6 @@
  */
 #define HSI2C_HS_TX_CLOCK      1000000
 #define HSI2C_FS_TX_CLOCK      100000
-#define HSI2C_HIGH_SPD         1
-#define HSI2C_FAST_SPD         0
 
 #define EXYNOS5_I2C_TIMEOUT (msecs_to_jiffies(1000))
 
@@ -200,15 +198,7 @@ struct exynos5_i2c {
        int                     trans_done;
 
        /* Controller operating frequency */
-       unsigned int            fs_clock;
-       unsigned int            hs_clock;
-
-       /*
-        * HSI2C Controller can operate in
-        * 1. High speed upto 3.4Mbps
-        * 2. Fast speed upto 1Mbps
-        */
-       int                     speed_mode;
+       unsigned int            op_clock;
 
        /* Version of HS-I2C Hardware */
        struct exynos_hsi2c_variant     *variant;
@@ -279,7 +269,7 @@ static void exynos5_i2c_clr_pend_irq(struct exynos5_i2c *i2c)
  * Returns 0 on success, -EINVAL if the cycle length cannot
  * be calculated.
  */
-static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
+static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, bool hs_timings)
 {
        u32 i2c_timing_s1;
        u32 i2c_timing_s2;
@@ -292,9 +282,10 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
        unsigned int t_sr_release;
        unsigned int t_ftl_cycle;
        unsigned int clkin = clk_get_rate(i2c->clk);
-       unsigned int div, utemp0 = 0, utemp1 = 0, clk_cycle;
-       unsigned int op_clk = (mode == HSI2C_HIGH_SPD) ?
-                               i2c->hs_clock : i2c->fs_clock;
+       unsigned int op_clk = hs_timings ? i2c->op_clock :
+               (i2c->op_clock >= HSI2C_HS_TX_CLOCK) ? HSI2C_FS_TX_CLOCK :
+               i2c->op_clock;
+       int div, clk_cycle, temp;
 
        /*
         * In case of HSI2C controller in Exynos5 series
@@ -305,33 +296,21 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
         * FPCLK / FI2C =
         * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + FLT_CYCLE
         *
-        * utemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
-        * utemp1 = (TSCLK_L + TSCLK_H + 2)
+        * clk_cycle := TSCLK_L + TSCLK_H
+        * temp := (CLK_DIV + 1) * (clk_cycle + 2)
+        *
+        * Constraints: 4 <= temp, 0 <= CLK_DIV < 256, 2 <= clk_cycle <= 510
+        *
         */
        t_ftl_cycle = (readl(i2c->regs + HSI2C_CONF) >> 16) & 0x7;
-       utemp0 = (clkin / op_clk) - 8;
-
-       if (i2c->variant->hw == HSI2C_EXYNOS7)
-               utemp0 -= t_ftl_cycle;
-       else
-               utemp0 -= 2 * t_ftl_cycle;
-
-       /* CLK_DIV max is 256 */
-       for (div = 0; div < 256; div++) {
-               utemp1 = utemp0 / (div + 1);
-
-               /*
-                * SCL_L and SCL_H each has max value of 255
-                * Hence, For the clk_cycle to the have right value
-                * utemp1 has to be less then 512 and more than 4.
-                */
-               if ((utemp1 < 512) && (utemp1 > 4)) {
-                       clk_cycle = utemp1 - 2;
-                       break;
-               } else if (div == 255) {
-                       dev_warn(i2c->dev, "Failed to calculate divisor");
-                       return -EINVAL;
-               }
+       temp = clkin / op_clk - 8 - t_ftl_cycle;
+       if (i2c->variant->hw != HSI2C_EXYNOS7)
+               temp -= t_ftl_cycle;
+       div = temp / 512;
+       clk_cycle = temp / (div + 1) - 2;
+       if (temp < 4 || div >= 256 || clk_cycle < 2) {
+               dev_warn(i2c->dev, "Failed to calculate divisor");
+               return -EINVAL;
        }
 
        t_scl_l = clk_cycle / 2;
@@ -356,7 +335,7 @@ static int exynos5_i2c_set_timing(struct exynos5_i2c *i2c, int mode)
                div, t_sr_release);
        dev_dbg(i2c->dev, "tDATA_HD: %X\n", t_data_hd);
 
-       if (mode == HSI2C_HIGH_SPD) {
+       if (hs_timings) {
                writel(i2c_timing_s1, i2c->regs + HSI2C_TIMING_HS1);
                writel(i2c_timing_s2, i2c->regs + HSI2C_TIMING_HS2);
                writel(i2c_timing_s3, i2c->regs + HSI2C_TIMING_HS3);
@@ -376,14 +355,14 @@ static int exynos5_hsi2c_clock_setup(struct exynos5_i2c *i2c)
         * Configure the Fast speed timing values
         * Even the High Speed mode initially starts with Fast mode
         */
-       if (exynos5_i2c_set_timing(i2c, HSI2C_FAST_SPD)) {
+       if (exynos5_i2c_set_timing(i2c, false)) {
                dev_err(i2c->dev, "HSI2C FS Clock set up failed\n");
                return -EINVAL;
        }
 
        /* configure the High speed timing values */
-       if (i2c->speed_mode == HSI2C_HIGH_SPD) {
-               if (exynos5_i2c_set_timing(i2c, HSI2C_HIGH_SPD)) {
+       if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
+               if (exynos5_i2c_set_timing(i2c, true)) {
                        dev_err(i2c->dev, "HSI2C HS Clock set up failed\n");
                        return -EINVAL;
                }
@@ -409,7 +388,7 @@ static void exynos5_i2c_init(struct exynos5_i2c *i2c)
                                        i2c->regs + HSI2C_CTL);
        writel(HSI2C_TRAILING_COUNT, i2c->regs + HSI2C_TRAILIG_CTL);
 
-       if (i2c->speed_mode == HSI2C_HIGH_SPD) {
+       if (i2c->op_clock >= HSI2C_HS_TX_CLOCK) {
                writel(HSI2C_MASTER_ID(MASTER_ID(i2c->adap.nr)),
                                        i2c->regs + HSI2C_ADDR);
                i2c_conf |= HSI2C_HS_MODE;
@@ -747,26 +726,14 @@ static int exynos5_i2c_probe(struct platform_device *pdev)
        struct device_node *np = pdev->dev.of_node;
        struct exynos5_i2c *i2c;
        struct resource *mem;
-       unsigned int op_clock;
        int ret;
 
        i2c = devm_kzalloc(&pdev->dev, sizeof(struct exynos5_i2c), GFP_KERNEL);
        if (!i2c)
                return -ENOMEM;
 
-       if (of_property_read_u32(np, "clock-frequency", &op_clock)) {
-               i2c->speed_mode = HSI2C_FAST_SPD;
-               i2c->fs_clock = HSI2C_FS_TX_CLOCK;
-       } else {
-               if (op_clock >= HSI2C_HS_TX_CLOCK) {
-                       i2c->speed_mode = HSI2C_HIGH_SPD;
-                       i2c->fs_clock = HSI2C_FS_TX_CLOCK;
-                       i2c->hs_clock = op_clock;
-               } else {
-                       i2c->speed_mode = HSI2C_FAST_SPD;
-                       i2c->fs_clock = op_clock;
-               }
-       }
+       if (of_property_read_u32(np, "clock-frequency", &i2c->op_clock))
+               i2c->op_clock = HSI2C_FS_TX_CLOCK;
 
        strlcpy(i2c->adap.name, "exynos5-i2c", sizeof(i2c->adap.name));
        i2c->adap.owner   = THIS_MODULE;