static void setDisplayControl(int ctrl, int disp_state)
{
/* state != 0 means turn on both timing & plane en_bit */
- unsigned long ulDisplayCtrlReg, ulReservedBits;
+ unsigned long reg, reserved;
int cnt;
cnt = 0;
/* Set the primary display control */
if (!ctrl) {
- ulDisplayCtrlReg = PEEK32(PANEL_DISPLAY_CTRL);
+ reg = PEEK32(PANEL_DISPLAY_CTRL);
/* Turn on/off the Panel display control */
if (disp_state) {
/* Timing should be enabled first before enabling the plane
* because changing at the same time does not guarantee that
* the plane will also enabled or disabled.
*/
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, TIMING, ENABLE);
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
+ POKE32(PANEL_DISPLAY_CTRL, reg);
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, PLANE, ENABLE);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
/* Added some masks to mask out the reserved bits.
* Sometimes, the reserved bits are set/reset randomly when
* writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
* reserved bits are needed to be masked out.
*/
- ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
- FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
- FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE);
+ reserved = PANEL_DISPLAY_CTRL_RESERVED_MASK;
/* Somehow the register value on the plane is not set
* until a few delay. Need to write
*/
do {
cnt++;
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
- } while ((PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) !=
- (ulDisplayCtrlReg & ~ulReservedBits));
+ POKE32(PANEL_DISPLAY_CTRL, reg);
+ } while ((PEEK32(PANEL_DISPLAY_CTRL) & ~reserved) !=
+ (reg & ~reserved));
printk("Set Panel Plane enbit:after tried %d times\n", cnt);
} else {
/* When turning off, there is no rule on the programming
* next vertical sync. Need to find out if it is necessary to
* wait for 1 vsync before modifying the timing enable bit.
* */
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, PLANE, DISABLE);
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
+ POKE32(PANEL_DISPLAY_CTRL, reg);
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- PANEL_DISPLAY_CTRL, TIMING, DISABLE);
- POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
+ POKE32(PANEL_DISPLAY_CTRL, reg);
}
} else {
/* Set the secondary display control */
- ulDisplayCtrlReg = PEEK32(CRT_DISPLAY_CTRL);
+ reg = PEEK32(CRT_DISPLAY_CTRL);
if (disp_state) {
/* Timing should be enabled first before enabling the plane because changing at the
same time does not guarantee that the plane will also enabled or disabled.
*/
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, TIMING, ENABLE);
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, ENABLE);
+ POKE32(CRT_DISPLAY_CTRL, reg);
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, PLANE, ENABLE);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, ENABLE);
/* Added some masks to mask out the reserved bits.
* Sometimes, the reserved bits are set/reset randomly when
* writing to the PRIMARY_DISPLAY_CTRL, therefore, the register
* reserved bits are needed to be masked out.
*/
-
- ulReservedBits = FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
- FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
- FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE) |
- FIELD_SET(0, CRT_DISPLAY_CTRL, RESERVED_4_MASK, ENABLE);
-
+ reserved = CRT_DISPLAY_CTRL_RESERVED_MASK;
do {
cnt++;
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
- } while ((PEEK32(CRT_DISPLAY_CTRL) & ~ulReservedBits) !=
- (ulDisplayCtrlReg & ~ulReservedBits));
+ POKE32(CRT_DISPLAY_CTRL, reg);
+ } while ((PEEK32(CRT_DISPLAY_CTRL) & ~reserved) !=
+ (reg & ~reserved));
printk("Set Crt Plane enbit:after tried %d times\n", cnt);
} else {
/* When turning off, there is no rule on the programming
* vertical sync. Need to find out if it is necessary to
* wait for 1 vsync before modifying the timing enable bit.
*/
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, PLANE, DISABLE);
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, PLANE, DISABLE);
+ POKE32(CRT_DISPLAY_CTRL, reg);
- ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
- CRT_DISPLAY_CTRL, TIMING, DISABLE);
- POKE32(CRT_DISPLAY_CTRL, ulDisplayCtrlReg);
+ reg = FIELD_SET(reg, DISPLAY_CTRL, TIMING, DISABLE);
+ POKE32(CRT_DISPLAY_CTRL, reg);
}
}
}
/* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */
- if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
- PANEL_PLL_CTRL_POWER_OFF) ||
- (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
- PANEL_DISPLAY_CTRL_TIMING_DISABLE)) {
+ if (!(PEEK32(PANEL_PLL_CTRL) & PLL_CTRL_POWER) ||
+ (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL),
+ DISPLAY_CTRL, TIMING) ==
+ DISPLAY_CTRL_TIMING_DISABLE)) {
return;
}
while (delay-- > 0) {
/* Wait for end of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- PANEL_VSYNC);
- } while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- PANEL_VSYNC);
- } while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
}
} else {
/* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */
- if ((FIELD_GET(PEEK32(CRT_PLL_CTRL), CRT_PLL_CTRL, POWER) ==
- CRT_PLL_CTRL_POWER_OFF) ||
- (FIELD_GET(PEEK32(CRT_DISPLAY_CTRL), CRT_DISPLAY_CTRL, TIMING) ==
- CRT_DISPLAY_CTRL_TIMING_DISABLE)) {
+ if (!(PEEK32(CRT_PLL_CTRL) & PLL_CTRL_POWER) ||
+ (FIELD_GET(PEEK32(CRT_DISPLAY_CTRL),
+ DISPLAY_CTRL, TIMING) ==
+ DISPLAY_CTRL_TIMING_DISABLE)) {
return;
}
while (delay-- > 0) {
/* Wait for end of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- CRT_VSYNC);
- } while (status == SYSTEM_CTRL_CRT_VSYNC_ACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */
do {
- status = FIELD_GET(PEEK32(SYSTEM_CTRL),
- SYSTEM_CTRL,
- CRT_VSYNC);
- } while (status == SYSTEM_CTRL_CRT_VSYNC_INACTIVE);
+ status = PEEK32(SYSTEM_CTRL);
+ } while (!(status & SYSTEM_CTRL_PANEL_VSYNC_ACTIVE));
}
}
}
projects / karo-tx-linux.git / blobdiff