#define PLL_CTRL_POWER BIT(17)
#define PLL_CTRL_INPUT BIT(16)
#ifdef VALIDATION_CHIP
- #define PLL_CTRL_OD 15:14
+ #define PLL_CTRL_OD_SHIFT 14
+ #define PLL_CTRL_OD_MASK (0x3 << 14)
#else
- #define PLL_CTRL_POD 15:14
- #define PLL_CTRL_OD 13:12
+ #define PLL_CTRL_POD_SHIFT 14
+ #define PLL_CTRL_POD_MASK (0x3 << 14)
+ #define PLL_CTRL_OD_SHIFT 12
+ #define PLL_CTRL_OD_MASK (0x3 << 12)
#endif
-#define PLL_CTRL_N 11:8
-#define PLL_CTRL_M 7:0
+#define PLL_CTRL_N_SHIFT 8
+#define PLL_CTRL_N_MASK (0xf << 8)
+#define PLL_CTRL_M_SHIFT 0
+#define PLL_CTRL_M_MASK 0xff
#define CRT_PLL_CTRL 0x000060
-#define CRT_PLL_CTRL_BYPASS 18:18
-#define CRT_PLL_CTRL_BYPASS_OFF 0
-#define CRT_PLL_CTRL_BYPASS_ON 1
-#define CRT_PLL_CTRL_POWER 17:17
-#define CRT_PLL_CTRL_POWER_OFF 0
-#define CRT_PLL_CTRL_POWER_ON 1
-#define CRT_PLL_CTRL_INPUT 16:16
-#define CRT_PLL_CTRL_INPUT_OSC 0
-#define CRT_PLL_CTRL_INPUT_TESTCLK 1
-#ifdef VALIDATION_CHIP
- #define CRT_PLL_CTRL_OD 15:14
-#else
- #define CRT_PLL_CTRL_POD 15:14
- #define CRT_PLL_CTRL_OD 13:12
-#endif
-#define CRT_PLL_CTRL_N 11:8
-#define CRT_PLL_CTRL_M 7:0
#define VGA_PLL0_CTRL 0x000064
-#define VGA_PLL0_CTRL_BYPASS 18:18
-#define VGA_PLL0_CTRL_BYPASS_OFF 0
-#define VGA_PLL0_CTRL_BYPASS_ON 1
-#define VGA_PLL0_CTRL_POWER 17:17
-#define VGA_PLL0_CTRL_POWER_OFF 0
-#define VGA_PLL0_CTRL_POWER_ON 1
-#define VGA_PLL0_CTRL_INPUT 16:16
-#define VGA_PLL0_CTRL_INPUT_OSC 0
-#define VGA_PLL0_CTRL_INPUT_TESTCLK 1
-#ifdef VALIDATION_CHIP
- #define VGA_PLL0_CTRL_OD 15:14
-#else
- #define VGA_PLL0_CTRL_POD 15:14
- #define VGA_PLL0_CTRL_OD 13:12
-#endif
-#define VGA_PLL0_CTRL_N 11:8
-#define VGA_PLL0_CTRL_M 7:0
#define VGA_PLL1_CTRL 0x000068
-#define VGA_PLL1_CTRL_BYPASS 18:18
-#define VGA_PLL1_CTRL_BYPASS_OFF 0
-#define VGA_PLL1_CTRL_BYPASS_ON 1
-#define VGA_PLL1_CTRL_POWER 17:17
-#define VGA_PLL1_CTRL_POWER_OFF 0
-#define VGA_PLL1_CTRL_POWER_ON 1
-#define VGA_PLL1_CTRL_INPUT 16:16
-#define VGA_PLL1_CTRL_INPUT_OSC 0
-#define VGA_PLL1_CTRL_INPUT_TESTCLK 1
-#ifdef VALIDATION_CHIP
- #define VGA_PLL1_CTRL_OD 15:14
-#else
- #define VGA_PLL1_CTRL_POD 15:14
- #define VGA_PLL1_CTRL_OD 13:12
-#endif
-#define VGA_PLL1_CTRL_N 11:8
-#define VGA_PLL1_CTRL_M 7:0
#define SCRATCH_DATA 0x00006c
#ifndef VALIDATION_CHIP
#define MXCLK_PLL_CTRL 0x000070
-#define MXCLK_PLL_CTRL_BYPASS 18:18
-#define MXCLK_PLL_CTRL_BYPASS_OFF 0
-#define MXCLK_PLL_CTRL_BYPASS_ON 1
-#define MXCLK_PLL_CTRL_POWER 17:17
-#define MXCLK_PLL_CTRL_POWER_OFF 0
-#define MXCLK_PLL_CTRL_POWER_ON 1
-#define MXCLK_PLL_CTRL_INPUT 16:16
-#define MXCLK_PLL_CTRL_INPUT_OSC 0
-#define MXCLK_PLL_CTRL_INPUT_TESTCLK 1
-#define MXCLK_PLL_CTRL_POD 15:14
-#define MXCLK_PLL_CTRL_OD 13:12
-#define MXCLK_PLL_CTRL_N 11:8
-#define MXCLK_PLL_CTRL_M 7:0
#define VGA_CONFIGURATION 0x000088
-#define VGA_CONFIGURATION_USER_DEFINE 5:4
-#define VGA_CONFIGURATION_PLL 2:2
-#define VGA_CONFIGURATION_PLL_VGA 0
-#define VGA_CONFIGURATION_PLL_PANEL 1
-#define VGA_CONFIGURATION_MODE 1:1
-#define VGA_CONFIGURATION_MODE_TEXT 0
-#define VGA_CONFIGURATION_MODE_GRAPHIC 1
+#define VGA_CONFIGURATION_USER_DEFINE_MASK (0x3 << 4)
+#define VGA_CONFIGURATION_PLL BIT(2)
+#define VGA_CONFIGURATION_MODE BIT(1)
#endif
#define PANEL_DISPLAY_CTRL 0x080000
-#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK 31:30
-#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0
-#define PANEL_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 3
-#define PANEL_DISPLAY_CTRL_SELECT 29:28
-#define PANEL_DISPLAY_CTRL_SELECT_PANEL 0
-#define PANEL_DISPLAY_CTRL_SELECT_VGA 1
-#define PANEL_DISPLAY_CTRL_SELECT_CRT 2
-#define PANEL_DISPLAY_CTRL_FPEN 27:27
-#define PANEL_DISPLAY_CTRL_FPEN_LOW 0
-#define PANEL_DISPLAY_CTRL_FPEN_HIGH 1
-#define PANEL_DISPLAY_CTRL_VBIASEN 26:26
-#define PANEL_DISPLAY_CTRL_VBIASEN_LOW 0
-#define PANEL_DISPLAY_CTRL_VBIASEN_HIGH 1
-#define PANEL_DISPLAY_CTRL_DATA 25:25
-#define PANEL_DISPLAY_CTRL_DATA_DISABLE 0
-#define PANEL_DISPLAY_CTRL_DATA_ENABLE 1
-#define PANEL_DISPLAY_CTRL_FPVDDEN 24:24
-#define PANEL_DISPLAY_CTRL_FPVDDEN_LOW 0
-#define PANEL_DISPLAY_CTRL_FPVDDEN_HIGH 1
-#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK 23:20
-#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0
-#define PANEL_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 15
-
-#define PANEL_DISPLAY_CTRL_TFT_DISP 19:18
-#define PANEL_DISPLAY_CTRL_TFT_DISP_24 0
-#define PANEL_DISPLAY_CTRL_TFT_DISP_36 1
-#define PANEL_DISPLAY_CTRL_TFT_DISP_18 2
-
-
-#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY 19:19
-#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_DISABLE 0
-#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY_ENABLE 1
-#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL 18:18
-#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_DISABLE 0
-#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL_ENABLE 1
-#define PANEL_DISPLAY_CTRL_FIFO 17:16
-#define PANEL_DISPLAY_CTRL_FIFO_1 0
-#define PANEL_DISPLAY_CTRL_FIFO_3 1
-#define PANEL_DISPLAY_CTRL_FIFO_7 2
-#define PANEL_DISPLAY_CTRL_FIFO_11 3
-#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK 15:15
-#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0
-#define PANEL_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1
-#define PANEL_DISPLAY_CTRL_CLOCK_PHASE 14:14
-#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0
-#define PANEL_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1
-#define PANEL_DISPLAY_CTRL_VSYNC_PHASE 13:13
-#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0
-#define PANEL_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1
-#define PANEL_DISPLAY_CTRL_HSYNC_PHASE 12:12
-#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0
-#define PANEL_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1
-#define PANEL_DISPLAY_CTRL_VSYNC 11:11
-#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_HIGH 0
-#define PANEL_DISPLAY_CTRL_VSYNC_ACTIVE_LOW 1
-#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING 10:10
-#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_DISABLE 0
-#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING_ENABLE 1
-#define PANEL_DISPLAY_CTRL_COLOR_KEY 9:9
-#define PANEL_DISPLAY_CTRL_COLOR_KEY_DISABLE 0
-#define PANEL_DISPLAY_CTRL_COLOR_KEY_ENABLE 1
-#define PANEL_DISPLAY_CTRL_TIMING 8:8
-#define PANEL_DISPLAY_CTRL_TIMING_DISABLE 0
-#define PANEL_DISPLAY_CTRL_TIMING_ENABLE 1
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR 7:7
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_DOWN 0
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR_UP 1
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN 6:6
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DISABLE 0
-#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_ENABLE 1
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR 5:5
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_RIGHT 0
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR_LEFT 1
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN 4:4
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DISABLE 0
-#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_ENABLE 1
-#define PANEL_DISPLAY_CTRL_GAMMA 3:3
-#define PANEL_DISPLAY_CTRL_GAMMA_DISABLE 0
-#define PANEL_DISPLAY_CTRL_GAMMA_ENABLE 1
-#define PANEL_DISPLAY_CTRL_PLANE 2:2
-#define PANEL_DISPLAY_CTRL_PLANE_DISABLE 0
-#define PANEL_DISPLAY_CTRL_PLANE_ENABLE 1
-#define PANEL_DISPLAY_CTRL_FORMAT 1:0
-#define PANEL_DISPLAY_CTRL_FORMAT_8 0
-#define PANEL_DISPLAY_CTRL_FORMAT_16 1
-#define PANEL_DISPLAY_CTRL_FORMAT_32 2
+#define PANEL_DISPLAY_CTRL_RESERVED_MASK 0xc0f08000
+#define PANEL_DISPLAY_CTRL_SELECT_SHIFT 28
+#define PANEL_DISPLAY_CTRL_SELECT_MASK (0x3 << 28)
+#define PANEL_DISPLAY_CTRL_SELECT_PANEL (0x0 << 28)
+#define PANEL_DISPLAY_CTRL_SELECT_VGA (0x1 << 28)
+#define PANEL_DISPLAY_CTRL_SELECT_CRT (0x2 << 28)
+#define PANEL_DISPLAY_CTRL_FPEN BIT(27)
+#define PANEL_DISPLAY_CTRL_VBIASEN BIT(26)
+#define PANEL_DISPLAY_CTRL_DATA BIT(25)
+#define PANEL_DISPLAY_CTRL_FPVDDEN BIT(24)
+#define PANEL_DISPLAY_CTRL_DUAL_DISPLAY BIT(19)
+#define PANEL_DISPLAY_CTRL_DOUBLE_PIXEL BIT(18)
+#define PANEL_DISPLAY_CTRL_FIFO (0x3 << 16)
+#define PANEL_DISPLAY_CTRL_FIFO_1 (0x0 << 16)
+#define PANEL_DISPLAY_CTRL_FIFO_3 (0x1 << 16)
+#define PANEL_DISPLAY_CTRL_FIFO_7 (0x2 << 16)
+#define PANEL_DISPLAY_CTRL_FIFO_11 (0x3 << 16)
+#define DISPLAY_CTRL_CLOCK_PHASE BIT(14)
+#define DISPLAY_CTRL_VSYNC_PHASE BIT(13)
+#define DISPLAY_CTRL_HSYNC_PHASE BIT(12)
+#define PANEL_DISPLAY_CTRL_VSYNC BIT(11)
+#define PANEL_DISPLAY_CTRL_CAPTURE_TIMING BIT(10)
+#define PANEL_DISPLAY_CTRL_COLOR_KEY BIT(9)
+#define DISPLAY_CTRL_TIMING BIT(8)
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN_DIR BIT(7)
+#define PANEL_DISPLAY_CTRL_VERTICAL_PAN BIT(6)
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN_DIR BIT(5)
+#define PANEL_DISPLAY_CTRL_HORIZONTAL_PAN BIT(4)
+#define DISPLAY_CTRL_GAMMA BIT(3)
+#define DISPLAY_CTRL_PLANE BIT(2)
+#define PANEL_DISPLAY_CTRL_FORMAT (0x3 << 0)
+#define PANEL_DISPLAY_CTRL_FORMAT_8 (0x0 << 0)
+#define PANEL_DISPLAY_CTRL_FORMAT_16 (0x1 << 0)
+#define PANEL_DISPLAY_CTRL_FORMAT_32 (0x2 << 0)
#define PANEL_PAN_CTRL 0x080004
#define PANEL_PAN_CTRL_VERTICAL_PAN 31:24
#define PANEL_COLOR_KEY_VALUE 15:0
#define PANEL_FB_ADDRESS 0x08000C
-#define PANEL_FB_ADDRESS_STATUS 31:31
-#define PANEL_FB_ADDRESS_STATUS_CURRENT 0
-#define PANEL_FB_ADDRESS_STATUS_PENDING 1
-#define PANEL_FB_ADDRESS_EXT 27:27
-#define PANEL_FB_ADDRESS_EXT_LOCAL 0
-#define PANEL_FB_ADDRESS_EXT_EXTERNAL 1
-#define PANEL_FB_ADDRESS_ADDRESS 25:0
+#define PANEL_FB_ADDRESS_STATUS BIT(31)
+#define PANEL_FB_ADDRESS_EXT BIT(27)
+#define PANEL_FB_ADDRESS_ADDRESS_MASK 0x1ffffff
#define PANEL_FB_WIDTH 0x080010
-#define PANEL_FB_WIDTH_WIDTH 29:16
-#define PANEL_FB_WIDTH_OFFSET 13:0
+#define PANEL_FB_WIDTH_WIDTH_SHIFT 16
+#define PANEL_FB_WIDTH_WIDTH_MASK (0x3fff << 16)
+#define PANEL_FB_WIDTH_OFFSET_MASK 0x3fff
#define PANEL_WINDOW_WIDTH 0x080014
-#define PANEL_WINDOW_WIDTH_WIDTH 27:16
-#define PANEL_WINDOW_WIDTH_X 11:0
+#define PANEL_WINDOW_WIDTH_WIDTH_SHIFT 16
+#define PANEL_WINDOW_WIDTH_WIDTH_MASK (0xfff << 16)
+#define PANEL_WINDOW_WIDTH_X_MASK 0xfff
#define PANEL_WINDOW_HEIGHT 0x080018
-#define PANEL_WINDOW_HEIGHT_HEIGHT 27:16
-#define PANEL_WINDOW_HEIGHT_Y 11:0
+#define PANEL_WINDOW_HEIGHT_HEIGHT_SHIFT 16
+#define PANEL_WINDOW_HEIGHT_HEIGHT_MASK (0xfff << 16)
+#define PANEL_WINDOW_HEIGHT_Y_MASK 0xfff
#define PANEL_PLANE_TL 0x08001C
-#define PANEL_PLANE_TL_TOP 26:16
-#define PANEL_PLANE_TL_LEFT 10:0
+#define PANEL_PLANE_TL_TOP_SHIFT 16
+#define PANEL_PLANE_TL_TOP_MASK (0xeff << 16)
+#define PANEL_PLANE_TL_LEFT_MASK 0xeff
#define PANEL_PLANE_BR 0x080020
-#define PANEL_PLANE_BR_BOTTOM 26:16
-#define PANEL_PLANE_BR_RIGHT 10:0
+#define PANEL_PLANE_BR_BOTTOM_SHIFT 16
+#define PANEL_PLANE_BR_BOTTOM_MASK (0xeff << 16)
+#define PANEL_PLANE_BR_RIGHT_MASK 0xeff
#define PANEL_HORIZONTAL_TOTAL 0x080024
-#define PANEL_HORIZONTAL_TOTAL_TOTAL 27:16
-#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END 11:0
+#define PANEL_HORIZONTAL_TOTAL_TOTAL_SHIFT 16
+#define PANEL_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16)
+#define PANEL_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff
#define PANEL_HORIZONTAL_SYNC 0x080028
-#define PANEL_HORIZONTAL_SYNC_WIDTH 23:16
-#define PANEL_HORIZONTAL_SYNC_START 11:0
+#define PANEL_HORIZONTAL_SYNC_WIDTH_SHIFT 16
+#define PANEL_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16)
+#define PANEL_HORIZONTAL_SYNC_START_MASK 0xfff
#define PANEL_VERTICAL_TOTAL 0x08002C
-#define PANEL_VERTICAL_TOTAL_TOTAL 26:16
-#define PANEL_VERTICAL_TOTAL_DISPLAY_END 10:0
+#define PANEL_VERTICAL_TOTAL_TOTAL_SHIFT 16
+#define PANEL_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16)
+#define PANEL_VERTICAL_TOTAL_DISPLAY_END_MASK 0x7ff
#define PANEL_VERTICAL_SYNC 0x080030
-#define PANEL_VERTICAL_SYNC_HEIGHT 21:16
-#define PANEL_VERTICAL_SYNC_START 10:0
+#define PANEL_VERTICAL_SYNC_HEIGHT_SHIFT 16
+#define PANEL_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16)
+#define PANEL_VERTICAL_SYNC_START_MASK 0x7ff
#define PANEL_CURRENT_LINE 0x080034
#define PANEL_CURRENT_LINE_LINE 10:0
#define VIDEO_DISPLAY_CTRL_GAMMA 3:3
#define VIDEO_DISPLAY_CTRL_GAMMA_DISABLE 0
#define VIDEO_DISPLAY_CTRL_GAMMA_ENABLE 1
-#define VIDEO_DISPLAY_CTRL_PLANE 2:2
-#define VIDEO_DISPLAY_CTRL_PLANE_DISABLE 0
-#define VIDEO_DISPLAY_CTRL_PLANE_ENABLE 1
#define VIDEO_DISPLAY_CTRL_FORMAT 1:0
#define VIDEO_DISPLAY_CTRL_FORMAT_8 0
#define VIDEO_DISPLAY_CTRL_FORMAT_16 1
#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3
#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0
#define VIDEO_ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1
-#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE 2:2
-#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0
-#define VIDEO_ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1
#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT 1:0
#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_8 0
#define VIDEO_ALPHA_DISPLAY_CTRL_FORMAT_16 1
#define ALPHA_DISPLAY_CTRL_CHROMA_KEY 3:3
#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_DISABLE 0
#define ALPHA_DISPLAY_CTRL_CHROMA_KEY_ENABLE 1
-#define ALPHA_DISPLAY_CTRL_PLANE 2:2
-#define ALPHA_DISPLAY_CTRL_PLANE_DISABLE 0
-#define ALPHA_DISPLAY_CTRL_PLANE_ENABLE 1
#define ALPHA_DISPLAY_CTRL_FORMAT 1:0
#define ALPHA_DISPLAY_CTRL_FORMAT_16 1
#define ALPHA_DISPLAY_CTRL_FORMAT_ALPHA_4_4 2
/* CRT Graphics Control */
#define CRT_DISPLAY_CTRL 0x080200
-#define CRT_DISPLAY_CTRL_RESERVED_1_MASK 31:27
-#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0
-#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 0x1F
+#define CRT_DISPLAY_CTRL_RESERVED_MASK 0xfb008200
/* SM750LE definition */
-#define CRT_DISPLAY_CTRL_DPMS 31:30
-#define CRT_DISPLAY_CTRL_DPMS_0 0
-#define CRT_DISPLAY_CTRL_DPMS_1 1
-#define CRT_DISPLAY_CTRL_DPMS_2 2
-#define CRT_DISPLAY_CTRL_DPMS_3 3
-#define CRT_DISPLAY_CTRL_CLK 29:27
-#define CRT_DISPLAY_CTRL_CLK_PLL25 0
-#define CRT_DISPLAY_CTRL_CLK_PLL41 1
-#define CRT_DISPLAY_CTRL_CLK_PLL62 2
-#define CRT_DISPLAY_CTRL_CLK_PLL65 3
-#define CRT_DISPLAY_CTRL_CLK_PLL74 4
-#define CRT_DISPLAY_CTRL_CLK_PLL80 5
-#define CRT_DISPLAY_CTRL_CLK_PLL108 6
-#define CRT_DISPLAY_CTRL_CLK_RESERVED 7
-#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26
-#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1
-#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0
-
-
-#define CRT_DISPLAY_CTRL_RESERVED_2_MASK 25:24
-#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 3
-#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0
+#define CRT_DISPLAY_CTRL_DPMS_SHIFT 30
+#define CRT_DISPLAY_CTRL_DPMS_MASK (0x3 << 30)
+#define CRT_DISPLAY_CTRL_DPMS_0 (0x0 << 30)
+#define CRT_DISPLAY_CTRL_DPMS_1 (0x1 << 30)
+#define CRT_DISPLAY_CTRL_DPMS_2 (0x2 << 30)
+#define CRT_DISPLAY_CTRL_DPMS_3 (0x3 << 30)
+#define CRT_DISPLAY_CTRL_CLK_MASK (0x7 << 27)
+#define CRT_DISPLAY_CTRL_CLK_PLL25 (0x0 << 27)
+#define CRT_DISPLAY_CTRL_CLK_PLL41 (0x1 << 27)
+#define CRT_DISPLAY_CTRL_CLK_PLL62 (0x2 << 27)
+#define CRT_DISPLAY_CTRL_CLK_PLL65 (0x3 << 27)
+#define CRT_DISPLAY_CTRL_CLK_PLL74 (0x4 << 27)
+#define CRT_DISPLAY_CTRL_CLK_PLL80 (0x5 << 27)
+#define CRT_DISPLAY_CTRL_CLK_PLL108 (0x6 << 27)
+#define CRT_DISPLAY_CTRL_CLK_RESERVED (0x7 << 27)
+#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC BIT(26)
/* SM750LE definition */
-#define CRT_DISPLAY_CTRL_CRTSELECT 25:25
-#define CRT_DISPLAY_CTRL_CRTSELECT_VGA 0
-#define CRT_DISPLAY_CTRL_CRTSELECT_CRT 1
-#define CRT_DISPLAY_CTRL_RGBBIT 24:24
-#define CRT_DISPLAY_CTRL_RGBBIT_24BIT 0
-#define CRT_DISPLAY_CTRL_RGBBIT_12BIT 1
-
-
-#define CRT_DISPLAY_CTRL_RESERVED_3_MASK 15:15
-#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0
-#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1
-
-#define CRT_DISPLAY_CTRL_RESERVED_4_MASK 9:9
-#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_DISABLE 0
-#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_ENABLE 1
+#define CRT_DISPLAY_CTRL_CRTSELECT BIT(25)
+#define CRT_DISPLAY_CTRL_RGBBIT BIT(24)
#ifndef VALIDATION_CHIP
- #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC 26:26
- #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_DISABLE 1
- #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0
- #define CRT_DISPLAY_CTRL_CENTERING 24:24
- #define CRT_DISPLAY_CTRL_CENTERING_DISABLE 0
- #define CRT_DISPLAY_CTRL_CENTERING_ENABLE 1
+ #define CRT_DISPLAY_CTRL_CENTERING BIT(24)
#endif
-#define CRT_DISPLAY_CTRL_LOCK_TIMING 23:23
-#define CRT_DISPLAY_CTRL_LOCK_TIMING_DISABLE 0
-#define CRT_DISPLAY_CTRL_LOCK_TIMING_ENABLE 1
-#define CRT_DISPLAY_CTRL_EXPANSION 22:22
-#define CRT_DISPLAY_CTRL_EXPANSION_DISABLE 0
-#define CRT_DISPLAY_CTRL_EXPANSION_ENABLE 1
-#define CRT_DISPLAY_CTRL_VERTICAL_MODE 21:21
-#define CRT_DISPLAY_CTRL_VERTICAL_MODE_REPLICATE 0
-#define CRT_DISPLAY_CTRL_VERTICAL_MODE_INTERPOLATE 1
-#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE 20:20
-#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_REPLICATE 0
-#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE_INTERPOLATE 1
-#define CRT_DISPLAY_CTRL_SELECT 19:18
-#define CRT_DISPLAY_CTRL_SELECT_PANEL 0
-#define CRT_DISPLAY_CTRL_SELECT_VGA 1
-#define CRT_DISPLAY_CTRL_SELECT_CRT 2
-#define CRT_DISPLAY_CTRL_FIFO 17:16
-#define CRT_DISPLAY_CTRL_FIFO_1 0
-#define CRT_DISPLAY_CTRL_FIFO_3 1
-#define CRT_DISPLAY_CTRL_FIFO_7 2
-#define CRT_DISPLAY_CTRL_FIFO_11 3
-#define CRT_DISPLAY_CTRL_CLOCK_PHASE 14:14
-#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_HIGH 0
-#define CRT_DISPLAY_CTRL_CLOCK_PHASE_ACTIVE_LOW 1
-#define CRT_DISPLAY_CTRL_VSYNC_PHASE 13:13
-#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_HIGH 0
-#define CRT_DISPLAY_CTRL_VSYNC_PHASE_ACTIVE_LOW 1
-#define CRT_DISPLAY_CTRL_HSYNC_PHASE 12:12
-#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_HIGH 0
-#define CRT_DISPLAY_CTRL_HSYNC_PHASE_ACTIVE_LOW 1
-#define CRT_DISPLAY_CTRL_BLANK 10:10
-#define CRT_DISPLAY_CTRL_BLANK_OFF 0
-#define CRT_DISPLAY_CTRL_BLANK_ON 1
-#define CRT_DISPLAY_CTRL_TIMING 8:8
-#define CRT_DISPLAY_CTRL_TIMING_DISABLE 0
-#define CRT_DISPLAY_CTRL_TIMING_ENABLE 1
-#define CRT_DISPLAY_CTRL_PIXEL 7:4
-#define CRT_DISPLAY_CTRL_GAMMA 3:3
-#define CRT_DISPLAY_CTRL_GAMMA_DISABLE 0
-#define CRT_DISPLAY_CTRL_GAMMA_ENABLE 1
-#define CRT_DISPLAY_CTRL_PLANE 2:2
-#define CRT_DISPLAY_CTRL_PLANE_DISABLE 0
-#define CRT_DISPLAY_CTRL_PLANE_ENABLE 1
-#define CRT_DISPLAY_CTRL_FORMAT 1:0
-#define CRT_DISPLAY_CTRL_FORMAT_8 0
-#define CRT_DISPLAY_CTRL_FORMAT_16 1
-#define CRT_DISPLAY_CTRL_FORMAT_32 2
-#define CRT_DISPLAY_CTRL_RESERVED_BITS_MASK 0xFF000200
+#define CRT_DISPLAY_CTRL_LOCK_TIMING BIT(23)
+#define CRT_DISPLAY_CTRL_EXPANSION BIT(22)
+#define CRT_DISPLAY_CTRL_VERTICAL_MODE BIT(21)
+#define CRT_DISPLAY_CTRL_HORIZONTAL_MODE BIT(20)
+#define CRT_DISPLAY_CTRL_SELECT_SHIFT 18
+#define CRT_DISPLAY_CTRL_SELECT_MASK (0x3 << 18)
+#define CRT_DISPLAY_CTRL_SELECT_PANEL (0x0 << 18)
+#define CRT_DISPLAY_CTRL_SELECT_VGA (0x1 << 18)
+#define CRT_DISPLAY_CTRL_SELECT_CRT (0x2 << 18)
+#define CRT_DISPLAY_CTRL_FIFO_MASK (0x3 << 16)
+#define CRT_DISPLAY_CTRL_FIFO_1 (0x0 << 16)
+#define CRT_DISPLAY_CTRL_FIFO_3 (0x1 << 16)
+#define CRT_DISPLAY_CTRL_FIFO_7 (0x2 << 16)
+#define CRT_DISPLAY_CTRL_FIFO_11 (0x3 << 16)
+#define CRT_DISPLAY_CTRL_BLANK BIT(10)
+#define CRT_DISPLAY_CTRL_PIXEL_MASK (0xf << 4)
+#define CRT_DISPLAY_CTRL_FORMAT_MASK (0x3 << 0)
+#define CRT_DISPLAY_CTRL_FORMAT_8 (0x0 << 0)
+#define CRT_DISPLAY_CTRL_FORMAT_16 (0x1 << 0)
+#define CRT_DISPLAY_CTRL_FORMAT_32 (0x2 << 0)
#define CRT_FB_ADDRESS 0x080204
#define CRT_FB_ADDRESS_STATUS 31:31
#define CRT_FB_WIDTH_OFFSET 13:0
#define CRT_HORIZONTAL_TOTAL 0x08020C
-#define CRT_HORIZONTAL_TOTAL_TOTAL 27:16
-#define CRT_HORIZONTAL_TOTAL_DISPLAY_END 11:0
+#define CRT_HORIZONTAL_TOTAL_TOTAL_SHIFT 16
+#define CRT_HORIZONTAL_TOTAL_TOTAL_MASK (0xfff << 16)
+#define CRT_HORIZONTAL_TOTAL_DISPLAY_END_MASK 0xfff
#define CRT_HORIZONTAL_SYNC 0x080210
-#define CRT_HORIZONTAL_SYNC_WIDTH 23:16
-#define CRT_HORIZONTAL_SYNC_START 11:0
+#define CRT_HORIZONTAL_SYNC_WIDTH_SHIFT 16
+#define CRT_HORIZONTAL_SYNC_WIDTH_MASK (0xff << 16)
+#define CRT_HORIZONTAL_SYNC_START_MASK 0xfff
#define CRT_VERTICAL_TOTAL 0x080214
-#define CRT_VERTICAL_TOTAL_TOTAL 26:16
-#define CRT_VERTICAL_TOTAL_DISPLAY_END 10:0
+#define CRT_VERTICAL_TOTAL_TOTAL_SHIFT 16
+#define CRT_VERTICAL_TOTAL_TOTAL_MASK (0x7ff << 16)
+#define CRT_VERTICAL_TOTAL_DISPLAY_END_MASK (0x7ff)
#define CRT_VERTICAL_SYNC 0x080218
-#define CRT_VERTICAL_SYNC_HEIGHT 21:16
-#define CRT_VERTICAL_SYNC_START 10:0
+#define CRT_VERTICAL_SYNC_HEIGHT_SHIFT 16
+#define CRT_VERTICAL_SYNC_HEIGHT_MASK (0x3f << 16)
+#define CRT_VERTICAL_SYNC_START_MASK 0x7ff
#define CRT_SIGNATURE_ANALYZER 0x08021C
#define CRT_SIGNATURE_ANALYZER_STATUS 31:16
#ifndef VALIDATION_CHIP
/* Auto Centering */
#define CRT_AUTO_CENTERING_TL 0x080280
- #define CRT_AUTO_CENTERING_TL_TOP 26:16
- #define CRT_AUTO_CENTERING_TL_LEFT 10:0
+ #define CRT_AUTO_CENTERING_TL_TOP_MASK (0x7ff << 16)
+ #define CRT_AUTO_CENTERING_TL_LEFT_MASK 0x7ff
#define CRT_AUTO_CENTERING_BR 0x080284
- #define CRT_AUTO_CENTERING_BR_BOTTOM 26:16
- #define CRT_AUTO_CENTERING_BR_RIGHT 10:0
+ #define CRT_AUTO_CENTERING_BR_BOTTOM_MASK (0x7ff << 16)
+ #define CRT_AUTO_CENTERING_BR_BOTTOM_SHIFT 16
+ #define CRT_AUTO_CENTERING_BR_RIGHT_MASK 0x7ff
#endif
/* sm750le new register to control panel output */
#define I2C_BYTE_COUNT_COUNT 3:0
#define I2C_CTRL 0x010041
-#define I2C_CTRL_INT 4:4
-#define I2C_CTRL_INT_DISABLE 0
-#define I2C_CTRL_INT_ENABLE 1
-#define I2C_CTRL_DIR 3:3
-#define I2C_CTRL_DIR_WR 0
-#define I2C_CTRL_DIR_RD 1
-#define I2C_CTRL_CTRL 2:2
-#define I2C_CTRL_CTRL_STOP 0
-#define I2C_CTRL_CTRL_START 1
-#define I2C_CTRL_MODE 1:1
-#define I2C_CTRL_MODE_STANDARD 0
-#define I2C_CTRL_MODE_FAST 1
-#define I2C_CTRL_EN 0:0
-#define I2C_CTRL_EN_DISABLE 0
-#define I2C_CTRL_EN_ENABLE 1
+#define I2C_CTRL_INT BIT(4)
+#define I2C_CTRL_DIR BIT(3)
+#define I2C_CTRL_CTRL BIT(2)
+#define I2C_CTRL_MODE BIT(1)
+#define I2C_CTRL_EN BIT(0)
#define I2C_STATUS 0x010042
-#define I2C_STATUS_TX 3:3
-#define I2C_STATUS_TX_PROGRESS 0
-#define I2C_STATUS_TX_COMPLETED 1
-#define I2C_TX_DONE 0x08
-#define I2C_STATUS_ERR 2:2
-#define I2C_STATUS_ERR_NORMAL 0
-#define I2C_STATUS_ERR_ERROR 1
-#define I2C_STATUS_ERR_CLEAR 0
-#define I2C_STATUS_ACK 1:1
-#define I2C_STATUS_ACK_RECEIVED 0
-#define I2C_STATUS_ACK_NOT 1
-#define I2C_STATUS_BSY 0:0
-#define I2C_STATUS_BSY_IDLE 0
-#define I2C_STATUS_BSY_BUSY 1
+#define I2C_STATUS_TX BIT(3)
+#define I2C_STATUS_ERR BIT(2)
+#define I2C_STATUS_ACK BIT(1)
+#define I2C_STATUS_BSY BIT(0)
#define I2C_RESET 0x010042
#define I2C_RESET_BUS_ERROR 2:2
#define DMA_1_SIZE_CONTROL_SIZE 23:0
#define DMA_ABORT_INTERRUPT 0x0D0020
-#define DMA_ABORT_INTERRUPT_ABORT_1 5:5
-#define DMA_ABORT_INTERRUPT_ABORT_1_ENABLE 0
-#define DMA_ABORT_INTERRUPT_ABORT_1_ABORT 1
-#define DMA_ABORT_INTERRUPT_ABORT_0 4:4
-#define DMA_ABORT_INTERRUPT_ABORT_0_ENABLE 0
-#define DMA_ABORT_INTERRUPT_ABORT_0_ABORT 1
-#define DMA_ABORT_INTERRUPT_INT_1 1:1
-#define DMA_ABORT_INTERRUPT_INT_1_CLEAR 0
-#define DMA_ABORT_INTERRUPT_INT_1_FINISHED 1
-#define DMA_ABORT_INTERRUPT_INT_0 0:0
-#define DMA_ABORT_INTERRUPT_INT_0_CLEAR 0
-#define DMA_ABORT_INTERRUPT_INT_0_FINISHED 1
-
-
-
-
+#define DMA_ABORT_INTERRUPT_ABORT_1 BIT(5)
+#define DMA_ABORT_INTERRUPT_ABORT_0 BIT(4)
+#define DMA_ABORT_INTERRUPT_INT_1 BIT(1)
+#define DMA_ABORT_INTERRUPT_INT_0 BIT(0)
/* Default i2c CLK and Data GPIO. These are the default i2c pins */
#define DEFAULT_I2C_SCL 30
projects / karo-tx-linux.git / blobdiff