ENGR00270697-2 net:fec: correct fec MDC clock source

ENGR00270697-2 net:fec: correct fec MDC clock source

For imx6 serial silicon, fec MDC clock parent is ipg 66MHz.
The current clock file define the clock source is enet_pll8 50Mhz.
So, the MDC clock is more than 2.5Mhz after divider.

The phy Ar8031 work fine in current MDC clock, which shows the phy
have exceeding flexibility. Correct the parent clock source to make
MDC clock little than 2.5Mhz.

Signed-off-by: Fugang Duan  <B38611@freescale.com>