MLK-9961-3 arm:dts:imx6x: Change PLL1 clock management.

Add support to leave PLL1 enabled since its required whenever ARM-PODF is
changed. With this patch PLL1 is set to bypassed mode (and enabled) whenever
ARM is sourced from step_clk.
Also change imx6dl.dtsi to use #defines instead of hard-coded numbers for
busfreq clocks.

Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@freescale.com>

diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index a67da2a03d9171f7c23172315d550adedcd32730..66bf5b0efa12ec5b3c1a5d87ad9708a9f6ed1fa5 100644 (file)
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -39,9 +39,12 @@
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_STEP>,
                                 <&clks IMX6QDL_CLK_PLL1_SW>,
-                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                                <&clks IMX6QDL_CLK_PLL1_SYS>,
+                                <&clks IMX6QDL_PLL1_BYPASS>,
+                                <&clks IMX6QDL_CLK_PLL1>,
+                                <&clks IMX6QDL_PLL1_BYPASS_SRC> ;
                        clock-names = "arm", "pll2_pfd2_396m", "step",
-                                     "pll1_sw", "pll1_sys";
+                                     "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
                        arm-supply = <&reg_arm>;
                        pu-supply = <&reg_pu>;
                        soc-supply = <&reg_soc>;
@@ -58,8 +61,13 @@
        soc {
                busfreq {
                        compatible = "fsl,imx6_busfreq";
-                       clocks = <&clks 171>, <&clks 6>, <&clks 11>, <&clks 104>, <&clks 172>, <&clks 58>,
-                               <&clks 18>, <&clks 60>, <&clks 20>, <&clks 3>, <&clks 230>, <&clks 22> , <&clks 8>;
+                       clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
+                               <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>,
+                               <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>,
+                               <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>,
+                               <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>,
+                               <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> ,
+                               <&clks IMX6QDL_CLK_PLL3_PFD1_540M>;
                        clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
                                "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m";
                        interrupts = <0 107 0x04>, <0 112 0x4>;

diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index cfda9d8aa0083557eaa15b3c92a4825efd0279b1..16486119cc0fdbc70741756052a2a8ca4a5b82e9 100644 (file)
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -47,9 +47,12 @@
                                 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
                                 <&clks IMX6QDL_CLK_STEP>,
                                 <&clks IMX6QDL_CLK_PLL1_SW>,
-                                <&clks IMX6QDL_CLK_PLL1_SYS>;
+                                <&clks IMX6QDL_CLK_PLL1_SYS>,
+                                <&clks IMX6QDL_PLL1_BYPASS>,
+                                <&clks IMX6QDL_CLK_PLL1>,
+                                <&clks IMX6QDL_PLL1_BYPASS_SRC> ;
                        clock-names = "arm", "pll2_pfd2_396m", "step",
-                                     "pll1_sw", "pll1_sys";
+                                     "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
                        arm-supply = <&reg_arm>;
                        pu-supply = <&reg_pu>;
                        soc-supply = <&reg_soc>;

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 073c731fa8bb00db7fdb4808ea3648c4d2afb2e5..1b1e5f319c9372e36de09ab49d2fb736bfe4652c 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -61,9 +61,12 @@
                        clock-latency = <61036>; /* two CLK32 periods */
                        clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
                                        <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
-                                       <&clks IMX6SL_CLK_PLL1_SYS>;
+                                       <&clks IMX6SL_CLK_PLL1_SYS>,
+                                       <&clks IMX6SL_PLL1_BYPASS>,
+                                       <&clks IMX6SL_CLK_PLL1>,
+                                       <&clks IMX6SL_PLL1_BYPASS_SRC> ;
                        clock-names = "arm", "pll2_pfd2_396m", "step",
-                                     "pll1_sw", "pll1_sys";
+                                     "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
                        arm-supply = <&reg_arm>;
                        pu-supply = <&reg_pu>;
                        soc-supply = <&reg_soc>;
@@ -118,11 +121,12 @@
                                        <&clks IMX6SL_CLK_PLL1_SW>, <&clks IMX6SL_CLK_PRE_PERIPH2_SEL>,
                                        <&clks IMX6SL_CLK_PERIPH2_CLK2_SEL>, <&clks IMX6SL_CLK_PERIPH2_CLK2_PODF>,
                                        <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_PLL2_BYPASS_SRC>, <&clks IMX6SL_PLL2_BYPASS>,
-                                       <&clks IMX6SL_CLK_PLL2>;
+                                       <&clks IMX6SL_CLK_PLL2>, <&clks IMX6SL_CLK_PLL1>, <&clks IMX6SL_PLL1_BYPASS>,
+                                       <&clks IMX6SL_PLL1_BYPASS_SRC>;
                        clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph",
                                "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "pll1_sys", "periph2", "ahb",
                                "ocram", "pll1_sw", "periph2_pre", "periph2_clk2_sel", "periph2_clk2", "step", "pll2_bypass_src",
-                               "pll2_bypass", "pll2";
+                               "pll2_bypass", "pll2", "pll1", "pll1_bypass", "pll1_bypass_src";
                        fsl,max_ddr_freq = <400000000>;
                };
 

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 2a05307b03334275620c0b2d5d58a3bd6d405ad0..d4d6d4586e36a668efd660f90981f258e4e8b77b 100644 (file)
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -76,9 +76,12 @@
                                 <&clks IMX6SX_CLK_PLL2_PFD2>,
                                 <&clks IMX6SX_CLK_STEP>,
                                 <&clks IMX6SX_CLK_PLL1_SW>,
-                                <&clks IMX6SX_CLK_PLL1_SYS>;
+                                <&clks IMX6SX_CLK_PLL1_SYS>,
+                                <&clks IMX6SX_PLL1_BYPASS>,
+                                <&clks IMX6SX_CLK_PLL1>,
+                                <&clks IMX6SX_PLL1_BYPASS_SRC> ;
                        clock-names = "arm", "pll2_pfd2_396m", "step",
-                                     "pll1_sw", "pll1_sys";
+                                     "pll1_sw", "pll1_sys", "pll1_bypass", "pll1", "pll1_bypass_src";
                        arm-supply = <&reg_arm>;
                        soc-supply = <&reg_soc>;
                };