ARM: dts: apq8064: add gsbi7 i2c support

This patch adds support to gsbi7 i2c which is used in some of the new
boards.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index 7f856f6a451f99b6b5b040bddf60dbfc8ea953c7..6c465063e4103055ab63e84143b534e71d64bd00 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -234,4 +234,29 @@
                        function = "gsbi7";
                };
        };
+
+       i2c7_pins: i2c7 {
+               mux {
+                       pins = "gpio84", "gpio85";
+                       function = "gsbi7";
+               };
+
+               pinconf {
+                       pins = "gpio84", "gpio85";
+                       drive-strength = <16>;
+                       bias-disable;
+               };
+       };
+
+       i2c7_pins_sleep: i2c7_pins_sleep {
+               mux {
+                       pins = "gpio84", "gpio85";
+                       function = "gpio";
+               };
+               pinconf {
+                       pins = "gpio84", "gpio85";
+                       drive-strength = <2>;
+                       bias-disable = <0>;
+               };
+       };
 };

diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index ce463a334ccea7a4c48c3ad6b437de3de4d78d98..977231bd226e93c9aef223fc7db4815c718a8a9a 100644 (file)
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -1120,6 +1120,19 @@
                                clock-names = "core", "iface";
                                status = "disabled";
                        };
+
+                       gsbi7_i2c: i2c@16680000 {
+                               compatible = "qcom,i2c-qup-v1.1.1";
+                               pinctrl-0 = <&i2c7_pins>;
+                               pinctrl-1 = <&i2c7_pins_sleep>;
+                               pinctrl-names = "default", "sleep";
+                               reg = <0x16680000 0x1000>;
+                               interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>;
+                               clocks = <&gcc GSBI7_QUP_CLK>,
+                                        <&gcc GSBI7_H_CLK>;
+                               clock-names = "core", "iface";
+                               status = "disabled";
+                       };
                };
 
                rng@1a500000 {