MLK-10161-3: ARM: imx6sx: Add SPDIF_GCLK clock in clock tree

As spdif driver will register SPDIF clock to regmap, regmap will do
clk_prepare in init function, so SPDIF clock is prepared in probe, then its
root clock (pll clock) is prepared also, which cause the arm can't enter
low power mode.
Add SPDIF_GCLK in clock tree which share same gate bits with SPDIF clock.
Its root clock is ipg clock, and register it to regmap, then the issue can be
fixed.

Signed-off-by: Shengjiu Wang <shengjiu.wang@freescale.com>

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 8c83fb1813a0fd07e20a68276fba979bebf624f8..d787c5d734a54340d2a9e5251689ea73182bbe2c 100644 (file)
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -274,7 +274,7 @@
                                        dmas = <&sdma 14 18 0>,
                                               <&sdma 15 18 0>;
                                        dma-names = "rx", "tx";
-                                       clocks = <&clks IMX6SX_CLK_SPDIF>,
+                                       clocks = <&clks IMX6SX_CLK_SPDIF_GCLK>,
                                                 <&clks IMX6SX_CLK_OSC>,
                                                 <&clks IMX6SX_CLK_SPDIF>,
                                                 <&clks 0>, <&clks 0>, <&clks 0>,

diff --git a/arch/arm/mach-imx/clk-imx6sx.c b/arch/arm/mach-imx/clk-imx6sx.c
index 053ee04d3b3aa2120da5ba861bde9e62fae5dd87..06dfe9bdd4bff2bb7c900cc29d2c499f115b0d80 100644 (file)
--- a/arch/arm/mach-imx/clk-imx6sx.c
+++ b/arch/arm/mach-imx/clk-imx6sx.c
@@ -508,6 +508,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
        clks[IMX6SX_CLK_SPBA]         = imx_clk_gate2("spba",          "ipg",               base + 0x7c, 12);
        clks[IMX6SX_CLK_AUDIO]        = imx_clk_gate2_shared("audio",  "audio_podf",        base + 0x7c, 14, &share_count_audio);
        clks[IMX6SX_CLK_SPDIF]        = imx_clk_gate2_shared("spdif",  "spdif_podf",        base + 0x7c, 14, &share_count_audio);
+       clks[IMX6SX_CLK_SPDIF_GCLK]   = imx_clk_gate2_shared("spdif_gclk",    "ipg",        base + 0x7c, 14, &share_count_audio);
        clks[IMX6SX_CLK_SSI1_IPG]     = imx_clk_gate2_shared("ssi1_ipg",      "ipg",        base + 0x7c, 18, &share_count_ssi1);
        clks[IMX6SX_CLK_SSI2_IPG]     = imx_clk_gate2_shared("ssi2_ipg",      "ipg",        base + 0x7c, 20, &share_count_ssi2);
        clks[IMX6SX_CLK_SSI3_IPG]     = imx_clk_gate2_shared("ssi3_ipg",      "ipg",        base + 0x7c, 22, &share_count_ssi3);

diff --git a/include/dt-bindings/clock/imx6sx-clock.h b/include/dt-bindings/clock/imx6sx-clock.h
index b47ff25d9b383cd689956b0423c76ff3132947f3..c399bbbac973ddd973b98de31e389f1203b06c4f 100644 (file)
--- a/include/dt-bindings/clock/imx6sx-clock.h
+++ b/include/dt-bindings/clock/imx6sx-clock.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ * Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -279,6 +279,7 @@
 #define IMX6SX_CLK_LVDS2_OUT           266
 #define IMX6SX_CLK_LVDS2_IN            267
 #define IMX6SX_CLK_ANACLK2             268
-#define IMX6SX_CLK_CLK_END             269
+#define IMX6SX_CLK_SPDIF_GCLK          269
+#define IMX6SX_CLK_CLK_END             270
 
 #endif /* __DT_BINDINGS_CLOCK_IMX6SX_H */