powerpc: Fix hardware IRQs with MMU on exceptions when HV=0

commit 3e96ca7f007ddb06b82a74a68585d1dbafa85ff1 upstream.

POWER8 allows us to take interrupts with the MMU on.  This gives us a
second set of vectors offset at 0x4000.

Unfortunately when coping these vectors we missed checking for MSR HV
for hardware interrupts (0x500).  This results in us trying to use
HSRR0/1 when HV=0, rather than SRR0/1 on HW IRQs

The below fixes this to check CPU_FTR_HVMODE when patching the code at
0x4500.

Also we remove the check for CPU_FTR_ARCH_206 since relocation on IRQs
are only available in arch 2.07 and beyond.

Thanks to benh for helping find this.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/powerpc/kernel/exceptions-64s.S b/arch/powerpc/kernel/exceptions-64s.S
index 3684cbdd87926cf3ff4437c283629f933c36c081..bb1107597140633d8b11d55e4909a0e6bb3416a1 100644 (file)
--- a/arch/powerpc/kernel/exceptions-64s.S
+++ b/arch/powerpc/kernel/exceptions-64s.S
@@ -740,7 +740,7 @@ hardware_interrupt_relon_hv:
                _MASKABLE_RELON_EXCEPTION_PSERIES(0x502, hardware_interrupt, EXC_HV, SOFTEN_TEST_HV)
        FTR_SECTION_ELSE
                _MASKABLE_RELON_EXCEPTION_PSERIES(0x500, hardware_interrupt, EXC_STD, SOFTEN_TEST_PR)
-       ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_206)
+       ALT_FTR_SECTION_END_IFSET(CPU_FTR_HVMODE)
        STD_RELON_EXCEPTION_PSERIES(0x4600, 0x600, alignment)
        STD_RELON_EXCEPTION_PSERIES(0x4700, 0x700, program_check)
        STD_RELON_EXCEPTION_PSERIES(0x4800, 0x800, fp_unavailable)