"phys_baseaddr";
interrupts = <0 9 0x04>, <0 10 0x04>;
interrupt-names = "irq_3d", "irq_2d";
- clocks = <&clks 143>, <&clks 27>,
+ clocks = <&clks 26>, <&clks 27>,
<&clks 121>, <&clks 122>,
- <&clks 0>;
+ <&clks 74>;
clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk",
"gpu2d_clk", "gpu3d_clk",
"gpu3d_shader_clk";
hdmi_video: hdmi_video@020e0000 {
compatible = "fsl,imx6dl-hdmi-video";
- reg = <0x020e0000 0x1000>;
+ reg = <0x020e0000 0x1000>;
reg-names = "hdmi_gpr";
interrupts = <0 115 0x04>;
clocks = <&clks 124>, <&clks 123>;
&hdmi {
compatible = "fsl,imx6dl-hdmi";
};
-
-&ldb {
- clocks = <&clks 33>, <&clks 34>,
- <&clks 39>, <&clks 40>,
- <&clks 135>, <&clks 136>;
- clock-names = "di0_pll", "di1_pll",
- "di0_sel", "di1_sel",
- "di0", "di1";
-};
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
- <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ <0 0 0 2 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks 144>, <&clks 206>, <&clks 189>;
clock-names = "pcie", "pcie_bus", "pcie_phy";
status = "disabled";
reg = <0x02040000 0x3c000>;
reg-names = "vpu_regs";
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>,
- <0 12 IRQ_TYPE_LEVEL_HIGH>;
+ <0 12 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "vpu_jpu_irq", "vpu_ipi_irq";
clocks = <&clks 168>, <&clks 140>, <&clks 142>;
clock-names = "vpu_clk", "mmdc_ch0_axi", "ocram";
<&clks 39>, <&clks 40>,
<&clks 41>, <&clks 42>,
<&clks 184>, <&clks 185>,
- <&clks 205>, <&clks 206>,
- <&clks 207>, <&clks 208>;
+ <&clks 209>, <&clks 210>,
+ <&clks 211>, <&clks 212>;
clock-names = "ldb_di0", "ldb_di1",
"ipu1_di0_sel", "ipu1_di1_sel",
"ipu2_di0_sel", "ipu2_di1_sel",
"di0_div_3_5", "di1_div_3_5",
"di0_div_7", "di1_div_7",
"di0_div_sel", "di1_div_sel";
+
gpr = <&gpr>;
status = "disabled";
clk[cko1_sel] = imx_clk_mux("cko1_sel", base + 0x60, 0, 4, cko1_sels, ARRAY_SIZE(cko1_sels));
clk[cko2_sel] = imx_clk_mux("cko2_sel", base + 0x60, 16, 5, cko2_sels, ARRAY_SIZE(cko2_sels));
clk[cko] = imx_clk_mux("cko", base + 0x60, 8, 1, cko_sels, ARRAY_SIZE(cko_sels));
- clk[di0_div_sel] = imx_clk_mux("ldb_di0_div_sel", base + 0x20, 10, 1, di0_div_sels, ARRAY_SIZE(di0_div_sels));
- clk[di1_div_sel] = imx_clk_mux("ldb_di1_div_sel", base + 0x20, 11, 1, di1_div_sels, ARRAY_SIZE(di1_div_sels));
+ clk[di0_div_sel] = imx_clk_mux("ldb_di0_div_sel", base + 0x20, 10, 1, di0_div_sels, ARRAY_SIZE(di0_div_sels));
+ clk[di1_div_sel] = imx_clk_mux("ldb_di1_div_sel", base + 0x20, 11, 1, di1_div_sels, ARRAY_SIZE(di1_div_sels));
/* name reg shift width busy: reg, shift parent_names num_parents */
clk[periph] = imx_clk_busy_mux("periph", base + 0x14, 25, 1, base + 0x48, 5, periph_sels, ARRAY_SIZE(periph_sels));
clk_register_clkdev(clk[ipu1_di1_sel], "ipu1_di1_sel", "20e0000.ldb");
clk_register_clkdev(clk[ipu2_di1_sel], "ipu2_di1_sel", "20e0000.ldb");
- if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
- cpu_is_imx6dl()) {
- clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
- clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
- }
-
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di0_sel], clk[ipu2_di0_pre]);
clk_set_parent(clk[ipu2_di1_sel], clk[ipu2_di1_pre]);
+ clk_set_parent(clk[di0_div_sel], clk[ldb_di0_div_7]);
+ clk_set_parent(clk[di1_div_sel], clk[ldb_di1_div_7]);
+
/*
* The gpmi needs 100MHz frequency in the EDO/Sync mode,
* We can not get the 100MHz from the pll2_pfd0_352m.
}
/* ipu clock initialization */
- clk_set_parent(clk[ldb_di0_sel], clk[pll2_pfd0_352m]);
- clk_set_parent(clk[ldb_di1_sel], clk[pll2_pfd0_352m]);
+ if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) ||
+ cpu_is_imx6dl()) {
+ clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]);
+ clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]);
+ } else {
+ clk_set_parent(clk[ldb_di0_sel], clk[pll2_pfd0_352m]);
+ clk_set_parent(clk[ldb_di1_sel], clk[pll2_pfd0_352m]);
+ }
clk_set_parent(clk[ipu1_di0_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu1_di1_pre_sel], clk[pll5_video_div]);
clk_set_parent(clk[ipu2_di0_pre_sel], clk[pll5_video_div]);